Intel 80386

- 32bit
- 30Marks

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Q. List the salient features of 80386.

Any 8 features [1 mark each] (S-13)

1. It is a 32-bit microprocessor i.e. all the registers are 32bit in size.

2. It can operate on 8-bit, 16-bit or 32-bit data.
3. It has 32-bit data bus.
4. It has 32-bit address bus. Thus it can access 2^32 i.e.4GB
of physical memory and 2*4gb*2^13= 64 TB of virtual
memory.
5. The memory management of 80386 supports virtual
memory, paging and four level protection. The available
physical memory is divided into pages of 4KB each.
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6. It supports 80387 math coprocessor. The 80387

supports higher precision (32-bit) numerical operations.
7. It has 8 debug registers (DR0-DR7) which provides
hardware debugging and control.
8. It is designed in fully pipelined architecture & has
three queues for fetch, decode & execute.
9. It has on-chip address translation cache.
10. It is upward compatible all the previous members of
80x86 family.

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11. It runs at 20MHz and 33MHz.

12. It supports three operating modes: Real, Protected
Virtual (PVAM) and Virtual 8086.
13. It is also available in 3 versions :
i. 80386 SX 16 bit up (286)
ii. 80386 DX full 32 bit
iii. 80386 EX full 32 bit + on chip DRAM Controller

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Q. Draw and explain the internal architecture of 80386.

(4M for diag, 4M for expln.) (W-13)

Q. Draw the internal architecture of 80386. Also explain the

following pin of 80386
BE0 to BE3
D/C
LOCK
BUSY
(Architecture with label = 4 M each pin functionality 1M X= 4M) (S-14)

Ali Karim Sir

Architecture

6 functional units
Bus Interface unit
Prefetch unit
Decode unit
Memory Management Unit, consisting of
Segmentation unit
Paging unit
Execution unit

The figure shows the architecture of 80386.

It is divided in 3 sections
1) MMU
2) CPU
3) BIU
1) Central Processing Unit :It consist of execution unit containing 8 General purpose
register, 8 special purpose register used for data handling &
calculation of offset address.
Central unit also consists of instruction unit of which decode
& op code bytes received from 16 byte code queue &
arrange them into 3 byte instruction decoded queue.
It also consists of ALU containing barrel shifter.
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2) MMU : It consists of segmentation & paging unit.

Segmentation unit allows maximum 4 GB segments.
Paging unit organizes physical memory in the form of
pages of 4kb size.
The segment unit & paging unit work together for MMU
to access virtual memory to provide protection
mechanism.

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3) BIU :It contains

request prioritizes,
address driver,
pipeline bus size control,
MUX trans receiver
to deal with memory of i/o device. This unit is
responsible to access M/IO devices.

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PIN DIAGRAM OF 80386

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CLK
2 X CLOCK

ADDRESS
BUS

31

BE 3 #
32 BIT
DATA

31

DATA
BUS

BE 2 #
BE 1 #
BE 0 #

ADS

W / R #

NA #
BS
BUS
CONTROL

16

HOLD
BUS
ARBITRATION

D / C#

READY

HLDA

32 BIT
ADDRESS

BYTE
ENABLI
NES

M / IO

80386
PROCESSOR

LOCK

BUS CYCLE
DEFINATION

PEREQ
BUSY
ERROR

#
#

COPROCESS
OR
SIGNALLING

INTR
V

CC

NMI
INTERRUPTS
RESET

13

GND

POWER
CONNECTIO
NS

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Signal Descriptions of 80386

CLK2 : The input pin provides the basic system clock timing
for the operation of 80386.
D0 D31: These 32 lines act as bidirectional data bus during
different access cycles.
A31 A2: These are upper 30 bit of the 32- bit address bus.
BE0 to BE3: Output - It selects the access of byte, word, double
word of data. These signals are generated by A0 & A1 used to
validate the data

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W/R#: The write / read output distinguishes the write and read
cycles from one another.

D/C#: Output - Whenever it is 1, it indicates the data bus

contains data & when 0 up is in halt state or executes
interrupt acknowledgement.

M/IO#: This output pin differentiates between the memory and

I/O cycles.

LOCK#: The LOCK# output pin enables the CPU to prevent

the other bus masters from gaining the control of the system
bus.

NA#: The next address input pin, if activated, allows address

15pipelining, during 80386 bus cycles.
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ADS#: The address status output pin indicates that the address
bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0#
to BE3# ) are carrying the respective valid signals.
The 80386 does not have any ALE signals and so this signals
may be used for latching the address to external latches.

READY#: The ready signals indicates to the CPU that the

previous bus cycle has been terminated and the bus is ready for
the next cycle. The signal is used to insert WAIT states in a bus
cycle and is useful for interfacing of slow devices with CPU.

VCC: These are system power supply lines.

VSS: These return lines for the power supply.

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BS16#: The bus size 16 input pin allows the interfacing of 16

bit devices with the 32 bit wide 80386 data bus. Successive 16
bit bus cycles may be executed to read a 32 bit data from a
peripheral.

HOLD: The bus hold input pin enables the other bus masters
to gain control of the system bus if it is asserted.

HLDA: The bus hold acknowledge output indicates that a valid

bus hold request has been received and the bus has been
relinquished by the CPU.

BUSY#: The busy input signal indicates to the CPU that the
coprocessor is busy with the allocated task. Input - This signal
is sent by co processor. It is active low signal causing 80286
17to wait or escape instruction
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ERROR#: The error input pin indicates to the CPU that the
coprocessor has encountered an error while executing its
instruction.

PEREQ: The processor extension request output signal

indicates to the CPU to fetch a data word for the coprocessor.

INTR: This interrupt pin is a maskable interrupt, that can be

masked using the IF of the flag register.

NMI: A valid request signal at the non-maskable interrupt

request input pin internally generates a non- maskable interrupt
of type2.
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RESET: A high at this input pin suspends the current operation

and restart the execution from the starting location.

N / C : No connection pins are expected to be left open while

connecting the 80386 in the circuit.

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With labeled neat diagram explain memory organization of

80386. (1 marks for interfacing 3 marks for description)

The 80386 processor address 4GB memory with

the help of BE 0 to BE3 and A2 to A31 address
lines.
The A0 and A1 are enclosed with the bus enable
BE signal BE 0 to BE3 .
It selects the access of byte, word, double word of
data. These signals are generated by A0 & A1
used to validate the data.

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Memory Organization:
The memory is divided into four 8 bit wide
memory banks, each containing upto 16 bytes of
memory.
This 32 bit wide memory organization allows
bytes, words or double words of memory to be
accessed directly.
Memory location range from 00000000H to
FFFFFFFFH.
The four memory banks are accessed via bank
Enable signals BE3#-BE0#.

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This arrangement allows:

1) A byte to be accessed when one bank enable
signal is activated by microprocessor.
2) A word can be accessed when two bank enable
signals are activated.

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Register Organisation

The 80386 has eight 32 - bit general purpose registers which

may be used as either 8 bit or 16 bit registers.
A 32 - bit register known as an extended register, is represented
by the register name with prefix E.
Example : A 32 bit register corresponding to AX is EAX,
similarly BX is EBX etc.
The 16 bit registers BP, SP, SI and DI in 8086 are now
available with their extended size of 32 bit and are names as
EBP,ESP,ESI and EDI.
AX represents the lower 16 bit of the 32 bit register EAX.
BP, SP, SI, DI represents the lower 16 bit of their 32 bit
counterparts, and can be used as independent 16 bit registers.
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GENERAL DATA AND ADDRESS REGISTERS

31
16 15

AX

EAX

BX

EBX

CX

ECX

DX

EDX

SI

ESI

DI

EDI

BP

EBP

SP

ESP

SEGMENT SELECTOR REGISTERS

CS
SS

CODE SEGMENT
STACK SEGMENT

DS
ES

DATA SEGMENT

FS
GS
INSTRUCTION POINTER AND FLAG REGISTER
31
16 15
IP
FLAGS

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0
EIP
EFLAGS

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The six segment registers available in 80386 are CS, SS, DS,
ES, FS and GS.
The CS and SS are the code and the stack segment registers
respectively, while DS, ES, FS, GS are 4 data segment
registers.
A 16 bit instruction pointer IP is available along with 32 bit
counterpart EIP.
Flag Register of 80386: The Flag register of 80386 is a 32 bit
register. Out of the 32 bits, Intel has reserved bits D18 to D31, D5
and D3, while D1 is always set at 1.Two extra new flags are
added to the 80286 flag to derive the flag register of 80386.
They are VM and RF flags.
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FLAGS

31
F
L
A RESERVED FOR
INTEL
G
S

18

17

VM

16

RF

15

14 13

NT

IOPL

12

OF

11

10

DF

IF

TF

SF

ZF

AF

PF

FLAG REGISTER OF 80386

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CF

VM - Virtual Mode Flag: If this flag is set, the 80386 enters

the virtual 8086 mode within the protection mode. This is to be
set only when the 80386 is in protected mode. In this mode, if
any privileged instruction is executed an exception 13 is
generated. This bit can be set using IRET instruction or any
task switch operation only in the protected mode.
RF- Resume Flag: This flag is used with the debug register
breakpoints. It is checked at the starting of every instruction
cycle and if it is set, any debug fault is ignored during the
instruction cycle. The RF is automatically reset after successful
execution of every instruction, except for IRET and POPF
instructions.
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Control Registers: The 80386 has three 32 bit control registers

CR0, CR2 and CR3 to hold global machine status independent
of the executed task. Load and store instructions are available
to access these registers.

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PG- Paging Enable

If PG is Set to enable On Chip Paging Unit.
If PG is reset to disable On Chip Paging Unit.
R- Reserved
This bit is reserved and when loading CR0 care
should be taken to not alter the value of this bit.
TS- Task Switch flag
If this flag is set to 1, it will indicate the next
instruction using the processor extension and will
generate the exception 7.
It allows the CPU to test whether the current
processor extension is for current task.

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EM- Emulate processor extension flag

If this flag is set to 1, it allows the generation of exception 7
(processor extension not present ) and will permit the
emulation of the processor extension by the CPU.
(If this flag is set and the processor extension is absent it will
allow the CPU to work as a coprocessor)
MP- Monitor Processor extension flag

If this flag is set to 1, it allows the Wait instruction to

generate a processor extension absent exception i.e.
exception number 7.
In short when this flag is set to 1 it indicates the absence of
coprocessor (processor extension)
if its not present and permits the emulation of the processor
extension by the CPU.

PE- Protection Enable

The PE bit is used to switch between Real and Protected
Mode.
If it is set, 80386 operates in the Protected Mode and if PE is
reset, processor in Real Mode.
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PE bit can be set or reset only by loading MSW or CR0.

Explain functions of Debug register of 80386

(W-12)(diagram: 2 marks, explanation 2
marks)
Debug registers :
There is a set of 8 debug registers for hardware
debugging.
The DR0 to DR3 are used to store program
controllable breakpoint addresses.
DR4 and DR5 are not used and are reserved by
Intel.
The DR6 AND DR7 are used to hold the breakpoint
status and breakpoint control information
respectively.
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Debug register of 80386

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Explain test register format of 80386 with

suitable diagram. 4M [2M for diag, 2M for
expln.]
Test Register:- TR6 & TR7
Used to test translation look aside buffer (TLB)
used with paging.
TR6 & TR7 are used for translation look aside
buffer (TLB).

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V = 1 Valid TLB entry

D = 1 TLB entry invalid or dirty.
U = A bit for TLB.
W = Indicates that area addressed by TLB entry is
writable.
C = 0 Write or immediate look up (1) for TLB.
PL = hit of logic 1.
REP = Selects which block of TLB is written.
Hit rate : if the page is matched.
Miss rate : if the page is missed.
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Explain the system address register of

microprocessor 80386?(Diagram 2M &
Explain 2M)
80386 has 32registers resources in different
categories, system address register is one of
them.
System Address Registers: Four special
registers are defined to refer to the descriptor
tables supported by 80386.
The 80386 supports four types of descriptor tables

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Global descriptor table (GDT),

Interrupt descriptor table (IDT),
Local descriptor table (LDT) and
Task State Segment(TS)
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The addresses of these tables and segments are

stored in special registers known as System
Address and System Registers namely as.
GDTR Global Descriptor Table Register:
IDTR Interrupt Descriptor Table Register :
This register points to a table of entry points
for interrupt handler so These registers point to
the segment descriptor tables i.e. they hold linear
base address &16bit limit of GDT and IDT
respectively.
Task State Register:
This register points to the information needed
by the processor to define Local Descriptor Table
Register Above the current task LDTR
two
registers hold 16 bit selector for LDT & TSS
36descriptor respectively.
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ADDRESSING MODES: The 80386 supports overall eleven

addressing modes to facilitate efficient execution of higher
level language programs.

In case of all those modes, the 80386 can now have 32-bit
immediate or 32- bit register operands or displacements.

The 80386 has a family of scaled modes. In case of scaled

modes, any of the index register values can be multiplied by a
valid scale factor to obtain the displacement.

The valid scale factor are 1, 2, 4 and 8.

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Q. Explain Real Mode of 80386 (S-13)

[6 Marks for Description and 2 Marks for
Diagram]
Q. With suitable figure, explain Address translational in
Real Addressing mode of 80386
microprocessor. (W-12)
(04 marks for diagram, 04 marks for
explanation)

After reset, the 80386 starts from memory location

FFFFFFF0H under the real address mode.
In the real mode, 80386 works as a fast 8086 with
32-bit registers and data types.
In real mode, the default operand size is 16 bit but
32- bit operands and addressing modes may be
used with the help of override prefixes.
The segment size in real mode is 64k, hence the
32-bit effective addressing must be less
than
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0000FFFFFH.

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Memory Addressing in Real Mode:

In the real mode, the 80386 can address at the

most 1Mbytes of physical memory using address
lines A0-A19.
Paging unit is disabled in real addressing mode,
and hence the real addresses are the same as the
physical addresses.
To form a physical memory address, appropriate
segment registers contents (16-bits) are shifted
left by four positions and then added to the 16-bit
offset address formed using one of the addressing
modes, in the same way as in the 80386 real
address mode.

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The segment in 80386 real mode can be read,

write or executed, i.e. no protection is available.
Any fetch or access past the end of the segment
limit generates exception 13 in real address
mode.
The segments in 80386 real mode may be
overlapped or non-overlapped.
The interrupt vector table of 80386 has been
allocated 1Kbyte space starting from 00000H to
003FFH.

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Explain protected virtual addressing mode of

80386
(W-13)
[Diagram 2M, Description 2M]
In this mode 80386 can address 4 GB of physical
memory.
In this mode contents of segment register are
used as selector address descriptor containing
segment base address & access right bytes of a
segment.
The offset is added within segment base address
to calculate linear address & feature used as
physical address.
The paging unit works in this.
The large segment of a memory is divided into 4
kb size pages, the paging unit converts linear
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address into physical address.

48 / 32 BIT POINTER
SELECTOR
SELECTOR

OFFSET
OFFSET

31 / 15

47 / 31

SEGMENT LIMIT

ACCESS RIGHT
c

LIMIT
c
BASE ADDRESS
SEGMENT DESCRIPTOR

c
MEMORY OPERAND
c

UP TO
4 GB

c
SEGMENT BASE ADDRESS

Protected Mode Addressing Without Paging Unit

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SELECTED
SEGMENT

Q. Compare real mode and protected virtual mode of 80386

microprocessor.
(W-12)(1 Mark for each Point any four points)

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Explain paging and segmentation of Intel 80386. (S-13)

(diagram :1 marks and description 3 marks)
Segmentation is the process of dividing the main memory in 4
different segments (may not be of equal size.)
The process of paging and segmentation together is as shown as
below in diagram:

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Paging Operation:Paging is a memory management technique used for virtual

memory multitasking operation.
The paging divides memory into fixed sizes such as 928 bytes,
256 bytes ------ 1 kb, 2 k & 4 k ---- & so on.
They do not have any logical relation with a program as
compared to segment.
Paging unit converts complete map of a task into pages each of
size 4kb.
The task is executed in terms of pages.

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Each task has three components :

1) Page Directory 2) Page Table 3) Page
Page Directory:The size of page directory is 4 kb & each directory entry has 4
bytes, therefore total 1024 entries are possible in directory.
The table shows the entry format for page directory.
Page Table:Each page table is also of 4 kb & maximum 1024 entries are
possible similar to page directory.
It contains the starting address of page, the upper 20 bit D31
D12 use page frame address combined with lower 12 bits of
linear address A12 A21 are used to select 1024 page table
entries.

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Describe Enabling and Disabling of Paging in 80386.

(W-13)(4M)
The control register CR0 to CR3 controls the paging operation of
80386.
CR0 holds the MSW containing PG bit i.e. 31th bit. If PG = 1
page translation for linear address into physical address i.e.
paging operation is enabled.
Similarly if PG = 0 i.e. reset provides disabling or disable paging
operation.
After the PG bit is set, page translation takes effect on the text
instruction and
if the linear addresses from which you are executing are not at
the same physical address they were before page translation took
effect, you are going to wind up somewhere unexpected.
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For this reason take following steps:

Disable interrupt, including NMI.
Enable paging only from a page that is identified mapped
Flush the instruction prefetch queue immediate after the MOV
instruction that enables paging.
Disabling paging involves the same hazards that enabling it does.
Be sure that your code will be mapped the same physical space
after the page translation is turned off and flush the prefetch queue
afterward.

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What do you meant by TLB? How does it help the address

calculation procedure? (2M diagram and 2M Explanation)
Translation look aside buffer:
It is a cache of most recently accessed pages.
It is four way set associate 32 entry page table
TLB holds page table address translation to reduce the no. of
memory required for page table translation.
Address Calculation procedure

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The paging unit receives 32 bit linear address from segmentation

unit.
The upper 20 bit (a31 a12) gives page directory & path table
address bits, they are compared with all 32 bit entries in TLB.
If it matches physical address is calculated from match TLB
entries & place on address bus.
To speed up the conversion process of linear address to physical
address.
Cache of 32 X 4 byte is provided to store a 32 bit page table entry
that is known as TLB (Translation Loop aside Buffer).
If page table entry is not in TLB 80386 reads to appropriate page
directory entry & set or reset P & A bit.

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Explain paging and segmentation of Intel 80386. (W-13)

(diagram :4 marks and description 4 marks)
The paging unit operates under the control of segmentation unit.
The paging unit if enabled converts linear addresses into physical
address, in protected mode.
Paging Operation:
Paging is one of the memory management techniques used for
virtual memory multitasking operating system.
The segmentation scheme may divide the physical memory into a
variable size segments but the paging divides the memory into a
fixed size pages.
The segments are supposed to be the logical segments of the
program, but the pages do not have any logical relation with the
program.
The pages are just fixed size portions of the program module or
data.
The advantage of paging scheme is that the complete segment of a
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task
need not be in the physical memory at any time.

Only a few pages of the segments, which are required currently for
the execution need to be available in the physical memory.
Thus the memory requirement of the task is substantially reduced,
relinquishing the available memory for other tasks.
Whenever the other pages of task are required for execution, they
may be fetched from the secondary storage.
The previous page which are executed, need not be available in the
memory, and hence the space occupied by them may be
relinquished for other tasks.
Thus paging mechanism provides an effective technique to manage
the physical memory for multitasking
systems.

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Paging Unit:
The paging unit of 80386 uses a two level table mechanism to
convert a linear address provided by segmentation unit into
physical addresses.
The paging unit converts the complete map of a task into
pages, each of size 4K.
The task is further handled in terms of its page, rather than
segments.
The paging unit handles every task in terms of three
components namely page directory, page tables and page
itself.

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Paging Descriptor Base Register:

The control register CR2 is used to store the 32-bit linear address at
which the previous page fault was detected.
The CR3 is used as page directory physical base address register, to
store the physical starting address of the page directory.
The lower 12 bit of the CR3 are always zero to ensure the page size
aligned directory.
A move operation to CR3 automatically loads the page table entry
caches and a task switch operation, to load CR0 suitably.

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Page Directory :
This is at the most 4Kbytes in size.
Each directory entry is of 4 bytes, thus a total of 1024
entries are allowed in a directory.
The upper 10 bits of the linear address are used as an index to the
corresponding page directory entry.
The page directory entries point to page tables.
Page Tables:
Each page table is of 4Kbytes in size and many contain a maximum
of 1024 entries.
The page table entries contain the starting address of the page and
the statistical information about the page.
The upper 20 bit page frame address is combined with the lower 12
bit of the linear address.
The address bits A12- A21 are used to select the 1024 page table
entries.
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page table can be shared between the tasks. Ali Karim Sir

What is paging? Explain enabling and disabling

paging of 80386.
(paging :definition : 1 marks, enabling and
disabling explanation : 4 marks, diagram of CR0
register:1 mark)
Paging is one of the memory management techniques used for
virtual memory multitasking operating system.
The segmentation scheme may divide the physical memory into a
variable size segments but the paging divides the memory into a
fixed size pages.
The segments are supposed to be the logical segments of the
program, but the pages do not have any logical relation with the
program.
The pages are just fixed size portions of the program module or data.

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The effective address (offset) is added with segment base

address to calculate linear address. This linear address is
further used as physical address, if the paging unit is disabled,
otherwise the paging unit converts the linear address into
physical address.

The paging unit is a memory management unit enabled only in

protected mode. The paging mechanism allows handling of
large segments of memory in terms of pages of 4Kbyte size.

The paging unit operates under the control of segmentation

unit. The paging unit if enabled converts linear addresses into
physical address, in protected mode.

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