Documentos de Académico
Documentos de Profesional
Documentos de Cultura
Nov. 1, 2005
Fabian Goericke, Keunhan Park,
Geoffrey Williams
1
Outline
What is a DAC?
Resistor-string DAC
Specifications of DAC
Errors
Applications
2
What is a DAC?
1
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
DAC
3
What is a DAC?
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
Digital Input Signal
4
Rtotal 8 R
I VREF / Rtotal VREF /(8 R )
Vn Rn I n
R I
Vn
n R
I
n
Vn VREF
VREF
8 R
I
8
Example
VREF 8V
3
V3 8V 3V
8
7
1 1 0 6V
1 0 0 4V
1 1 1 7V
0 0 0 0V
8
R
Rf
2R
4R
+
2nR
10
Vout
Vout
V1 V2 V3 V4
R f I 2 R f (
I1 )
Rf
...
11 8 R
R 2R 4R
Most
significant
bit
Least
significant
bit
Rf = R / 2
V1 V2 V3 V4
...
R 2 R 4 R 8R
Vout R f I 2 R f (
I1 )
Rf
Vn = Vref, if bit is set
Vn = 0, if bit is clear
12
Advantages
Simple
Fast
Disadvantages
Needs
large range of resistor values (2000:1 for 12bit) with high precision in low resistor values
Needs very small switch resistances
13
4 bit converter
Vref
V3
V2
V1
V0
V0
Req
V1
V0
1
R
1/ 2 R 1/ 2 R
V0
R
1
V1 V1
RR
2
V1
R
1
V2 V2
RR
2
V2
R
1
V3 V3
RR
2
15
Vref
V0
2R
1
V0 Vref
8
Vout
R
1
V0 Vref
2R
16
16
b3b2b1b0
Vout b( N i )
i 1
Vref
i
Resolution
Vref
2N
17
(bi 0 or 1)
Advantages
Only
Disadvantages
More
confusing analysis
18
Specification of DAC
Resolution
Speed
Settling time
Linearity
Reference voltage
19
Specification - Resolution
VRef
N
2
N = Number of bits
20
Specification - Speed
settling
time of converter
21
The time required for the input signal voltage to settle to the
expected output voltage (within +/- of VLSB).
Fast converters reduce slew time, but usually result in longer ring
time.
tslew
tdelay
tring
22
Specification Linearity
23
Specification Linearity
Ideally, a DAC should produce a linear relationship
between a digital input and the analog output, this is not
always the case.
Linearity(Ideal Case)
Desired/Approximate Output
Digital Input
Perfect Agreement
NON-Linearity(Real World)
Analog Output Voltage
Desired Output
Approximate
output
Digital Input
24
Miss-alignment
Types:
Non-multiplier
manufacturer)
Multiplier
25
2 N 1
Vref
V fs 1
Vref
i 1
N
i 0 2
2
26
Errors
There are a multiple sources of error associated with DAC
Gain Error
Gain Error: Deviation in the slope of the ideal curve and
with respect to the actual High
DAC
output.
Gain
Desired/Ideal Output
Low Gain
Digital Input
28
Offset Error
Output Voltage
Desired/Ideal Output
Positive Offset
Negative Offset
Digital Input
29
30
Differential Non-Linearity
2VLSB
VLSB
Digital Input
31
Integral Non-Linearity
1VLSB
Digital Input
32
Digital Input
33
Resolution Errors
Poor Resolution(1 bit)
Vout
Desired Analog
signal
1
2 Volt. Levels
Approximate
output
34
Digital Input
Resolution Errors
Better Resolution(3 bit)
Vout
Desired Analog signal
111
8 Volt. Levels
Better approximation of
the of the desired output
signal due to the smaller
voltage divisions.
110
101
110
101
100
100
011
011
010
010
001
001
000
000
Digital Input
Approximate
output
35
Analog Output
Voltage
+VLSB
Expecte
d
-VLSB
Voltage
Settling time
36
Time
Common Applications
37
References
38
Questions?
39