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Textbook: Essentials of Computer Architecture, Author: Douglas E. Comer, 2005, Pearson Prentice Hall
Chapter Four
The Variety of Processors and
Computational Engines
State Tables
State tables describe the activities of a state diagram.
Moore Machine
Arrows are transitions
Labels on arrows are inputs
Outputs are associated with
states
1 indicates that turn off
alarm is yes
0 indicates that turn off
alarm is no
(b) Mealy Machine
Outputs associated with
transitions
Labels on directed arrows
indicates input/output
Modulo 6 Counter
Counts from 0 to 5 and starts over
U is input, 0 is
indicates no change,
1 is increment
counter
C used to indicate
when counter goes
from 101 to 000
Values 110 and 111
not used
Mealy
Moore
R: light is red
G: light is green
A: Alarm sounded
Use 3 bits to identify the state because there are six states
Identifies state based on output (state 100 is reached when output is 0100
N0 = P0U + P0U
00
0
1
01
0
1
11
0
X
U=1
10
0
X
N2 = P 2
P2/P1P0
0
1
N0 = P 0
00
0
1
01
0
0
11
1
X
10
0
X
11
0
X
10
1
X
N2 = P 2 P 0 + P 1 P 0
00
0
0
01
0
0
11
1
X
10
1
X
N1 = P 1
P2/P1P0
0
1
P2/P1P0
0
1
P2/P1P0
0
1
00
0
0
01
1
0
N1 = P1P0 + P2P1P0
00
0
0
01
1
1
11
1
X
10
0
X
P2/P1P0
0
1
N0 = P 0
00
1
1
01
0
0
11
0
X
10
1
X
00
0
0
X
1
Moore Machine
01
0
0
X
1
11
0
1
X
0
10
0
0
X
1
00
0
1
X
0
01
0
1
X
0
11
1
0
X
0
10
0
1
X
0
00
0
0
X
0
01
1
1
X
1
11
0
0
X
0
10
1
1
X
1
11
0
0
X
1
10
0
0
X
0
V0 = P0U + P0U
P2P1/P0U
00
01
11
10
00
1
0
X
0
01
0
0
X
0
C = P2P1P0U + P2P0U
P2/P1P0 00 01 11 10
0
0 0 0 0
1
1 1 X X
V2 = P 2
P2/P1P0 00 01 11 10
0
0 0 1 1
1
0 0 X X
V1 = P 1
P2/P1P0 00 01 11 10
0
0 1 1 0
1
0 1 X X
V0 = P 0
P2/P1P0 00 01 11 10
0
1 0 0 0
1
0 0 X X
C = P2P1P0
P2 P1 P0 U
N2 N1 N0 C
Output
P2P1/P0I
00
01
11
10
N2 = P 1
00
0
1
1
0
01
0
1
1
0
11
0
1
1
0
10
0
1
1
0
P2P1/P0I
00
01
11
10
N1 = P o
00
0
0
0
0
01
0
0
0
0
11
1
1
1
1
10
1
1
1
1
P2P1/P0I
00
01
11
10
N0 = I
00
0
0
0
0
01
1
1
1
1
11
1
1
1
1
10
0
0
0
0
P2P1/P0U 00
00
0
01
0
11
1
10
0
M = P 2 P1 P0
01
0
0
1
0
11
0
0
0
0
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Next State
P2P1/P0U
00
01
11
10
V2 = P 2
00
0
0
1
1
01
0
0
1
1
11
0
0
1
1
10
0
0
1
1
P2P1/P0U 00 01 11 10
00
0 0 0 0
01
0 0 1 0
11
0 0 0 0
10
1 1 0 1
N2 = P2P1P0 + P2P1U + P2P1P0U
P2P1/P0U
00
01
11
10
V1 = P1
00
0
1
1
0
01
0
1
1
0
11
0
1
1
0
10
0
1
1
0
P2P1/P0U 00 01 11 10
00
0 0 1 0
01
1 1 0 1
11
0 0 0 0
10
0 0 0 0
N1 = P2P1P0 + P2P1U + P2P1P0U
P2P1/P0U
00
01
11
10
00
0
0
1
0
01
0
0
1
0
11
1
1
1
1
10
1
1
1
1
01
1
0
0
0
11
0
0
0
0
10
0
0
0
0
V0 = P 0 + P 2 P1
P2P1/P0U 00
00
1
01
0
11
0
10
0
C = P2P1P0
P2P1/P0U 00 01 11 10
00
0 1 0 1
01
0 1 0 1
11
0 0 0 0
10
0 1 0 1
N0 = P2P0U + P2P0U + P1P0U + P1P0U
Next State
P2P1/P0U
00
01
11
10
V2 = P 2 P0
00
0
X
1
1
01
0
X
1
1
11
0
0
0
X
10
0
0
0
X
P2P1/P0U
00
01
11
10
V1 = P 1 P0
00
0
X
0
0
01
0
X
0
0
11
0
1
1
X
10
0
1
1
X
P2P1/P0U
00
01
11
10
00
0
X
0
1
01
0
X
0
1
11
1
0
1
X
10
1
0
1
X
P2P1/P0U
00
01
11
10
00
0
X
1
1
01
0
X
1
0
11
0
1
1
X
10
0
0
1
X
P2P1/P0U 00 01
00
0 0
01
X X
11
1 0
10
0 0
N1 = P1U + P0U
11
1
1
1
X
10
0
1
1
X
P2P1/P0U 00 01
00
0 1
01
X X
11
0 0
10
0 0
N0 = P2U + P0U
11
1
1
0
X
10
1
1
1
X
N2 = P2U + P1U
01
1
X
0
0
11
0
0
0
X
10
0
0
0
X
FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.
FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.
FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.
FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.