Execution Unit &

Addressing Modes of
8086

VARIOUS REGISTERS IN EU

FLAG REGISTER

It is a 16-bit status register within the EU of

8086.
There are nine flags in 8086.
Six of these are status flags and three are
control flags.
Status Flags are used to indicate some
condition produced by an instruction
Control Flags are used to control certain
operation of the processor
3

8086 FLAG REGISTER

STATUS FLAGS

CF- Carry Flag It is set if carry out of MSB.

PF- Parity Flag It is set if result has even parity.
AF- Auxiliary Flag Used for BCD.
ZF- Zero Flag It is set if result is 0.
SF- Sign Flag It is set if result is negative.
OF- Overflow Flag It is set if signed result is
out of the range.

CONTROL FLAGS
TF-Single step Trap Flag It is to be set if
single step mode (debugging) is needed.
IF- Interrupt Flag It is to be set, for
allowing or prohibiting interruption
request.
DF- Direction Flag If set, string
instruction automatically decrements the
address (string data transfers proceed
from high address to the low address.

POINTER AND INDEX

REGISTERS
There are two pointer and two index
registers in the EU of 8086.
These registers are used to store the
offset addresses of memory locations
relative to the segment registers.

POINTER REGISTER
Two pointer registers are :
Stack pointer The value in the SP
always represents the offset of the next
stack location that can be accessed.
Base pointer It also represents an offset
relative to SS register but is employed in
the based addressing mode of 8086.
8

EU Operation
1. Fetch an instruction from instruction
queue
2. According to the instruction, EU control
logic generates control signals.
(This process is also referred to as instruction
decoding)

AH
BH
CH
DH
SP
BP
SI
DI

3. Depending on the control signal,

EU performs one of the following
operations:
An arithmetic operation
A logic operation
Storing a datum into a register
Moving a datum from a register
Changing flag register

AL
BL
CL
DL

ALU
Flag register

Microprocessor System Design

General purpose
register

ALU Data bus

(16 bits)

EU
control

instruction
1011000101001010

3-9

Instruction Machine Codes

Instruction machine codes are binary numbers
For Example:
1000100011000011
MOV

MOV AL, BL

Register
mode

Machine code structure

Opcode

Mode

Operand1 Operand2

Some instructions do not have operands, or have only one operand

Opcode tells what operation is to be performed.

(EU control logic generates ALU control signals according to Opco
Mode indicates the type of a instruction: Register type, or Memory type

Operands tell what data should be used in the operation. Operands can
be addresses telling where to get data (or where to store results)
Microprocessor System Design

3-10

INDEX REGISTER
Two index registers are:
Source index (SI)- It is used to store an
offset address for source operand.
Destination index (DI)- It is used for
storage of an offset address for the
destination operand.

11

Memory Segmentation
A segment is a 64KB block of memory starting from any 16-byte
boundary
For example: 00000, 00010, 00020, 20000, 8CE90, and E0840 are all valid
segment addresses
The requirement of starting from 16-byte boundary is due to the 4-bit
left shifting

Segment registers in BIU

15

0
CS

Code Segment

DS

Data Segment

SS

Stack Segment

ES

Extra Segment

Microprocessor System Design

3-12

Memory Address Calculation

Segment addresses must be stored
in segment registers

Segment
address

Offset is derived from the combination

of pointer registers, the Instruction
Pointer (IP), and immediate values

0000

Offset

Memory address

Examples
CS 3 4 8 A 0
4 2 1 4
IP +
Instruction address3 8 A B 4

SS 5 0 0 0 0
F F E 0
SP+
Stack address5 F F E 0

DS 1 2 3 4 0
0 0 2 2
DI +
Data address 1 2 3 6 2
Microprocessor System Design

3-13

Fetching Instructions
Where to fetch the next instruction?
8088

Memory

CS 1 2 3 4
IP
0012

12352 MOV AL, 0

12352

Update IP
After an instruction is fetched, Register IP is updated as follows:

IP = IP + Length of the fetched instruction

For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction
the IP is updated to 0014
Microprocessor System Design

3-14

Accessing Data Memory

There is a number of methods to generate the memory address when
accessing data memory. These methods are referred to as
Addressing Modes
Examples:
Direct addressing: MOV AL, [0300H]
1 2 3 4 0
0 3 0 0
Memory address1 2 6 4 0
DS

(assume DS=1234H)

Register indirect addressing: MOV AL, [SI]

1 2 3 4 0
0 3 1 0
Memory address1 2 6 5 0
DS

(assume DS=1234H)
(assume SI=0310H)

Microprocessor System Design

3-15

ADDRESSING MODES OF
8086

The addressing modes available in Intel 8086

are:
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Relative Addressing
6. Indexed Relative Addressing
7. Based Indexed Relative Addressing

16

The MOV instruction

MOV

AX , BX

Destination

Source

17

Register Addressing Mode

With the Register Addressing mode the operand to

be accessed is specified as residing in an internal
register of the 8086.
Examples
Assembly Language

Size

Operation

MOV AL, BL
8-bits
Copies BL into AL
MOV CH, CL
8-bits
Copies CL into CH
MOV AX, CX
16-bits
Copies CX into AX
MOV SP, BP
16-bits
Copies BP into SP
MOV BX, ES
16-bits
Copies ES into BX
MOV ECX, EBX
32-bits
Copies EBX into ECX
Both
and the
destination
operands
MOV the
ESP,source
EDX
32-bits
Copies EDX
into ESP
have
been
internal
MOV ES,
DS specified as
the contents
Not allowedof
(segment-to-segment)
registers
of the 8086
MOV BL, DX
Not allowed (mixed sizes)
18

Immediate Addressing Mode

If a source operand is part of the instruction

instead of the contents of a register or
memory location, it represents what is called
the immediate operand and is accessed
using immediate addressing mode. Typically
immediate operand represents constant data
Immediate operands can be either a byte or
word of data
Example:

MOV AL , 15H (2 bytes) MOV CX,

4AC2H (3bytes).
19

Direct Addressing Mode

Direct
addressing
differs
from
immediate
addressing, that the locations following the
instruction op-code hold an Offset which is a 16bit offset of the storage location of the operand from
the current value in the data segment (DS) register.
offset is combined with the contents of DS in the
BIU to produce the physical address of the operand.

Example: MOV CX , [1000]

This stands for move the contents of the memory

location, which is offset by 1000H from the current
value in DS into internal register CX
CX

[DS*10+1000]H
20

Register Indirect Addressing Mode

Register indirect addressing is similar to direct addressing, that an

effective address is combined with the contents of DS to obtain a
physical address. However it differs in a way that the offset is
specified. Here offset resides in either a pointer register or an index
register within the 8086.The pointer register can be either a base
register BX or a base pointer register BP and the index register can
be source index register SI or the destination index register DI
Example MOV AX , [SI]

This instruction moves the contents of the memory location offset by

the value of offset in SI from the current value in DS to the AX
register.

AX

[DS*10+[SI]]H

21

Based Addressing Mode

In the based addressing mode, the physical address of

the operand is obtained by adding a direct or indirect
displacement of the contents of either base register BX
or base pointer register BP and the current value in DS
and SS respectively.
Example : MOV [BX + SI] , AL
This instruction uses base register BX and direct
displacement SI to derive the EA of the destination
operand. The based addressing mode is implemented by
specifying the base register in the brackets followed by a
period and direct displacement .The source operand is
located in the byte accumulator AL
22

Indexed Addressing Mode

Indexed addressing mode works identically to

the based addressing but it uses the contents
of the index registers instead of BX or BP, in
the generation of the physical address.
Example

MOV AL , [SI+10]

The source operand has been specified using

direct index addressing. The notation this
time is such, which is a direct displacement,
prefixes the selected index register, SI.
23

Based Indexed Addressing Mode

Combining the based addressing mode and the

indexed addressing mode together results in a
new, more powerful mode known as based
indexed addressing.
Example:

MOV AH , [BX] . BETA [SI]

Here the source operand is accessed using the

based indexed addressing mode. The effective
address of the source operand is obtained as
offset = [BX]+BETA+[SI]

24

25

26