Lecture 9 Sequential Logic

Prof. Sin-Min Lee

Department of Computer Science

4 Basic types of Flip-Flops

SR, JK, D, and T
JK ff has 2 inputs, J and K need to be asserted
at the same time to change the state
D ff has 1 input D (DATA), which sets the ff
when D = 1 and resets it when D = 0
T ff has1 input T (Toggle), which forces the ff
to change states when T = 1
SR ff has 2 inputs, S (set) and R (reset) that set
or reset the output Q when asserted

Gated D-Latch
Ensures S and R inputs never equal to 1 at the
same time
Useful in control application where setting or
resetting a flag to some condition is needed
Stores bits of information
Constructed from a gated SR latch and a Data
latch

Analysis of Sequential Systems

Goal:
Decide the timing and functional behavior
from the implementation of a sequential
system composed of FFs and logic gates

Types:
Functional analysis
Timing analysis

Characteristic Equation of FFs

The origin of the name for the JK flip-flop is detailed by P. L.

Lindley, a JPL engineer, in a letter to EDN, an electronics
newsletter. The letter is dated June 13, 1968, and was published
in the August edition of the newsletter. In the letter, Mr. Lindley
explains that he heard the story of the JK flip-flop from Dr.
Eldred Nelson, who is responsible for coining the term while
working at Hughes Aircraft.
Flip-flops in use at Hughes at the time were all of the type that
came to be known as J-K. In designing a logical system, Dr.
Nelson assigned letters to flip-flop inputs as follows: #1: A & B,
#2: C & D, #3: E & F, #4: G & H, #5: J & K. Given the size of
the system that he was working on, Dr. Nelson realized that he
was going to run out of letters, so he decided to use J and K as
the set and reset input of each flip-flop in his system (using
subscripts or somesuch to distinguish the flip-flops), since J and
K were "nice, innocuous letters."

Dr. Montgomery Phister, Jr., an engineer

under Dr. Nelson at Hughes, picked up the
idea that J and K were the set and reset
input for a "Hughes type" of flip-flop,
which he then termed "J-K flip-flops," a
name that he carried with him when he left
for Scientific Data Systems in Santa
Monica.

Implement D Flip-flop by T Flip-flop

Q
D

T = D Q + D Q
D
D

Implement JK Flip-flop by D Flip-flop

Q
0

00

01

JK

JK
00

01

11

11

10

10

Q+

D = J Q + K Q

J
D

K
Q

Implement JK Flip-flop by T Flip-flop

Q+

Q
0

00

01

JK

JK
00

01

11

11

10

10

JK

Q+
T

Q+

00

01

10

11

T = J Q + K Q

J
T

K
Q

Implement T Flip-flop by JK Flip-flop

Q
T

Q Q+

00

01

10

11

Q
T

J=T

K=T

Recap - Sequential Systems

Example:
Design a D FF with a JK FF and AND, OR, NOT gates:

To Be CLK
Designed

Sequential Systems - Cont.

D(t)
0
1
01--1
-0
JK

Sequential Systems - Cont.

D

K = D

J=D

CLK

Recap - Sequential Systems

Example:
Design a D FF with a JK FF and AND, OR, NOT gates:

To Be CLK
Designed

T & J-K Flip-Flops

Sequential Circuit

Sequential Circuit (4)

Sequential Circuit (6)

Analysis of Sequential Circuit Logic Diagrams

C o m b in a t io n a llo g ic
z
x

y
y

C lo c k

M em ory
(a )
D

C
Q
Q
0

(b )

Figure 8.8

4 t/D

Timing Diagram for Figure 8.8 (a)

C lo c k
x

Y = D

z
0

6
G litc h

Figure 8.9

t/D

State Table and State Diagram for Figure 8.8 (a)

In p u t
0

P resen t
sta te

In p u t
0

P resen t
sta te

0
y

y
1

In p u t

P resen t
sta te

0 /0

1 /0

A /0

B /0

1 /0

0 /1

B /0

A /1

N e x t s ta te /o u tp u t
(b )

(a )

x/
z
1 /0

0 /0
A

N e x t s ta te /o u tp u t
(c )

0 /0
B

1 /1
(d )

Figure 8.10

K-Maps for Circuit of Figure 8.8 (a)

0
0
y

y
1

xk

In p u t
1

P resen t
sta te

A /0

B /0

B /0

A /1

yk
(a )

(b )

Figure 8.11

+ 1

(c )

/z k

Synchronous Sequential Circuit with T Flip-Flop --

y
y

Q
Q

T
C

Figure 8.12

C lo c k

Timing Diagram

C lo c k
x

T
z
0

Figure 8.13

State Table and State Diagram

yk

xk

yk 0

1
y k + 1 / z k

1 /0

0 /0

1 /0

0 /1

x
P resen t
sta te

y k + 1 / z k

(a )

1 /1
(d )

B /0

A /0

B /0

A /1
(c)

x/
z
0 /0

N e x ts ta te /o u tp u t

(b )

1 /0

B
0 /0

K-Maps for Example

0
0
y

xk

0
0

y
1

y
1

zk

(a )

(b )

1 /0

0 /0

1 /0

0 /1
+ 1

1*

0*

/z k

(d )

+ 1

(c)

yk

yk

yk

xk

Example 2.Synchronous Sequential Circuit with JK

Flip-flops
z

y1

C
K

y2

y2

y1

C
K

C lo c k

Timing Diagram and State Table for Example 2

C
x

y1

y2

J1 = xy2
K1 = x
J2 = x
K 2 = x + y1
z = xy1 y2

(a )
x
y1 y2

00

0 0 /0

0 1 /0

01

0 0 /0

1 0 /0

11

0 0 /0

1 1 /1

10

0 0 /0

1 1 /0
(b )

K-Maps for Example 2

x
y1 y2

00

01

11
10

y1 y2

x
0

00

01

11

10

J1

y1 y2

x
0

00

01

11
10

y1 y2

x
0

00

01

11

10

J2

y1 y2

00

01

11

10

Generating the State Table From K-maps -Example 2

x
y1 y2

00
01

01

1
01

01

00

01

11

10

11

11

01

01

10

10

10

01

01

00

10

J1 K

J2 K

J1 K
(a )

J2 K

y1 y2

00

00

01

01

00

11
10

y1 y2

00

0 0 /0

0 1 /0

10

01

0 0 /0

1 0 /0

00

11

11

0 0 /0

1 1 /1

00

11

10

0 0 /0

1 1 /0

Y1 Y2
(b )

Y 1 Y 2/z
(c )

Example 3.Synchronous Sequential Circuit

Synthesis
x

A
1 /1
0 /0

1 /0

0 /0

0 /0

1 /0

0 /0

1 /0

D /0

B /0

D /0

C /0

D /0

B /0

D /0

A /1

(a ) C o m p le te ly s p e c ifie d c ir c u it

x
1 /1

A
0 /-

0 /1 /C

B
1 /1

0 /0

B /-

-/1

B /0

C /1

A /-

A /-

(b ) I n c o m p le te ly s p e c ifie d c ir c u it

Introductory Synthesis Example -- Example 3

x

S ta te

y1 y2

y 1 y 2

z
1

A /0

B /0

00

0 0 /0

0 1 /0

A /0

C /1

01

0 0 /0

1 1 /1

B /0

D /0

11

0 1 /0

1 0 /0

C /1

D /0

10

1 1 /1

1 0 /0

y 1 y 2
00

( c ) T rY a 1n Ys i 2t /i oz n
ta b le

( b ) S t a t e
a s s ig n m e n t

(a )S t a te ta b le

y 1y 2

00

y 1 y 2

00

01

01

01

11

11

11

10

10

10

z
(d )O u tp u tK m a p

D 1 (= Y 1 )

D 2 (= Y 2 )

(e )E x c it a tio n K m a p s

y1
y1

y2
y2

D 1

D 2

( f ) L o g ic d ia g r a m

C lo c k

Flip-flop Input Tables -- Example 3

S ta te
R e q u ir e d
tr a n s itio n s
in p u ts
Q ( t) Q (t+ e )
D (t)

S ta te
tr a n s itio n s
Q (t ) Q (t+ e )

R e q u ir e d
in p u ts
S (t)
R (t)

(a )D flip flo p

(b )C lo c k e d S R

S ta te
R e q u ir e d
tr a n s itio n s
in p u ts
Q ( t) Q (t+ e )
T (t)

S ta te
tr a n s itio n s
Q (t ) Q (t+ e )

R e q u ir e d
in p u ts
J (t)
K (t)

(c )C lo c k e d T f lip flo p

(d )C lo c k e d J K flip flo p

Generating the JK Flip-flop Excitation Maps -Example 3

y1y2

y1y2

0 1 /0

00

0d

0d

00

0d

1d

0 1 0 0 /0

1 1 /1

01

0d

1d

01

d1

d0

1 1 0 1 /0

1 0 /0

11

d1

d 0

11

d0

d1

1 0 1 1 /1

1 0 /0

10

d0

d0

10

1d

0d

Y 1Y 2/z

0 0 0 0 /0

J 1K

y1y2

J 2K

( a ) T r a n s it io n t a b le

y1y2

y1y2

(b )E x c ita tio n ta b le

y1y2

y1y2

00

00

00

00

01

01

01

01

11

11

11

11

10

10

10

10

J1

(c )E x c ita tio n m a p s

Clocked JK Flip-Flop Implementation -Example 3

x
z

y1
y1
y2
y2

Q
Q

Q
Q

J1

C
K

J2
C
K2
C lo c k

Application Equation Method for Deriving

Excitation Equations -- Example 3
x
y1 y2

00

01

11
10

y1 y2

y1
1

x
0

00

01

y2

11

10

Registers

Two independent flip-flops with clear and preset

Registers

Missing Q, preset, clocks ganged

Inversion bubbles cancelled, so loaded with rising
Can make 8- bit register with this