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ASIC Course
Saeed Bakhshi
May 2004
Class presentation based on ISSCC2003 paper: A
Outlines
Memory Evolution
What is DDR?
DDR Architecture
High Speed Memory Design Considerations
DDR-II Architecture
A 1.8V, 700Mb/s/pin, 512Mb DDR-II SDRAM with
On-Die Termination and Off-Chip Driver Calibration
A paper from:
History of Memory
Memory Evolution
1979 DRAM
1997 SDRAM
Next Generation Memories RAMBUS, DDR SDRAM
This was due to the limitations the older memory has when
working with systems using higher bus speeds (over 75 MHz).
What is DDR?
DDR Terminology
Name
Clock Freq.
Data Rate
DDR200
DDR266
DDR333
DDR400
100 MHZ
133 MHZ
167 MHZ
200 MHZ
200 MHZ
266 MHZ
300 MHZ
400 MHZ
DDR Architecture
DDR Architecture
DDR Architecture
DDR Architecture
Output Driver
DDR Architecture
SSTL stands for Series Stub Terminated Logic and has been
defined and standardized within JEDEC.
Series resistors are incorporated in the SSTL signaling
technology for main memory applications.
These resistors can be very effective in dissipating any
reflected wave energy traveling along the module traces and
isolating the module stubs from the main memory bus.
Proper termination of the bus transmission lines, reducing
signal reflections.
The result is improved signal quality, higher clock frequencies,
and lower EMI emissions.
SSTL inputs are typically a differential pair common source
amplifier with one input tied to the VTT reference.
Reflection
Crosstalk and interference
SSN (simultaneously switching noise)
DDR II
DDR II
Signal integrity
Power Consumption
4-bit pre-fetch
On-die termination
Off-chip driver calibration
DDR Evolution
DDR-II Architecture
4-bit Pre-fetch
In SDRAM each output buffer can relase a single bit per clock cycle.
DDR (I)
In DDR, every I/O buffer can output two bits per clock cycle. Each
read command will transfer two bits from the array into the DQ. Since
the data are fetched from the array before they are released, the
memory parlance describes this as "prefetch of 2".
The simplest way to conceptualize this is to use two separate data lines
from the primary sense amps to the I/O buffers.
The DQs are then outputting the data in a time multiplexed manner,
meaning one bit at a time on the same output line
The easy way to do this is to collect the two bits in two separate pipeline
stages and then release them in the order of the queue on the rising and
the falling edge of the clock.
Because two bits are released to the bus per pin and clock cycle, the
protocol used is called double data rate or DDR.
4-bit Pre-fetch
DDR2 SDRAM
achieves high-speed
operation by 4-bit
prefetch architecture.
In 4-bit prefetch
architecture, DDR2
SDRAM can read/write
4 times the amount of
data as an external bus
from/to the memory cell
array for every clock,
and can be operated 4
times faster than the
internal bus operation
frequency.
It is true that lower voltage swings enable higher frequencies but after
a certain point, the ramping of the voltages will show a significant
skew.
The skew can be reduced by increased drive strength, however, with the
drawback of a voltage overshoot / undershoot at the rising and falling
edges, respectively.
The solution in DDR was to add clock forwarding in form of a simple data
strobe.
DDR II takes things further by introducing a bidirectional, differential I/O
buffer strobe consisting of DQS and /DQS as pull-up and pull-down
signals.
Differential means that the two signals are measured against each other
instead of using a simple strobe signal and a reference point.
In theory the pull-up and pull-down signals should be mirror-symmetric to
each other but reality shows otherwise.
Contents
Introduction
Data Path Architecture
Conclusion
Introduction
CHIP Architecture
On-Die Termination
On Die Termination
Thank You