2 of 42 Acorn Computer? Acorn Computers Limited, based in Cambridge, England. In 1979, Acorn Atom released. Made up with 6502 1Mhz 8 bits CPU. Not Very famous. When Acorn meet BBC ( British Broadcasting Corporation), new computer was born?
3 of 42 The Birth of ARM. As acorn cant find any processor ready on the market is acceptable for their needs, they want to design new processor. Make new processor need great investment and experience? Luckily the papers from the Berkeley RISC I were designed. After some custom modifications by acorn, new RISC processor was born ! The ARM ( Advanced RISC Machine ).
4 of 42 Architectural Inheritance from Berkeley RISC Used: Load- store architecture Fixed- length 32- bit instructions 3 address format Rejected: Register windows=> Costly o Use Shadow Registers in ARM Delayed branches Single cycle execution of all instructions Memory Access o Multiple Cycles when no separate data and instruction memory support o Auto-indexing Addressing Modes
Result: RISC with a few CISC features 5 of 42 What is RISC/CISC? Reduced Instruction Set Computer Fewer Addressing modes. Fewer Instructions available. For example, ARM, NEC VR series. Complex Instruction Set Computer More Instructions available Many addressing modes. For example, Intel x86.
6 of 42 Advantages of RISC? Smaller die size Simple instructions - simple processor require less transistors. Shorter development time Simple processor take less effort to design. Higher performance? Disadvantages: Complex compiler poor code density 7 ARM Programmer Model
8 ARM History ARM Acorn RISC Machine (1983 1985) Acorn Computers Limited, Cambridge, England ARM Advanced RISC Machine 1990 ARM Limited, 1990 ARM has been licensed to many semiconductor manufacturers
9 ARMs visible registers User level 15 GPRs, PC, CPSR (current program status register) Remaining registers are used for system-level programming and for handling exceptions r13_und r14_und r14_irq r13_irq SPSR_und r14_abt r14_svc user mode fiq mode svc mode abort mode irq mode undefi ned mode usable in user mode system modes only r13_abt r13_svc r8_fiq r9_fiq r10_fiq r1 1_fiq SPSR_irq SPSR_abt SPSR_svc SPSR_fiq CPSR r14_fiq r13_fiq r12_fiq r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r1 1 r12 r13 r14 r15 (PC) 10 ARM CPSR format N (Negative), Z (Zero), C (Carry), V (oVerflow) mode control processor mode T control instruction set T = 1 instruction stream is 16-bit Thumb instructions T = 0 instruction stream is 32-bit ARM instructions I F interrupt enables N Z C V unused mode 31 28 27 8 7 6 5 4 0 I F T 11 ARM memory organization Linear array of bytes numbered from 0 to 2 32 1 Data items bytes (8 bits) half-words (16 bits) always aligned to 2-byte boundaries (start at an even byte address) words (32 bits) always aligned to 4-byte boundaries (start at a byte address which is multiple of 4) half -word4 word16 0 1 2 3 4 5 6 7 8 9 10 11 byte0 byte 12 13 14 15 16 17 18 19 20 21 22 23 byte1 byte2 half -word14 byte3 byte6 address bi t 31 bi t 0 half -word12 word8 12 ARM instruction set Load-store architecture operands are in GPRs load/store only instructions that operate with memory Instructions Data Processing use and change only register values Data Transfer copy memory values into registers (load) or copy register values into memory (store) Control Flow o branch o branch-and-link save return address to resume the original sequence o trapping into system code supervisor calls 13 ARM instruction set (contd) Three-address data processing instructions Conditional execution of every instruction Powerful load/store multiple register instructions Ability to perform a general shift operation and a general ALU operation in a single instruction that executes in a single clock cycle Open instruction set extension through coprocessor instruction set, including adding new registers and data types to the programmers model Very dense 16-bit compressed representation of the instruction set in the Thumb architecture 14 I/O system I/O is memory mapped internal registers of peripherals (disk controllers, network interfaces, etc) are addressable locations within the ARMs memory map and may be read and written using the load- store instructions Peripherals may use either the normal interrupt (IRQ) or fast interrupt (FIQ) input normally most interrupt sources share the IRQ input, while just one or two time-critical sources are connected to the FIQ input Some systems may include external DMA hardware to handle high-bandwidth I/O traffic 15 ARM exceptions ARM supports a range of interrupts, traps, and supervisor calls all are grouped under the general heading of exceptions Handling exceptions current state is saved by copying the PC into r14_exc and CPSR into SPSR_exc (exc stands for exception type) processor operating mode is changed to the appropriate exception mode PC is forced to a value between 00 16 and 1C 16 , the particular value depending on the type of exception instruction at the location PC is forced to (the vector address) usually contains a branch to the exception handler; the exception handler will use r13_exc, which is normally initialized to point to a dedicated stack in memory, to save some user registers return: restore the user registers and then restore PC and CPSR atomically