Chapter 4

I/O Subsystem Organization and

Interfacing
Cs 147

Peter Nguyen
General Information
Computer generally consists of
three subsystems
Communication between
subsystems by buses
The processors sends out the
address to be accessed in
memory or the address of the
I/O device via the address bus
Data bus carries data between
the subsystems
Information sent on the control
bus coordinates all data
transfers
The processor goes through an
instruction cycle
Fetch an instruction from
memory, and decode the
instruction, and execute the
instruction

All instructions are fetched and
decoded in the same way, but
the execute cycle is different for
every instruction
Three Sections of the CPU

The register section, used for data storage
The arithmetic/logic unit, performs
computations on data with the CPU
The control unit outputs signals to control
the rest of the processor
Types of Memory Chips

ROM, PROM, EPROM, and EEPROM are all
read only memory chips (data does not change)

SRAM and DRAM, these are random access
memory (data change or lost when the computer is
turned off)

Two types of I/O access
Memory mapped I/O

Treats I/O device as if it
were a memory location
The same instructions are
used to access both
memory and I/O devices,
but memory and the I/O
device cannot both use the
same address
Isolated I/O

Different instructions are
used to access I/O devices
and memory
Requires an additional
control line to distinguish
between the two, but this
allows memory and I/O
devices to both use the
same address
Presentation Outline : Part I

Input Module
Output Module
Bi-directional Module
An overall view within the organization of a
simple computer

-Definition -
_________________________
Memory is defined as homogeneous
From the CPUs perspective, each
location is read from and written to in
exactly the same way
Whats the correlation ?
They are quite different but the
comparisons is needed in order to
understand the structure and
organization of the computer
Memory vs. I/O
Every memory has a
unique address

Each memory location is
read from and written to in
exactly the same way,
performs the same
function that is, its stores
a data value or an
instruction for use by the
CPU
Every I/O device has a
unique address

Perform vastly different
functions; even though,
they are part of the same
subsystem
The major components of the Input Module

Input device (keyboard, mouse, )
Tri-state buffers
Data bus

Enable logic (Address bus and Control Bus)
An input device: (a) with its interface and (b) the
enable logic for the tri-state buffers


The tri-state buffers are used
in input device interfaces to
make sure that no more than
one device writes data to the
bus at any time.
What is Enable Logic ?
Enable logic is the key to this design.
Because of the unique address, enable logic must
not enable the buffers unless it receives the correct
address from the address bus. It must also get the
correct control signals from the control bus.
Components of the Output Module

Output device (monitor)
Register
Data bus


Enable Logic (Address bus and Control bus)

Output Device
___
The output devices read data from the bus, rather
that write data to it, they do not need the buffers.
The data can be made available to all output
devices; only the device with the correct address
will read it in.
Load Logic
In the Output Module the load logic plays the role of the
enable logic in the input device interface. When this logic
receives the correct address and control signals, it asserts the
LD signal of the register, causing it to read data from the
systems data bus.
__
By doing so, the output device can then read the
data from the register at its leisure while the CPU
performs other tasks.
Components of the bi-directional module




I/O device (hard disk drive)
Two interfaces (one input, tri-state and one output, register)
Logic elements (gates to check address on the address bus)

Bi-directional module
I/O devices are much slower than CPUs and
memory
Timing problems exist when interacting
with the CPU
How does the CPU work around this
processes ?
Ready
Normal inputs are high when the CPU outputs the address
of the I/O device and the correct control signals, enabling the
tri-state buffers of the I/O device interface, the I/O device
sets READY low.
The CPU reads this signal and continues to output the same
address and control signals
which cause the buffers to remain
enabled.
By having the extra clock cycles generated when
READY is set low
This is called wait states

Ready is good for small processes
Many systems actually use the
interrupts
For larger computers

Interrupts

Direct memory access, DMA
Interrupts
Performs useful work while waiting
for the much slower I/O devices
Direct memory access (DMA)
method used to bypass the CPU in
the transferring process
Building a Simple Computer


CPU
8K of ROM, starting with address 0
8K of RAM
Memory mapped
Bidirectional I/O with a port address of 80000H
Read and Write control lines
Central Processing Unit (CPU)
Relatively
Simple
CPU

16-bit addresses pin
Systems data bus accesses
Read control lines
Write control lines
The memory subsystem
Memory Subsystem
0000 0000 0000 0000
0001 1111 1111 1111
To access the memory chip, the processor must
supply an address used by the chip, as well as the
proper control signals
Memory
ROM
RAM
Address 000
Address 001
Combinatorial logic is used to realize these functions
and set the chip enable signals of the memory chips
ROM chip will output data only when its output enable and
chip enable signals are asserted
RAM has two control inputs , RD and WR. Both
the read and write signals from the control bus can
drive these two signals
I/O subsystem
Register Tri-state buffers
I/O Device
Freehand drawing of a computer organization
Historical Perspective
Please see attached
Questions ?