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CMOS VLSI

Agenda
INTRODUCTION
BASICS OF CMOS
CAPACITANCE IN CMOS
PHYSICAL AND GEOMETRICAL EFFECTS
FABRICATION PROCESS
CMOS CIRCUITS
SIZING
SCALING METHODS
CMOS LAYOUT
INTRODUCTION
Introduction
INTEGRATED CIRCUITS
IC TECHNOLOGY
TRENDS IN VLSI
Some terminology associated with IC are
Substrate : It is supporting material upon or within
which an IC is fabricated
Monolithic IC : An IC whose elements are formed in
place upon or within a semiconductor
with at least one element formed within
the substrate
Hybrid IC : Consist of two or more IC types
Wafer : It is the basic physical unit used in
processing.
Chip : one of the repeated ICs on a wafer
Integrated Circuits
Advantage of IC circuits over discrete components are.

Size : Smaller both wires and transistor are
shrunk to micro as compared to millimeter
or centimeter of discrete components.

Speed : Hundred times faster than PCB.

Power : Less power due to small size of circuits on
chip.
Integrated Circuits
IC Technologies
The IC technology can be categorized ,depending on the
number of transistors, as :

1975 Memory, Computers,
Signal Processors
10,000-100,000 VLSI

1970 Microprocessors, ADC 1000-10,000 LSI
1965 Registers, Filters 100-1000 MSI
1960 Gates, Op-amps, Linear
app
1-100 SSI
YEAR FUNCTION No.of active
Devices (BJT/FET)
IC
Micro Electronics
Active Substrate
Silicon GaAs
Bipolar
N P CMOS TTL ECL
(Good Resistors)
Fast
Current : Majority None thro gate
Current : Majority + Minority
thro base
Microelectronics Technology
Inert Substrate
MOS
IC Technologies
Two basic technologies used for manufacturing ICs are
Bipolar
MOS


Bipolar : The main technology is low-power-schottky TTL
Disadvantage: High power dissipation.
Used for SSI and MSI.

MOS : LSI technology uses MOSFETS since these can be
packed in small area.
P-MOS Technology : It uses P-MOSFET s.
Mobility of holes - 240 cm
2
/v*sec
Holes are majority carriers & hence this is relatively slow.
N-MOS Technology : It uses N-MOSFET s
Mobility of electrons -650 cm
2
/v*sec
Since electrons are majority carriers this technology is
faster than P-MOS.
C-MOS Technology :It uses combination of P-channel and
N-channel MOS.
Comparison-CMOS and Bipolar
Technologies
Unidirectional
devices
Bi-directional
devices
Direction
High Low Fan-out
Low High Packaging density
Low High Noise margin
Low High Input impedance
High Low Static power dissipation
BIPOLAR CMOS FACTORS
Trends in VLSI
Minimum geometrical feature size.
Increase in speed of digital circuit. Use of GaAs for very
high frequency.
Increase in complexity of a circuit function and device
count.
Increasing designer productivity and evergrowing
dependence on the computer in the design process.
Continual shift of where design, production, and
markets are geographically located.
Growing coupling of specific process and its processing
equipment.
BASICS
Basics
FIELD EFFECT PRINCIPLE
FEATURE SIZE
DEVICE COUNT
MOS TRANSISTOR
TRANSISTOR WORKING
Field Effect Principle
d
L
I
tox
Vg
Gate
Conductor
(Channel)
E
W
V = - n.E
V
j=p.v= -n.q. n.E
Change in Vg influences p and hence j
Cg = 1800 . W . L F
Change in gate charge A Qg = -Cg . A Vg causes the following change in channel
charge
+Cg . A Vg = 1800 .W.L. A Vg = W.L.tcond. A p
|An| = |Ap/q| = 1.13 x 1016. A Vg/tcond electrons/m3
If 1 V change in Vg causes 1% change in current density j then
tcond = 1.13 x 1018 / n

Field Effect Principle
L
Vg
SiO2
tox
Gate
Channel
Copper
<1atom
n=1028 electron/m3
tcond=11.3 x 10-11 m
n-Silicon
About 10
n=1021 electron/m3
tcond=1130 m
N-MOSFET
layout
The ratio of minimum allowable value of gate width(W) and gate
length(L) is called as minimum feature size.
Thus feature size is function of IC technology.
Feature Size
Feature Size
Typically L = 1 to 10 m, W= 2 to 500 m and the thickness of oxide layer is in
the range 0.02 to 0.1 m.
How many devices that can be fabricated on a 4 inch silicon wafer
with 5 technology ?
N = No of devices = Hr
2
/ (5 X 5
2
) = 3 X 10
8
N
Thus 1/10th decrease in Feature size increase the Device
count 100 times.
Device Count
MOS Transistors
INVERSION LAYER N-MOS TRANSISTOR
TRANSISTOR VOLTAGE
MOSFET
DEPLETION TYPE MOS
ENHANCEMENT TYPE MOS
CMOS
Inversion Layer n-MOS Transistor
n+
n+
L
P-
Gate
Drain
Source
tox
W
Substrate
GATE Electrode: Metal
plate e.g. aluminium or
molybdenum, or a heavily
doped and thus low ohmic
polycrystalline silicon
layer
Source and Drain are
heavily doped to minimise
series resistance.
In p-type transistor contain a p+ source and drain and n-type substrate
MOS: Metal Oxide
Semiconductor SiO2
MOS transistors
D
S
B
G
D
S
B
G
Id
Is
Ig
Id
Is
Ig
n-Channel p-Channel
Vds
Vbb
Vdg
Vgs
Vds
Vbb
Vdg
Vgs
+
+
+
+
-
-
-
-
+
+
+
+
-
-
-
-
For P-channel MOS substrate is of N type and source, drain are
formed with P type material.
For N-channel MOS substrate is of P type while source & drain
are formed with N type material.
Gate is polycrystalline silicon electrode and is insulated from
substrate by thin layer of silicon dioxide SiO
2

Since the gate is insulated, MOSFETs are also called as
Insulated Gate Field Effect Transistors ( IGFET )
It is a voltage controlled device, the current through channel is
controlled by voltage applied to gate.
MOSFETs can be configured either as
Enhancement type MOSFET
OR
Depletion type MOSFET
Metal Oxide Semiconductor FET
Depletion type MOS
In Depletion MOS structure, the source & drain are
diffused on P- substrate as shown above.
Positive voltages enhances number of electrons from
source to drain.
Negative voltage applied to gate reduces the drain
current
This is called as normally ON MOS.
It consists of lightly doped p-type substrate into which
two highly doped n
+
regions are diffused.
When the gate voltage V
GS
= 0 volt, there is no
conduction path between source and drain, hence the
drain current is zero.
Since the gate is insulated positive voltage may be
applied to gate, it will produce electric field across
substrate.
Enhancement NMOS
Enhancement NMOS
This field will end on induced negative charges in p
substrate.

These negatively charged electrons, which are minority
carriers in p substrate, form an inversion layer. Current
flows from source to drain through this induced
channel.

More the positive voltage, More is the induced charge
& hence more current flows from source to drain.

This is also called Normally Off MOS, since drain
current is zero for zero gate voltage.

CMOS integrated circuits use enhancement type
transistors only.

CMOS Technology
As shown above PMOS transistor is formed in a separate n-type region
known as n-well.
Transistor Working
WORKING IN CUTOFF REGION
WORKING IN LINEAR REGION
WORKING IN SATURATION REGION
COMPARISON OF P-MOS AND N-MOS
SOME EQUATIONS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ +
+
+
+
+
Vgs=0V
S
D
G
n+ n+
B
P-
Z
Z
|f
Ee
Ei
Ef
Ev
MOS
Vgs=Vds=Vsb=0V
MOS Transistor Operation - CutOff Region
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ +
+
+
+
+
S
D
G
n+ n+
B
P-
Z
|f
Ee
Ei
Ef
Ev
MOS
0<Vgs<VT, Vds=Vsb=0V, Ids=0
+ + + + +
0<Vgs<Vt
MOS Transistor Operation - CutOff Region
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ +
+
+
Vgs=VT
S D
G
n+ n+
B
P-
Z
|f
Ee
Ei
Ef
Ev
MOS
+
+
|f
Vgs=VT, Vds=Vbs=0, Ids=0
Depletion Layer
+ + + + + + + +
MOS Transistor Operation - CutOff Region
MOS Transistor Operation - CutOff Region
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ +
+
+
Vgs>VT
S D
G
n+ n+
B
P-
Z
|f
Ee
Ei
Ef
Ev
MOS
|f
Vgs>VT, Vds=Vbs=0, Ids=0
+ + + + + + + +
Depletion Layer
Inversion Layer Mobile Charge
Inversion region
As gate voltage is increased number of electrons will be
attracted to the substrate surface under the gate to make
n-type.

The n-type region which is created electrically in the p
substrate is called the inversion layer.

The gate-to-source voltage necessary to create the
inversion layer is called the threshold voltage (Vt).

After formation of inversion layer the current flow from
drain to source or source to drain if small voltage is
applied
Enhancement NMOS-Operation
Linear Region
Increase in gate-source voltage(Vgs) beyond threshold
voltage (Vt)brings additional electrons under gate
causing increase in inversion layer.

If large drain-source voltage is applied ,this voltage
itself will tend to deplete the inversion layer due to
potential drop across the region formed by current flow
Enhancement NMOS-Operation
Linear Region
MOS Transistor Operation - Linear Region
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ +
+
+
Vgs>VT>0
S
G
n+ n+
B
P-
+ + + + + + + +
0<Vds<Vgs-VT
Vgs constant
Ids increases w.r.t. Vds
0
1 2 3 4 5 6 7 8
1
2
3
4
Vds(V)
Id(mA)
Vgs=Vt+4
Vgs=Vt+3
Vgs=Vt+2
Vgs=Vt+1
Vgs<Vt
I-V Characteristics
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Vgs>VT>0
S
G
n+ n+
B
P-
+ + + + + + + +
Vds=Vgs-VT=Vdssat
MOS Transistor Operation - Linear Region
Vgs constant
Ids reaches Idssat
Vgs=Vt+4
Vgs=Vt+3
Vgs=Vt+2
Vgs=Vt+1
Vgs<Vt
0
1 2 3 4 5 6 7 8
1
2
3
4
Vds(V)
Id(mA)
Vds=Vgs-Vt
+
+
+ + +
+
+
+
+
+
+
+
+
+
+
+
+
+
Vgs>VT>0
S
G
n+ n+
B
P-
+ + + + + + + +
Vds>Vgs-VT
MOS Transistor Operation - Saturation Region
Vgs constant Ids ideally constant
When V
DS
> V
GS
V
T
, V
GD
< V
T
, the channel becomes pinched- off & transistor is
said to be in saturation.
Conduction is brought by drift mechanism of electrons under the influence of
positive drain voltage and effective channel length is modulated.
Vgs=Vt+4
Vgs=Vt+3
Vgs=Vt+2
Vgs=Vt+1
Vgs<Vt
0
1 2 3 4 5 6 7 8
1
2
3
4
Vds(V)
Id(mA)
Vds=Vgs-Vt
V
GS
> V
T
, V
IN
> V
T
V
DS
> V
GS
- V
T

V
GS
< V
T
, V
IN
<V
T
+ V
DD

V
DS
< V
GS
- V
T

SATURATED

V
GS
> V
T
, V
IN
> V
T
V
DS
< V
GS
- V
T

V
GS
< V
T
, V
IN
<V
T
+ V
DD

V
DS
> V
GS
- V
T

NON-
SATURATED

V
OUT
> V
IN
- V
T
V
OUT
< V
IN
- V
T
V
OUT
< V
IN
- V
T
V
OUT
> V
IN
- V
T
V
GS
< V
T
V
IN
< V
T
V
GS
>V
T
V
IN
> V
T
+ V
DD
CUT-OFF
N-DEVICE P-DEVICE REGION OF
OPERATION
Voltage Relation For Regions Of
Operation Of CMOS Inverter
some equations
Ig = 0

0
when Vgs < Vt (cutoff), Vds > 0

(K W/L) (Vgs Vt- Vds/2) Vds)
Id = when Vgs > Vt, 0 < Vds <Vgs Vt(Linear)

( K W/2L) (Vgs Vt)**2)
when Vgs > Vt, Vds > Vgs Vt(saturation)



Enhancement NMOS-Operation
Enhancement NMOS-Operation
Ids Ids
Ids Ids
n-channel p-channel
Enhancement
Depletion
Vgs
Vgs
Vgs Vgs
Vds>0
Vds>0
Vds<0
Vds<0
Vt
Vt Vt
Vt
Vt>0 Vt<0
Vt>0
Vt<0
CAPACITANCE IN MOS
MOS Device Capacitance Estimation
Bulk Cap.
Junction Cap.
Overlap Cap.
Capacitance in MOS
p-substrate
n+ n+
Csb Cdb
Cgb
Cgs
Cgd
Cgdo
Cgso
drain
source
gate
b
d
g
s
Cgd Cgdo
Cgs
Cgso
Cgb
Cdb
Cdb
Capacitance in MOS
Vg<<Vt for p-type and
Vg>>Vt for n-type substrate.
The surface potential |s is highly
negative and majority carriers
in the p-type substrate will
form a surface layer of holes.
This accumulation layer will be
thin in comparison with the
oxide thickness and exists as
long as Vg is much smaller
than Vt.
The silicon then behaves like a
metal plate. The MOS
capacitance then equal to the
oxide capacitance Cox.
Deviation occurs at the high
frequency (>1GHz) where
dielectric relaxation time tR
plays the role.
Vg Vg Vg
++++++++++
+
+ +
+
+
+
+
+
+
+ +
+ +
+
+ +
+
+
+
+
+
+
+
+
+ +
+
+
+
+
+ +
+
+
channel
Depletion
layer
tox
At low
frequency
At high
frequency
Vg Vt 0
x x
C
Cmin
Cox
accumulation depletion inversion
Vg~Vt, thus |s~02|f

As Vgs gradually becomes more
positive, for a p-type substrate,
the accumulation layer will
decrease.
A depletion layer will be created
under the gate when |s >0. A
voltage change AV at the gate
causes a change AQ in the charge
at the edge of the depletion layer.
This is below rather than at the
silicon surface and yield a higher
value for the term tox in the
capacitance expression C=cA/tox.
The capacitance therefore
decreases.

Vgs>>Vt for p-type and Vg<<Vt for
n-type substrate
Now |s is highly positive and an
inversion layer is created. This is thin
compared to the oxide thickness.
At low frequencies (100kHz) the
capacitance will again be equal to the
oxide capacitance Cox.
However, the inversion layer for the p-
type substrate consists of electrons
which are supplied and absorbed by
the substrate. This relies on the
thermal generation and recombination
of electrons.
For a constant temperature the speed
of the generation/recombination
process is limited. This accounts for
low capacitance for higher frequencies
(>1MHz). At these high frequencies
the capacitance Ct wil be about equal
to the depletion layer capacitance.
PHYSICAL AND
GEOMETRICAL EFFECTS ON
MOS TRANSISTORS
Physical And Geometrical Effects
On Mos Transistors
SUBMICRON CONSIDERATIONS
VARIATIONS IN I-V CHARACTERISTICS
MOBILITY VARIATION
THRESHOLD VOLTAGE VARIATION
TUNNELING
CHANNEL LENGTH MODULATION
STATIC DRAIN FEEDBACK
SMALL CHANNEL EFFECTS
PUNCH THROUGH
HOT CARRIER EFFECT
LATCH UP
Sub-micron Considerations
When dimensions of MOS device go below 1 then its
behaviour deviates substantially than actual MOS
operation that has been discussed so far.

For sub-micron range the channel length becomes
comparable to other device parameters such as depth of
drain and source junctions, and width of their depletion
regions.

Such devices are called short channel transistors &
represents the deviation form ideal model.

The I-V characteristics of short channel device deviate
considerably from the ideal equations.
I
D
= |{( V
GS
-V
T
)V
DS
(V
DS
2
)/2} -----Linear region
I
D
= (k
n
/2) W/L(V
GS
-V
T
)
2
(1+ V
DS
) ----Saturation region
The most important reasons for this difference are the Velocity
saturation and mobility degradation.
Velocity saturation : Carrier velocity is given as;
u
n
=
n
E
x
=
n
*dv/dx
This states that carrier velocity is proportional to electric field &
is independent of value of that field, i.e it is constant.
Variation in I-V characteristics
But when the electric field along the channel reaches a critical
value E
max
, velocity of carriers tend to saturate( i.e carriers
reach their maximum limited velocity ).
Current under the velocity saturated condition is
I
DSAT
= u
SAT
* C
ox
* W (V
GS
- V
DSAT
- V
T
)
Thus the saturation current linearly depends on the gate-
source voltage.
Also, I
D
is independent of L in velocity saturated devices.
Reduction in the channel length causes reduction in the
electron mobility even at normal electric field levels. This is
called mobility degradation
Variation in I-V characteristics
Mobility Variation
The mobility M describes the ease with which carriers drift in
the substrate material

It is defined as ratio of average carrier drift velocity V to the
Electric field E.


Mobility can vary in number of ways viz :

According to the type of charge carrier. [ WHY ??]

Increase in doping concentration decreases mobility.

Increase in temperature decreases mobility.
As device dimensions are reduced threshold voltage becomes
function of L,W and V
DS

The threshold voltage is not constant with respect to the
voltage difference between the substrate and the source of
the MOS transistor. This is known as substrate bias effect
or body- effect .
Threshold Voltage Variation
Tunnelling
The gate is separated from the substrate by an oxide of
thickness t
ox
, Generally the gate current in a MOS
Transistor is zero
When the gate oxide is very thin, a current can flow from
gate to source/drain
This happens due to electron tunnelling through the gate
oxide
This gate-current is proportional to the area of the gate.
This effect puts a limit on the minimum thickness of the
gate oxide layer, as processes are scaled
Channel Length Modulation
In the saturation region, the ideal characteristics of a MOS
transistor shows a constant current region, i.e.drain current
I
DS
remains constant, with increase in V
DS.
This characteristics assumes that carrier mobility is
constant.It does not take into account the variation in
channel length due to change in V
DS
.
However, in saturation, as V
DS
increases, channel- length L
decreases by a very small amount such that L
eff
= L - D
L
This decrease in L, increases the [W/ L] ratio, and hence
increases I
DS
due to increase in .
For long channel lengths, influence of channel variation is
of little consequence, but as devices are scaled down this

variation has be taken into account.
Channel Length Modulation
+
+
+ + +
+
+
+
+
+
+
+
+
+
+
+
+
+
Vgs>VT>0
S
G
n+ n+
B
P-
+ + + + + + + +
Vds>Vgs-VT
A L
L
L-A L
Idssat=[W/(L-AL)].| /2.(Vgs-Vt)**2
The voltage (Vds-Vdssat) across
this pinchoff region modulates AL
AL=o . (Vds-Vdssat)**1/2
o=(2c0.crsi/q.N)**1/2
o = channel shortening factor
The influence of this effect
will be lower for devices with
substrate with high substrate
dope level N.
Channel Length Modulation
Ids
Vds
Vgs=5V
Vgs=4V
Vgs=3V
oIds/oVds
-VE
Early Voltage :
VE=Ids/(oIds/oVds)
=([1/(L-AL)].[oAL/oVds])**-1
Ideally the input resistance
of the MOS transistor
operating in saturation
region is infinite. But it is in
fact finite and largely
determined by Early voltage.
Empirically the Early voltage has following properties :
It increases with higher substrate doping level
It is proportional to L-AL
It is characteristic for each process
It typically lies between 15V and 50V
Static Drain Feedback
(Drain induced barrier lowering)
The depletion area below gate is influenced by the channel
potential, which varies from source to drain. The depletion
charge therefore is largely determined by Vds.
The depth of drain depletion region is directly proportional to the
drain potential. A deeper depletion region contains more
minority carriers. These carriers reduce the barrier which a
gate potential must surmount when creating an inversion
later. An increase in drain potential therefore results in a
reduction of the threshold voltage.
AVT=- Vds
The effect of this static drain feedback is considerable in short
channel transistors which operate to the threshold voltage.
Channel length modulation and static drain feedback cause the
drain current to vary with Vds in the saturation region.
Both effects reduce transistors output impedance.
Small Channel Effects
The electrical behavior of a MOS transistor is primarily
determined by its gain factor |, its threshold voltage Vt
and its body factor K.
The values of these parameters are largely dependent
on the width W and length L of a transistor.
The influence of these dependence increases as
transistor dimension decrease.

SHORT CHANNEL EFFECTS
NARROW CHANNEL EFFECTS
MODELLING OF SMALL CHANNEL EFFECTS
Short Channel Effect
n+ n+
p-
Vgs
Vds
Vs
Even in the absence of the gate
voltage the regions under the
gate in the vicinity of the source
and drain are inherently depleted
of majority carriers, I.e. holes
and electrons in nMOS and pMOS
transistors, resp.
In a short channel transistor the
distance between these depletion
regions is small. The creation of
the complete depletion area
under the gate therefore requires
the small gate voltage i.e.
threshold voltage is reduced.
This effect can be reduced by shallow source and drain diffusions. However the
associated smaller diffusion edge radii cause a higher electric field near the drain
edge of the channel when Vds>Vgs>Vt. One way to overcome this problem is to
reduce the supply voltage.
Shallow Source Drain diffusion also increases the resistance of these areas. This
in turn increases the need to use silicides.
n+ n+
Narrow Channel Effect
Channel Stop
Implant
p-substrate
LOCOS field
oxide
Depletion
Layer
p p
Birds
beak
The Birds beak of the LOCOS
oxide produces a depletion area
along the channel sides of the
MOS transistor which is larger
than in the ideal situation.
Relative magnitude of this
increase becomes more significant
as channel widths decrease.
The gate voltage is then required to be increased in order to sustain
the charge in the relatively larger depletion area of a narrow channel
transistor.
Consequently the threshold voltage of the narrow channel transistor
is higher than for the wide channel transistor.
Modeling of small channel effects
Short Channel Effects tend to lower the threshold
voltage while narrow channel effect increase it.
Therefore these effects partly, if not completely,
compensate each other in a transistor with a both short
and narrow channel. For modeling purpose both effects
can simply be added.
The influence of the transistors dimensions on its body
factor K and on the mobility of its career can simply be
modeled in a similar manner.
A short channel results in a lower Vt, a lower and a lower
K-factor.
A narrower channel results in a higher Vt, a lower and a
higher K-factor.
Punch-through
Vg<Vt
Vs
Vd
Vb
n- n-
p-substrate
Drain Source depletion regions
merge when large reverse bias
voltage applied to the drain-
substrate junction.
Likely to occur with the transistors
with small channel lengths.
Many electrons start flowing from
source to drain even though Vgs<Vt.
Vpt=[q/2c0cr].N.L**2
N=substrate dope
L=channel length
The effect can be reduced during processing by increasing the dope level of the
substrate with a so called anti-punch-through (APT) implantation.
The associated increase in the threshold voltage can be compensated by reducing
the oxide thickness.
Hot Carrier Effects
ELECTRIC FIELD IN MOS TRNSISTORS
IMPACT IONIZATION
HOT CARRIER DECRADATION
REDUCING MAXIMUM ELECTRIC FIELD IN MOS
Electric Field in MOS transistors
gate
d
s
Ex
V
X[m]
Potential distribution in a saturated n-mos
Horizontal electric field Ex=dV/dx as a
function of x
The bulk of the voltage drop
occurs in the transistor pinch off
region near the drain junction.
This causes a sharp peak in the
horizontal electric field.
Maximum electric field (Emx) is
slightly in the drain region.
Emx depends on two groups of
parameters:
Bias voltages on the transistor
terminals.
Geometrical parameters of the
transistor.
Horizontal Electric Field Effect
Impact ionization and hot career degradation effect
occurs in a MOS transistor when significant number of
mobile charge carriers in the channel becomes
sufficiently energetic.
This happens when the horizontal electric field in the
transistor becomes larger than 2 x 105 V/cm.
Impact ionization increases the drain current and
produces a substrate current.
Hot career degradation causes a permanent change in
transistor I-V characteristic.
For same operating voltage the above effects are more
significant in the n-channel transistors than p-channel.
Impact Ionization
A conduction electron may collide with a silicon atom at a
lattice point in an nMOS transistor channel.
If such a collision involves a high energy electron then it can
cause the transition of an electron from the valance band to
the conduction band. This produces an extra conduction
electron and a hole. Both electrons flow to the drain and the
hole drifts to the substrate. This gives rise to an increase in the
drain source current Ids and to a substrate current Ib.

0
1
2
3
4
5
6
-Ib (A)
Vgs (V)
Vds=6V
5.5V
5V
Substrate Current Ib as
a function of Vgs for
different values of Vds
Impact Ionization
1
10V
Vgs
-Ib/Ids
10-5
10-4
10-3
10-2
10-1
-Ib, Ids
10-9
10-8
10-7
10-6
10-5
10-3
10-2
10-1
-Ib
Ids
At Vds=6V
The ratio Ib/Ids increases
for decreasing Vgs. This
value saturates when Vgs
decreases to the transistor
threshold voltage.
Increasing Vgs results in a
higher Ids and a more even
distribution of the electric
field over the length of the
channel. This reduces Emx
value.
The degree in which impact
ionization occurs and the
magnitude of Ib are directly
proportional to the square of
Emx. The reduction in Emx
therefore causes a reduction
in Ib/Ids.
Hot-carrier Degradation
Impact ionization generates high-energy
electrons and holes. These carriers can
scatter towards the Si-SiO2 interface
and enter the SiO2 if they have sufficient
energy. The required energy is at least
3.2eV for electrons and 3.8eV for holes.
The number of carriers that satisfy these
conditions is very small.
The carriers may become trapped in the
SiO2, giving rise to oxide charge. The
sign and magnitude of the resulting
extra space charge are dependent on the
bias condition of the transistor.
The degradation of transistor current
voltage characteristics which is caused
by this injection of both types of carriers
into SiO2 is called hot carrier
degradation.
0
1 2 3
10
20
30
40
Vgs(V)
Ids(A)
AVt
Vds=100mV
L=1.6m
Before
After
Hot-carrier Degradation
The change in the I-V characteristic is due to an increase in the
transistors threshold voltage and a decrease in its gain factor |.
It can be analyzed by measuring the gate voltages for a certain
current. The difference between these is called the threshold voltage
shift AVt.
AVt = A exp[B.t]
A = is determined by value of the maximum electric field in the transistor.
It also depends on the exact position of this maximum w.r.t. gate
oxide and drain junction.
B = 0.6 to 0.1 for nMOS transistor with a conventional arsenic source and
drain diffusion.
t = time
The maximum applicable change in Vt depends on the circuit application.
For general application it is set to 100mV. The time required for this
change to occur under given electrical stress condition is defined as
transistor life time, Tlf.
Methods for preventing Hot carrier degradation include the graded drain
and lightly doped drain.
Graded Drain Structure
(Reducing Maximum Electric Field)
The junction between the drain and
the substrate is made much
more gradual simply by
implanting phosphorous with
the relatively low concentration
in the highly concentrated n+
area.
The phosphorous has much higher
diffusion coefficient than arsenic
in this area and therefore
diffuses much further. This
results in a donor profile with a
low gradient.
The graded drain reduces the
maximum electric field by about
30%. This implies that the
operating voltage can be
increased by 50% for the given
transistor dimension.
Impurity
concentration
gate
drain
x
As
P
Phosphorous (P) implanted with Arsenic (As)
Lightly Doped Drain Structure
(Reducing Maximum Electric Field)
A polysilicon gate upon a gate oxide is
taken.
Phosphorous with a concentration
which varies from 1 x 1013 to 4 x 1013
atoms per cm3 is subsequently
implanted.
This is followed by an anisotropic etch
which leaves the oxide spacers on
both sides of the gate.
A subsequent highly concentrated
implantation of arsenic and a drive-in
diffusion produce the resulting n- and
n+ areas.
The magnitude of the transistors
horizontal electric field as a function
of x has its maximum value of 50% of
that obtained in a comparable
transistor with conventional arsenic
drain and source areas.
poly-gate
poly-gate
poly-gate
poly-gate
As As
As
P
P
P P
As
Ex
x
spacer
n-
n+
Two factors account for this significant
reduction.

The first is the relatively long region with
a low donor concentration. A depletion
area will form much sooner in this area
than in the n+ area. A large proportion of
the drain source voltage drop is distributed
over this area.
The second factor is the extra separation
between the gate and the n+drain area.

The LDD transistor is very difficult to
create and has the added disadvantage of
possible increased series resistance in the
source and drain due to n- areas.

LATCH-UP In CMOS Circuits
Latch-up is condition in which parasitic components gives
rise to establishment of low-resistance conducting path
between V
DD
& V
SS

This results in chip self-destruction or system failure.

Latch-up may be induced by the glitches on the supply
rails or by incident radiation.
Physical Origin Of Latch-up
Physical Origin Of Latch-up
V
SS
Latch-up Mechanism
R
substrate
R
well
Q
2
Q
1
If sufficient current is drawn from NPN
emitter then NPN ( Q
2
)turns on when
V
BE
~ 0.7V.
When NPN turns on, note that emitter
current increases exponentially with V
BE
Current flowing through the parasitic n-well
resistors will eventually turn on the parasitic
PNP
As PNP turns on, the NPN base current
increases and voltage drop across R
substrate

also increases, further increasing the NPN
emitter current (Q2 turns on harder), which
further increases the PNP base current,
which again further increases NPN base
current.
Remedies for the latch-up problem
One way is to keep the p-substrate tied very closely
(i.e.close proximity) to GND (most negative supply) to
reduce substrate resistance (RS1 &RS2), and the n-well
tied very closely to VDD to reduce RW1 & RW2.
Each well must have a substrate contact of appropriate
type (n-type for n-well).
Place substrate contacts as close as possible to the
source connection of transistors connected to the supply
rails.
Place a substrate contact for every 5- 10 transistors
Lay out n and p- transistors with packing of n- devices
towards Gnd and p- devices towards V
DD
FABRICATION PROCESS
Fabrication of MOS Transistor
The MOS fabrication process consists of

Photolithography
Etching
Oxidation
Deposition
Implantation
Diffusion

Then we will see the fabrication of the CMOS transistor
Photolithography
The integration of circuit requires translation of its
specifications to a description of layers necessary for IC
fabrication : represented in LAYOUT.
This layout is subjected to functional, electrical and
design-rule checks.
Layout is stored in computer file, converted to series of
commands that control an electron-beam pattern
generator (EBPG) which creates an of each mask on a
photographic plate called RETICLE.
A step-and-repeat camera is used to project an array of
image of reticle on to the final MASTER MASK. This mask
is normally produced in a thin chrome film on a glass
plate.
These working emulsion masks are used during the
photolithographic processing steps.
Photolithographic Procedures
Light source
Optical System
Mask
Photo
Lacquer
Silicon
wafer
1. One-to-one contact printing :- the
emulsion mask is brought in contact with
wafers during exposure. The resulting
wear limited the number times the mask
could be exposed.
2. Proximity printing :- mask and wafers
are separated by 5 to 10 micron during
exposure.
3. Wafer scan method :- achieve sharp
overall image by employing optical
system which can move w.r.t. the mask
and wafer.
4. Step-and-repeat projection :- employs
a stepper to move the wafer w.r.t. the
optical system and mask.
1
2 3
4
Light source
Optical
system
Optical
system
1. One-to-one contact printing :-
2. Proximity printing :-
3. Wafer scan method :-
4. Step-and-repeat projection :-
Pattern Transfer From
Mask To Wafer
WAFER
SiO2
Si3N4
Photo resist layer
mask
exposed
Wafer + Oxide (or Nitride)
Coverage with photo lacquer Masking + exposure Exposed Photo resist Development of the photo resist Etching of the nitride Removal of the photo resist layer
Etching
There are several etching techniques:-
Wet-etching: wafer is immersed in a chemical etching
liquid. The process is isotropic - etching rate is same in
all directions.
Dry-etching: both physical and chemical processes are
used. The process is anisotropic - etching is limited to
one direction due to the perpendicular trajectory of the
employed ions at the wafer surface.
Plasma-etching: wafers are immersed in a gaseous
plasma containing chlorine and fluorine ions that etch
SiO2.
Sputter-etching: wafer is bombarded with the by gas
ions such as Argon(Ar) which physically dislodge atoms
at the wafer surface.
Oxidation
A thermal oxide is used for the isolation of the transistor
areas in a MOS IC.
This thick oxide is created by exposing the monocrystalline
silicon substrate to pure oxygen or water vapour at a
high temperature of 900 to 1200 deg. The oxygen and
water vapour molecules can easily diffuse through the
resulting silicon-dioxide.
Si + O2 -> SiO2
Si + 2H2O -> SiO2 + 2H2
The LOCOS (local oxidation of silicon) process is an
oxidation technique has a universal acceptance. Silicon
is consumed at the water surface in this method. The
resulting silicon-dioxide layer extends about 46% below
and 54% above the original wafer surface.
Deposition
The deposition is of thin layer of dielectric material,
polysilicon and metal. Most commonly used dielectrics
are silicon-dioxide and silicon-nitride.
Deposition occurs via a chemical process called Chemical
Vapour Deposition (CVD).
Si(OC2H5)4 -> SiO2 + by-products
3SiCl2H2 + 4NH3 -> Si3N4 + 6HCl + 6H2
The following reaction takes place during polysilicon
deposition
SiH4 -> Si + 2H2
Metal layers are deposited by means of both physical and
chemical methods. The physical methods are
evaporation and sputtering.
In sputtering, an aluminium target is bombarded with
argon ions and a flux of aluminium flows from target to
wafer surface.
Implantation
The ion implantation(doping in MOS process) takes place
in an ion implanter which comprises a vaccum chamber
and an ion source which can emit phosphorous arsenic
or boron ions.
Silicon wafers are placed in a vacuum chamber and the
ions are accelerated into the silicon under the influence
of electric and magnetic field. The penetration depth
depends on the ion energy.
Ion implantation is characterized by the following
parameters :
the type of ions
the accelerating voltage
the current strength
the implementation duration
The disadvantage is about $3 million...
Diffusion
Diffusion is often two step process -
The first step is called predeposition and comprises the
deposition of a high concentration of the required
impurity. The impurity penetrates some tengths of a
micron into a silicon at a temperature of 800 to 1200
deg. Silicon atoms in the lattice are then substituted by
impurity atoms.
The second step is drive-in diffusion. This high temperature
step decreases the surface impurity concentration and
forces the impurities to penetrate deeper in to the
wafer.
Fabrication of CMOS Devices
P-well and n-well

Technologies used for CMOS fabrications include

N-well process
P-well process
Twin-tub process
Silicon on insulator.

P-Wells and N-Wells
A p- transistor is built on an n- substrate and an n- transistor
is built on a p-substrate
P-well N-well
P substrate
contact
p
+
N substrate
contact
n
+
OUT
IN
G G
D S
n
+
n
+
p
+
p
+
In order to have both types of transistors on the same
substrate, the substrate is divided into well regions (Shaded
region in the standard cells)
Two types of wells are available - n- well and p- well
In a p- substrate, an n- well is used to create a local region of n
type Substrate, wherein the designer can create p- transistors
In a n- substrate, a p- well creates a local p- type substrate
region, to accommodate the n- transistors.
Hence, every p- device is surrounded by an n- well, that must
be connected to V
DD
via a V
DD
substrate contact.
Similarly, n- devices are surrounded by p- well connected to
GND using a GND substrate contact.
P-Wells and N-Wells
P-well CMOS Process
nMOS transistors are formed in a diffused p-well
pMOS and the p-well are formed in a n- substrate. This
requires the p-well doping concentration much higher
than that of the substrate.
n-
p
p-well
n+ n+
p+ p+
pMOST nMOST
P-well CMOS Process
P-impurity level at the bottom
boundary of the p-well is exactly
equal to the n- substrate doping
concentration.
The impurity concentration
where the n-channel transistors
are formed at p-well surface is
about 10 times larger than the p-
well bottom.
The performance of the nMOS
transistor affected by lower
mobility of holes, relatively large
source/drain capacitance and a
large body-effect.
Development and application of
pure p-well CMOS process is
stagnated totally.

SUBSTRATE
n-dope
WELL
p-dope
n+
n+
p-well
n
-
s
u
b
s
t
r
a
t
e

z
z
Typical fabrication processes for n-well are similar to
that of p-well process except that n-well is implanted
rather than p-well.
Nwell CMOS circuits are superior to P-well because of
lower substrate bias effects on transistor threshold
voltage & inherently low parasitic capacitance associated
with source & drain regions and also lower mobility of
holes ( p ~ n/3).
N-Well CMOS Process
n-well
pMOST nMOST
p -
n+ n+
p+ p+
n
Twin-tub CMOS process
One type of transistor is always affected by a low
performance due to the necessarily high dope of the
well in both the previous methods.
An alternative process implements the nMOS and pMOS
transistors in their own respective wells.
The p-well and n-well are fabricated in a very lightly
doped epitaxial(epi) layer on the top of the p+ or n+
substrate.
pMOST nMOST
p well
n+ n+
p+ p+
n well
epi-layer
p+ or n+ type substrate
Twin-tub CMOS process
The high dope of the n+ or p+ substrate is used to
prevent the latch-up problem.
Each well can be optimized to yield the highest
performance for both type of transistors. This can be
done by minimizing source/drain junction
capacitance and body effect.
Both wells are each others complement and can
formed using a single mask.
Better scaling properties which facilitate rapid
transfer of a design from one process generation to
another.
Silicon-on-insulator CMOS
Above CMOS processes require rather deep n-well
and/or p-well diffusion to achieve low threshold voltage
(~ 1V). The resulting lateral diffusions necessitate
relatively large spacing between p and n type
transistors.
The resulting increase in IC area can be avoided. This
gives complete isolation of nMOS and pMOS transistors
removing the possibility of latch up.
n+ n+ n-
p+ p+ p-
nMOST pMOST
Isolating substrate
Silicon-on-insulator CMOS process
Both nMOS and pMOS transistors requires no
overcompensating impurity dopes. So small body effect
and source/drain capacitance.
No bottom junctions for n+ and p+ regions gives less
parasitic capacitance making SoI CMOS process suitable
for fast circuits.
Sapphire is employed as the insulating substrate in SoI-
CMOS process though it is more expensive than silicon.
The SIMOX (separation by implantation of oxygen)
process provides a cheap alternative for Silicon-on-
sapphire.
CMOS CIRCUITS
CMOS Circuits
INVERTERS
TRANSISTORAS A SWITCH
COMPLEMENTARY LOGIC GATES
TRANSMISSION GATES
LOGIC DESIGN USING TRANSMISSION GATES
POWER DISSIPATION
Inverter
Symbol:
0 1
1 0
Out In
Truth table for inverter
in out
The logic equation for the
given symbol is
out = in
Static Load Inverters
Static load inverter are Rationed logic gates where logic levels
are determined by relative dimensions of composing transistors.
Transfer function of inverter varies with load.
When I = 1, inverter dissipates
static power
Switching point of inverter
depends on ratio of R to R
ON
(on
resistance of NMOS device.)
R
Ron
Vcc
0
5
0
1
Problems
On chip resistors are large
Static power consumption
VOL = Vcc * Ron/(Ron+R) = 0
Large tpLH
Active-resistive Load
Load device is always on, looks like a load resistor.
Dissipates static power when I = 1, V
GS
= 0V always
V
OH
= 5V; VOL nearly 0V, depending on ratio of R
ON
_dep
to R
ON
_enh.
Depletion-mode devices were used before it was
economical to put both p-type and n-type devices on
the same die.


Problems with this

Extra process step
Static power consumption
V
OL
= 0
Large tpLH


The CMOS Inverter
# No static power
consumption (almost)
# VOH = VDD; VOL = 0
# tpLH = tpLH If properly
designed
# Low Impedance
connection to ground and
VDD
- More fab. Stages
- Lower hole mobility


The CMOS Inverter
0 1
Vdd
Gnd
Complementary i.e. output
have always a low impedance
connection to GND or VDD
i/p nmos pmos Vout o/p
0
1
ON
OFF
OFF Vdd
Gnd
1
0 ON
The CMOS Inverter
Rin=infinite ,Rout=0
Noise Margin = VDD/2,
Gain = infinite
NML = VIL - VOL = 2 - 0 = 2V
NMH = VOH - VIH = 5 - 3 = 2V
ACTUAL CHARACTERISTICS
V
IH
= 3
V
IL
= 2
Noise Margin
V
OH(MIN)
V
IH(MIN)

V
OL(MAX)
V
IL(MAX)
Output characteristics
Input characteristics
Logic High
Output range
Logic High
input range

Logic low
input range
Logic low
output range
Determines the allowable variation in input voltage of gate so
that output is not affected.
Is specified in terms of two parameters
Low noise margin - NM
L
= V
IL(MAX)
- V
OL(MAX)
High noise margin - NM
H
= V
OH(MIN)
-

V
IH(MIN)

Inverter Load Characteristics
Vinp
Vinn
Vds(Vdd - Vdsp)
Taking the absolute value of the p device , Vds , and
superimposing yields the following curve.
The input/output transfer curve may be determined by
the points of common Vgs intersection
Characteristics
A
B
C
D
E
Non-saturated (linear-region)
since V
SD[p]
< V
SG[p]
- |V
T[p]
|

Saturated as (V
DS[n]
= V
OUT
) >
V
DD
/2 &
(V
GS[n]
= V
in
) < V
DD
/2
V
T[n]
< V
in
<V
DD
/2

B

V
OUT
= V
DD
as V
DS[P]
= 0
As V
DS[P]
= V
OUT
V
DD
OUTPUT
Non-saturated (linear)
since V
SD[p]
< V
SG[p]
- |V
T[p]
|
P-DEVICE

Cut-off since V
in
< V
T[n]
N-DEVICE
0 < V
in
< V
T[n]
CONDITION
A REGION
Characteristics
V
OUT
= V
SS
Cut-off

Non-saturated
V
in
>V
DD
-||V
T[p]
|
E
Saturated

Non-saturated.

V
DD
/2 < V
in
< V
DD
-
V
T[p]
|

D
V
OUT
= f(V
in
)
V
in
- V
T[n]
< V
OUT
< V
in
+
V
T[p]
|

OUTPUT
Saturated
V
SD[p]
> V
SG[p]
- |V
T[p]
|
V
OUT
< V
in
+ |V
T[p]
|
P-DEVICE

Saturated since
V
DS[n]
> V
GS[n]
V
T[n]
&
V
OUT
> V
in
V
T[n]
N-DEVICE
V
in
= V
DD
/ 2
CONDITION
C
REGION
Characteristics
The ratio n (gain of NMOS) / p (gain of PMOS) determines the
switching point of the CMOS inverter.
|
n
/|
p
RATIO
The switching speed of the CMOS gate is limited by time taken
to charge and discharge the load capacitance
Switching characteristics of CMOS
inverter
Calculation of rise & fall time
T
fall
= R
fall
* C
LOAD

Rise Time : The time required for
the output to rise from 10% to
90% of its steady state value and
is given as
Fall Time : The time required for
output to fall from 90% to 10%
of its steady state value.
T
rise
= R
rise
* C
LOAD
Thus to achieve high speed circuits, the load capacitance should
be minimized.
Lowering the supply voltage on a circuit will reduce the speed
of the gates in that circuit.
The delay of transistor decreases as the width of transistor is
increased or length is decreased..
For equally sized n and p transistors
n
= 2
p
Hence T
fall =
T
rise
/2
To equalize the rise and fall times of an inverter I.e T
rise =
T
fall

must have
n
=
p
This means, that channel width for the p-device must be
increased to twice of the n-device. Hence if Lin = Lp then W
p
=
2*W
n
Thus
n
=
p
provides equal current source and sink
capabilities.
Thus equal charge and discharge times
Calculation of rise & fall time
It defines the response of gate for change in input.

Is measured between 50% transition points of input and
output waveforms.
Gate displays different response times for rising and falling
waveforms.
T
plh

Defines response time of gate for low to high output
transition
T
phl
Defines response time of gate for high to low output
transition
The overall propagation delay is average of these two
T
D
= (T
phl
+ T
plh
)/2


Delay Time
CMOS Inverter - Summary
CMOS inverter uses actively driven P-channel transistor is
used as pull-up drive.
It allows maximum logic voltage level swing.
Eliminates the static power dissipation as no current flows
fromV
DD
to ground in steady state.
No of transistors is 2N.
It is ratio-less logic I.e. Output logic levels are independent
of ratio of pull-up and pull-down transistor sizes.
Resistance of N-channel transistor is R
n
L
n
/W
n
* K
n


Resistance of P-channel transistor is R
p
L
p
/W
p
* K
p
But
n
= 2.5
p
, hence
n
= 2.5
p
.
Hence in order to achieve symmetrical operation(equal rise &
all time ) we must have (L
n
* W
p
)/ (L
p
* W
n
)= k
n
/k
p
=2.5.
Thus with this sizing N & P transistors have equal I-V
characteristics.
P-MOS source is tied to V
DD
, used
to pull signals up.
Control output
G= 1 D=0
G= 0 D=Z
Control Output
G= 0 D= 1
G= 1 D= Z
MOS Transistors As Switch
N-MOS source is tied to ground,
used to pull signals down
Why N-MOS Transistor Produces
Weak 1?
S
G
D
Vdd
Vs Vd
0 0
1 1
2 2
3 3
4 4
4.3 4.3
5 4.3
5 4 3 2
1
0.7
NMOS will conduct if V
GS
>= V
T

If V
T
= 0.7V , V
G
= 5V and V
S
= 0V -> 5V then C is charged towards
V
DD
- V
T
(5 - 0.7 = 4.3) for V
GS
>= V
T

Why PMOS Transistor produces
weak 0 ?
PMOS will conduct if V
GS
< V
T

If V
T
= - 0.7V and V
GS
= 0V > 5V
then C is charged towards V
DD
since
| V
GS
| > | V
T
| (5V >0.7V)
When source goes from 5V to 0V
PMOS will stop conducting when
| V
GS
| < | - 0.7 V | and V
D
will
be left at 0.7V, thus produces
weak 0.
S
D
G
Vdd
5 4 3 2 1 0.7
MOS Transistors as Switch
SWITCH G
INPUT (SOURCE) OUTPUT(DRAIN)



X

Z


V
DD
STRONG 0
V
SS
WEAK 1




X

Z


V
DD
STRONG 1
V
SS
WEAK 0
I/P O/P
G=1
G=0
G=0
G=0
Series Connection Of Switches
If N switches are placed in
series Y=0 if A & B are 1.

Thus yields an NAND
function.
Y = /(A * B)

If P switches are placed in
series Y=1 if A & B are 0.

Thus yields an NOR
function.
Y = /A . /B
Parallel Connection Of Switches
When P switches are placed in
parallel Y=1 if either A or B is 0.

Thus yields an NAND function.
Y = /A +/B
When N switches are placed in
parallel Y=0 if either A or B is 1.

Thus yields an NOR function.
Y =/(A + B)
Complementary Logic Gate Design
A CMOS gate is combination of two networks as shown
below
PUN
Y= /F
V
SS
V
DD
I/P
I/P
Pull Up Network (PUN) consists of
P-MOS transistors. Thus implements
the logic function F.
PDN
Pull Down Network (PDN) consists of
N-MOS transistors. Thus implements
the logic function /F.
This complementary combination of F and /F is very necessary.
WHY???
NAND Gate Design
A
B
Y
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A
B
0
0
1
1
1 1
1 0
/A + /B
A . B
NAND Circuit
B
Vdd
Y
A
NOR GATE DESIGN
A
B
Y
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
B
0
0
1
1
1 0
0 0
/A . /B
A + B
NOR circuit
AND Gate Design
Poorly Designed AND gate !!!
WHY ?
AND Gate Design
Instead use this !
Designing compound gates
To implement the function F = /((A+B+C)*D)
For PUN
F = /((A+B+C)*D) = (/A . /B ./C)+(/D)
For PDN
/F = /[/((A+B+C)*D)] = (A+B+C).(D)
Transmission gate
By combining an N-switch and P-Switch in parallel perfect
transmission of both 1s and 0s is achieved.
When I=0 both N & P
devices are OFF
V
IN
V
OUT
X Z
When I=1 both N & P
devices are ON
V
IN
V
OUT
V
DD
V
DD

V
SS
V
SS

Transmission gate
Schematic icons for transmission gate
Most widely used
Transmission Gate Characteristics
2:1 multiplexer
Y = SA +/SB
This implementation will need total 6 Transistors
4 Transistors for two pass gates
2 Transistors for inversion of S
Thus transmission gate logic uses less gates than the
design with normal gates.
Transmission Gate Characteristics
But it has got Demerits !

It is non restoring logic output levels may or may not settle
at V
DD
or V
SS
(as it passes logic level at input to output )
where as CMOS gates provides restoring logic.


It has no drive capability, drive comes from original A, B
inputs What about CMOS gate?

Transmission gates provide no isolation between input and
output.

Then Why & Where Transmission gates are used ?
2:1 MUX Using
Transmission gate
Y = SA + /SB
A B S Y
X 0 0 0(B)
X 1 0 1(B)
0 X 1 0(A)
1 X 1 1(A)
When S= 1, S1 is ON and S2 is OFF. Hence input A is
connected to the output.
When S= 0, S1 is OFF and S2 is ON. Hence input B is
connected to the output.

EN I O
0 X Z
1 0 1
1 1 0
Tristate Inverter
Total 6 transistors !
EN Q
1 D
0 Q
old
D LATCH Positive level sensitive
How will the
circuit function ?
When EN = 1, switch S1 is closed and S2 is open.
Hence Output-Q follows Input D
D-LATCH WITH EN = 1
When EN = 0, switch S1 is open and S2 is closed.
Output-Q is isolated from Input D.
Output retains the value of D at the falling edge of EN
WHY ???
D-LATCH WITH EN = 0
D-latch with asynchronous reset
How to implement asynchronous clear?
Edge Triggered D - Register
By combining two latches in master-slave arrangement,
edge triggered register can be constructed.
For positive edge triggered first latch(master) is negative
level- sensitive latch
Rising Edge Triggered D register
How will the the circuit function ?
When CLK= 0 , S1 and S4 are closed /Q
m
follows D, and Q
is stored in the inverter loop.
D-REGISTER WITH CLK = 0
D-REGISTER WITH CLK = 1
At CLK=1,
S1 is open and S2 is closed. Hence /Q
m
LATCHES the value of D, that
existed on the rising edge of CLK.
S3 is closed and S4 is open. Hence Q gets the value of /Q
m
[ I.e. the
value of D on the rising edge of CLK].
Q is isolated from changes on D input.
In case of negative edge triggered register master is positive
level-sensitive latch.
Edge Triggered D-register
Guess The Functionality ?
Where Does Power Go In CMOS
Power dissipated in a CMOS circuit is categorised as
follows,

Static dissipation :
Due to leakage currents

Dynamic dissipation :
Due to charging and discharging of internal & load
capacitance.

Short circuit dissipation :
Due to short circuit path between V
DD
and GND during
switching

Impact of rise/fall time on short circuit current.

Static dissipation is due to,
Leakage currents in the reversed-biased diodes formed
between the substrate (or well) and source/drain regions.
Sub threshold conduction, also contributes to static
dissipation. Sub threshold leakage increases exponentially
as threshold voltage decreases.
Total static power dissipation is given as
p
static=

n
leakage current * V
DD
Where n is the number of devices in a CMOS Circuit.
As all these currents are negligible, static power dissipation
in CMOS is almost zero.
Static Dissipation
Dynamic Power Dissipation
G
G
S
S
D
D
Cl
Vdd
Charging Current
IN
OUT
During low to high transition part of energy drawn from
supply is dissipated in PMOS. During high to low transition
stored energy on capacitor is dissipated in NMOS transistor.
Dynamic power dissipation gives measure of this energy
consumption

Dynamic Power Dissipation
The average dynamic power consumption for input frequency
of F is P
dynamic
= C
L
* V
DD
2
* F
Power dissipation is independent of device parameters
This can be reduced by decreasing C
L
, V
DD
or F
Short Circuit Dissipation
It is the DC power consumed during switching.
A direct current path from V
DD
to ground exists when both N
and P transistors are conducting simultaneously during
switching.
Short circuit consumption is given by
P
sc
= I
mean
* V
DD

Thus for an inverter without load, assuming T
r
= T
f
= T
rf
P
sc
=

/12 (V
DD
2 V
T
)

3
T
rf
* F

Short- circuit power depends on W/ L ratios of the transistors
Greater the rise-fall time of the signals, larger is the power
consumed.

Short Circuit Dissipation
Input switching waveform & model for short circuit current.
I
peak
is determined by the saturation current of devices,
hence is proportional to the sizes of the transistor.
TIME
Id
Vin
Vth
Vdd-Vth
Ipeak
Impact of rise/fall times
on short-circuit currents
Power dissipation due to short circuit current is minimised by
minimizing the rise and fall time of input and output signal.
SIZING OF
TRANSISTORS
Sizing of transistors in Gate
Symmetrical drive capability of CMOS allows comparable
transition time for output voltages irrespective of direction
of transition.
Primary effect of sizes of pull-up and pull-down
transistors is on equivalent resistance of transistors in
conduction state.
To obtain symmetrical characteristics at output rise and
fall time should be same which says R
N
= R
P

Resistance of N-channel is given as R
N
o L
N
/W
N
*K
N

Resistance of P-channel is given as R
P
o L
P
/W
P
*K
P

Sizing of transistors in Gate
Sizing of the gates is always done considering the
resistance offered in the charging and the discharging
path for the current.
Points to be considered are:
p-MOS transistor offers resistance twice more than that
offered by n-MOS.
We put p-MOS always in PUN and n-MOS in PDN.
Resistance in the PUN should be equal to that in PDN.
Width of the transistor is inversely proportional to
resistance of the transistor.
R=L.K/W
So for same resistance p-MOS transistor width is twice
than that of n-MOS
Sizing of NAND gate
R
R
R/2
R/2
R R
R 1/W
R/2 2W
& R 2W
2W
2W
2W
2W
Each transistor have the size of 2W,
so NAND gate occupies space of 8W on the silicon wafer
Sizing of NOR gate
R
R
R 1/W
R W
& R/2 4W
Transistors have different sizes in PUN and PDN of W and 4W,
so NOR gate occupies space of 10W on the silicon wafer
R R
R/2
R/2
W
W
4W
4W
HENCE NAND GATE IS ALWAYS PREFERED OVER NOR GATE
Sizing Of Transistor
- The speed of a CMOS gate depends
on how fast the load capacitance
can be charged/ discharged
- Load capacitance depends on the
fan- out of the gate, and the size of
the gates connected to the output
- Increasing the size of the p-
transistors decreases the rise- time
of the gate
- Increasing the transistor sizes of
the N and P- block also increases
the input capacitance of the gate (i.
e. the input delays will increase at
the expense of the output delays)
Sizing Of Transistor
Progressive Sizing:
m 4 discharge C
L


I.e. Increase size downwards
m1>m2 > m3 >m4
C3
C2
C1
m 3 discharge C
L
+ C
3
m 2 discharge C
L
+ C
3
+ C
2
m 1 discharge C
L
+ C
3
+ C
2
+ C
1
MORE INPUT CAPACITANCE, MORE CHARGE, SO TO KEEP
DISCHARGE TIME = CHARGE TIME -> INCREASE TRANSISTOR SIZE
Sizing Of Transistor
Stage Ratio
When It is desired to drive large load capacitances such as
long buses, I/O buffers and off-chip capacitive loads.

This is achieved by using a chain of inverters where each
successive inverter is made larger than the previous one.

The ratio by which each stage is increased in size is called
stage ratio .

The signal delays encountered in driving the off chip load
directly from a minimum sized inverter is unacceptable.

The optimisation to be achieved here is to minimize the
delay between input and output while minimizing the area
and power dissipation.
Stage Ratio
?
Inverter 1 is a minimum- sized device.
Subsequent inverter device sizes increase by a factor of a
Delay of each stage is a * T
d
, where T
d
=delay of minimum
sized inverter driving an identically sized inverter
Hence total delay ( delay through the n stages ) is n * a * T
d

Cg is load of first driver which is minimum- sized device
If C
gN
is the load capacitance of the N
th
inverter then C
gN
= C
g
*
a
N
To guarantee that none of capacitances internal to the chain of
inverters exceed C
load
[ why ?? ] we must have C
g
* a
n
= C
L

here n = N +1


I.e a
n
= C
L/
C
g
Stage Ratio
Hence a = [C
L/
C
g
]
1/n

Total delay = n * [C
L/
C
g
]
1/n
* T
d

The optimum value of n is
n
opt
= ln [C
L/
C
g
]
Now optimum value of a i.e a
opt
can be calculated as;
a
n
= C
L/
C
g
a
ln [CL/ Cg]
= C
L/
C
g

Taking natural log of both sides we get a = 2.7
But the actual stage ratio is given by
a
opt
= exp[(k+a
opt
)/a
opt
]
Where k = C
drain
/C
gate
For 1 process k = 0.215, hence a
opt
= 2.93
For 2.5 process k = 3.57 which gives a
opt
= 5.32
Stage Ratio
Stage Ratio Graph
Different processes will have different stage ratios from 2 to 10.
SCALING METHODS
Scaling Methods
Scaling is method in which device geometries migrate to
lower sizes while still maintaining the same device
characteristics.
This is done by scaling the critical parameters of a device
in accordance to a given criteria.
Scaling methods include
Lateral scaling
Constant field scaling
Constant voltage scaling
Lateral Scaling
Here the only parameter that is scaled is the gate length L
This method of scaling is also called gate- shrink
It can be easily done to an existing mask design
Power dissipation increases by the factor
Input capacitance of the transistor decreases by the factor
- A dimensionless scaling factor is applied to,
All dimensions (including vertical dimensions such as tox )
are decreased by .
Device voltages are decreased by
Concentration densities are increased by
As a result,
Depletion thickness d.
Threshold voltage V
T
Drain Current I
DS
also get scaled by the same factor
Since the voltage V
DD
is scaled, the electric field in the device
remains constant
Hence, the operating characteristics of the device remain the
same even after scaling
Power dissipation decreases by
2
Constant Field Scaling
Similar to constant field scaling, except that voltage V
DD
is
kept Constant
The current I
DS
increases by the factor
Speed of the device increases by the factor
Number of transistors per unit area increases by the
factor
2
As a result, the current density increases by the factor
3

Proportionately wider metal wires are required for more
densely packed structures
Power dissipation increases by the factor
This will increase the need for cooling devices/ structures
for the IC
Power dissipation of above 1- 2 Watts require specialised
cooling fins or packaging
Constant Voltage Scaling
CMOS LAYOUT
CMOS Layout
LAYERS
STICK DIAGRAM
LAYOUT DESIGN RULES
EXAMPLES
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+)
Green
CMOS Process Layers
Stick Diagram
Before the cell can be constructed from a transistor schematic it
is necessary to develop a strategy for the cell's basic layout.

Stick Diagrams are a means for the design engineer to visualize
the cell routing and transistor placement.

Steps involved in stick diagram construction.

STEP 1 :
Identify each transistor by a unique name of its gate signal
Identify each connection to the transistor by a unique name



Figure 1:
Schematic
and Graph

Stick Diagram
Figure.2
Euler path

Stick Diagram
STEP2 :

Eulers paths : A path the traverses each node in the path, such
that each edge is visited only once.

The path is defined by the order of each transistor name.

The Euler path of the Pull up network must be the same as the
path of the Pull down network.

Euler paths are not necessarily unique.
It may be necessary to redefine the function to find a Euler
path.
F = E + (CD) + (AB) = (AB) +E + (CD)



Stick Diagram
Next step is to lay out the stick diagram :

Trace two green lines horizontally to represent the NMOS
and PMOS devices.

The gate contact to the devices are represented by vertical
strips.

Surround the NMOS device in a yellow box to represent the
surrounding Pwell material.

Stick Diagram
Figure 3: Connection
label layout
Stick Diagram
Surround the PMOS device in a green box to represent the
surrounding N-well material.

Trace a blue line horizontally, above and below the PMOS and
NMOS lines to represent the Metal 1 of V
DD
and V
SS
.

Label each Poly line with the Euler path label, in order from
left to right.

Place the connection labels upon the NMOS and PMOS
devices.

Place the VDD, VSS and all output names upon the NMOS and
PMOS devices
Stick Diagram
Figure 3: Connection
label layout
Stick Diagram
Stick Diagram
Schematic
Stick-diagram NAND Gate
Stick Diagram NOR Gate
Layout Design Rules
Design rules provide guidelines for preparing the photo masks
used in the fabrication of IC & consists of minimum-width ( line
widths ) and minimum-spacing ( interlayer ) constraints.
The main goal of layout rules gives a circuit with optimum
yield in as small an area as possible without compromising
reliability of the circuit.
Design rules specify the fundamental unit as minimum line
width.
It stands for the minimum mask dimension that can be
safely transferred to the semiconductor material. The
minimum line width is set by resolution of the patterning
process ( lithographic process )
The interaction between different layers.
Even for the same minimum dimension, design rules tend
to differ form company to company and from process to
process.
One approach to address this is to use scalable design rules.
These include
1. Lambda ( ) based rules.
2. Micron rules.
Lambda ( ) based rules : These defines all the rules as function
of single parameter called .

Scaling of the minimum dimension is accomplished simply by
changing the value of .. This results in linear of all dimensions.
When mapping the transistor schematic/layout to a particular
technology, the actual W, L will be calculated as:
W' (actual, microns ()) = W (microns)
L' (actual, microns) = L (microns)
(lambda ) is dimensionless unit called as scaling factor.
Layout Design Rules
Scaling factor allows transistor W/L values specified in
schematic to be technology independent.(feature-size
independent way of setting out mask dimensions to scale.)
Scaling factor allows transistor W/L values specified in
schematic to be technology independent.(feature-size
independent way of setting out mask dimensions to scale.)
Scaling factor lambda is foundry/silicon vendor dependent
For MOSIS foundry vendors,
1.2 technology = 0.6
0.8 technology = 0.4.
Typically the minimum gate length is set to 2 and width is
varied.
Layout Design Rules
But linear scaling is possible over a limited range of dimensions,
hence these rules are not used by industry. Normal industrial
practice is to deal with micron rules .

Micron rules expresses the design rules in absolute dimensions
and hence can exploit the features of a given process to a
maximum degree.

These are usually given as list of minimum feature sizes and
spacing for al the masks required in an given process.
Layout Design Rules
Design Rules
Examples
from AMS
0.6micron
technology
Intra-Layer Design Rules
Vias and Contacts
N Transistor Layout
Bulk
Drain
Source
Gate
Thin-Oxide
P Transistor - Layout
n
-
Bulk Source
Gate
Drain
Thin-Oxide
Parallel/Series Transistors
Large MOS Transistors
AND Gate Layout
AND Gate - Layout
Inverter Layout
Inverter Layout
4-Input NAND Gate
Pseudo NMOS NAND Gate
Logic Graph for F = (A+B)C
Layout F = (A+B)C
Logic Graph for
F = /(AB+CD)
Pass Transistor Based Multiplexer
F
Pass Transistor Based
Multiplexer

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