Counter Circuits and Applications

Group 6

Overview
Analysis of Sequential Circuits. Ripple Counters.
Design of Divide-by-N Counters. Ripple Counter ICs. Applications.
System Design Applications. Seven-Segment LED Display Decoders.

Synchronous Counters.
Synchronous Up/Down-Counter ICs. Applications.

Analysis of Sequential Circuits

Using Timing Diagrams to analyze.

Ripple Counters
J-K flip-flops are in the toggle mode. Output Q is cascaded to the next clock input.

Ripple Counters(contd)
Ideal Timing Diagram.

Ripple Counters(contd)
Ripple: the input clock trigger isnt connected to each flip-flop directly but propagate thru all the flip-flops. Non-ideal Timing Diagram:

Ripple Counters(contd)
Down counter:

Design of Divide-by-N Counters

An example of MOD-5 counter.

Design of Divide-by-N Counters (contd)

Glitch effect: NAND propagation time 15ns & Flip-flop Reseting time 30ns (For 74LS76 and 7400).

Design of Divide-by-N Counters (contd)

MOD-5 counter which counts in the sequence 6-7-8-9-10-6-7-8-9-10-,etc.

Ripple Counter ICs - 7493

7493: a divide-by-2 and a divide-by-8 MR1,MR2 can be utilized to do MOD-N.

Ripple Counter ICs 7493 (contd)

External connection as a MOD-16 counter.

Ripple Counter ICs 7493 (contd)

External connection as a MOD-12 counter.

Ripple Counter ICs 7490

7490: a divide-by-2 and a divide-by-5.
1 0 1 0 1 0

Ripple Counter ICs - 7492

7492: a divide-by-2 and a divide-by-6.
1 0 0 1 0 1

System Design Application

A 3-digit decimal counter (000 999)
When the count changes from (1001) to (0000), the 23 output line goes from HIGH to LOW and trigger the next counter.

Seven-Segment LED Display Decoders

7447: the most popular common-anode decoder. It has a lamp test (LT) input for testing all segments, and it also has ripple blanking input and output (RBI,RBO).

Synchronous Counters
Synchronous counters eliminate the propagation delay problem because all the clock inputs (cp) are tied to a common clock.

Synchronous Counters(contd)
A MOD-6 synchronous binary up-counter.

PL(Parallel Two When separate TCD Load) clock & an D inputs: HIGH) becomes place any counting LOW, binary it up is MR(Master Reset): active-HIGH Reset for U(normally 0~D 3: C pU for value and used C to onindicate for D counting ,that andthe down. drive maximum minimum the One PLclock line count count LOW. must is is resetting the Q3 outputs to zero. pD 0~D be held HIGH reached and the while count counting is about with to the recycle other. to zero(carry the maximum(borrow condition). condition). It can be used It can as be the next stage used as theof next a multistage stage of a counter. multistage counter.

Synchronous Up/DownCounter ICs

Applications of Synchronous Counter ICs

A divide-by-200 using synchronous counters.
Parallel Load Value 200

Borrow Condition