MULTIPLICATION AND DIVISION ALGORITHMS

Instructor: Prof. Ten Eyck Course: Computer Architecture (CMSC 415)

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Presented by: Manpreet Bhullar & Matt Hattersley

Binary Multiplication
147 * 85 10010011 Multiplicand * 01010101 Multiplier 10010011 00000000 10010011 00000000 10010011 00000000 10010011 00000000 011000011001111 Product

12495

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Multiply Algorithm Version 1

Multiplier0 = 1
1. Test Multiplier0

Multiplier0 = 0

1a. Add multiplicand to product & place the result in Product register

2. Shift the Mcand register left 1 bit

3. Shift the Mplier register right 1 bit

64th No: < 64 repetitions repetition?

Yes: 64 repetitions
Done
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Multiplication Hardware 1

32-bit multiplicand
64 bits

Shift_left

16-bit multiplier Shift_right 32-bit ALU 16 bits

lsb
32-bit product 32 bits Write Control

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Multiplication Hardware
Product: initialized to all 0s Control: decides when to shift the Multiplier and Multiplicand registers and when to write new values to Product register At the end, the multiplier is out of the product register and the product contains the result

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For Version 1:

Step-by-step transition in the registers during the multiplication process 1

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Thinking about new algorithm

Changes can be made: -instead of shifting multiplicand left, shift product right -adder can be shortened to length of the multiplier & multiplicand(8 bits in our example) -place multiplier in right half of the product register(multiplier will disappear as product is shifted right -add multiplicand to left half of product

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Multiply Algorithm Final Version

Product = 1
1. Test Product00

Product = 0

1a. Add multiplicand to the left half of product & place the result in the left half of Product register

2. Shift the Product register right 1 bit.

64th No: < 64 repetitions repetition?

Yes: 64 repetitions
Done
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For FinalVersion :

Step-by-step transition in the registers during the multiplication process (Final)

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Multiplication Hardware(Final)

multiplicand
16 bits

Shift_left

16-bit ALU

product 32 bits

Write Control Test Shift_right

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Multiply in MIPS
Can

multiply variable by any constant using MIPS sll and add instructions: i' = i * 10; /* assume i: $s0 */
sll $t0, $s0, 3 # i * 23 add $t1, $zero, $t0 sll $t0, $s0, 1 # i * 21 add $s0, $t1, $t0

MIPS mult

multiply instructions: mult, multu

$t0, $t1 puts 64-bit product in pair of new registers hi, lo; copy to $n by mfhi, mflo 32-bit integer result in register lo
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Multiplying Signed numbers

Main difficulty arises when signed numbers are involved. Naive approach: convert both operands to positive numbers, multiply, then calculate separately the sign of the

product and convert if necessary.

A better approach: Booths Algorithm. Booths idea: if during the scan of the multiplier, we observe a

sequence of 1s, we can replace it first by subtracting the multiplicand

(instead of adding it to the product) and later, add the multiplicand, after seeing the last 1Computer of the sequence. Architecture Project

For Example:
0110 x 0011 (6x3) This can be done by (8- 2) x3 as well, or (1000 - 0010) x 0011 (using 8 bit words) At start, product = 00000000, looking at each bit of the multiplier 0110, from right to left: 0: product unchanged: 00000000 , shift multiplicand left: 00110 1: start of a sequence: subtract multiplicand from product: 00000000 - 00110 = 11111010 , shift multiplicand left: 001100 1: middle of sequence, product unchanged: 11111010, shift multiplicand left: 0011000

0: end of sequence:
add multiplicand to product: 11111010 + 0011000 = 00010010 = 18 shift multiplicand left: 00110000
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Booths Algorithm
Scan the multiplier from right to left, observing, at each step, both the current bit and the previous bit: 1. Depending on (current, previous) bits: 00 : Middle of a string of 0s: do no arithmetic operation. 10 : Beginning of a string of 1s: subtract multiplicand.

11 : Middle of a string of 1s: do no arithmetic operation.

01 : End of a string of 1s: add multiplicand. 2. Shift multiplicand to the left.
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Integer Division
(10) 0001 1001 0000 1010 divided into 1111 1010 -1010 1011 -1010 10 101 1010 -1010 quotient (25) dividend (250)

0 remainder
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Division Algorithm 1
2a. Shift the Quotient register to the left setting the new rightmost bit to 1.

Start: Place Dividend in Remainder 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.

Remainder 0

Test Remainder

Remainder < 0

2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0.

3. Shift the Divisor register right 1 bit. n+1 repetition? No: < n+1 repetitions

Yes: n+1 repetitions (n = 8 here) Done

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Division Hardware
Shift Right

Divisor

16 bits
Quotient 16-bit ALU 8 bits Write Control

Shift Left

Remainder

16 bits

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Integer Division
ALU,

Divisor, and Remainder registers: 16 bit; Quotient register: 8 bits; 8 bit divisor starts in left of Divisor reg. and it is shifted right 1 on each step Remainder register initialized with dividend

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For Version 1:

Step-by-step transition in registors during division process1

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Division Algorithm (Final)

Start: Place Dividend in Remainder

1. Shift the Remainder register left 1 bit

2. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.

Remainder 0

Test Remainder

Remainder < 0

3a. Shift the Remainder register to the left setting the new rightmost bit to 1.

3b. Restore the original value by adding the Divisor register to the left half of Remainder register, & place the sum in the left half of Remainder register. Also shift the Remainder register to the left, setting the new rightmost bit to 0.

n repetition?

No: < n repetitions

Yes: n repetitions (n = 8 here) Done. Shift left half of Remainder right 1 bit
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Division Hardware (Final)

Divisor

8 bits
8-bit ALU Shift Right Remainder Write Control Test Shift Left

16 bits

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For Final Version:

Step-by-step transition in registers during division process (Final)

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Mult/Div Hardware

Divisor/multiplicand

8 bits
Carryout of adder 8-bit ALU

alu_control

Shift_left, shift_right Write

Top half

Control

16 bits

Result/lsb msb

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