Understand SPI format and data transfersgure the control registers Transmit and receive data Module exercise:

Configure the SPI to transmit and receive characters to/from another device in Master mode at a 1 MHz rate

Clock Generation Module (CGM)

System Integration Module (SIM)

LVI

IRQ
RESET

68HC08 CPU

COP

BREAK

Timer Interface Module (TIM)

Direct Memory Access Module (DMA)

Internal Bus (IBUS)

Serial Communications Interface (SCI)

Serial Peripheral Interface (SPI)

Random Access Memory (RAM)

Electronically Programmable ROM

Monitor ROM

Features of the SPI module include the following: Full-Duplex Operation Master and Slave Modes Separate Transmit and Receive Registers Four Master Mode Frequencies (Maximum = Bus Frequency 2) Maximum Slave Mode Frequency = Bus Frequency Separate Clock Ground for Reduced Radio Frequency (RF) Interference Serial Clock with Programmable Polarity and Phase Bus Contention Error Flag Overrun Error Flag Two Separately Enabled Interrupts with DMA or CPU Service: SPRF (SPI Receiver Full) SPTE (SPI Transmitter Empty) Programmable Wired-OR Mode I2C (Inter-Integrated Circuit) Compatibility

Three registers control and monitor SPI operations:

SPI Control Register (SPCR) SPI Status and Control Register (SPSCR) SPI Data Register (SPDR)

Master mode

Only a master SPI initiates a transmission Data is shifted out via Master Out Slave In (MOSI) line Data is shifted in via Master In Slave Out (MISO) line Transmission ends after 8 cycles of serial clock (SPSCK)
Transfer synchronized to serial clock (SPSCK) from Master Data is shifted in via the Master Out Slave In (MOSI) line Data is shifted out via the Master In Slave Out (MISO) line

Slave Mode

MASTER
MOSI
Shift Register MISO SPSCK Baud Rate Gen. SS +5v

SLAVE

Shift Register

Slave Select (SS)

SS

Master mode

Slave mode
completes

SS held high during transmission Acts as error detection input Can be general purpose output SS must remain low until transmission 0 = Enables slave 1 = Disables slave

READ: SPCR WRITE: RESET:

SPRIE

DMAS SPMSTR CPOL

CPHA

SPWOM

SPE

SPTIE

SPI Control Register (SPCR)

SPI Master (SPMSTR)

Selects master mode or slave mode operation 1 = Master mode 0 = Slave mode

SPI Enable (SPE) 1 = SPI module enabled 0 = SPI module disabled

Recommend disabling SPI before initializing or SPI Master and Slave need identical clock polarity and changing clock phase, clock polarity, or baud phase settings rate Clock Polarity (CPOL) Determines clock state when idle Clock Phase (CPHA)

1 = Begin capturing data on second clock cycle edge 0 = Begin capturing data on first clock cycle edge* When CPHA = 0, the SS must be deasserted and reasserted between each transmitted byte

SPI Control Register (SPCR)

SPI modules need identical Clock polarity and phase

CPHA

CPOL

SS SPSCK SPSCK SPSCK SPSCK MSB Bit 6 Bit 4 Bit 3 Bit 2 LSB

0 1 0 1

0 0 1 1

MOSI/MISO Capture Strobe

Bit 5

Bit 1

READ: SPSCR WRITE: RESET:

SPRF

OVRF

MODF

SPTE

0
SPR1 SPR0

SPI Status and Control Register (SPSCR)

SPI rate select bits (SPR1, SPR0)

Sets the Master SPSCK clock frequency No effect in the Slave devices Baud Rate = CGMOUT / Baud Rate Divisor

SPR1:SPR0 00 01 10 11

System Clock Divided By 2 8 32 128

Baud Rate (System Clock Freq. = 8 MHz) 4 MHz 1 MHz 250 KHz 62.5 KHz

READ: SPDR WRITE: RESET: UNAFFECTED BY RESET Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPI Data Register (SPDR)

Read/Write buffer for SPI data Write operation

Writes data to transmit data register

Read operation
Reads data in receive data register

READ: SPSCR WRITE: RESET:

SPRF

OVRF

MODF

SPTE

0 SPR1 SPR0

SPI Status and Control Register (SPSCR)

SPI Receiver Receiver Full (SPRF)

Set when a byte is shifted from shift register to the receive data register Cleared by reading SPSCR then reading SPDR

SPI Transmitter Empty (SPTE)

1 = Receive data register full 0 = Receive data register not full

Set when a byte is transferred from SPDR to the shift register Cleared by reading SPDR register

1 = Transmit data register empty 0 = Transmit data register not empty

READ:

SPCR
WRITE: RESET:

SPRIE

DMAS SPMSTR CPOL

CPHA

SPWOM

SPE

SPTIE

SPI Control Register (SPCR)

SPI Receiver Interrupt Enable Bit (SPRIE)

Interrupt generated when SPRF flag set

SPI Transmit Interrupt Enable (SPTIE))

Interrupt generated when SPTE flag set

1 = Interrupt enabled 0 = Interrupt disabled

Direct Memory Access Select (DMAS)

interrupts

Selects either DMA or CPU interrupt request SPRIE/SPTIE bits still enable or disable

SPI Initialization sequence 1) Initialize SPI clock frequency ( SPR1 and SPR0 in SPSCR ) 2) Set clock configuration ( CPOL and CPHA bits in SPSCR ) 3) Select Master/Slave operation ( SPMSTR in SPCR ) 4) Enable interrupts if desired ( SPTIE, SPRIE in SPCR ) 5) Enable the SPI system ( SPE in SPCR )

Should enable Master before Slaves

Simple Polled operation 1) Initialize the SPI 2) Select SS to Slave device (hardware dependent 3) Write byte to SPDR 4) Wait for SPI Transmitter Empty Flag (SPTE) 5) Read the SPDR 6) Release SS to Slave (hardware dependent)

Initialize a SPI to the following: Master mode 1 MHz baud rate ( 8 MHz system clock ) Clock phase = 1 and clock polarity = 0 Polled operation

Part 1:

Write a procedure to transmit the character in the Accumulator to the Slave device. Then wait for the received character and place it into the Accumulator. (The Master SS is tied to VDD and the Slave SS is tied to ground)

Part 2:

SPI Config & Transmit Exercise

Write a routine that configures the SPI as a master, non-interrupt driven and then transmits the value $55. The SPI is connected to a serial-in/parallel out 8-bit shift register. The shift register is chip-selected with the PB3 line at low voltage level. Between transfers, the PB3 line must be high. It requires the clock to idle low and takes data on rising clock edges. The serial clock cannot exceed 300 KHz. Assume System Clock Frequency = 8 MHz. Write your program here: Suggested program steps:
Addresses for: Port B Data register Port F Data register Port B Data Direction register Port F Data Direction register SPI Control register SPI Status and Control register SPI Data (Read=rcv, Write=xmt) CONFIGURATION: Select P ort F inputs/outputs & levels : 1. Make PB3 output value high. 2. Make PB3 an output. 3. Load accumulator with " MOSI & SPSCK = outputs" value. " MISO & SS* = inputs" value. 4. Store accumulator to DDRF register. Select master mode, clock operation, & enable SPI: 5. Load ACC. with value that selects freq 300 KHz. 6. Store accumulator to SPSCR register. 7. Load accumulator with value that selects master mode, clock phase = rising edge, polarity = idle low, active pullup outputs, interrupts disabled, SPI enabled. 8. Store accumulator to SPCR register. Send $55 to shift register: 9. Make PB3 output low (chip-select shift register). 10. Load accumulator with $55. 11. Store accumulator to SPDR register. 12. Stay here until transmission is complete. 13. Make PB3 output high (deselect shift register). 14. Done, stay here.
HC08-SPIExer

PTB PTF DDRB DDRF SPCR SPSCR SPDR

EQU EQU EQU EQU EQU EQU EQU

$01 $09 $05 $0D $10 $11 $12

READ:
SPCR WRITE: RESET: 0 0 0 0 1 0 0 0 SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE

SPI Control Register (SPCR)

SPI Wired OR Mode (SPWOM)

Configures MISO, MOSI, and SPSCK outputs to be

open-drain drivers Allows multiple-master systems Provides some protection against CMOS latchup

READ: SPSCR WRITE: RESET:

SPRF

OVRF

MODF

SPTE

0 SPR1 SPR0

SPI Status and Control Register (SPSCR)

Overflow flag (OVRF)

Failure to read data register before it is over written Incoming data bytes are lost
Data register contents unaffected

Mode Fault flag (MODF)

Cleared by reading the data register

Master mode only Indicates another master tried to access this device Set when another device pulls SS pin low Cleared by a write to the SPSCR

Low Power Modes

WAIT

STOP

SPI mode remains active SPI registers are not accessible Except by DMA Enabled SPI interrupts will exit wait mode SPI module becomes inactive No affect on register conditions Operation continues after an external

interrupt

READ: SPCR WRITE: SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE

READ: SPSCR WRITE:

SPRF

OVRF

MODF

SPTE

0 SPR1 SPR0

READ: SPDR WRITE: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPI Config & Transmit Solution

Write a routine that configures the SPI as a master, non-interrupt driven and then transmits the value $55. The SPI is connected to a serial-in/parallel out 8-bit shift register. The shift register is chip-selected with the PB3 line at low voltage level. Between transfers, the PB3 line must be high. It requires the clock to idle low and takes data on rising clock edges. The serial clock cannot exceed 300 KHz. Assume System Clock Frequency = 8 MHz. Write your program here: Suggested program steps:
Addresses for: Port B Data register Port F Data register Port B Data Direction register Port F Data Direction register SPI Control register SPI Status and Control register SPI Data (Read=rcv, Write=xmt) CONFIGURATION: Select P ort F inputs/outputs & levels : 1. Make PB3 output value high. 2. Make PB3 an output. 3. Load accumulator with " MOSI & SPSCK = outputs" value. " MISO & SS* = inputs" value. 4. Store accumulator to DDRF register. Select master mode, clock operation, & enable SPI: 5. Load ACC. with value that selects freq 300 KHz. 6. Store accumulator to SPSCR register. 7. Load accumulator with value that selects master mode, clock phase = rising edge, polarity = idle low, active pullup outputs, interrupts disabled, SPI enabled. 8. Store accumulator to SPCR register. Send $55 to shift register: 9. Make PB3 output low (chip-select shift register).

PTB PTF DDRB DDRF SPCR SPSCR SPDR

EQU EQU EQU EQU EQU EQU EQU

$01 $09 $05 $0D $10 $11 $12

BSET BSET LDA STA LDA STA LDA #$22 SPSCR #$02 DDRF #$06 #3,DDRB

#3,PTB

STA BCLR LDA STA WAIT

SPCR #3,PORTB #$55 SPDR

10. Load accumulator with $55. 11. Store accumulator to SPDR register.

12. Stay here until transmission is complete. BRCLR #7,SPSCR,WAIT

BSET DONE BRA

#3,PORTB DONE

13. Make PB3 output high (deselect shift register). 14. Done, stay here.
HC08-SPISol