Processor Organization & Register Organization

Interconnection structures
Computer consists of set of components (or modules) of 3 basic types. CPU Memory I/O These components communicate with each other. The collection of paths connecting various modules is called as Interconnection structure.

There may be different designs of interconnection structure depending upon exchanges that must be made b/w the modules.

Computer Components:

Processor Organization
Central Processing Unit :

The organization of a simple computer with one CPU and two I/O devices

Processor Organization Cont

Processor Organization Cont

Things that the CPU must do: Instruction Execution Steps:
1. Fetch an instruction from memory into instr. Register 2. Change program counter to point to next instruction

3. Determine type of instruction just fetched (Decode)

4. If instructions uses word in memory, determine where Fetch word, if needed, into CPU register(Fetch data)

5. Execute the instruction(Process the data A & L Manip.)

6. Write Data: Result of execution to be stored in Memory or I/O 7. Go to step 1 to begin executing following instruction (Next Instr)

Processor Organization Cont

To do all these things CPU needs : To store data and instruction temporarily while an Instruction is executing.. To remember the location of next Instruction
CPU needs small Internal Memory i.e. Register

Processor Organization Cont

Similarity between Internal structure of the Computer as whole and IS of CPU (collection of major elements) Computer : CPU, I/P, O/P and Memory

CPU: Control Unit, ALU and Register

Register Organization
CPU must have some working space (fast access and close to CPU) This space is efficiently used to store intermediate values The most convenient way to communicate registers is trough common bus system

Register Organization Cont.

Registers in CPU performs two roles:

User Visible register : To minimize main memory references by optimizing register uses (enables m/c
and assembly level Programmer)

Control and Status register: Used by control unit to control the CPU operation

Register Organization Cont.

User visible Registers: General Purpose: Can contain the operand for any opcode. (as there are some dedicated registers like SR for
stack operations)

Data: Used to hold only data. Address: Used to hold addresses

(ex, pointer, Index register, Stack Pointer registers) Segment

Condition codes: Are the bits set by CPU h/w as the result of operation(ex ,Flag Register)

Register Organization Cont.

Control and Status Register:
To control the CPU Operations

Four Registers generally used are

Program Counter: Contains the address of the next instruction to be fetched Instruction Register: Contains the Instruction most recently fetched Memory Address Register: Contains the address of a location in memory Memory Buffer Register: Contains the data to be written in the memory or the data most recently read.

Register Organization Cont.

Bus organization for 7 CPU registers

Clock Input R1 R2 R3 R4 R5

2 MUX BUS A and BUS B ALU 3 X 8 Decoder

R6 R7

Load (7 lines)

SELA

MUX

MUX

SELB

38 decoder

A bus

B bus

SELD OPR

Arithmetic logic unit (ALU)

Output
(a) Block diagram

SELA

SELB

SELD

OPR

(b) Control word

Register Organization Cont.

Bus organization for 7 CPU registers:
2 MUX: select one of 7 register or external data input by SELA and SELB BUS A and BUS B : form the inputs to a common ALU ALU : OPR determine the arithmetic or logic microoperation The result of the micro-operation is available for external data output and also goes into the inputs of all registers

3 X 8 Decoder: select the register (by SELD) that receives the information from ALU

Register Organization Cont.

An operation is selected by the ALU operation selector (OPR). The result of a microoperation is directed to a destination register selected by a decoder (SELD).

Control word: The 14 binary selection inputs (3 bits for SELA, 3 for SELB, 3 for SELD, and 5 for OPR)

Register Organization Cont.

Binary selector input

R1 R2 R3

1 ) MUX A selector (SELA) : to place the content of R2 into BUS A 2) MUX B selector (SELB) : to place the content of R3 into BUS B 3 ) ALU operation selector (OPR) : to provide the arithmetic addition R2 + R3 4) Decoder selector (SELD) : to transfer the content of the output bus into R1

Encoding of Register Selection Fields:

SELA or SELB = 000 (External Input) : MUX selects the external data SELD = 000 (None) : no destination register is selected but the contents of the output bus are available in the external output

Register Organization Cont.

Example
Micro-operation : R1 R2 - R3
Control word

Field:
Symbol: Control word:

SELA
R2 010

SELB
R3 011

SELD
R1 001

OPR
SUB 00101

Stack Organization
Stack: A storage device that stores information in
such a manner that the item stored last is the first item retrieved. Also called last-in first-out (LIFO) list. Useful for compound arithmetic operations and nested subroutine calls.

Stack Organization Cont

Register Stack : Stack pointer (SP): A register that holds the address of the top item in the stack. SP always points at the top item in the stack Push: Operation to insert an item into the stack. Pop: Operation to retrieve an item from the stack. A stack can be organized as a collection of a finite number of registers.

Stack Organization Cont

Register Stack :
In a 64-word stack, the stack pointer contains 6 bits. The one-bit register FULL is set to 1 when the stack is full; EMPTY register is 1 when the stack is empty. The data register DR holds the data to be written into or read from the stack.

Push & Pop Operation

PUSH: Sequence of microOperation

POP: Sequence of microOperation

Increment Stack Pointer

SP SP + 1

Read item from the top of stack

DR M[SP]

Write item on top of the stack

M[SP] DR

Decrement stack pointer

SP SP - 1

Check if the stack is full

If ( SP = 0) then (FULL 1)

Check if stack is empty

If ( SP = 0) then (EMPTY 1)

Mark the stack not empty

EMPTY 0

Mark the stack not full

FULL 0

STACK OPERATIONS REVERSE POLISH NOTATION (postfix)

Reverse polish notation :is a postfix notation (places operators after operands) (Example) Infix notation Reverse Polish notation =A+B = AB+

A stack organization is very effective for evaluating arithmetic expressions A * B + C * D (AB *)+(CD *) AB * CD * +
( 3 * 4 ) + ( 5 * 6 ) 34 * 56 * +

STACK OPERATIONS

Evaluation procedure:
1. Scan the expression from left to right. 2. When an operator is reached, perform the operation with the two operands found on the left side of the operator. 3. Replace the two operands and the operator by the result obtained from the operation.
(Example) Infix postfix 3 * 4 + 5 * 6 = 42 34*56*+

12 5 6 * + 12 30 + 42

STACK OPERATIONS

Reverse Polish notation evaluation with a stack.

stack evaluation: Get value If value is data: push data Else if value is operation: pop, pop evaluate and push.

(Example) using stacks to do this. 3 * 4 + 5 * 6 = 42 => 3 4 * 5 6 * +

Instruction Formats
Layout of bits in an instruction Includes op-code Includes (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set Instruction code format with parts : Mode + Op. Code + Address Mode : Used to specify the type of Instruction Op. Code : Specify 8 possible operations(3bits) Address : Specify the address of an operand(12 bits). If an operation in an instruction code does not need an operand from memory, the rest of the bits in the instruction(address field) can be used for other purpose
15 14 12 11 0

Op. Code

Address

Instruction Formats Cont

Memory reference Instruction
0/1 Opcode
Address ( Opcode = 000 through 110)

Register reference Instruction

0 1 1 1 Register Operation ( Opcode = 111 , I = 0)

I/O Instruction
1 1 1 1 I/O Operation ( Opcode = 111 , I = 0)

Instruction Formats Cont

Instruction Length
Affected by and affects:
Memory size Memory organization Bus structure CPU complexity CPU speed

Allocation of Bits
Number of addressing modes Number of operands Register versus memory Number of register sets Address range

PDP-11 Instruction Format

Pentium Instruction Format

Types of Operations
Operation Type Arithmetic/Logical(Data Manipulation) Example ADD, SUB, MULT, DIV, AND, OR, INR/DCR, Shift, Rotate

Data Transfer
Control System FP Decimal String Graphics

LOAD, STORE, MOV

BRANCH, JUMP, CALL, RET OS Call, VM routines FADD, FSUB, FMULT, FDIV, FCOMP Dec ADD, MULT, Dec-Char convert MOV, COMPARE, SEARCH Pixel Ops, Compress/Decompress

Arithmetic/Logic, data transfer & Control : 96% usage

Simple instructions dominate.

Instruction Types
1. Memory Reference 3. Input/output Reference 2. Register Reference

Instruction Formats
Number of operands Instruction sets may be categorized by the maximum number of operands explicitly specified in instructions. Number of operands in an instruction format depends on the internal CPU Organization:

Single Accumulator Organization General register Organization Stack Organization

Thus a system has

Zero address instruction: One address instructions: Two address instructions: Three address instructions:

 Zero address instructions :

Stack is used. Arithmetic operation pops two operands from the stack and pushes the result.

Stack-organized computer does not use an address field for the instructions ADD, and MUL
Evaluate X = ( A + B ) * ( C + D )
PUSH PUSH A B C D

ADD
PUSH PUSH ADD MUL

POP

TOS A TOS B TOS ( A B ) TOS C TOS D TOS (C D ) TOS (C D ) ( A B ) X TOS

Advantages: No memory addresses needed during the operation. Disadvantages: results in longer program codes.

One address instructions (1-operand m/c) So called accumulator machines, include early computers Instructions specify a single right operand (constant, a register, or a memory location), with the implicit accumulator as the left operand load a, add b, store c. All operations are done between the AC register and memory operand

Instruction: ADD X Micro-operation: AC -> AC + M[X]

LOAD A ADD B STORE T

AC M [ A] AC AC M [ B] M [T ] AC

Advantages: fewer bits are needed to specify the address. Disadvantages: results in writing long programs.

Two address instructions (2-operand) Two address registers or two memory locations are specified, one for the final result.

Each address fields specify either a processor register or a memory operand

Many CISC and RISC machines fall under this category. MOV MOV ADD MOV R1, A R2, B R1, R2 X, R1

R1 M [ A] R 2 M [ B] R1 R1 R 2 M [ x] R1

Advantages: results in writing medium size programs Disadvantages: more bits are needed to specify two addresses.

Three address instructions (3-operand )

Three address registers or memory locations are specified, one for the final result It is also called general address organization.
Instruction: ADD R1, R2, R3 Microoperation: R1 R2 + R3

ADD R1, R2, R3

R1 R2 R3

Advantages: results in writing short programs Disadvantages: more bits are needed to specify three addresses.

(A + B) * ( C+D)
Three-address instructions Two-address instructions

ADD R1, A, B

R1 M[A] + M[B]
ADD R2, C, D R2 M[C] + M[D] MUL X, R1, R2 M[X] R1 * R2

MOV R1, A R1 M[A] ADD R1, B R1 R1 + M[B] MOV R2, C R2 M[C] ADD R2, D R2 R2 + M[D] MOV X, R2 M[X] R2 MUL X, R1 M[X] R1 * M[X]

(A + B) * ( C+D)
One-address instructions Zero-address instructions

LOAD A AC M[A] ADD B AC AC + M[B] STORE T M[T ] AC LOAD C AC M[C] ADD D AC AC + M[D] MUL T AC AC * M[T ] STORE X M[X] AC Store

PUSH A
PUSH B ADD

TOS A
TOS B TOS (A+B)

PUSH C
PUSH D ADD MUL POP X

TOS C
TOS D TOS (C+D) TOS (C+D)*(A+B) M[X] TOS

Operand Locations
Accumulator (before 1960):1 address add A : acc acc + mem[A] Stack (1960s to 1970s): 0 address add : tos tos + next Memory-Memory (1970s to 1980s):2/3 address add A, B: mem[A] mem[A] + mem[B] add A, B, C: mem[A] mem[B] + mem[C] Register-Memory (1970s to present):2 address add R1, A : R1 R1 + mem[A] load R1, A: R1 mem[A] Register-Register, also called Load/Store (1960s to present):2/3 address add R1, R2,R3: R1 R2 + R3 load R1, R2 : R1 mem[R2] store R1, R2 : mem[R1] R2

Example: C = A + B

Stack
Push A
S[++tos] = M[A]

Accumulator
Load A
accum = M[A]

Reg-Mem
Load R1, A
R1 = M[A]

Load-Store
Load R1, A
R1 = M[A]

Push B
S[++tos] = M[B]

Add B
accum += M[B]

Add R3, R1, B

R3 = R1 + M[B]

Load R2, B
R2 = M[B]

Add
t1= S[tos--]; t2= S[tos--]; S[++tos]= t1 + t2

Store C
M[C] = accum

Store R3, C
M[C] = R3

Add R3, R1, R2

R3 = R1 + R2

Pop C
M[C] = S[tos--]

Store R3, C
M[C] = R[3]

Summary of ISA
No of memory address 1 0 0 Max no of operands Arch Examples Advantages Disadvantages

1 0 3

Acc Stack LoadStore X86 (for FP operations) ARM, MIPS, Sparc, PowerPC

Less Hardware, high code density Less Hardware, high code density Fixed length instruction, simple code gen, CPI similar for all instr., easy decoding Data without load instruction. Easy Instr encoding.

Memory bottleneck Memory, pipeline bottlenecks IC high. Large programs

Registermemory

80x86, Motorola 68k, IBM 360/370

Src operand (mem) destroyed. Num registers less. CPI varies. Variable length instructions. Mem access bottleneck.

2 Or 3

2 Or 3

MemoryMemory [not used]

VAX

No registers needed for temporaries. Most compact

Operand Location: Registers vs. Memory

Pros and cons of registers
+ Faster, direct access + Simple cost model (fixed latency, no misses) + Short identifier Must save/restore on procedure calls, context switches Fixed size (larger-sized structures must live in memory)

Pros and cons of more registers

+ Possible to keep more operands for longer in faster memory Shorter operand access time, lower memory traffic Longer specifiers Larger cost for saving CPU state Trend towards more registers 8 (x86) -> 32 (MIPS/Alpha/PPC) -> 128 (IA-64) Driven by increasing compiler involvement in scheduling

Memory addressing
Endianness: How is byte ordered in a word: where is the LSB?
Small End Big End

Big-endian: LSB in big end, Ex: Sparc, IBM

Address Bigendian Smallendian

Small-endian: LSB in small end

Ex: Intel 8086 Bi-endian: PowerPC, MIPS (supports both)

00 01 10 11 12 34 56 78 78 56 34 12

Example: Pentium 32-bit addressing

Addressing modes

Register

Immediate

Memory

Direct [displacement]

Indirect

Register [Base]

Based [Base + disp ]

Indexed [index + scale * disp ]

Based-indexed [ scaled]

Scalefactor No scale factor [Base + (index *scale) [Base + Index + disp] + disp ]

Instruction Cycle