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VHDL 360

by: Mohamed Samy

Samer El-Saadany

Copyrights
Copyright 2010 to authors. All rights reserved All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners.
VHDL 360 2

Module 1
Create your first model for a simple logic circuit

Objective
Create your first VHDL model for simple logic circuits Skills gained:
Know the basic structure of a VHDL model (entity, architecture) Model simple combinational logic

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Outline
Entity Architecture Internal Signals Expressions & Operators With-Select When-Else

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VHDL Design Units


After understanding our first model*, lets move forward & understand how to construct one

*Module 0: Introduction to VHDL


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VHDL Design Units


A VHDL Model (Design unit) consists of:
Entity
Define ports (inputs and outputs)

Architecture
Define operation (input/output relation)

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Entity Description
<mode>: port direction
IN: Input that can only be read OUT: Output that can only be written to INOUT: Input or output can be read and
written to

Syntax:
entity <entity_name> is port ( <port_name> : <mode> <type>; <port_name> : <mode> <type>; -- last port has no semicolon <port_name> : <mode> <type> ); End entity;

Example: ENTITY model1 PORT( a b c d e END model1 ; IS --VHDL is case insensitive : IN std_logic; : IN std_logic; : IN std_logic; : IN std_logic; : OUT std_logic );

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Entity Description
Types:
VHDL offers the following standard types:
Integer: -2 to 2 -1 Bit, Bit_vector
31 31

Bit values:
0 1 U X 0 1 Z W L H - -- Binary Zero -- Binary One -- Uninitialized -- Forcing Unknown -- Forcing Zero -- Forcing One -- High Impedance -- Weak Unknown -- Weak Zero -- Weak One -- Dont Care

Std_logic values

IEEE Packages offer more types:


Std_logic, std_logic_vector
Require use of appropriate IEEE packages Example: Using IEEE Types
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY model1 IS PORT( a : IN bit_vector(3 downto 0); b : IN bit; c : IN bit; d : IN bit; e : OUT bit ); END model1 ;

Example: Using Standard Types

ENTITY model1 IS PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; e : OUT std_logic_vector(7 downto 0) ); END model1 ;

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Exercise 1
Write the entity of the following:
1-bit Full Adder

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Answer of Exercise 1
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY fullAdder IS PORT( In1, In2, CarryIn : IN std_logic; Sum : OUT std_logic; CarryOut : OUT std_logic); END fullAdder;

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Architecture Description
A given architecture represents one possible implementation for its associated entity
Architecture declaration: defines internal signals, components, types etc to be used in architecture body Architecture body: defines implementation details of input/output relationship

Syntax:
architecture <arch_name> of <entity_name> is -- architecture declarations begin -- architecture body end architecture;

Multiple architectures can exist for each entity


Example: Internal signals ARCHITECTURE rtl OF model1 IS SIGNAL x : std_logic; signal <sig_name> : <sig_type>; SIGNAL y : std_logic; BEGIN x <= a AND b; Concurrent Assignments y <= c AND d; e <= x OR y; END rtl;
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Architecture Body
Architecture body can only contain concurrent statements, in this module we will only focus on
Concurrent assignments With-select When-else

Concurrent Assignments
LHS can be an internal signal or an output port RHS is an expression that operates on internal signal and/or input ports

Syntax:
<target> <= <expression>;

Example:
ARCHITECTURE expr OF example1 IS SIGNAL u, w, x, y, z : std_logic; SIGNAL a, b, c : integer; BEGIN x <= y AND z; -- logical expression w <= NOT x; u <= w; -- direct assignment c <= a + b; -- arithmetic expression END expr;
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Arithmetic Operators +,-,*,/ Logical Operators NOT AND, NAND OR, NOR XOR, XNOR

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Internal signals
We use Internal Signals for:
Internal connections in structural description Intermediate calculations Avoid illegal port usage situations:
Read Output port

Syntax:
architecture <arch_name> of <entity_name> is -- architecture declarations signal <sig_name> : <sig_type>; begin -- assign to internal signal <sig_name> <= <expression>; -- read the internal signal <sig_name> <= <expression>; end architecture;
Illegal use of an output port (used as the and gate input)

Example:

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY illegal IS PORT( A : IN std_logic; B : IN std_logic; C : IN std_logic; F : OUT std_logic; G : OUT std_logic); END illegal ; ARCHITECTURE struct OF illegal IS -- Internal signal declarations SIGNAL sig1 : std_logic; SIGNAL sig2 : std_logic; SIGNAL sig3 : std_logic; BEGIN F <= sig3 AND sig1 AND C; G <= F AND sig1 AND sig2; -- Reading Out port F is illegal sig3 <= NOT(A); sig1 <= NOT(B); sig2 <= NOT(C); END struct;
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Example:

Internal signals

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY legal IS PORT( A : IN std_logic; B : IN std_logic; C : IN std_logic; F : OUT std_logic; G : OUT std_logic); END legal ; ARCHITECTURE struct OF legal IS -- Internal signal declarations SIGNAL sig1 : std_logic; SIGNAL sig2 : std_logic; SIGNAL sig3 : std_logic; SIGNAL sig4 : std_logic; BEGIN sig4 <= sig3 AND sig1 AND C; -- using internal signal sig4 G <= sig4 AND sig1 AND sig2; F <= sig4; sig3 <= NOT(A); sig1 <= NOT(B); sig2 <= NOT(C); END struct;
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Internal Signals used for intermediate relations

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Expressions & Operators


Each operator is defined for specific data type(s)
Arithmetic operators are defined for standard integer types Logical operators are defined for the standard bit, bit_vector types Logical & arithmetic operators are defined for std_logic & std_logic_vector types in IEEE std_logic_* packages You need to use the appropriate package before applying an operator on a type Example:
ARCHITECTURE struct OF expr IS -- Internal signal declarations SIGNAL x, y, z : integer; BEGIN -- Operators can be chained to form complex expressions F <= C AND (NOT(B)) AND (NOT(A)); -- parentheses control association of operators and operands -- use parentheses for readability G <= (C OR (NOT(A))) XOR (NOT(B) AND (B NOR C)); Z <= X + Y; -- using addition operator defined for integer type END struct;

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Operators*
Operation
std_logic <= std_logic AND std_logic; std_logic_vector <= std_logic _vector AND std_logic_vector; boolean <= std_logic_vector > std_logic_vector; boolean <= std_logic_vector /= std_logic_vector; std_logic_vector <= std_logic_vector +/- integer std_logic_vector <= std_logic_vector +/- integer std_logic_vector <= std_logic_vector +/std_logic_vector std_logic_vector <= std_logic_vector +/- std_logic

Package
ieee.std_logic_1164 ieee.std_logic_1164

Comments
Similarly NAND, OR, NOR, XORetc Similarly NAND, OR, NOR, XORetc Similarly < , >=, <= Not Equal operator Unsigned addition/subtraction Signed addition/subtraction Unsigned addition/subtraction Signed addition/subtraction

ieee.std_logic_1164 ieee.std_logic_1164 ieee.std_logic_unsigned ieee.std_logic_signed ieee.std_logic_unsigned ieee.std_logic_signed

*More operator will be presented throughout the course


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Operators
Example:
-- Library & package used for architecture scope

LIBRARY ieee; USE ieee.std_logic_unsigned.all;

-- Need to use unsigned arithmetic operators

ARCHITECTURE expr OF example1 IS SIGNAL u, w : std_logic_vector(3 downto 0); SIGNAL a : integer; BEGIN
-- Adding an integer to an std_logic_vector returning std_logic_vector

u <= w + a; END expr;

Wheres the Carry Out?!

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Exercise 2
Write the architecture of the following:
1-bit Full Adder

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Answer of Exercise 2
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fullAdder IS PORT( In1, In2, CarryIn : IN std_logic; Sum : OUT std_logic; CarryOut : OUT std_logic); END fullAdder; ARCHITECTURE expr OF fullAdder IS signal temp : std_logic; BEGIN temp <= In1 XOR In2; Sum <= temp XOR CarryIn; CarryOut <= (In1 AND In2) OR (CarryIn AND temp); END expr;

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Architecture Body
With-Select
<select_signal> can be an internal signal or an input port <target> can be an internal signal or an output port <value> constants representing one of possible <select_signal> values. When others is a must if not all values of <select_signal> are covered

Syntax:
With <select_signal> select
<target> <= <expression> when <value>, <expression> when <value>, . < expression> when others;

Example:

Architecture behave of mux_with is b Begin c With sel select d F <= a when "00", b when "01", c when "10", d when others; -- needed to cover missing sel values End Architecture;

Sel(1:0)

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Architecture Body
When-else
LHS can be an internal signal or an output port RHS is an expression that operates on internal signal and/or input ports when the branch condition is true Last else branch covers all missing conditions

Syntax:
<target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition> else <expression> ;

Example:
Architecture behave of mux_when is Begin F <= a when sel = "00" else b when sel = "01" else c when sel = "10" else d; -- This is one statement with semicolon at the end only End Architecture ;

a b c d Sel(1:0)

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Exercise 3
Write the entity and architecture of the following (using with-select then using when-else):
2x4 Decoder 4x2 Encoder
a 4 F a 2 4

Encoder4x2

Decoder2x4

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Decoder 2x4(with-select)
library IEEE; a use IEEE.std_logic_1164.all; 2 entity decoder2x4 is port(a: in std_logic_vector(1 downto 0); F: out std_logic_vector(3 downto 0)); end entity; Architecture behave of decoder2x4 is Begin with A select F <= "0001" when "00", "0010" when "01", "0100" when "10", "1000" when others; End Architecture;
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F 4

Decoder 2x4 (when-else)


library IEEE; a use IEEE.std_logic_1164.all; 2 entity decoder2x4 is port(a: in std_logic_vector(1 downto 0); F: out std_logic_vector(3 downto 0) ); end entity; Architecture behave of decoder2x4 is Begin F <= "0001" when a = "00" else "0010" when a = "01" else "0100" when a = "10" else "1000"; End Architecture; F 4

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Encoder4x2 (with-select)
library IEEE; use IEEE.std_logic_1164.all; entity encoder4x2 is port(a: in std_logic_vector(3 downto 0); F: out std_logic_vector(1 downto 0) ); end entity;

Architecture behave of encoder4x2 is Begin With a select F <= "00" when "0001", "01" when "0010", "10" when "0100", "11" when others; End Architecture;

a 4 2

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Next Module
Module 2: Writing more complex Models

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Contacts
You can contact us at:
http://www.embedded-tips.blogspot.com/

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