Documentos de Académico
Documentos de Profesional
Documentos de Cultura
Why Signal Integrity What is Signal Integrity When to use Signal Integrity Where to use Signal Integrity Who does the Signal Integrity How to Validate Signal Integrity
When to do SI Analysis
Product Concept Design Stage Functional Distribution of System Elements Mid Design Issues - Clock Distribution, etc. PCB Placement Analysis PCB Post Layout - Pre Fabrication Manufacturing Tolerance Analysis Post Fabrication Validation
Design Subsystems (FSB, PCI, AT, TDM) Complete Boards Connected System Elements
Material Variations Power Distribution Signal Crosstalk PCB Layout PCB Construction
EXPERIENCE
10 Years QUAD experience 30+ Years Electrical Engineering Experience GTL, (P)ECL, CMOS, etc. to > 1GHz
Why SI - Physics
SI is ENERGY CONTROL Generated Energy is 105 to 108 above receivers needs High Spectral Energy is absorbed by:
Terminations Material in board coupling to nearby lines Radiation to free space (License Required)
Home
Why SI - Image
Customer Confidence! Make it work correctly for customer Reliability breeds customer loyalty Market Timing for New Technology
Vendor to Vendor variations Vendor product changes over time Passive component tolerance analysis Monte Carlo analysis required
Gtek, Polyemide and Teflon based material Copper/Solder conductivity variations Etching control of geometry
Stackup control for impedance Impedance Controlled Fabrication Stackup measurement techniques Test Coupons
Verify Signal Integrity on entire board Test Board Operation with System Test System Operation for timing and signal
Monte Carlo Analysis Identify Critical Failure Items Establish Manufacturing Restriction
Where SI - Clocks
Validate Clock Timing Distribution Check Clock waveform at destination Confirm Clock Skew designs Validate Clock Signal Termination Build Clock Skew budget
Where SI - Busses
Validate Bus Topology Validate Bus Termination Schema Validate Bus Signal Integrity Validate Bus Timing Validate Bus Driver tolerance
Where SI - I/O
Differential I/O I/O noise coupling from board I/O noise coupling into board All I/O above 5 MHz Line terminations for Critical I/O Signal Cross Talk to local signals