1.

Single Phase Inverters:

Single-phase Inverters can be found as half-bridge and full-bridge topologies. Although, the
power range they cover is the low one, they are widely used in power supplies, single-phase
UPSs, and currently to form high-power static power topologies, such as the multicell
configurations that . The main features of both approaches are reviewed and presented in the
following.
1.Single Phase Half Bridge Inverter:
Figure shows the power topology of a half-bridge Inverter, where two large capacitors are
required to provide a neutral point N, such that each capacitor maintains a constant voltage vi /
2. Because the current harmonics injected by the operation of the inverter are low-order
harmonics, a set of large capacitors (C+ and C) is required. It is clear that both switches S+
and S cannot be on simultaneously because a short circuit across the dc link voltage source vi
would be produced. There are two defined (states 1 and 2) and one undefined (state 3) switch
state as shown in Table. In order to avoid the short circuit across the dc bus and the undefined
ac output-voltage condition, the modulating technique should always ensure that at any instant
either the top or the bottom switch of the inverter leg is on.
Switch States For Half Bridge Inverter
2.Single Phase Full Bridge Inverter
Muhammad Ashfaque
2K9/ELE/43
1
2
2,3,..
1
2
2
2,3,..
1
2
1
1
1
1
1
1
3%
on
n
o
on
n
o
on
n
o
on
n
o
o
V
HF for n
V
THD V
V
V
DF
V n
V
DF for n
V n
LOH V

>

,
>

Figure shows the power topology of a full-bridge Inverter. This inverter is similar to the half-
bridge inverter; however, a second leg provides the neutral point to the load. As expected, both
switches S1+ and S1 (or S2+ and S2) cannot be on simultaneously because a short circuit
across the dc link voltage source vi would be produced. There are four defined (states 1, 2, 3,
and 4) and one undefined (state 5) switch state as shown in Table. The undefined condition
should be avoided so as to be always capable of defining the ac output voltage always. In order
to avoid the short circuit across the dc bus and the undefined ac output voltage condition, the
modulating technique should ensure that either the top or the bottom switch of each leg is on at
any instant. It can be observed that the ac output voltage can take values up to the dc link value
vi , which is twice that obtained with half-bridge VSI topologies. Several modulating
techniques have been developed that are applicable to full-bridge VSIs. Among them are the
PWM (bipolar and unipolar) techniques.
Switch States For Full Bridge Inverter
3. Three Phase Inverter
Muhammad Ashfaque
2K9/ELE/43
1,3,5,.
4
( ) sin
0 2, 4,..
S
o
n
V
v t n t
n
for n

2
( )
0
1( )
2
4
0.90
2
o rms S S
S
o rms S
V V d V
V
V V

The standard three-phase VSI topology is shown in Fig and the eight valid switch states are
given in Table . As in single-phase VSIs, the switches of any leg of the inverter (S1 and S4, S3
and S6, or S5 and S2) cannot be switched on simultaneously because this would result in a
short circuit across the dc link voltage supply. Similarly, in order to avoid undefined states in
the VSI, and thus undefined ac output line voltages, the switches of any leg of the inverter
cannot be switched off simultaneously as this will result in voltages that will depend upon the
respective line current polarity.
Switch States For Three Phase Inverter
4.Three Phase PWM Inverters
Muhammad Ashfaque
2K9/ELE/43
5.Delta & Y Connected:
For a delta-connected load, the phase current can be obtained directly from the line to line
voltages. once the phase currents are known, the line currents can be determined.
For a Y- connected load, the line to neutral voltages must be determined to find the line
currents (phase).
6.Single Pulse PWM
Muhammad Ashfaque
2K9/ELE/43
1,3,5,.
1,3,5,.
1,3,5,.
4
( ) sin( ) sin ( )
3 6
4
( ) sin( ) sin ( )
3 2
4 7
( ) sin( ) sin ( )
3 6
S
ab
n
S
bc
n
S
ca
n
V n
v t n t
n
V n
v t n t
n
V n
v t n t
n

( ) 1( )
4 4
sin( ) sin( ) 0.7797
3 3 2 2
S S
Ln rms L rms S
V V n
V V V
n



In single pulse-width modulation control, there is only one pulse per half- cycle and the width
of the pulse is varying to control the output voltage. Fig. shows the generation of gating signals
of single pulse width modulation. The gating signals are generated by:
i. Convert the reference signal to the square wave signal. This process is obtained by inter the
reference signal to the zero-crossing circuit witch consider the positive part of the input signal
is positive part of the output signal(square wave) and the negative part of the input signal is
negative part of the output signal
ii. Then, the output signal of zero-crossing circuit is become control signal of the ramp
generator. Ramp generator integrate the input signal to the saw-toothed signal
iii. Then, the output of the ramp generator inter to the comparator circuit which compare
between the variable d.c level and the ramp wave. The certain d.c level gives the certain pulse
width and any change in the d.c level will produce change in the pulse width.
7.Multiple Pulse PWM
Muhammad Ashfaque
2K9/ELE/43
2 1
2
s
d t t
T
MT M

( )
( ) / 2
2
( )
/ 2
2
2
o rms S S
V V d V

1,3,5,.
4
( ) sin sin
2
S
o
n
V n
v t n t
n

The harmonic content can be reduced by using several pulses in each half-cycle of output
voltage. The generation of gating signals for turning on and off transistors .The gating signals
are produced by comparing reference signal with triangular carrier wave.
8. Phase Displacement
Muhammad Ashfaque
2K9/ELE/43
1
2
m m
s
d t t
T
MT M
p

+


( )
( ) / / 2
2
( )
/ / 2
2
2
p
o rms S
p
S
p
V V d
p
V

1,3,5,.
( ) sin
o n
n
v t B n t

Voltage control can be obtained by using multiple inverters & summing the output voltages of
individual inverters. A single phase full bridge inverter can be perceived as the sum of two half
bridge inverters. Phase displacement produces an output voltage , whereas a delay angle of
produces an output as shown in fig.
9.The Space vector Modulation:
At present, the control strategies are implemented in digital systems, and therefore digital
Muhammad Ashfaque
2K9/ELE/43
( )
1,3,5,.
1,3,5,.
1,3,5,.
1
2
( ) sin
2
( ) sin ( )
4
( ) sin cos ( )
2 2
4
sin
2
2
o rms S
S
ao
n
S
bo
n
S
ab
n
S
o
V V
V
v t n t
n
V
v t n t
n
V n
v t n t
n
V
V

1,3,5,.
1,3,5,.
1,3,5,.
1
2
( ) sin ( )
2
( ) sin ( )
4
( ) cos( ) sin( )
4
cos( )
2
S
ao
n
S
ao
n
S
ab
n
S
o
V
v t n t
n
V
v t n t
n
V
v t n n t
n
V
V

modulating techniques are also available. The SV-based modulating technique is a digital
technique in which the objective is to generate PWM load line voltages that are on average
equal to given load line voltages. This is done in each sampling period by properly selecting the
switch states from the valid ones of the VSI Table and by proper calculation of the period of
times they are used. The selection and calculation times are based upon the SV transformation.
The Space vector Representation
10.Bipolar Notches:
Muhammad Ashfaque
2K9/ELE/43
(2 / 3) (2 / 3)
2
( )
3
j j
a b c
u t u u e u e

1 + +
]
r
( )
j t
x y m
u t u ju V e

+
r
2 1
( )
3 2
3
( )
3
x a b c
y b c
u u u u
u u u
1
+
1
]

A pair of unwanted harmonics at the output of single phase inverters can be eliminated by
introducing a pair of symmetrically placed bipolar voltage notches.
The Fourier series of output voltage can be expressed as:
10.Unipolar Notches
Muhammad Ashfaque
2K9/ELE/43
1,3,5,.
( ) sin
o n
n
v t B n t

[ ]
1 2
1 2
0
1 2
1 2 3 4
3 5 1 2
4
sin( ) sin( ) sin( )
4 1 2cos 2cos
4
1 2cos 2cos 2cos 2cos ..
0, 23.62 33.3
S
n
S
S
n
o o
V
B n d n d n d
V n n
n
V
B n n n n
n
For B B and

1
+
1
]
+ 1

1
]
+ +


Muhammad Ashfaque
2K9/ELE/43
1,3,5,.
( ) sin
o n
n
v t B n t

[ ]
1
2
/ 2
0
1 2
1 2 3 4
3 5 1 2
4
sin( ) sin( )
4 1 cos cos
4
1 cos cos cos cos ..
0, 17.83 37.93
S
n
S
S
n
o o
V
B n d n d
V n n
n
V
B n n n n
n
For B B and

1
+
1
]
+
1

1
]
+ +