Introduction to Digital Signal Processing

g g

Review of Analog Filtering Discrete-Time Signal Processing

n n n

Difference Equations z-transform Discrete-Time Fourier Transform

g g g g

Introduction to Digital Filter Design Implementation of Digital Filters Fixed Point vs Floating Point number representation Coefficient Quantization Effects

Introduction to Digital Signal Processing Santiago Marco Universitat de Barcelona

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Realizacin de Filtros Digitales

Veamos algunas propiedades de los diagramas de bloques

x

Conexiones en cascada: La funcin de Transferencia global de una conexin en cascada es el producto de las funciones de Transferencia individuales. Conexiones en paralelo: La funcin de Transferencia global de una conexin en paralelo es la suma de las funciones de Transferencia individuales. Conexin en realimentacin: La salida se realimenta en la entrada directamente o a travs de otros subsistema. La funcin de Transferencia global viene dada por la relacin (ver figura): G( z ) H T (z ) = 1 + G( z ) H ( z )

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Captulo 10 : Implementacin de Filtros Digitales

5 Curso-Tratamiento Digital de Seal

Realizacin de Filtros Digitales

H1 H2 H 1H 2
Conexin de dos sistemas en Cascada

H1

H 1+ H 2

H2
Conexin en paralelo de dos sistemas

G -

G 1+GH

H
Un sistema sencillo con realimentacin

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Captulo 10 : Implementacin de Filtros Digitales

5 Curso-Tratamiento Digital de Seal

Realizacin de Filtros Digitales

Los filtros digitales pueden realizarse usando elementos correspondientes a las operaciones de multiplicacin, adicin y almacenaje de datos. El almacenaje de un dato significa retrasar su uso una cantidad normalmente igual al periodo de muestreo. Este retraso se representa mendiante z-1 (retraso de una unidad), z-2 (dos unidades, etc).
x[n]

Ax[n]

x[n]

z -1
Elemento Almacenador

x[n-1]

Elemento Multiplicador

x[n]

+ y[n]

x[n]y[n]

Elemento Sumador

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Captulo 10 : Implementacin de Filtros Digitales

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Realizacin de Filtros Digitales

Filtros FIR (MA): Son filtros no recursivos cuya funcin de Transferencia HMA(z) y su correspondiente ecuacin diferencia y[n] son de la forma, H MA (z ) = B0 + B1 z 1 ++ BM z M y[n] = B0 x[n] + B1 x[n 1]++ BM x[n M ] Este filtro puede realizarse utilizando el diagrama de la figura
x[n]
z -1 B1 z -1 B2
+

B0

y[n]

z -1 BM

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Captulo 10 : Implementacin de Filtros Digitales

5 Curso-Tratamiento Digital de Seal

Realizacin de Filtros Digitales

Filtros Autoregresivos: Son filtros recursivos cuya funcin de Transferencia HAR(z) y su correspondiente ecuacin diferencia y[n] son de la forma,
H AR (z ) = 1 1 + A1 z 1 ++ AN z N

y[n] = A1 y[n 1] AN y[n N ] + x[n]

Este filtro puede realizarse utilizando el diagrama de la figura,

x[n]
+

y[n]
z -1

+
+

-A1 z -1

+
+

-A2

z -1 -AN

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Captulo 10 : Implementacin de Filtros Digitales

5 Curso-Tratamiento Digital de Seal

Realizacin de Filtros Digitales

Filtros ARMA: Son la combinacin de los dos anteriores. Su funcin de Transferencia y ecuacin diferencia son, 1 M
H (z ) = B0 + B1 z ++ BM z 1 + A1 z 1 ++ AN z N = H AR (z )H MA (z ) y[n] = A1 y[n 1] AN y[n N ] + B0 x[n]++ BM x[n M ]

El diagrama de filtro puede hacerse de varias formas,

x[n]
z -1 B1 z -1 B2
+

B0

y[n]
z -1

+
+

-A 1 z -1

+
+

-A 2

z -1 BM -A N

z -1

HMA(z) HAR(z)
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Realizacin de Filtros Digitales

x[n]
+

B0 z -1 z -1 B1 z -1 z -1 B2

y[n]

+
+

-A1

+
+

-A2

z -1 -AN

z -1 BM

HAR(z)HMA(z)

Esta dos formas son lgicamente idnticas. Se denominan forma directa I. Requieren el uso de (N+M) elementos de memoria, (N+M) sumadores y (N+M+1) multiplicadores. Esta ltima forma sugiere la eliminacin M elementos de memoria, ya que estn repetidos. El diagrama resultante se denomina forma directa II.
Captulo 10 : Implementacin de Filtros Digitales 9

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5 Curso-Tratamiento Digital de Seal

Realizacin de Filtros Digitales

x[n]
+

B0 z -1

y[n]

+
+

-A 1 z -1

B1

+
+

-A 2

B2

Forma directa II

z -1 -A M BM

z -1 -A N

De la forma directa II pasamos a la forma transpuesta o cannica. Consiste en sustituir los nodos por sumas, las sumas por nodos, invertir el sentido de las flechas y finalmente intercambiar los coeficientes y x[n] e y[n].
Captulo 10 : Implementacin de Filtros Digitales 10

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5 Curso-Tratamiento Digital de Seal

Realizacin de Filtros Digitales

x[n]
B0
+

y[n]

z -1 B1
+

-A 1

z -1 B2
+

-A 2

Forma Transpuesta o Cannica

z -1 BM
+

-A M

z -1 -A N

Esta forma da lugar a una realizacin con N elementos de memoria, (N+M+1) multiplicadores y N sumadores.
Captulo 10 : Implementacin de Filtros Digitales 11

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Realizacin de Filtros Digitales

Las funciones de Transferencia pueden representarse mediante sumas de fracciones parciales (en paralelo), o mediante producto de factores (en cascada). Supongamos un funcin de Transferencia H(z), expresada como suma de fracciones. Los pares de polos complejos conjugados deben ser combinaL dos en trminos de 2 orden, b1i z 1 + b0 i N + 1
H (z ) = b0 +
2 + a1i z 1 + 1 i =1 a2 i z

L = int 2

Esta funcin de Transferencia puede representarse a travs de la forma directa II o de la forma Transpuesta, dando lugar a las formas Paralela II y Paralela Transpuesta (Figura T13). La funcin de Transferencia puede expresarse tambin como producto de L L z 2 + z 1 + 1 trminos, 2i 1i
H (z ) = 0 H i ( z ) = 0
i=0 i =0

2 i z 2 + 1i z 1 + 1

lo que da lugar a las formas en cascada, Cascada II y Cascada Transpuesta (Figura T14).
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Realizacin de Filtros Digitales

b0 b0 b 01
+

+ x[n]

b 01

z -1
x[n]

z -1
b 11
+

+ -a 1 1

b 11

-a 1 1

z -1
-a 2 1

y[n]

z -1
-a 2 1

y[n]

b 0L

b 0L

z -1
+ + -a 1 L

z -1
b 1L b 1L
+

-a 1 L

z -1
-a 2 L

z -1

Paralelo II y Paralelo Transpuesta

-a 2 L

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5 Curso-Tratamiento Digital de Seal

Realizacin de Filtros Digitales

x[n]

y[n]

z -1
+ + - 1 1

z -1
1 1
+

+ - 1 L

1 L

z -1
- 2 1

z -1
1 1
- 2 L

1 L

Forma en Cascada II
x[n]

y[n]

z -1
1 1
+

z -1
+

- 1 1

1 L

- 1 L

z -1
0 1
+

z -1
+

- 2 1

0 L

- 2 L

Forma en Cascada Transpuesta

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Fixed Point Notation

A K-Bit fixed point number can be interpreted as either:

n n

an integer (i.e): 20645 fractional number (i.e:0.75)

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

Integer Fixed Point Representation

N-bit fixed point, 2s complement representation X = -bN-1 2N-1 + bN-2 2N-2 + + b020
g g

Difficult to use due to possible overflow

n

In a 16-bit processor, the dynamic range is 32767 to 32768.

g

example, 200 350 = 70000, which is an overflow!

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

Fractional Number representation

g g g g

g g

Also called Q-format Fractional representation suitable for DSPs algorithms. Number range is between 1 and -1 Multiplying a fraction by a fraction always results in a fraction and will not produce an overflow (e.g., 0.99 x 0.9999 less than 1) Successive additions may cause overflow Represent numbers between
n

-1.0 and 1 2(N-1), when N is number of bits

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

Fractional Number representation

g g g

Equivalent to scaling Q represents the Quantity of fractional bits Number following the Q indicates the number of bits that are used for the fraction. Q15 used in 16 bit DSP chip, resolution of the fraction will be 2^15 or 30.518e6 n Q15 means scaling by 1/215 n Q15 means shifting to the right by 15

Example: how to represent 0.2625 in memory:

n

Method 1 (Truncation): INT[0.2625*215]= INT[8601.6]

= 8601 = = 8602 =

0010000110011001
n

Method 2 (Rounding): INT[0.2625*215+0.5]= INT[8602.1]

0010000110011010

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

Truncating or Rounding?

g g

Which one is better? Truncation

n

Magnitude of truncated number always less than or equal to the original value g Consistent downward bias

Rounding
n

Magnitude of rounded number could be smaller or greater that the original value
g

Error tends to be minimized (positive and negative biases)

Popular technique: rounding to the nearest INT[251.2] = 251 (Truncate or floor) ROUND [ 251.2] = 252 (Round or ceil) ROUNDNEAREST [251.2] = 251

Example:
n n n

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

Some Fractional Examples (16 bits)

Integer (15 bits) 16Q0

Fraction (15 bits)

1Q15 or Q15 Used in DSP

Binary pt poistion .
2Q14 Upper 2 bits Remaining 14 bits

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

How to Compute Fractional Number

NQ n Format bN-1bN-2b0 bn-1bn-2b0

-2NbN-1++21b1+20b0+2-1bn-1 + 2-2bn-2+2-nb0
Example 1110 Integer Representation 4Q0: -23 + 22 + 21 = -2 11.10 Fractional 2Q2 Representation: -21 + 20 + 2-1 = -2 + 1 + 0.5 = -0.5 (Scaling by 1/22) 1.110 Fractional Q3 Representation: -20 + 2-1 + 2-2 = -1 + 0.5 + 0.25 = 0.25 (Scaling by 1/23)
Introduction to Signal Processing Santiago Marco Universitat de Barcelona 7

Q format Multiplication
g

Product of two Q15 numbers is Q30.

So we must remember that the 32-bit product has two bits in front of the binary point.
n

Since NxN multiplication yields 2N-1 result Addition MSB sign extension bit

Typically, only the most significant 15 bits (plus the sign bit) are stored back into memory, so the write operation requires a left shift by one.

Q15 Extension sign bit Sign bit X 15 bits 15 bits

Q15

16-bit memory

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

Real Numbers (from Stallings)

g g

Numbers with fractions Could be done in pure binary

n

1001.1010 = 24 + 20 +2-1 + 2-3 =9.625

g g

Where is the binary point? Fixed?

n

Very limited How do you show where it is?

Moving?
n

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

Floating Point (from Stallings)

Sign bit

Biased Exponent

Significand or Mantissa

g g g

+/- .significand x 2exponent Point is actually fixed between sign bit and body of mantissa Exponent indicates place value (point position)

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

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Floating Point Examples (from Stallings)

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Signs for Floating Point (from Stallings)

g g

Mantissa is stored in 2s compliment Exponent is in excess or biased notation

n n n n n

e.g. Excess (bias): 128 8 bit exponent field Pure value range 0-255 Subtract 128 to get correct value Range -128 to +127

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Normalization (from Stallings)

g g g

FP numbers are usually normalized i.e. exponent is adjusted so that leading bit (MSB) of mantissa is 1 Since it is always 1 there is no need to store it

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

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IEEE 754 (from Stallings)

g g g g

Standard for floating point storage 32 and 64 bit standards 8 and 11 bit exponent respectively Extended formats (both mantissa and exponent) for intermediate results

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

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IEEE 754 Formats (from Stallings)

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FP Arithmetic +/- (from Stallings)

g g g g

Check for zeros Align significands (adjusting exponents) Add or subtract significands Normalize result

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FP Arithmetic x/ (from Stallings)

g g g g g g

Check for zero Add/subtract exponents Multiply/divide significands (watch sign) Normalize Round All intermediate results should be in double length storage

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Quantization effects: Direct - form

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Quantization effects: Gold-Rader Structure

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Quantization effects: Kingsbury Structure

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

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Quantization effects: Zlzer Structure

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

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Quantization of a FIR filter

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

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Quantization effects: Parallel implementation

Introduction to Signal Processing Santiago Marco Universitat de Barcelona

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