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Hi ngh ton quc v iu khin v T ng ho - VCCA-2011

Tch hp cc thut ton iu khin trn FPGA theo hng SOC Integration of control algorithms on FPGA in the direction of SOC
L B Dng, Bi Th Thanh Quyn Vin Cng ngh Thng tin, Vin KH&CN Vit nam e-Mail: lbdung@ioit.ac.vn Tm tt
Bi bo trnh by phng php tch hp cc thut ton iu khin nh PID, Fuzzy, thch nghivo chip FPGA. y cc qu trnh o, phn mm x l, cc b Vi x l, cc thut ton iu khin c tch hp vo mt file v c np vo FPGA theo hng SOC (System On Chip). s, cc thut iu khin, cc b Vi x l vo mt chip FPGA. N dung ca bi bo c trnh by theo: i) Phn m u, ii) Tip cn h thng, iii) Xy dng, thit k cc h thng th nghim o v iu khin trn cng ngh FPGA v phn iv) Kt lun

2. Tip cn h thng
Cc h thng o lng, x l s liu v iu khin bao gm rt nhiu thnh phn. Vic tch hp cc thnh phn ca h thng iu khin vo mt file cn phi c thc hin theo nhng yu cu nht nh v theo nhng trnh t nht nh. 2.1 Thit k cc Vi iu khin theo VHDL Ni chung t trc n nay chng ta thng lm quyen vi cc b Vi x l cng: B vi x l ARM, b vi x l 8051 vic thit k cc thit b o, iu
PIC.vhd

Abstract:
The article presents the method of integration of control algorithms such as PID, Fuzzy, adapted ... the FPGA chip. Here the process of measuring, processing software, the microprocessor, the control algorithms ... integrated into a file and loaded into the FPGA in the direction of SOC (System On Chip).

K hiu
K hiu yd(t) yp(t) e(t) de(t) u(t) n v ngha Gi tr t, gi tr cn Tn hiu ra ca h thng iu khin Sai lch iu khin=yd(t)yp(t) o hm ca sai lch iu khin Tc ng iu khin

Prom.vhd

Core.vhd

Dram.vhd

H.2

S phn cp thc th

Ch vit tt
SOC VHDL FPGA PIC System on chip Very High speed intergrated circuit Hardware Description Language Field Programmable Gate Array Programmable Intelligent Computer

1. M u
Xy dng v thit k cc thit b iu khin cha ng tt c cc thnh phn o, x l s, cc thut ton iu khin. c tch hp vo mt file v sau np vo FPGA l mt trong nhng ni dung nghin cu, pht trin trong nhng nm gn y. Trn th trng, nh thy c rt nhiu thit b vi kch c rt nh nhng cha ng rt nhiu cc thnh phn, v d cc thit b di ng bao gm rt nhiu chc nng thu, pht, x l cuc gi, son tho vn bncc thnh phn ca thit b c tch hp trn mt chip, thu nh ng k thit b v mt vt l v hn th na cc thit b cn mang tnh thng minh cao rt ph hp cho cc dch v a phng tin. Bi bo trnh by phng php tch hp cc thnh phn o, x l

khin thng xut pht t cc b Vi x l c sn nh vy. Tuy nhin bn cnh cc b Vi x l c sn chng ta cn thy tn ti cc b Vi x l mm (soft core) c vit trn ngn ng VHDL vi d trn H. 1 l cu trc ca b vi x l PIC. Microchip PIC xy dng trn FPGA bng ngn ng VHDL thc hin mch logic t hp c chc nng ging nh cc tnh nng ca mt con chip PIC ca hng Microchip. Thit k bao gm bn thc th l PIC, Prom, Dram, v Core. Thc th PIC l thc th mc cao nht (top level) bao cha cc thc th cn li. Cc thc th ny c thc hin trong cc tp tin c tn tng ng vi tn ca thc th v c ui l .vhd. H. 1 m t s phn cp thc th ca thit k. 2.2 Thc th PIC, Core, Prom, Dram Thc th PIC c khai bo theo cu trc ca VHDL, trong thc th ny khai bo c cha cc thc th cn li ca h thng. Cc thc th ca lp di l Core, Dram, Prom c tch hp trong thc th PIC v c dng tng th trn H.2. Vic xy dng cc file .vhd trn cn phi c nghin cu t m, phi th nghim nhiu ln vi cc tnh hung khc nhau, th hin y cc chc nng ca b Vi iu khin.
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Hi ngh ton quc v iu khin v T ng ho - VCCA-2011


S c ci t nh sau: void main( void ) { //Cu hnh choTIMER) //Chp nhn ngt TIMER0 // Chp nhn ngt . // To TASK 1 . // nh thi } 3.1.2 ng dng h a tc nghip cho iu khin mt nt giao thng xy dng mt h x l a tc v cho iu khin cc n xanh v b m .cho mt nt giao thng, chng ti thc hin nh sau: Mi mt hng i l mt tc v cho thc hin cc cng vic. Bt n xanh hay . Thc him m li theo mt khong thi gian nht nh cho thi gian i hay thi gian c php i. Mi mt nt giao thng c th c n 5 tc v. Kh nng thc hin s lng ln cc tc v ph thuc vo thi gian x l ca b Vi iu khin. Trn H. 4. cho kt qu th nghim nhng h x l a tc v vo FPGA chy trn KIT spartan 3E. S thut ton cho mt tc v trn H.6

H.2

S tch hp cc thc th

3. Xy dng, thit k cc h thng th nghim o v iu khin trn cng ngh FPGA theo hng SOC
Sau khi xy dng c cc thnh phn ca b Vi iu khin mm, chng ta c th thit k cc h thng o v x l s liu v iu khin 3.1 H thng tch hp a tc v thi gian thc trn cng ngh FPGA Ngy nay cc h tc nghip trn cc h nhng cng c thit k x l a tc v [1,2,3]. Cc h tc nghip x l a tc v l phn mm iu khin chuyn dng thng c dng trong nhng ng dng in ton nhng c ti nguyn b nh hn ch v yu cu ngt ngho v thi gian p ng tc thi, tnh sn sng cao v kh nng t kim sot mt cch chnh xc. p ng cc yu cu cng nh tch hp vo FPGA, cc Modules thc th ca b Vi iu khin cn c nhng vo FPGA bao gm: Modul thc th chia tn Module thc th Vi iu khin Module thc th DRAM Module thc th chng trnh a tc v Tu theo thit k, cc Modules ny c th vit trn VHDL, verlog, hoc vit trn C Trong h th nghim ny chng ti s dng 2 ngn ng l VHDL v C. 3.1.1 Thit k chng trnh iu khin a tc v. Trn Hnh 3 miu t s thut ton cho h thng x l a tc v
Bt u

H.4

M phng kt qu thc hin hai tc v trn KIT FPGA.

3.2 Thit k h iu khin m cho iu khin nhit trn cng ngh FPGA. S thit k h iu khin m c th hin trn H.5

Khi to Salvo v LCD cng cc thanh ghi

To cc TASK

H.5
nh thi cc TASK

S d khi b iu khin m

Chy TASK thch hp

H.3

S thut ton

Theo H 5 cc thnh phn ca b iu khin m gm: H s t l u vo Qu trnh m ho Suy din m trn c s h lut Gii m H s t l u ra

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Hi ngh ton quc v iu khin v T ng ho - VCCA-2011


Bt u

t con tr ca LCD v u dng

ng BLUE_1=48?

Sai

Xut chui k t ra mn hnh

Xut chui k t ra mn hnh

Chuyn i hng n v v hng chc ca RED_1 thnh m ASCII

Chuyn hng n v v hng chc ca BLUE_1 thnh m ASCII

Xut RED_1 ra mn hnh

Xut BLUE_1 ra mn hinh

ng RED_1=0?

Sai

ng BLUE_1=0?

Sai

Gim BLUE_1 i mt

Gim RED_1 i mt

BLUE_1=48 RED_1=32

Gim BLUE_1 i mt

TR 1s

H.6

S thut ton cho mt tc v Ri: if e is NB and de is PS then u is PS

Trn H.7 l s ca b iu khin m s dng FPGA.

H.7

S thit k b iu khin m s dng cng ngh FPGA

Bng 1 H lut cho b iu khin m

H lut ca b iu khin m c xy dng theo bng 1. T bng 1 cc tn hiu vo c biu din cho nhit o c v c m ho bi NB (Negative big), NS (Negative small), Z (zero), PB (Positive big), PS (Positive small). H lut iu khin m c biu din di dng bng 1 trong e l sai lch iu khin gia nhit o c vi nhit t, de l tc thay i ca sai lch iu khin v u l tc ng iu khin th hin thi im th k v lut th i c dng:

H.8

Ma trn suy din ca b iu khin m

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H,8 l s lp t h thng iu khin. [2] Le Ba Dung, Bui Nguyen Dai: A real time multitasking operating software based on IBM PC for data acquisition, processing and control. The Sixth National Conference on Automation VICA 6, H ni, 2005. L B Dng, Bi Nguyn i, Trn Th Hong. Xy dng h thng nhng a nhim v thit k my tnh n Board vi vi x l Intel x86. Tuyn tp Hi tho CNTT, Hi phng, 2005 L B Dng, Bo co ti Thit k B x l chuyn dng cho o lng v iu khin. Vin KH&CN Vit nam 2009

[3]

[4]
H.9 S thit k phn cng

Trn H.10 l kt qu ca h iu khin m cho nhit th nghim trn cng ngh FPGA.

L.B.Dng tt nghip i hc CVUT Praha nm 1974 v Ph.D ti Vin CNTT Vin KHCN Vit nam nm 1996. Nm 1986-1987 Cng tc vin KH ti Vin L thuyt thng tin v t ng ho, Vin Hn lm KH Tip khc. Nm 19891990 Cng tc vin KH ti Vin KFKI, Vin hn lm KH Hungary. Cc vn lnh vc KH quan tm hin nay l xy dng cc h thng minh t d liu, cc h m, n ron v gii thut di truyn, cc Cng ngh FPGA v hng SOC.
H.10 Kt qu th nghim cho iu khin nhit s dng cng ngh FPGA

4. Kt lun
Bi bo trnh by mt phng php thit k h o, x l v iu khin tch hp vo cng ngh FPGA. y l mt hng nghin cu mi, rt c ngha trong o lng v iu khin. N cho php khai thc c th mnh ca k thut lp trnh v phn cng ca cng ngh. Tc gi xin chn thnh cm n cc ti H th nghim o v gim st qu trnh qua Internet s dng FPGA v Nghin cu xy dng h thng tch hp a dch v trn nn mng di ng khng dy bng thng rng WiMAX 4G c v, h tr kinh ph thc hin c kt qu qu trnh nghin cu.

T. T. Quyen Bui received her B.S. and M.S. degrees in Hanoi University of Technology, Vietnam, in 2001 and 2006, respectively. She is currently a Ph.D. program student in the School of Mechanical Engineering, Pusan National University, Korea. Her research interests include robotics, vision systems, and navigation of autonomous vehicles.

Ti liu tham kho


[1] L B Dng. B vi diu khin PIC16F84 v phn mm tc nghip thi gian thc cho thu thp x l d liu v iu khin. Tp ch Khoa hc cng ngh (6 trng H) s 44-45 tr. 32-36

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