CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024

Data sheet acquired from Harris Semiconductor SCHS202C

November 1997 - Revised October 2003

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

Description
The HC4024 and HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave ip-ops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

Features
Fully Static Operation

[ /Title (CD74 HC402 4, CD74 HCT40 24) /Subject (High Speed CMOS

Buffered Inputs Common Reset Negative Edge Clocking Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH

Ordering Information
PART NUMBER CD54HC4024F3A CD54HCT4024F3A CD74HC4024E CD74HC4024M CD74HC4024MT CD74HC4024M96 CD74HC4024PW CD74HC4024PWR CD74HC4024PWT CD74HCT4024E CD74HCT4024M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld PDIP 14 Ld SOIC

NOTE: When ordering, use the entire part number. The sufxes 96 and R denote tape and reel. The sufx T denotes a small-quantity reel of 250.

Pinout
CD54HC4024, CD54HCT4024 (CERDIP) CD74HC4024 (PDIP, SOIC, TSSOP) CD74HCT4024 (PDIP, SOIC) TOP VIEW
CP 1 MR 2 Q7 3 Q6 4 Q5 5 Q4 6 GND 7 14 VCC 13 NC 12 Q1 11 Q2 10 NC 9 Q3 8 NC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2003, Texas Instruments Incorporated

CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 Functional Diagram

12 1 11 Q2 9 Q3 6 Q4 5 Q5 MR 2 4 Q6 3 Q7

Q1

CP

TRUTH TABLE CP COUNT X MR L L H OUTPUT STATE No Change Advance to Next State All Outputs Are Low

H = High Voltage Level, L = Low Voltage Level, X = Dont Care, = Transition from Low to High Level, = Transition from High to Low.

Logic Diagram
1 CP CP Q 1 Q1 CP Q R 2 MR CP Q 2 CP Q R CP Q 3 CP Q R CP Q 4 CP Q R CP Q 5 CP Q R CP Q 6 CP Q R CP Q 7 CP Q R

7 GND 14 VCC Q1 12 Q2 11 Q3 9 Q4 6 Q5 5 Q6 4 Q7 3

CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024

Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA

Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . 86 PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . 113 (Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024

DC Electrical Specications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

VCC (V)

-4

4.5

3.98

3.84

3.7

0.02

4.5

0.1

0.1

0.1

4.5

0.26

0.33

0.4

0 0 -

5.5 5.5 4.5 to 5.5

100

0.1 8 360

1 80 450

1 160 490

A A A

HCT Input Loading Table

INPUT CP, MR UNIT LOADS 0.5

NOTE: Unit Load is ICC limit specied in DC Electrical Table, e.g., 360A max at 25oC.

Prerequisite for Switching Specications

25oC PARAMETER HC TYPES Maximum Input Pulse Frequency fMAX 2 4.5 6 Input Pulse Width tW 2 4.5 6 Reset Removal Time tREM 2 4.5 6 6 30 35 80 16 14 50 10 9 5 24 29 100 20 17 65 13 11 4 20 24 120 24 20 75 15 13 MHz MHz MHz ns ns ns ns ns ns SYMBOL VCC (V) MIN MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS

CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024

Prerequisite for Switching Specications
PARAMETER Reset Pulse Width SYMBOL tW VCC (V) 2 4.5 6 HCT TYPES Maximum Input Pulse Frequency Input Pulse Width Reset Recovery Time Reset Pulse Width fMAX tW tREC tW 4.5 4.5 4.5 4.5 25 20 10 20 20 25 13 25 16 30 15 30 MHz ns ns ns (Continued) 25oC MIN 80 16 14 MAX -40oC TO 85oC MIN 100 20 17 MAX -55oC TO 125oC MIN 120 24 20 MAX UNITS ns ns ns

Switching Specications Input tr, tf = 6ns

PARAMETER HC TYPES Propagation Delay Time (Figure 1) CP to Q1 Output CL =15pF CL = 50pF Qn to Qn + 1 tPLH, tPHL CL = 50pF tPLH, tPHL CL = 50pF 2 4.5 5 6 2 4.5 CL =15pF CL = 50pF MR to Qn tPLH, tPHL CL = 50pF 5 6 2 4.5 5 6 Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 2 4.5 6 Input Capacitance Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay Time (Figure 2) CP to Q1 Output Qn to Qn + 1 tPLH, tPHL tPLH, tPHL tPLH, tPHL CL = 50pF CL =15pF CL = 50pF CL =15pF CL = 50pF CL =15pF 4.5 5 4.5 5 4.5 5 17 6 17 40 15 40 50 19 50 60 22 60 ns ns ns ns ns ns CIN CPD CL = 50pF CL =15pF 5 11 6 14 30 140 28 24 75 15 13 170 34 29 75 15 13 10 175 35 30 95 19 13 215 43 27 95 19 16 10 210 42 36 110 22 19 255 51 43 110 22 19 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF TEST SYMBOL CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

MR to Qn

CD54/74HC4024, CD54/74HCT4024
Switching Specications Input tr, tf = 6ns
PARAMETER Output Transition Input Capacitance Power Dissipation Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi + (CLVCC2 fi/M) where: M = 21, 22, 23, 24,25, 26, 27 fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. (Continued) VCC (V) 4.5 5 25oC MIN TYP 30 MAX 15 10 -40oC TO 85oC -55oC TO 125oC MIN MAX 19 10 MIN MAX 22 10 UNITS ns pF pF

TEST SYMBOL CONDITIONS tTLH, tTHL CL = 50pF CIN CPD CL =15pF CL =15pF

Test Circuits and Waveforms

trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK trCL = 6ns tWL + tWH = tfCL = 6ns 2.7V 0.3V I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH

tr = 6ns INPUT 90% 50% 10%

tf = 6ns VCC

tr = 6ns INPUT GND 2.7V 1.3V 0.3V

tf = 6ns 3V

GND tTLH 90%

tTHL

tTLH 90% 50% 10% tPHL tPLH

tTHL

INVERTING OUTPUT

INVERTING OUTPUT tPHL tPLH

1.3V 10%

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

PACKAGING INFORMATION
Orderable Device CD54HC4024F CD54HCT4024F3A CD74HC4024E CD74HC4024EE4 CD74HC4024M CD74HC4024M96 CD74HC4024M96E4 CD74HC4024M96G4 CD74HC4024ME4 CD74HC4024MG4 CD74HC4024MT CD74HC4024MTE4 CD74HC4024MTG4 CD74HC4024PW CD74HC4024PWE4 CD74HC4024PWG4 CD74HC4024PWR CD74HC4024PWRE4 CD74HC4024PWRG4 CD74HC4024PWT CD74HC4024PWTE4 CD74HC4024PWTG4 CD74HCT4024E CD74HCT4024EE4 CD74HCT4024M CD74HCT4024ME4 Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP PDIP PDIP SOIC SOIC Package Drawing J J N N D D D D D D D D D PW PW PW PW PW PW PW PW PW N N D D Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 1 1 25 25 50 TBD TBD Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Lead/Ball Finish A42 A42 CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 250 250 250 90 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 250 250 250 25 25 50 50 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS &

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Orderable Device

Status (1)

Package Type SOIC

Package Drawing D

Pins Package Eco Plan (2) Qty no Sb/Br) 14 50 Green (RoHS & no Sb/Br)

Lead/Ball Finish

MSL Peak Temp (3)

CD74HCT4024MG4
(1)

ACTIVE

CU NIPDAU

Level-1-260C-UNLIM

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Aug-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC TSSOP TSSOP D D PW PW 14 14 14 14

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 16.4 16.4 12.4 12.4 6.5 6.5 6.9 6.9

B0 (mm) 9.0 9.0 5.6 5.6

K0 (mm) 2.1 2.1 1.6 1.6

P1 (mm) 8.0 8.0 8.0 8.0

W Pin1 (mm) Quadrant 16.0 16.0 12.0 12.0 Q1 Q1 Q1 Q1

CD74HC4024M96 CD74HC4024MT CD74HC4024PWR CD74HC4024PWT

2500 250 2000 250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Aug-2010

*All dimensions are nominal

Device CD74HC4024M96 CD74HC4024MT CD74HC4024PWR CD74HC4024PWT

Package Type SOIC SOIC TSSOP TSSOP

Package Drawing D D PW PW

Pins 14 14 14 14

SPQ 2500 250 2000 250

Length (mm) 346.0 346.0 346.0 346.0

Width (mm) 346.0 346.0 346.0 346.0

Height (mm) 33.0 33.0 29.0 29.0

Pack Materials-Page 2

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