Low Cost Flip Chip Bumping Technologies

CL Wong and James How Advance Manufacturing System & Technology Motorola Electronics Pte Ltd 10 Ang MO Kio St 64, Ang MO Kio Industrial Park3, Singapore 569087

Abstract The 97Pb 13Sn solder bump flip chip metallurgy based on the evaporative technology is one of the driving factors of miniaturization in portable electronic products due to its size and its compatibility with the surface mount technology. However, it is relatively a high cost IC packaging option due to the inherent expensive bumping cost , couple with the high PCB cost which requires 63Snl37Pb eutectic bumping. As such, various low cost bumping option were presently been developed. They are the printed solder bump, electroplated eutectic solder bump, gold stud bumping and the electroless Ni I Au bump. The bumping methods and the assembly methods of these various flip chips onto substrates are described and presented. The gold ( Au ) stud bump, which is based on the wire bonding technology offers a low cost flip chip solution for low I10 count ICs. The unconventional method of assembling this Au stud bump flip chip on a substrate based on the direct thermocompression technology is presented in detail. Lastly, the electroless Ni I Au bump, used in conjuction with Anisotropic Conductive paste or film, is also presented. This combination is expected to yield the lowest cost flip chip option. Introduction Flip Chip on Board process specifically refers to the interconnection of unpackaged integrated circuits directly to an organic substrate. The present conventional solder based flip chip is typically of the evaporated high lead solder bump. This flip chip assembly is also known as the C4 ( Control Collapse Chip Connection ) assembly. As the high lead solder bump do not melt at the normal surface mount reflow temperatures, eutectic solder bumps are required at the corresponding flip chip site on the PCB substrate. Figure 1 shows the cross-sectional view of the flip chip on board configuration.

temperature solder bumps of the chip does not melt and it provides a standoff between the chip and the board. Figure 2 shows a cross-sectional picture of a C4 flip chip structure.

400x mayjnificalion

Figure 2 : Schematic of the C4 flip chip on board structure after reflow. The evaporative solder based flip chip is a relatively higher cost flip chip option. This is because of 2 main reasons : i) the evaporative solder bumps are expensive due to the high capital cost of evaporative technology. ii) the need for eutectic bumps on the PCB substrates increases the PCB cost significantly. Because of the high cost of this type of flip chip assembly, flip chip implementation into products has not been very aggressive. In order to achieve both miniaturization and cost advantages, newer low cost bumping technologies for flip chip has been developed by the industry. In this paper, the evaporative solder bump technology is first being discussed, followed by other low cost bumping technologies.

97Pb I 3 5n a 3 S n i37Pb

Figure 1 : Hip chip on board configuration The flip chip attachment to the PCB substrate is done during the reflow process. At temperatures above 183 C, eutectic solder on the substrate will melt and wet up to the high lead solder bumps of the flip chip, forming an interconnection between the chip and the PCB. The high

2. Evaporate Solder Bumping Technology The evaporate solder bumping technology is the most common bumping technology presently been used in flip chip assemblies.. The metallurgy of the bump on the die is 95Pbl 5 Sn or 97Pbl 3Sn. The bump structure was originally used on ceramic substrates. However, its application has now expanded to organic substrates with the requirement of an eutectic 63Sn I 37Pb bump on the organic substrates. The process flow for the Evaporative Solder Bumping process is shown in Figure 3.

0-78034157-0/97 $10.00 01997 IEEE

244

1997 IEEVCPMT Electronic PackagingTechnology Conference

umping echnology
vaporated igh Lead 'nted solder lectroplated
U Stud bumping

COSt/g'' wafer

CostLDie
$1.00

$200
$120

$0.60
$0.40

$80

$70
$10

$0.35

UBM Evaporation

i/Au

Table 1.0 : Generic cost comparison of the various bumping technologies.

High Pb Evaporation

n
Reflow
Figure 3 : Evaporative solder bumping process The solder bump is deposited on the wafer through a molybdenum metal mask. The molybdenum metal mask are first aligned to the bond pads on the wafer and clamped. The assembly is then mounted in an evaporator. The first process is the cleaning process which purpose is to remove all the oxides on the wafer. Thereafter, the sequential evaporation of a chromiuin layer, a phased chromium / copper layer, a copper layer and a Au layer are deposited to form the UBM . A high lead solder is then evaporated on top of the UBM. The wafer is the send for reflow whereby the high lead structure will melt and form a sphere shaped solder bump.

3.1 Printed Solder Paste Bump Technology 3.1.1 Bumping Method The printed solder paste bumping technology takes many forms. Figure 4 explains the approach that was developed by Delco.

UBM sputtering

t
Dry Resist application

Resist Patterning

Solder paste printing

3. Low Cost Flip Chip Bumping Options The low cost bumping technologies that would be presented in this paper are: i) Printed solder bump technology ii) Electroplated solder bump technology iii) Stud bumping technology iv) Electroless NickeYGold bumping technology
Table 1.O details the cost comparison of these technologies as oppose to the common evaporative bumping technology.

245

1997 IEEVCPMT Electronic PackagingTechnology Conference

A1

TiWICu

Reflow
UBM Sputtering

Strip Resist
Figure 4 : Printed Solder Paste Bump Process The first process is the formation of the UBM by sputtering. The UBM is made up of 3 sputtering process whereby Aluminium ( A1 ), followed by Nickel ( Ni ) and Copper (Cu ) is deposited on the Aluminum pads. The next process involves applying a dry film resist on the wafer. The resist is patterned and develop to expose the pads. Solder paste is then printed into the resist film openings. The wafer is then send for reflow whereby the paste will melt and form a spherical eutectic shaped solder balls.The advantage of this process beside its obviously low cost is that this process allows for good metallurgical control. Besides, many different solder metallurgy could be experimented to determine the best alloy combination for a particular flip chip assembly. The disadvantage of this process is the pitch limitation of the solder printing process. At present, the smallest pitch that could be achieve is approximately 200 microns.
Photoresist application, patterning & developing

Electroplate Cu

&=!!a
Solder Electroplate solder Strip Photoresist & Etch UBM

3.1.2 Assembly Method The flip chip assembly for the eutectic solder bumps are very similar to the high lead evaporative solder bump. The only difference between the two is that the printed eutectic solder bumps do not require bumping on the PCB substrates. The detail assembly process is shown in Figure 5.

*
Fluxing Fli Chi Placement Reflow

U
Reflow

Figure 6 : Electroplating bumping process. Figure 5 : Process flow for solder bump fiip chip assembly. Incoming wafers are first inspected and ultrasonic cleaned. Then the adhesion and seed layers of Titanium and copper are deposited. Next, the wafer is coated with a plating resist. The resist is subsequently masked, exposed and developed. Additional copper is electroplated to build up the copper stud bump base. Eutectic solder is then plated on top of the copper stud bump until it reaches the top of the resist. Next, the plating resist is strip away and thereafter, the seed and adhesion layers are etched away.

3.2 Electroplated Solder Bump Technology 3.2.1 Bumping Method The electroplated process is shown in Figure 6. This process is attractive due to its lower equipment cost.

246

1997 IEEWCPMT Electronic Packaging Technology Conference

The plated bumps are then send for reflow, resulting in a spherical shaped bump.

3.2.2 Assembly Method The assembly process for the electroplated eutectic solder bump flip chip is similar to the printed eutectic solder bump flip chip. This is because the metallurgy of the bumps are the same, regardless of the way it was process in the wafer fabs. The assembly process flow is similar to that of figure 5. 3.3 Stud Bumping Technology 3.3.1 Bumping Method The process of Au stud bumping is perform with a modified wire bonder. The advantage of this process is that Au bumping is done directly on the Aluminium pad and no UBM is required, resulting in significant cost savings. The process employs the single pad bumping technology derived from ball bonding of gold wires. After formation of the ball and the first bond, normally the next step for conventional wire bonding is loop formation followed by the second bond. Instead of this, the ball bumping will break off the wire above the ball.
The complete process for Au stud bumping is shown in Figure 7.

Figure 8 : SEM picture of the Au stud bump before coining.

Figure 9 : SEM picture of the Au stud bump after coining. The primary advantage of stud bumping technology is the significant lower bumping cost for lower I/O counts ICs. For higher count I/Os, this process is not feasible as the stud bumping process is a serial process.

3..3.2 Assembly method In order to attach the die to the substrate, two ( 2 ) methods could be employed. The first is the typical industry method of using conductive adhesive as an interconnect material to attach the Au bump to the substrates as depicted in Figure 10.

t
Bump formation

start

Alignment

Bumping

Retract
ctive ive Transfer & Apply ConductiveAdhesive

L
Retract

Coining

Figure 7 : Stud bumping process flow Figure 8 and figure 9 shows the SEM picture of a Au stud bump before and after the coining process. The height of the Au bump after coining is approximately 25 um.

Mounting

Underfilling

Figure 10 : Stud bumping with conductive adhesive process assembly

247

1997 IEEVCPMT Electronic PackagingTechnologyConference

The second method is by using thermocompression method to attach the Au bumps to the substrate. The thermocompression method of attachment was fully investigated as this process was found to be very cost effective due to the fine pitch processability. The first method of attachment via conductive adhesive is done by dipping the Au bumps with conductive adhesive, placing the chip on the substrate and thereafter, curing the conductive adhesive. Lastly, the chip is underfilled. The process is shown in Figure 10. The second method of attaching the gold stud bump flip chip to a substrate is done by the thermocompression process. The attachment is between the gold ( Au ) bump on the die to a Tin ( Sn ) on Copper ( Cu ) substrate. The substrate under investigation is a flexible substrate which is a polymide substrate with copper runners and immersion tin ( Sn ) plating finish. The polymide thickness is 25 um with 10 to 15 um copper and a tin plating finish of less than 1.0 um thick. Thermocompression is a process in which a liquid - phase bonding is achieve between two opposing components subjected to compressive force under temperature for a predetermine amount of time. To achieve bonding, heat is transfer through these two components to bring the tin on the substrate to a liquid state. During this state, the tin will wet to the gold ( Au ) bump and form a reliable metallurgy. In order to achieve this, the interface between the bump and the substrate needs to be elevated to the melting point of tin, which is at 232 C. The bonding sequence is such that the bonder picks up a die, aligns the die and bonds the die to the substrate under temperature and pressure. The bonding machine requires a top and bottom heater in-order to achieve the required temperature and pressure for reliable bonding. The configuration of the heaters are as shown in Figure 11. The temperature settings on the top and bottom heater must be such that the melting point of tin is reached, in-order to provide metallurgical reaction between tin and gold. Figure 12 shows a crosssectional view of the Au/Sn metallurgy. Figure 12 : Cross-sectional picture of AdSn metallurgy.

3.4 Electroless Nickel / Gold bumping Technology 3.4.1 Bumping Method In the electroless nickel / gold plating process, no external voltage is applied to the wafers for plating as oppose to the electroplated process. Because of the ease of processing whereby the wafers are dipped in a series of plating baths, this process is significantly less expensive compared to other bumping technologies. Figure 13 shows the Electroless nickel / gold process.

A1 Si

Passivation

Aluminium Cleaning

Zn

t
t

Zincation

Nickel Deposition

Chip

4+ X, Y & theta adiustment

U

Bottom Heater

Au Coating Figure 13 : Electroless Ni I Au bumping process.

The first step is the cleaning process whereby the aluminium bond pads is stripped of any oxides by either acidic or alkaline etch. After cleaning, the wafers is subjected to zincate treatment inorder to prepare the Aluminium pads for nickel deposition. This is done in a zinc bath which deposits zinc crystals on the Aluminium

Figure 11 : Thermocompression bonding process for Au bump to Sn substrate.

248

1997 IEEWCPMT Electronic PackagingTechnologyConference

which will initiate the nickel plating. The wafers are then send for nickel deposition in a nickel bath. Once the nickel is plated to a desirable height, a flash of gold is deposited on the nickel bump to prevent oxidation of the nickel. In order to attach the Ni bumps to the substrate, two approach could be utilized. The first is to apply eutectic solder on the Ni bump. In this instant, the Ni bump acts as a UBM. The second approach of attachment is that this chip could be used with Anisotropic Conductive Film to provide an electrical contact to the substrate. Figure 14 shows a picture of the electroless Ni / Au bumps, with a bump pitch of 60 um.

First, the ACF is pre-tag to the flip chip site on the substrate. The chip is then mounted on the substrate with pressure and temperature applied. The force that is applied results in the compression of the conductive particles under the Nickel I Au bumps and this creates an electrical connectivity between the chip and the substrate.
4. Discussion

Figure 14 : Picture of the Electroless Ni / Au bumps.

3.4.2 Assembly Method The assembly process for electroless Ni / Au bumps to the substrates depends on the type of approach used. For Ni I Au bumps with an eutectic solder cap, the method of assembly to the substrate is very similar to that of the printed eutectic solder bumps. However, for Ni / Au bumps with Anisotropic Conductive Paste ( ACP ) , the method of assembly is shown in Figure 15.
Au coated Conductive particle

As presented above, there are a variety of low cost bumping technology that could replace the present expensive high lead evaporative solder bump. Among all the low cost bumping technology, the stud bumping method is a good candidate for implementation as this gold bumping technology is mature which is based on wire bonding technology. However, this technology is not suitable for very high volume due to the nature of the serial bumping process. For high volume production, the lowest assembly cost is expected to be achieve by using Electroless Ni / Au bumps with Anisotropic Conductive paste or film. With a bumping cost of approximately $10 I wafer, this bumping method is the most cost effective and is expected be accelerate widespread flip chip implementation in the near future. However, there are a few issues regarding electroless Ni / Au bumping which needs to be resolve before this technology could be extensively used. Some of these issues are the inconsistency of the plating process and the bump formation on any metallize area due to pin holes in the passivation layers.
One interesting point to note on the stud bumping and Electroless Ni I Au bumps is that the attachment of these bumps to the substrate is done by direct bonding which is different from the conventional reflow method of assembly. The other solder based bumps from the evaporated, printed and electroplated bumping technology all requires the reflow method of assembly. One disadvantage of this method is that there is a pitch limitation on the bumps due to the nature of the reflow process. At present, the pitch limitation for reflow process is approximately 200 um. However with direct bonding using Au stud bumps or Electroless Ni / Au bumps on the substrate, the process is capable of bonding up to 50 um pitch due to the accuracy of the machine used. With this very fine pitch capability, further cost saving is achieved by shrinking the die to accommodate the fine pitch bumps. The other disadvantages of the solder bumps of evaporated, printed and electroplated is that these flip chip dies requires redistribution layers which increase the cost of the die significantly. The redistribution layer is required to redistribute the bumps from the original peripheral pattern into an array pattern in-order to increase the pitch of the bumps, due to the pitch requirement for the reflow process. On the other hand, the Au stud bumps and the Electroless Ni I Au bumps which is assembled using the direct bonding method do not require the redistribution layer. This is because the assembly process is capable of using the original bumps on the peripheral of the die. Figure 16 shows a picture of a solder bump flip chip die with the redistribution below the bumps.

/ ACP

Substrate Apply ACP

Pressure & Temperature

Flip Chip Bonding

ACP Curing

Figure 15 : Anisotropic Conductive Film / Paste process using Ni I Au bumps.

249

1997 IEEVCPMT Electronic Packaging Technology Conference

Figure 16 : Solder bump flip chip with redistribution lines.

5. Summary The present solder bump flip chip based on the evaporated technology is relatively an expensive IC packaging assembly due to the inherent high bumping cost and high PCB cost which requires bumping. Various low cost flip chip bumping options is presently been developed. These are the printed solder bump, electroplated eutectic, Gold Stud bump and the Electroless Ni / Au technology. Among all these technologies, the stud bumping offers a good low cost bumping solution for low I/O count IC's in low volume production. This technology also provides a good start to flip chip development and accelerates the learning curve of flip chip technology. However, the potential future trend for low cost, high volume production is the Electroless Ni / Au bumping. The application of this bumping with Anisotropic Conductive Paste or Film will offer the cheapest flip chip solution. However, the areas of concern in Electroless Ni /Au needs to be resolved before widespread implementation of this technology could be seen.

6. References 1. CL W-ong, " Direct Chip Attach Process for Surface Mount Applications '' , Proceedings of the 1996 Globaltronics Technical Conference.
2. CL Wong, " Flip Chip Implementation In A Manufacturing Environment , Proceedings of the 1997 SEMICON Technical Symposium, pg. 37 - 41.
"

3. Deborah Patterson, " A Comparison of Popular Flip Chip Bumping Technologies " , Proceedings of the 1997 SEMICON Technical Symposium pg. 239 - 249. 4. John H. Lau, 1995.
"

Flip Chip Technologies '' McGraw Hill,

250

1997 IEEWCPMT Electronic PackagingTechnology Conference