Allen Bradley-PLC5 Programming Guide

PLC-5
A.I. SERIES
PROGRAMMING GUIDE
December 1997 Supersedes Doc. ID 9399-L5PG-04.17.95
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1997 Rockwell Software Inc. All rights reserved
Copyright Notice
Printed in the United States of America Portions copyrighted by Allen-Bradley Company, Inc. and used with permission. This manual and any accompanying Rockwell Software products are copyrighted by Rockwell Software Inc. Any reproduction and/or distribution without prior written consent from Rockwell Software Inc. is strictly prohibited. Please refer to the license agreement for details. Trademark Notices WINtelligent Series is a registered trademark. The Rockwell Software logo, RSAssistant, RSBatch, RSData, RSLogix Emulate 5, RSLogix Emulate 500, RSGuardian, RSHarmony, RSKeys, RSLinx, RSLogix 5, RSLogix 500, RSPower, RSPowerCFG, RSPowerRUN, RSServer32, RSServer, RSServer Toolkit, RSSql, RSToolbox, RSTrainer, RSTrend, RSTune, RSView32, RSView, RSWire, A.I. Series, Advanced Interface (A.I.) Series, AdvanceDDE, ControlGuardian, ControlView, INTERCHANGE, Packed DDE, PLC-500, WINtelligent, WINtelligent EMULATE 5, WINtelligent EMULATE 500, WINtelligent LINX, WINtelligent LOGIC 5, WINtelligent VIEW, WINtelligent RECIPE, WINtelligent VISION, WINtelligent VISION2 are trademarks of Rockwell Software Inc. PLC, PLC-2, PLC-3 and PLC-5 are registered trademarks, and Data Highway Plus, DH+, DHII, DTL, Network DTL, Pyramid Integrator, PanelBuilder, PanelView, PLC-5/250, PLC-5/20E, PLC5/40E , PLC-5/80E, SLC, SLC 5/01, SLC 5/02, SLC 5/03, SLC 5/04, and SLC 500 are trademarks of the Allen-Bradley Company, Inc. Microsoft, MS-DOS, Windows, and Visual Basic are registered trademarks, and Windows NT and Microsoft Access are trademarks of the Microsoft Corporation. Ethernet is a registered trademark of Digital Equipment Corporation, Intel, and Xerox Corporation. IBM is a registered trademark of International Business Machines Corporation. AIX, PowerPC, Power Series, RISC System/6000 are trademarks of International Business Machines Corporation. UNIX is a registered trademark in the United States and other countries, licensed exclusively through X/Open Company Limited. All other trademarks are the property of their respective holders and are hereby acknowledged. Warranty This Rockwell Software product is warranted in accord with the product license. The product's performance will be affected by system configuration, the application being performed, operator control and other related factors. The product's implementation may vary among users. This manual is as up-to-date as possible at the time of printing; however, the accompanying software may have changed since that time. Rockwell Software reserves the right to change any information contained in this manual or the software at anytime without prior notice. The instructions in this manual do not claim to cover all the details or variations in the equipment, procedure, or process described, nor to provide directions for meeting every possible contingency during installation, operation, or maintenance.
Table of Contents
1 2 Introduction ........................................................................................................1-1 How to Use This Manual ................................................................................................. 1-2 Planning Programs for Your Application..........................................................2-1 Functional Specification ........................................................................................... 2-2 Detailed Analysis ..................................................................................................... 2-2 Program Entry.......................................................................................................... 2-2 Testing ..................................................................................................................... 2-3 Acceptance ............................................................................................................... 2-3 Using Main Control Programs......................................................................................... 2-4 How the Processor Interprets the MCPs .................................................................... 2-4 Configuring Main Control Programs ............................................................................... 2-6 Specifying The Order of Main Control Programs...................................................... 2-6 Disabling Main Control Programs ............................................................................ 2-6 Monitoring Main Control Programs ................................................................................ 2-7 Using Interrupt Programs ................................................................................................ 2-8 Designing Programs for Your Application........................................................3-1 Machine Example ........................................................................................................... 3-2 Creating the Functional Specification.............................................................................. 3-3 Creating the Detailed Analysis ........................................................................................ 3-5 Entering the Program ...................................................................................................... 3-9 Using Other Processor Programming Features............................................................... 3-11 Examples of Special Programming Applications..................................................... 3-12 Checking for Completeness ........................................................................................... 3-13 SFC Building Blocks ..........................................................................................4-1 SFC Building Blocks....................................................................................................... 4-1 Step.......................................................................................................................... 4-1 Transition................................................................................................................. 4-2 Simple Path.............................................................................................................. 4-2 Selection Branch ...................................................................................................... 4-3 Simultaneous Branch................................................................................................ 4-4 GOTO and Label Statements .................................................................................... 4-5 Drawing an SFC.............................................................................................................. 4-6 Example SFC ........................................................................................................... 4-8 How Selection Branches Work.................................................................................. 4-9
PLC-5 A.I. Series Software Reference
How Simultaneous Branches Work ......................................................................... 4-10 Using GOTOs and Labels ....................................................................................... 4-11 Using the SFR Instruction.............................................................................................. 4-12 5 Writing Ladder Logic......................................................................................... 5-1 Converting Machine Statements to Ladder Logic............................................................. 5-2 Rung Logic Example ................................................................................................ 5-3 Example Discrete I/O Instructions ............................................................................ 5-3 Constructing Ladder Rungs ............................................................................................. 5-5 Writing Rung Logic.................................................................................................. 5-5 Writing Branch Logic ............................................................................................... 5-7 Arranging Input Instructions ......................................................................................... 5-10 Organizing Data Table Files.............................................................................. 6-1 Understanding Data Storage ............................................................................................ 6-2 Organizing Data into Files and Data Blocks .................................................................... 6-4 Default Data Table Files .................................................................................................. 6-6 Addressing Data Table Files............................................................................. 7-1 Specifying Logical Addresses .......................................................................................... 7-2 Using Address Mnemonics ....................................................................................... 7-4 Specifying I/O Image Addresses ...................................................................................... 7-6 Specifying Indirect Addresses .......................................................................................... 7-8 Specifying Indexed Addresses........................................................................................ 7-10 Indexed Addressing Example.................................................................................. 7-11 Specifying Symbolic Addresses...................................................................................... 7-12 SoftLogix 5 Symbols............................................................................................... 7-13 Addressing Frequently Used Files.................................................................................. 7-14 Status File for PLC5/10, PLC5/12, and PLC5/15 Processors.............................. 7-15 Status File for PLC5/25 Processors....................................................................... 7-15 Using a Selectable Timed Interrupt .................................................................. 8-1 Writing STI Ladder Logic ............................................................................................... 8-2 Setting Up an STI............................................................................................................ 8-3 Storing the Location of the STI File in the Processor Status File ............................... 8-3 Block Transfers Used Within an STI......................................................................... 8-4 Using a Processor Input Interrupt .................................................................... 9-1 Writing PII Ladder Logic................................................................................................. 9-2 PII Application Examples ................................................................................................ 9-4 Using Counter Mode................................................................................................. 9-4 Using Bit Transition Mode........................................................................................ 9-4 Setting Up a PII ............................................................................................................... 9-6
ii
Table of Contents
Configuring the PII .................................................................................................. 9-6 Block Transfers Used Within a PII ........................................................................... 9-7 Monitoring a PII.............................................................................................................. 9-8 PII Return Mask ....................................................................................................... 9-8 PII Accumulator ....................................................................................................... 9-8 PII Scan Times ......................................................................................................... 9-8 10 Writing a Fault Routine ....................................................................................10-1 Using Fault Routines ..................................................................................................... 10-2 Responses to a Major Fault ..................................................................................... 10-2 Major Fault Codes .................................................................................................. 10-3 Programming a Fault Routine........................................................................................ 10-8 Set an Alarm .......................................................................................................... 10-8 Clearing the Fault................................................................................................... 10-8 Using Shutdown Logic ..........................................................................................10-10 Testing a Fault Routine .........................................................................................10-10 Setting Up a Fault Routine ...........................................................................................10-11 Enabling a Fault Routine .......................................................................................10-11 Changing the Fault Routine from Ladder Logic.....................................................10-11 Clearing a Major Fault ..........................................................................................10-12 Setting PowerUp Protection........................................................................................10-13 Allowing or Inhibiting Startup...............................................................................10-13 Using Adapter Mode.........................................................................................11-1 Using Adapter Mode ..................................................................................................... 11-2 Operating in Adapter Mode........................................................................................... 11-3 Configuring an Original PLC-5 Processor for Adapter Mode.................................. 11-3 Configuring a New Platform PLC-5 Processor for Adapter Mode............................ 11-4 Transferring Discrete I/O and Block Data ..................................................................... 11-5 Programming Discrete Data Transfers........................................................................... 11-8 Using Rack 3.......................................................................................................... 11-8 Creating an Adapter Image File - Original PLC-5 Processors ................................. 11-9 Creating an Adapter Image File - New Platform PLC-5 Processors......................... 11-9 Transferring Bits between Supervisory (PLC-2) and Adapter Processors................11-10 Determining the Status of the Adapter Processor ...................................................11-11 Determining the Status of the Supervisory Processor .............................................11-12 Programming Considerations for Using Adapter Mode.................................................11-13 Programming Block Transfers - Original PLC-5 Processors .........................................11-14 Addressing Tips for Block Transfers......................................................................11-15 Example Ladder Logic .................................................................................................11-18 Supervisory Processor (PLC2/30, PLC3, PLC5, or PLC5/250) .......................11-18 Adapter Processor (PLC5/15, 5/25)....................................................................11-23
11
iii
Adapter Processor (New Platform Processors) ....................................................... 11-24 12 Using Scanner Mode ....................................................................................... 12-1 Operating in Scanner Mode ........................................................................................... 12-1 Configuring an Original PLC5 Processor for Scanner Mode.................................. 12-1 Configuring a New Platform PLC5 Processor for Scanner Mode ........................... 12-1 Transferring Discrete Data ............................................................................................ 12-2 Transferring Block Data ................................................................................................ 12-3 Queued Block Transfer Requests............................................................................. 12-4 Block Transfers to Local I/O ................................................................................... 12-4 Block Transfers to Remote I/O................................................................................ 12-4 Block Transfers in Fault Routines or Selectable Timed Interrupts (STIs)................. 12-5 Block Transfer Sequence Original PLC-5 Processors ..................................................... 12-6 Block Transfer Sequence New Platform PLC-5 Processors............................................. 12-8 Block Transfer Sequence with Status Bits ............................................................... 12-9 Block Transfer Timing: Original PLC-5 Processors .................................................... 12-11 Instruction Run Time............................................................................................ 12-11 Waiting Time in the Queue................................................................................... 12-11 Transfer Time....................................................................................................... 12-11 Block Transfer Timing: New Platform PLC-5 Processors............................................ 12-12 Instruction Run Time............................................................................................ 12-12 Waiting Time in the Holding Area........................................................................ 12-12 Transfer Time....................................................................................................... 12-12 When the Processor Detects a Major Fault ................................................................... 12-13 When a Resident Local I/O Rack Faults....................................................................... 12-14 When a Remote I/O Rack Faults .................................................................................. 12-15 Recovering from a Resident Local I/O or Remote I/O Rack Fault................................. 12-16 Using I/O Status File Bits to Monitor Rack Faults................................................. 12-16 Using Fault Routine and Ladder Logic to Recover................................................. 12-17
Index
iv
Introduction
Introduction
This manual provides you with information about programming the AllenBradley PLC5 family of programmable logic controllers. This information includes: Planning your projects Basics of SFC programming Basics of ladder logic programming Basics of the PLC5 data table, including the various methods you can use to address data table files Using selectable timed interrupts, processor input interrupts, and fault routines Setting up the processor for adapter and scanner mode Programming through a serial port
Note
Command Portal keys for this function: .UUKI
For information on the PLC5 instruction set, see the Instruction Set Reference or the instruction set help in the software (from the Online or Offline Editor, select [F6] Utility, [F9] Util2, [F7] Keyconf, [F4] Inshelp or press [Shift-F10]). PLC-5 processors can be grouped into three categories: Original (classic ), New Platform (NP5 or Enhanced), and Secure. As much as possible, this manual will refer to a group of processors rather than listing individual models. The table below lists the different processors in each category. (The processor type given includes all variants of that processor: L-Local, E-Ethernet, C-ControlNet, and V-VME.)
Original PLC-5/10 PLC-5/12 PLC-5/15 PLC-5/25 PLC-5/VME New Platform PLC-5/11 PLC-5/20 PLC-5/30 PLC-5/40 PLC-5/60 PLC-5/80 Secure PLC-5/16 PLC-5/26 PLC-5/36 PLC-5/46 PLC-5/66 PLC-5/86
1-1
PLC-5 A.I. Series Programming Guide
How to Use This Manual

This manual is a guide to programming the PLC5 family of programmable logic controllers. While this manual will not tell you everything about PLC5 programming, it does discuss the major program structures that you can use in your projects. Before you begin with your PLC5 project, read through Chapter 2 Planning Programs for Your Application. This chapter describes an AllenBradley recommended procedure for developing PLC5 programs using multiple main control programs. While much of the material in that chapter is devoted to New Platform and Secure PLC-5 processors, a great deal of the information applies to Original PLC-5 processors as well. For those using one main control program, or for those using earlier PLC5 processors, Chapter 3 Designing Programs for Your Application contains the AllenBradley recommended procedure for developing programs. Chapter 4 SFC Building Blocks describes the components of Sequential Function Charts. If your processor supports SFC programming, this chapter can help you get started with SFCs. The rest of the manual is to be used as a guidethe first place to turn when you have questions about: Using interrupt programs (selectable timed interrupts and program input interrupts) PLC-5 data table structures Adapter and scanner mode Serial port programming
1-2
Planning Programs for Your Application

AllenBradley recommends that you develop a design specification for your programming application. The design specification is a conceptual view of your application and is used to determine your sequential function chart (SFC) and ladder logic requirements. This chapter gives you an overview on how to plan your design specification for your processor; the next two chapters give you more specific detail to prepare your design specification. In planning and developing the programs for your application, we recommend that you use the Program Development model shown below.
Functional Specification
(general conception)
Acceptance Sign-off
Detailed Anaylsis
Testing
Program Development
Each box represents an activity that you perform. Begin with the functional specification, and move on to the detailed analysis. Based on the detailed analysis, you can enter your programs and test them. When testing is complete, you are ready to implement the programs in your application. This model also allows for interaction of the activities at the different levels. The detailed analysis can be used as the basis for developing your testing procedures and requirements. And, because the functional specification is well thought out, it can be used as the program signoff document.
2-1
Not all machine processes can be controlled with an SFC implementation; the following description of the program development model is generalized to fit most processes. The power of an SFC is that it is a descriptive programming language that you can use to describe your process in terms of machine states and transition conditions. Because this description executes your process control, your SFC provides the link between these two legs of the development model.
Functional Specification
The functional specification represents a very general view of your process or a description of operation. Identify the events and the overall order in which they must occur. This functional specification can be in any form: written statements, flowcharts, or rough-draft sequential function charts (SFC). Use the form that is most familiar to you. AllenBradley recommends that you generate a rough-draft SFC so that you have a better correspondence between your beginning diagrams and your finished program.
Detailed Analysis
In this phase, you take the functional specification and add the details of your process. Identify your inputs and outputs, specific actions and transitions between actions (that is, the bit-level details needed to write your program. If you are using a New Platform or Secure PLC-5 processor, you also determine the number of Main Control Programs (MCPs) and the programming method for each during this phase. Use MCPs when you are describing your process in terms of function or in terms of geography. You then break down those functions into ladder programs, sequential function charts (SFCs), or structured text. For typical SFC applications, an SFC program controls the order of events in your process by issuing commands. A command, such as fwd_conv_cmd to move a conveyor forward, is simply a data table storage bit (for example B3:0/7) which you set up in the SFC. You then program the ladder logic for fwd_conv_cmd in a separate ladder program to control the actual outputs to move the conveyor. The ability to have one SFC program defining the sequence and then separate ladder logic programs controlling outputs is the basis of New Platform and Secure PLC-5 processors main control program feature. For more information on this feature, see the next section, titled Using Main Control Programs. If you are using an Original PLC-5 processor, note that you can have only one main program. For information on planning a design specification using only one main program, see Chapter 3 Planning Programs for Your Application.
2-2
Program Entry
In this phase, you enter the programs into your computer using the SFC Editor, Ladder Editor, or Structured Text Editor. For more information on entering SFCs, ladder logic, or structured text, see the PLC5 A.I. Series Software Reference manual.
Testing
In this phase, you test the programs you have entered. You may want to consider using RSLogix Emulate 5 processor emulation to simulate your system.
Acceptance
Once testing is complete, your resulting programs should match your functional specification.
2-3
Using Main Control Programs

New Platform and Secure processors only New Platform and Secure PLC-5 processors can have up to 16 control programs active in a single PLC-5 processor to control your process. Each of these programs is called a main control program (MCP). This chapter describes the effects of using multiple main control programs and how a New Platform or Secure PLC-5 processor interprets the main control programs. By using several main control programs, you can define one main control program for each particular machine or function of your process. This allows you to separate sequential logic (SFCs) from ladder logic and structured text to subdivide your process and make troubleshooting easier. For example, you can specify an SFC program to define the order of events in the process and separate ladder logic and structured text programs to directly control the outputs. Each of these is a main control program. A main control program can be a sequential function chart, ladder program, or structured text program in any program file numbered 1 through 1999. You can use any mix of SFC, ladder, and structured text programs to define up to 16 main control programs. One data table is used by all MCPs (that is, you do not have a separate data table for each MCP).
How the Processor Interprets the MCPs

The main control programs are scheduled to execute in the order in which you specified on the Processor Configuration screen. An I/O image update and housekeeping takes place after each MCP is completed. After the last MCP is completed, all MCPs are then repeated in the same order. Note that the watchdog setpoint covers one scan of all MCPs. The drawing below shows how the processor interprets MCPs.
2-4
If the MCP is a ladder program, the program is executed normally (that is, rungs are executed from the first rung to the last, with all timers, counters, jumps and subroutines active). After the END instruction in the ladder program, the processor initiates an I/O update (reading local inputs, writing local outputs, reading remote buffers and writing remote outputs to the buffer). The next MCP is then started. If the MCP is a structured text program, the program is executed normally. After the last line in the structured text program, the processor initiates an I/O update and the next MCP is started. If the MCP is a sequential function chart, only the active steps are scanned and transitions from those active steps are examined; then (after one complete pass through the active steps) the processor initiates an I/O update and the next MCP is started.
2-5
Configuring Main Control Programs

New Platform and Secure PLC-5 processors only You configure which programs are your main control programs on the Processor Configuration screen.
Specifying The Order of Main Control Programs

On the Processor Configuration screen, specify the program file number and the order in which the MCPs should be run. This configuration is read before the MCP is executed; if you make a change to the configuration screen regarding an MCP, that change takes effect on the next execution of the MCP. You can also change the MCP information through ladder logic by manipulating the status file. The change then takes effect on the next execution of that MCP. You can have the same program file number specified more than once as a main control program. For example, you may want a program to execute frequently and have a higher priority over other programs. If you do not want to use multiple main programs, program your main SFC (program file 1) or ladder program (program file 2) and the processor will execute your main program. You do not need to make any entries on the Processor Configuration screen (the processor automatically enters the main file in the first MCP entry). For more information on how to specify your program file numbers on the configuration screen, see the PLC5 A.I. Series Software Reference manual.
Disabling Main Control Programs

Each MCP has an inhibit bit in the processor status file (S:79). You can set these bits to tell the processor to skip over the MCP until the bit is reset. Disable an MCP if you want to hold a machine state temporarily, regardless of transitions (for example, in machine fault conditions). Disabling an MCP can also help improve scan time; if you know you dont need to run one of your MCPs every scan, you can disable it until you need it.
!
Note
If you disable an MCP, outputs remain in the state that they were in during the last scan (that is, all actions remain active). Make sure you consider any outputs that might be controlled within that MCP before disabling it. Otherwise, injury to personnel or damage to equipment may result. If the disable bit is set for all MCPs, a minor fault occurs to warn you that no MCPs are executing.
2-6
Monitoring Main Control Programs

New Platform and Secure PLC-5 processors only The program scan times for each MCP are stored in the processor status file (S), displaying the previous and maximum scan time. The status file also stores the cumulative scan time, S:8 (the scan time for one complete pass through all MCPs), and the maximum cumulative scan time, S:9.
2-7
Using Interrupt Programs

If you are using interrupt programs (such as a Selectable Timed Interrupt or a Processor Input Interrupt), they have a higher priority than a main control program. The processor uses the following priorities for programs: 1. 2. 3. 4. Fault Routine Processor Input Interrupt (PII) Selectable Timed Interrupt (STI) Main Control Programs
If an interrupt occurs during the execution of an MCP, the processor stops the MCP, executes the interrupt program, and returns control to the MCP at the point that it was stopped. You can protect important parts of your main control programs from interruption by using the User Interrupt Disable (UID) and User Interrupt Enable (UIE) instructions. These instructions allow you to temporarily disable interrupts. If a condition arises that would normally call for the interrupt program, these instructions tell the processor to finish executing the rungs in the MCP first. For more information on these instructions, see the PLC5 A.I. Series Instruction Set Reference manual. Remember, however, that interrupt programs are reenabled at each END instruction (regardless of the UID state). If you want to completely disable an interrupt program, enter a 0 in the appropriate address of the processor status file. For Original PLC-5 processors, disable the STI by entering 0 in S:31, using the Processor Status screen For New Platform and Secure PLC-5 processors, disable the STI by entering 0 in S:31, and disable the PII by entering 0 in S:46, using the Processor Configuration screen.
For more information on disabling interrupts in the status file, see the PLC5 A.I. Series Software Reference manual.
2-8
Designing Programs for Your Application
3
Note

Based on the model discussed in the previous chapter and the information on using MCPs, this chapter uses a drillmachine example to help show how to complete the first two activities in the Program Development Model: functional specification and detailed analysis. Information on the program entry phase is in the remaining chapters of this manual and in the PLC-5 A.I. Series Software Reference manual. If you are using an Original PLC-5 processor, you can use only one main program. You can still apply some of the steps in this chapter, but you must incorporate them into your one main SFC and supporting ladder programs.
3-1
Machine Example
The following example uses a description of a specific machine operation to show how to identify conditions and actions and how to group the actions into steps of machine operation. The drawing below shows a hardware block diagram.
Off Auto Conveyor Motor Fwd Load Station Fwd Fwd
Advance Assembly
Drill Motor LS1 N.O.
Clamp CL1
N.C.
LS2
LS3 N.O.
N.O. LS4
Held Open LS5 N.O.
Unload Station
3-2
Creating the Functional Specification

The functional specification represents a general description of the operation of your process in Auto mode. Based on the drill machine example, this general description might be: 1. 2. 3. 4. The operator starts the conveyor by selecting AUTO. The operator puts a block of wood onto the conveyor. The wood moves into position and actuates LS1. When the wood is in position: a. b. c. 5. 6. The conveyor stops. CL1 clamps the wood. The drill station moves forward.
The drill station moves forward and closes LS3. This action turns on the drill motor. The drill station moves to full depth and closes LS4. This action: a. b. Stops forward motion of the drill station Initiates a 2second dwell
7. 8. 9.
The drill station backs up after the 2second dwell. The drill motor stops when LS3 is released. The drill station reaches home position and opens LS2. This action: a. b. c. Stops the reverse motion Opens the clamp Starts the conveyor forward
10. The wood is ejected when LS5 toggles to indicate the cycle is complete. We recommend that you create a roughdraft SFC to represent this general description. An SFC is drawn using a series of boxes and lines. A box represents a step, or one independent machine operation. A transition, shown as a in the drawing below, is a logic condition that lets the processor progress from one step to the next.
3-3
initialization
010
AUTO operator starts cycle
conveyor forward
011
LS1 wood in position
drill
012
LS4 hole drilled
dwell
013
TMR1 dwell timer done
reverse drill
014
LS2 station home
eject
015
LS5 wood ejected
For more information on the building blocks of SFC diagrams, see Chapter 4- SFC Building Blocks.
3-4
Creating the Detailed Analysis

Now that you have a functional specification, start filling it in with the details of your process. Identify the hardware requirements. The table below identifies hardware requirements for the inputs and outputs of the drill machine.
Input AUTO LS1 N.O. LS2 N.C. LS3 N.O. LS4 N.O. LS5 N.O. Output DSF DSB DM CL1 CMF TMR1 Part selector switch limit switch limit switch limit switch limit switch limit switch Part drive motor drive motor drill motor electric clamp drive motor timer Description select automatic mode part in place drill station home drill motor on drill station at full depth cycle complete Description move drill station forward move drill station back drill motor on clamp 1 on move conveyor forward dwell timer
Use the hardware requirements (with the functional specification) to match the inputs and outputs with the actions of the process. The table below shows the hardware requirements with the general description for the drill machine example.
When This Happens: AUTO switch closes LS1 closes Take This Action: conveyor moves forward conveyor stops clamp holds wood drill station advances drill motor starts drill station stops dwell timer starts drill station backs up drill motor stops (CMF = on) (CMF = off) (CL1 = on) (DSF = on) (DM = on) (DSF = off) (TMR1 = on) (DSB = on) (DM = off)
LS3 closes LS4 closes timer done LS3 opens
3-5
When This Happens: LS2 opens
Take This Action: drill station stops clamp releases wood conveyor starts wood is ejected (DSB = off) (CL1 = off) (CMF = on)
LS5 closes
Once you identify the individual actions, you can add these actions to your functional specification to complete the planning of your program. The following drawing shows the detailed analysis of the drill machine example.
3-6
ladder file initialization
action name
2
010
init
AUTO operator starts cycle ladder file 3 action name conv_frwd
conveyor forward
011
LS1 wood in position ladder file action name clamp_on drill_adv drill_on
drill
4 5 6 012
LS4 hole drilled
dwell 013 TMR1 dwell timer done ladder file 7 8 014 LS2 station home ladder file 9 action name clamp_off action name rev_drill drill_move
reverse drill
eject
015
LS5 wood ejected
3-7
Now that you have an SFC program that defines the individual machine actions for your process (Process Sequence MCP), you can create a ladder logic program that controls the outputs of those machine actions (Outputs MCP). The order in which you program these rungs does not matter. This program merely contains the ladder logic that defines a command for each machine action in your process. Your Process Sequence MCP determines in what order they are executed. You can also create a Modes MCP that defines the operation of your hardware in the different machine modes (Auto, Manual, Fault, Cycle Start/Stop, etc.).
3-8
Entering the Program

Once you have finished your detailed analysis, that is, you have the MCPs defined and programmed (for example, the drill machine has a Process Sequence MCP, Outputs MCP and a Modes MCP), enter the program into your computer. The example below illustrates what would be entered in the Process Sequence MCP, Outputs MCP and Modes MCP for one step from the drill machine.
3-9
Process Sequence MCP

(ladder logic for action) ladder file drill 4 5 6 action name clamp_on drill_adv drill_on fwd_drill_cmd *
012
LS4 hole drilled
* Any symbol can be used for this "command" to control an output. drill station forward
Ladder Logic for Outputs MCP

Auto mode fwd_drill_cmd * Fault mode
Manual mode
Jog pushbutton
Ladder Logic for Modes MCP (rung that controls Auto mode)
Auto pushbutton All_home Manual pushbutton Fault mode Auto mode
Auto mode
3-10
Using Other Processor Programming Features

Use your design specification to determine if you need one or more of the following special processor programming features: Power-up routines Timedriven interrupt routines Eventdriven interrupt routines Faultdriven interrupt routines
The table below explains when to use these special programming features.
If a Portion of Logic Mark that Should Execute: Portion with a: Description: Immediately upon Power-up/Fault detecting conditions Routine that require a startup Create a separate file for a controlled startup procedure, for the first time you start a program or when you start a program after system down time. The processor executes the power-up/fault routine to completion. Create a separate program file and specify the interrupt time interval. The processor interrupts the main logic program at the specified interval, runs the STI to completion, then resumes the main logic program where it left off.
At a specified time interval
Selectable Timed Interrupt (STI)
Immediately when an Processor Input Create a separate program file and specify 16 event occurs Interrupt (PII) inputs of an input word in the I/O rack. When the event(s) occurs, the processor interrupts the main logic program, runs the PII to completion, then resumes the main logic program where it left off. This feature is only available with New Platform and Secure PLC-5 processors. Immediately upon detecting a major fault Fault Routine Create a separate file for a controlled response to a major fault. The first fault detected determines which fault routine is executed. The processor executes the fault routine to completion. If the routine clears the fault, the processor resumes the main logic program where it was interrupted. If not, the processor faults and switches to program mode.
3-11
Examples of Special Programming Applications

The table below describes programming situations that might require special programming features.
If the Application is to: Eject a faulty bottle from a bottling line Send critical status to a supervisory processor via DH+ after detecting a major fault Monitor machine position every 250ms and calculate the average rateofchange Shut down plant floor devices upon detecting a major fault Restart the system after the system has been shut down Choose a: PII Fault routine STI Fault routine Powerup routine
Take a measurement and compare it with a standard every STI 1.0 seconds
3-12
Checking for Completeness

When you complete the functional specification and the detailed analysis, review them and check for missing or incomplete information such as: Insufficient input conditions Safety conditions Startup or emergency shutdown routines Alarms and alarm handling Fault detection and fault handling Message display of fault conditions Abnormal operating conditions
3-13
SFC Building Blocks
4
Note
SFC Building Blocks

This chapter describes the components used to create a Sequential Function Chart (SFC) and how to use those components in an SFC. SFCs are somewhat different between Original and New Platform processors. When changing the processor type from an Original to a New Platform processor, SFCs will be converted automatically. The reverse (from New Platform to Original), however, is not true.
SFC Building Blocks

An SFC uses the following types of building blocks: Step Transition Simple Path Selection Branch Simultaneous Branch GOTO statements and labels
Step
A step typically represents an independent machine state. One step of ladder logic runs repeatedly, top to bottom, until a logic condition (transition) lets the processor progress to the next step of the chart. You draw a step as a numbered and labeled box in the SFC. The number 007 in the example below represents the ladder file number that contains the ladder logic for that step.
4-1
Corresponding ladder logic Mixer 1
007
} Step
New Platform and Secure PLC-5 processors can have up to eight actions per step. An action is a subset of a step. Instead of assigning a single ladder file to a step, you can assign individual ladder files to actions of a step to better represent the individual pieces of your operation.
Transition
A transition represents the logic condition that lets the processor progress from one step to the next. You draw a transition as a numbered cross below its step (see the following drawing).
Corresponding ladder logic
017
EOT Transition
Every transition must contain at least one EOT (End of Transition) instruction.
Simple Path
A simple path contains a series of steps and transitions that execute one at a time in sequence.
4-2
SFC Building Blocks
Mixer 1
007
009
Dump 1
008
010
Selection Branch
A selection branch contains alternative paths from which the processor selects one. This is equivalent to an OR structure. Draw a selection branch as parallel paths connected with single horizontal lines (see the drawing below). Notice that transitions are located within the structures boundaries and are at the top of each parallel path.
003
011 Mixer 1 007 Mixer 7
014 012 Rinse 1
016 013
009 Dump 1 008
015
017
010
4-3
Simultaneous Branch
A simultaneous branch runs steps simultaneously that are in parallel paths (the processor shares processing time for each path). This is equivalent to an AND structure. Draw a simultaneous branch as parallel paths connected with double horizontal lines as shown in the following drawing. Notice that a common transition for the last step in all the paths is outside of the branch. The processor finishes running a simultaneous branch when it has scanned each step in each path at least once and the common transition is true.
Mixer 1
010
009 Dump 1 008 Mixer 7 012 Rinse 1 013
026
When using simultaneous branches, you may want to include a dummy step at the end of each path to synchronize the simultaneous actions. This dummy step merely holds each path (until all paths have been executed) before moving on to the transition. Using the example above, the structure would look like the following:
Mixer 1
010
009 Dump 1 008 Mixer 7 012 Rinse 1 013
Dummy
015
Dummy
015
Dummy
015
026
4-4
SFC Building Blocks
You can combine SFC building blocks (step, transition, selection branch, and simultaneous branch) to build structures that represent your programming application.
GOTO and Label Statements

A GOTO statement tells the processor to continue program execution at another location marked with a label. The example below shows a GOTO statement and its associated label.
003:
015
016 GO TO 003
017 018
019
4-5
Drawing an SFC
After you identify the major areas of machine operation, convert the logical paths and steps that you labeled in your design specification to SFC building blocks. The table below helps explain when to use which SFC building blocks. Note At this point, do not worry about the actual ladder logic for each step and transition. After you complete the SFC, you can develop the ladder logic.
Then Draw: A step/transition pair Using These Rules: A step must always be followed by a transition. For design purposes, number steps and transitions consecutively from 2. Start the path with a step; end the path with a transition.
If You Have: An independent machine state
A clearly defined chain of events that occur sequentially For example, in one heat treating area, the temperature must ramp up at a particular rate, maintain the temperature for a certain duration, then cool at a particular rate. Two or more alternative paths where only one is selected For example, depending on a build code, one station must either drill or polish.
A simple path of steps and transitions
A selection branch
The transitions beginning each path are scanned from left to right. The first true transition determines the path taken. For an Original PLC-5 processor, you can define up to 7 paths in the structure. For a New Platform or Secure PLC-5 processor, you can define up to 16 paths. See How Selection Branches Work on page 4-9. All paths are active in the structure. For an Original PLC-5 processor, you can define up to 7 parallel paths. For a New Platform or Secure PLC-5 processor, you can define up to 16 parallel paths. See How Simultaneous Branches Work on page 4-10.
Two or more parallel paths that must be scanned at least once For example, communications and block transfers must occur while control logic is executing.
A simultaneous branch
For special cases, use the rules listed in the following table.
4-6
SFC Building Blocks
If You Have: To jump within the SFC A step that needs to be run in multiple places within the SFC A step that can be ignored based on logic conditions
Then: Use a GOTO statement and label. See Using GOTOs and Labels on page 4-11. Repeat the step where needed or use a global subroutine that gets called from multiple steps by the same processor. Create two selection branches, one with and one without the step; place the step in a subroutine; or combine the step with another step that is segregated by an MCR zone. Nest the branch structures. The software supports as many levels of nested branches as you can store based on processor memory. Use the SFR instruction to reset the chart. See the Instruction Set Reference manual. Set the disable bit for the MCP on the Processor Configuration screen. See the PLC5 A.I.Series Software Reference manual.
An SFC branch structure within another branch structure (nesting) To reset the logic in an SFC program To disable a Main Control Program (New Platform and Secure PLC-5 processors only)
4-7
Example SFC
Initial Step
002
003
004
006 008
007 009
010 012
011
013
014
005
015
4-8
SFC Building Blocks
How Selection Branches Work

When a processor runs a selection branch, the processor finds the path that is true for the program scan and runs the steps and transitions in that path. If more than one path in a selection branch goes true at the same time, the processor chooses the leftmost path.
4-9
How Simultaneous Branches Work

When a processor runs the simultaneous branch, the processor scans the branch from lefttoright, toptobottom. It appears that the processor runs each path in the branch simultaneously. The following drawings show a typical scan sequence. Typical SFC Scan of a Simultaneous Branch
Typical SFC Scan of a Simultaneous Branch when a Transition Goes True

First: Then:
last scan/ post scan
false true false false transition transition transition transition
false true false false transition transition transition transition
first scan step added to list of steps to be scanned
4-10
SFC Building Blocks
The following table lists considerations for selecting SFC scan sequences.
Control Characteristic: When a transition is true, the processor scans that step one last time so that the processor can reset non-retentive outputs. Considerations: Your application may have to consider the extra time for the post scan. If you are using a New Platform or Secure PLC-5 processor, you can configure your SFC program to do a manual reset instead of an automatic reset.
The processor cannot exit the simultaneous The last step in each path of a simultaneous branch must be executed branch until the last step in each path has been executed. before the processor scans the common transition.
Using GOTOs and Labels

GOTO and label statements tell the processor to stop scanning the current path, jump to another step, and continue scanning. General Rules for GOTOs and Labels Each label must have a unique 3 digit number (001 250), the same as its corresponding GOTO. You can have up to 250 labels in one SFC. More than one GOTO can jump to the same label. You cannot jump into, out of, or between simultaneous branches. Use sparingly to avoid confusing the flow of the SFC.
Rules for Placing GOTOs and Labels You can only place GOTOs at the end of the SFC or after the last transition of a selection branch. You can only place labels immediately before a step or before a simultaneous branch. You cannot place a label between a step and its transition.
4-11
Using the SFR Instruction

New Platform and Secure PLC-5 processors only The SFR instruction resets the logic in an SFC. When an SFR instruction goes true, the processor performs a postscan/lastscan and then resets the logic in the SFC on the next program scan. The chart remains in this reset state until the instruction goes false. The SFR instruction also resets all retentive actions that are currently active.
Use the SFR instruction with care. Unexpected machine motion could injure personnel.
Use the SFR instruction to handle situations that require resetting your machines. For example, if a machine goes out of alignment, use the SFR to reset the chart, align the machine, and then disable the SFR to start the SFC again. For more information on the SFR instruction, refer to the Instruction Set Reference manual.
4-12
Writing Ladder Logic

After you have a design specification for your application, you are ready to create the ladder logic. This chapter shows you how to: Convert statements of machine operation into rungs of ladder logic with digital I/O instructions Construct ladder rungs in the correct format Arrange instructions for fast program scan Assign bit addresses to digital I/O instructions
5-1
Converting Machine Statements to Ladder Logic

Ladder logic is a program written in a format resembling an electrical ladder diagram. A programmable controller uses the program to sense inputs and control outputs. Ladder logic programs: Examine the on/off status of machine devices by reading bit data in the input and output image file Make decisions based on input and output conditions Control the on/off status bit data in the output image file which in turn controls the on/off status of output devices
To write ladder logic, you need to understand these definitions: Rung a logic statement that controls one or more bits based on the state of other bits examined. Ladder logic is composed of a listing of rungs. Each rung connects at one point to the left and right power rails. A rung must have at least one output instruction. Input (condition) instructions examine input and output conditions that then determine the true or false state of the instruction. These commands appear on the left side of a rungto the left of the output instructions. A rung may have multiple input instructions. Output (control) instructions control the state of a bit or bits based on input (condition) instructions. These commands are placed on the right side of a rung, to the right of the input instructions. Each rung must have at least one output instruction (or more).
5-2
Rung Logic Example

input (condition) instruction elements Rung 1 Rung 2 output instruction elements
Rung 3
Rung 4 Rung 5
Note
Each input instruction and output instruction you enter generates a rung element. As each input instruction is executed, the addressed bit is examined to see if it matches a certain condition (on or off). If the condition is found (rung 1 above), the rung element is set true. Input instructions must contain a continuous path of true elements from the start of the rung to the output instruction for the output instruction to be enabled. If a rung element is unconditioned (that is, has no input instructions as in rung 4 above), the output instruction is always enabled. The PLC5 A.I. ladder editor highlights logically true instructions when the processor is in run, remote run, or test mode.
Example Discrete I/O Instructions

The example rung format above uses the following discrete I/O instructions:
Name: Format: Description:
ExamineOn An input instruction that examines a bit for an ON condition as follows:

Then the instruction is: true false
If the bit is: ON (1) OFF(0)
5-3
Name: Format: Description:
Output Energize
An output instruction that controls the status of one bit (which in turn could control the on/off status of the output device).
If the instruction is: enabled (rung is true) disabled (rung is false) Then the bit is: set to 1 reset to zero
For information about other available instructions, refer to Allen-Bradley's Instruction Set Reference manual or to the online help in PLC-5 A.I. Series (accessed with the command sequence .UUKI or [Shift-F10] then [F4]).
5-4
Constructing Ladder Rungs

When you construct ladder rungs, there are guidelines you should follow for writing rung and branch logic.
Writing Rung Logic

When you write rung logic, follow these guidelines: Sort the actions to be taken from the conditions to be examined for each statement of machine operation. Select the appropriate input instruction for each condition and the appropriate output instruction for each action.
Some input devices and input modules use inverse (negative) logic where a logically true condition turns the bit off, and a logically false condition turns the bit on. If used incorrectly, these instructions can cause unexpected operation with damage to equipment or injury to personnel. Arrange input instructions on the lefthand side of the rung as shown in the table below.
If you have multiple input conditions and: all conditions must be true to take action (logical AND) any of several conditions must be true to take action (logical OR) Then arrange the instructions: in series
] [
in parallel
] [
] [
] [ ] [ ] [
in series and parallel
a combination of AND and OR conditions must be true to take action
] [ ] [
] [
5-5
Arrange output instructions on the righthand side of the rung as shown in the table below.
If you program: a single output instruction Then arrange the instruction(s):
at the far right
( )
multiple output instructions Note All parallel outputs are enabled when the logic path becomes true.
in parallel
( ) ( ) ( )
in a separate output branch
a conditioned output instruction
] [
Rung Example A statement of machine operation reads:
( ) ( )
Label each instruction with the name of the device it examines or controls. You can program as many instructions per rung as you want.
When LS1 and LS2 are closed, or when SW6 is closed, turn on FAN1 and BULB1.
Translate the statement to a rung as follows: The when indicates an input condition. The and indicates serial input conditions The or indicates parallel input conditions. The turn on portion of the statement indicates two outputs (in parallel). When input conditions provide a logically true path across the rung, the rung is true and the outputs are energized.
5-6
The drawing below shows what a rung would look like for the above statement of machine operation with the outputs in parallel.
LS1 LS2 FAN1 BULB1
SW6
Writing Branch Logic

Whenever you program instructions in parallel, you must create branches. Follow these rules for input and output branching. The number of parallel branches allowed is limited only by processor memory. Branches must not overlap. (A branch cannot start inside another and end outside it.) Branches may, however, be nested. See the section below. For example, this is not allowed:
An output branch must end with an output instruction. For example, input instruction (A) is not allowed in that position:
Nested Branching Input and output branches can be nested to avoid redundant instructions and to provide more efficient programming. A nested branch is a branch that starts or ends within another branch. You can nest branches up to four levels deep.
5-7
Nested Input and Output Branches
] [
] [ ] [ ] [ ] [ ] [ ] [
] [ ] [ ] [
( ) ( ) ] [ ( )
] [
Nested branching can be converted into non-nested branches by repeating instructions to make parallel equivalents.
A B C F
] [
] [ ] [
E D
] [
( )
] [
Nested Branch
] [
] [ ] [ ] [
E D
] [ ] [
C
( )
Non-Nested Equivalent Parallel Branch
Execution Time and Branch Structure Considerations In general, non-nested branches are more efficient than nested branches. Both of the examples shown below accomplish the same result with the same number of output instructions; however, the non-nested branching example is evaluated approximately 1 microsecond faster than the nested branching example.
5-8
Non-Nested Branching
Nested Branching
( ) ( ) ( )
( ) ( ) ( )
Branches can only be nested four deep, but are otherwise limited only by processor memory.
5-9
Arranging Input Instructions

You can improve or impede the rate of program scan by how you arrange instructions within a rung based on these two considerations: Place instructions most likely to be false, first in a rung. Place instructions most likely to be true, last in a rung.
For example:
Most likely to be FALSE Most likely to be TRUE
Place the input path that is most likely to be true as the top path in a branch. Place the less likely to be true input branches further down in the branch.
For example:
Path most likely to be true less likely least likely
5-10
Organizing Data Table Files

This chapter shows you how to organize data storage for your programs. All of the data your processor examines or changes is stored in files in data storage areas of memory. Data storage areas store: Data received from input modules Data to be sent to output modules; this data represents decisions made by the ladder logic Intermediate results made by the ladder logic Preloaded data such as presets and recipes
In addition, the processor uses other areas of data storage to: Control instructions Store system status
The drawing below shows the relationship between I/O modules, data storage, and ladder programs.
DATA STORAGE
Discrete Inputs INPUT MODULES Analog Inputs
I/O Image Files
Discrete Outputs Analog Outputs OUTPUT MODULES
Block transfer files
Other Data Files Examine Data LADDER PROGRAM Return Results
6-1
Understanding Data Storage

The processor divides data storage into: types, files, elements and bits. Data storage is divided into types. Types let you specify different formats and ranges to accommodate different types of data. Types are divided into files. Files let you group and organize logically related data. When you need to access data, you specify the file in which the data is stored.
Data Types file # integer file 7 file #
File 999
Files are made up of elements. Typically, these are 16bit data values. When you need to access this data, you specify it with a formatted address. For information on address formats refer to the Hardware Interface Configuration User's Guide or your Allen-Bradley documentation.
Integer File sample data integer elements 10201 File # 64 7779 2
6-2
Each element contains multiple bits. This is the smallest division of data. A bit contains a value of zero or one. When you need to access this data, you specify it with a formatted address.
Integer Element
276
0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 sample data Binary bit pattern for 276
Some sections of data storage are used to control instructions. Within these sections, data is subdivided into subelements at the bit or word level. When you need to access this data, you specify it with a formatted address.
Timer File # timer sub-elements samle data 2760 (preset .PRE) 432 (accumulated .ACC) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 control (control word contains enabled (.EN), timing (.TT), and done (.DN) bits)
Timer #
In addition to the processordefined structures, you can organize the data in files into data blocks that help group and organize logically related data. When you need to access this data, you specify only the starting address within the file instead of each individual address.
File # Starting addr (Length) Starting addr (Length) Starting addr (Length) up to 999 elements recipe A" data recipe B" data production counts
6-3
Organizing Data into Files and Data Blocks

When you organize data files, you can use processordefined data files, where each file starts at word 0, or subdivide these files into userdefined data blocks, where you specify the starting address of the first word in the data block. When you organize data, group data by similar kind, such as: The result of calculations Inputs from analog modules Outputs to analog modules Batch recipes
You might also want to leave room for future expansion when grouping data. Do this by leaving gaps between Note Data blocks within a file Groups of sequentially numbered files Modules in an I/O chassis
Gaps in the numbering system use several words of overhead memory for each file or data block you skip. However, if you plan on programming online, gaps are necessary since you cannot create or delete data files while in RUN mode. Use care when leaving gaps. Follow these rules when organizing your data files: Group large amounts of related data into files. Address the data files from 3999 as needed. The table on page 6-6 lists the default data table file numbers. Address the elements needed in each data file consecutively from 0999. Address the words of I/O image data according to how you configured your I/O:

037 (octal) for PLC-5/10, -5/12, -5/15, -5/11, -5/20 077 (octal) for PLC-5/25, -5/30 0-177 (octal) for PLC-5/40 0-277 (octal) for PLC-5/60, -5/80
6-4
When organizing bit data, address the bits in each element 015 (decimal) for binary or integer files. When addressing I/O image bits, address them 0007 or 1017 (octal).
6-5
Default Data Table Files

The table below lists the default data table files. These are the data table files that appear after you clear memory.
File Type: O output I input S status B binary (bit) T timer C counter R control N integer F floating point Last Address: O:037* I:037* S:31 B3/15 T4:0 C5:0 R6:0 N7:0 F8:0 Size (elements): 32* 32* 32 1 1 1 1 1 1 Size (words): 32* 32* 32 for Original 128 for New Platform 1 3 3 3 1 2
*depends on processor type
6-6
Addressing Data Table Files

This chapter explains how to use the following types of formats for addressing data files when you write your ladder programs: Logical address - an alphanumerically coded format with punctuation to specify the data location. For example: N23:0. See page 7-2. I/O image address - logical address format, but relates physical locations in the I/O chassis to memory locations in the I/O image file. For example: I:017/17. See page 7-6. Indirect address - logical address format, but lets you change address values in the base address with your ladder program. For example: N[N7:6]:0. See page 78. Indexed address - index prefix (#) followed by a logical address format, but offset by an index value from the processor status file. For example: #N23:0. See page 7-10. Symbolic address - ASCII character name that relates the address (of an element, sub-element, or bit) to what it represents in the application. For example: MIXER_1. See page 7-12.
7-1
Specifying Logical Addresses

Use a logical address to access a bit, element, subelement, data block, file, or I/O image bit. The format of a logical address corresponds directly to the location in data storage. 1. Specify the data type and file number. File numbers 0 through 8 are the default files. If you need additional storage, you can create files by specifying the appropriate identifier and a file number from 9 to 999. Refer to the table below.
Default Files File Type Output Input Status Bit Timer Counter Control Integer Floating Point String* ASCII BCD Block Transfer* Message* PID* SFC Status* ControlNet Message* Identifier O I S B T C R N F File Number 0 1 2 3 4 5 6 7 8 B T C R N F ST* A D BT* MG* PD* SC* CT* 3-999 User-Defined Files Identifier File Number
*File type only available on New Platform PLC-5 processors. Note 2. Although files 3 through 8 are defaults, they may be used for other purposes if deleted and then recreated as a different file type.
Include a colon (:) followed by the element number. You can substitute a semi colon (;) for the colon (:) delimiter.
7-2
3. 4
If you want to specify a bit number, include a front slash (/), period (.), or a space, followed by the bit number. A space appears as an underscore (_) character. If you want to address a member, such as a done bit or an accumulated value, include a front slash (/), period (.), or a space, followed by the mnemonic. A space appears as an underscore (_) character.
The table below summarizes how to address different data structures.

To Specify the Address of a: Element File Type File Number Element Delimiter Element Number File File Type File Number Bit Within a Binary File File Type File Number Bit Delimiter Bit Number Bit Within a Control File Element Number Sub-Element Delimiter Bit Mnemonic R6:7.DN B3/245 F8 Use These Parameters: N9:22
For more information on the structure and addressing of the different data types, refer to the 1785 PLC-5 Programmable Controllers Addressing Reference document. Note Use the / delimiter only for addressing bit numbers. Do not use it to address data bits by mnemonic. Never use it for a division symbol. The division symbol is the vertical bar ( | ).
7-3
The following table explains the examples shown above.

Valid Address: N9:22 F8 B3/245 R6:7.DN Type of Address: Element File Bit Bit Explanation: integer file 9, element 22 floatingpoint file 8 binary file 3, bit 245 (word 15, bit 5) control file 6, element 7, done bit
Using Address Mnemonics

Address mnemonics let you address members at the word or bit level according to name. The available address mnemonics depend on the type of data file (timer, counter, control, etc.) and the program instruction that you want to address. Certain PLC5 data file elements are made up of multiple words. For example, Timer and Counter elements use 3 words of processor memory per element, whereas PD file elements use 82 words per element. In order to address individual subelements or bits within these multiword data types you must use word or bit mnemonics. These mnemonics fall into two categories, reserved and nonreserved. Reserved mnemonics may be delimited in the manner described above for subelement words or bits, but cannot be used in conjunction with the ( _ ) character as a symbol name. For example, the symbol name SYM_1_ACC is not valid (unless SYM_1 is the symbol for a timer or counter, in which case PLC-5 A.I. Series will convert it to SYM_1.ACC and treat the _ACC as the accumulated value sub-element rather than part of a symbol).
7-4
The following is a partial list of reserved word (w) and bit (b) mnemonics. More mnemonics can be found in the 1785 PLC-5 Programmable Controllers Addressing Reference.
Timer .ACC (w) .PRE (w) .EN (b) .TT (b) .DN (b) Counter .ACC (w) .PRE (w) .CU (b) .CD (b) .DN (b) .OV (b) .UN (b) .UA (b) Control .POS (w) .LEN (w) .EN (b) .EU (b) .DN (b) .EM (b) .ER (b) .UL (b) .IN (b) .FD (b)
Nonreserved mnemonics can be accessed only by using the ( . ) delimiter. For example, if the symbol PID_LOOP1 is assigned to address PD21:0, then the setpoint subelement would be addressed as PID_LOOP1.SP but not as PID_LOOP1_SP or PID_LOOP1/SP.
7-5
Specifying I/O Image Addresses

Use an I/O image address to access an input or output bit in the I/O image table. The format of an I/O image address corresponds the physical location of the data in the I/O chassis to the storage location in the I/O image table. When you specify an I/O image address, include the following: Specify I for input or O for output. Include a colon (:) as a file delimiter followed by the I/O rack number: (00-37 octal)

00-03 octal for PLC5/10, -5/11, -5/12, -5/15, -5/20 00-07 octal for PLC5/25, -5/30 00-17 octal for PLC5/40 00-27 octal for PLC5/60, -5/80
Include the I/O group number (0-7). Include a front slash (/) as a terminal delimiter followed by the terminal number (0-7, 10-17).
7-6
The table below shows valid I/O image addresses.

To Specify This Address: Input Image Bit I for input 2-digit I/O rack number use 00-03 (or 00-07 PLC-5/25, -5/30) use 00-03 (or 00-17 PLC-5/40) use 00-03 (or 00-27 PLC-5/60, -5/80) I/O group number (0-7) Terminal number (00-07, 10-17) Output Image Bit O for output 2-digit I/O rack number use 00-03 (or 00-07 PLC-5/25, -5/30) use 00-03 (or 00-17 PLC-5/40) use 00-03 (or 00-27 PLC-5/60, -5/80) I/O group number (0-7) Terminal number (00-07, 10-17) O:017/00 Use These Parameters: In This Format: I:017/01
The following table shows some I/O image address examples.

Valid Address: I:017/01 O:017/00 Explanation: Input rack 1, I/O group 7, terminal 1 Output rack 1, I/O group 7, terminal 0
7-7
Specifying Indirect Addresses

With indirect addressing, one component of a logical address is represented by another logical address. The processor uses the value from the substitute address to form the indirect address. The substitute address is enclosed within brackets [ ]. For example, if the value in N7:0 is 13, then the indirect address T[N7:0]:0.ACC refers to address T13:0.ACC. Only word addresses can be used to specify an indirect value (not bit or multi-word addresses). Note that you cannot indirectly address I, O or S file types. Follow these guidelines when specifying indirect addresses: You can indirectly address a file number, word number, or bit number. The substitute address must be one of the following types: N, T, C, R, B, I, O, or S. Any T, C, or R address used must be a word-length sub-member address, such as T4:0.ACC. Enter the substitute address in brackets [ ].
Note
Instructions with indirect addresses execute slower than instructions with direct addresses because the processor has to look up each indirect address. Allocate addresses in the data table to include any indirect addresses you specify. The data table will not automatically expand to include indirect addresses.
Examples Indirect Component Indirect Address Refers To N[O:017]:8/4 T4:[O:017] N20:[O:017]/4 N20:8/[O:017] a file number an element number an element number a bit number If O:017 = 10, then the indirect address refers to N10:8/4 T4:10 N20:10/4 N20:8/10
The data table will expand to include an address used to specify an indirect address. For example, specifying the indirect address N11:[N22:33]/[N44:55] would cause the data table to expand to include the following addresses: N11:0, N22:33, and N44:55.
7-8
When using indirect addressing, the indirect address must point to a valid data file and/or element. During RUN mode operation, if the ladder execution comes across an invalid or out of range indirect address a run time error will occur and the PLC-5 processor will halt. If you are using a New Platform processor prior to series E, and if an invalid address destination is used in an FLL or COP instruction, the instruction will be terminated AFTER one word has been written at the invalid address. The processor continues to operate in run mode.
Note
To monitor or troubleshoot invalid address occurrences, condition the indirect address ladder rung with a limit test of the indirect address to insure that the address stays within the intended range. Conditioning of rungs may be especially advisable if the PLC-5 processor has no control over the indirect address that is being set (that is, the address is determined by values from an I/O module or a peer processor). If you are using a File Copy (COP) or a File Fill (FLL) instruction with Enhanced PLC-5 processors (Series D and earlier), and you specify an indirect address in the destination parameter, you may write data outside of the intended data table file and cause unpredictable controller operation. To ensure that your program correctly references the intended memory location, when using indirect addressing, we highly recommend that your program perform bounds checking via the ladder logic. Although no error messages are reported with New Platform PLC-5 processors (Series D and earlier), when data is written outside of the intended data table file with New Platform PLC-5 processors (series E and later), an indirect address out of range condition is detected, displaying one of the following fault codes:
This Fault Code 20 21 Indicates this Fault Indirect address out of range high Indirect address out of range low
7-9
Specifying Indexed Addresses

Indexed addresses add an offset value to the given logical address to determine the actual address. Indexed addresses consist of a prefix ( # ) followed by a logical address referred to as a base address. The offset value to be added to the base address is stored in the processor status file, word S:24. For example, if S:24 has a value of 12, then the indexed address #N7:10 would actually reference N7:22 in the data table. The value in S:24 can be positive or negative. The data table is not automatically expanded to accommodate indexed addresses. For example, if N7 contains 20 elements and S:24 contains a value of 30, then #N7:10 refers to an integer at address N7:40, which does not exist. That is, N7:40 is outside the bounds of file N7. This is referred to as crossing a file boundary, and causes a major fault.
The processor does not check indexed addresses to make sure that the addresses do not cross data table file boundaries. If the indexed address exceeds the data table area of memory, the processor initiates a run-time error and sets a major fault. Follow these guidelines when specifying indexed addresses: Make sure the offset value (positive or negative) does not cause the indexed address to exceed the file type boundary. When an instruction uses more than two indexed addresses, the processor uses the same index value for each indexed address. Set the offset word to the index value you want immediately before enabling an instruction that uses an indexed address.
File instructions manipulate the offset value stored at S:24. Make sure that you monitor or load the offset value you want prior to using an indexed address; failure to do so could result in unpredictable machine operation with possible damage to equipment and/or injury to personnel. When a User Error Handler, STI routine, or I/O Interrupt routine, is invoked, the S:24 value is stored, and when the routine ends, the original value is restored. Therefore, you cant use these routines to set the value in S:24.
7-10
The following instructions manipulate the offset value in S:24:

BSL/BSR DDT FFL/FFU LFL/LFU FAL Bit Shift Left/Right Diagnostic Detect FIFO Load/Unload LIFO Load/Unload File Arithmetic and Logic COP FLL FSC SQI/SQL/SQO FBC File Copy File Fill File Search and Compare Sequencer Input/Load/Output File Bit Compare
Indexed Addressing Example

The MVM instruction in this example uses an indexed address in both the source and destination addresses.
MVM Masked Move Source Mask Dest #N7:10 0 0033h #N11:5 0
If the offset value stored in S:24 is 10, then the addresses referenced in the instruction will be as follows.
Base Address Offset Address Source Destination N7:10 N11:5 N7:20 N11:15
7-11
Specifying Symbolic Addresses

With symbolic addresses, you can substitute a name for an address so the address will relate physically to the application. For example, you could substitute the name LS1 for input image bit I:007/10 to indicate the input from Limit Switch #1. When you specify symbolic address, follow these guidelines: The symbol can contain up to 15 of the following characters:

A - Z (upper case) 0-9 _ ! @ % ^ & ( ) | { } \ ; = + - , < > ' ` ~ " If you are using Structured Text, the characters $ ( ) | : ; + = - < and > are NOT valid in symbol names.
Note Note
You can substitute a symbolic address for both the element and bit addresses. Record the symbols you define and their corresponding logical addresses.
Do not use the % character in a symbol name even though it is allowed. Any occurrence of the % character in a symbol name will produce errors when importing or exporting a file. To use symbolic addresses, you assign symbols to logical addresses with the programming software. Symbols are a feature of the programming software, not the processor. If you use PLC5 A.I. on a terminal other than the one in which you defined symbols, you will not have access to the symbol database you created. The software stores the database on the hard disk of the programming terminal that you used to enter the symbols. After you define the symbol for an existing logical address, you can use the symbolic address anywhere else in ladder logic to reference that same address.
7-12
The following table shows some examples of valid symbolic addresses.

Type of Address: Input image Logical Address: I:015/00 I:015/03 I:015/06 O:013/00 O:013/02 O:013/04 F10:0 F10:1 Symbolic Address: LS1 AUTO1 SW1 M1 CL1 L1 CALC_1 CALC_2
Output image
Element
Note
You can use a symbol when addressing a subelement of a word address. Assign a symbol to the word address and then append the subelement mnemonic to the symbol for the word. For instance, if the symbol for T4:0 is TIMER, then the symbol for T4:0.DN is TIMER.DN.
SoftLogix 5 Symbols
If you are using the SoftLogix 5 controller, Structure Names must start and end with a letter. Structure Names may NOT contain any of the following characters: ` ~ ! @ # $ % ^ & * ( ) - + = { } [ ] | \ : ; " " < > ? , . / or a space
7-13
Addressing Frequently Used Files

For the best memory organization, address your most frequently used instructions between the end of the status file and physical word 256 for bit instructions or between the end of the status file and physical word 4096 for element instructions. Note Instructions programmed using bit addresses below word 256 and word addresses below 4096 use half as many storage words as addresses above these limits. The processor can also access the addresses below these limits more quickly than addresses above these limits. Data table files are contiguous in memory. I/O files 0 and 1 are fixed at 32 words in PLC5/10, 5/12, 5/15, -5/11, and -5/20 processors vary from 3264 words in PLC5/25, and -5/30 processors. The default is 32 in PLC-5/25 processors and 64 in PLC-5/30 processors. vary from 32128 words (128 is the default) in PLC5/40 processors vary from 32192 words (192 is the default) in PLC5/60 and -5/80 processors
Status file 2 is fixed at 32 words for Original PLC-5 processors and 128 words for New Platform PLC-5 processors. Files 3999 vary in size. These files contain only the number of words corresponding to the highest address that you assign (see the drawing below).
7-14
PLC-5/15 Word # 0 32 64
PLC-5/25 Word # 0 32-64
File Type File # output image 0
64-128
input image
96
96-160
status
256
binary, timer, counter, control, integer, floating point
3-999 according to your application
4096
Status File for PLC5/10, PLC5/12, and PLC5/15 Processors

The status file ends at word 95 for PLC5/10, PLC5/12, and PLC5/15 processors. Use addresses B3:0 - B3:159 in binary file 3 for your most frequently used binary addresses. Use addresses up to word 4096 in files 4 and greater for your most frequently used element addresses.
Status File for PLC5/25 Processors

The status file ends at word 159 for PLC5/25 processors if you use the entire input and output image files. Use addresses B3:0 - B3:95 in binary file 3 for your most frequently used binary addresses. Use addresses up to word 4096 in files 4 and greater for your most frequently used element addresses.
7-15
Using a Selectable Timed Interrupt

A selectable timed interrupt (STI) tells the processor to periodically interrupt program execution (due to an elapsed timer) to run an STI program once to completion. Then, the processor resumes executing the original program file from where it was interrupted. For example, you might want to use an STI to check the status of your PLC5 on the Data Highway link. You can also use an STI to perform immediate block transfers to local I/O. This chapter shows you how to set up and use a selectable timed interrupt (STI).
8-1
Writing STI Ladder Logic

Follow these guidelines when writing ladder logic for an STI program file: Store the STI program in a ladder file. Make sure the interrupt interval you specify (in word S:30) is longer than the execution time of the STI program. If it is not, an STI overlap occurs and the processor sets a minor fault bit at word 10, bit 2 of the status file. Note that the processors watchdog timer continues to run while the processor runs an STI program.
Note
If the interrupt occurs during the execution of an instruction, the processor stops executing the instruction, scans the interrupt file once to completion, and then resumes executing the instruction. In effect, execution of an STI is transparent to program execution time unless you specify too short an interval. An interval that is too short can cause the watchdog timer to time out or cause excessively long program scans.
8-2
Setting Up an STI
To set up an STI, you need to: Create the ladder file and enter the ladder logic Store the location (file number) of the STI program in the processor status file, S:31 Store the setpoint (interval) in S:30
Use ladder logic or the processor configuration screens to enter this information. See the PLC5 A.I. Series Software Reference manual.
Storing the Location of the STI File in the Processor Status File
The table below shows what to store in the processor status file for STI operation.
STI Characteristic: Explanation: Setpoint (interval) Address S:30 enter the setpoint of the STI in milliseconds (1 32,767). If you do not use an STI, enter 0.
Program file number Address S:31 enter the file number of the ladder file that contains the STI program. Entering a 0 in this field disables the interrupt.
For example, you could enter a 7 in S:31 and a 15 in S:30. This will cause the processor to execute ladder file 7 every 15 milliseconds. You can use only one STI at any particular time. However, you can enable or disable the interrupt, or change to a different interrupt file, or change the time between interrupts using ladder logic to change the values in word 30 and word 31 of the processor status file. Note For Original PLC-5 processors: If you disable the STI through ladder logic (by placing a 0 in word 30) and then later reenable the STI, it could take the processor as long as 255 milliseconds before the processor enables the STI. For New Platform PLC-5 processors: If you disable the STI through ladder logic (by placing a 0 in word 30), it could take the processor up to 100ms to reenable the STI. If you disable the STI by writing a 0 to word 31, the processor uses the value in word 30 to determine how often to check for a nonzero value in word 31.
Note
8-3
STI programs lengthen the program scan by an amount equal to the interrupt delay multiplied by the number of times the interrupt occurs during the program scan.
If you are using a New Platform PLC-5 processor, note that the STI last scan time and STI maximum scan time are stored in the status file (S:53 and S:54 respectively).
Block Transfers Used Within an STI

You can program immediate block transfers to a local I/O chassis using the STI program; the block transfer executes as if it was an immediate block transfer in a ladder program. Original PLC-5 Processors Do not use the STI for block transfers to remote I/O because the STI can lengthen program scan. If you program a block transfer in an STI to a remote I/O chassis, the STI delays program scan until the processor completes the immediate block transfer. If the immediate block transfer fails, the program scan could stop for 1/2 second, halting machine control. New Platform PLC-5 processors You can use the STI for a block transfer to remote I/O in New Platform PLC-5 processors. Remote block transfer instructions in an STI cause the processor to resume executing lower priority ladder programs while waiting for the block transfer to complete. If you want the STI to run to completion before returning to your main logic program, include a UID (User Interrupt Disable) and UIE (User Interrupt Enable) instruction pair in your STI program file. Place the block-transfer instruction inside of a UID/UIE pair.
8-4
Using a Processor Input Interrupt

New Platform Processors Only You can use a processor input interrupt (PII) as an event-driven interrupt or in high speed processing applications. For example, use a PII if you need to count inputs quickly to track production (such as in a canning line). Another instance in which you would use a PII is if your application calls for an immediate input update when a part is seen on a conveyor, and then requires an immediate output update to perform the next action (for example, when a part moving down a conveyor line is detected, you may need to stop it so the next piece can be added). Your PII program can contain these immediate update instructions to complete the highspeed control function. As your ladder program is running and the input condition occurs, the processor interrupts program execution and runs the PII program file. Then, the processor resumes executing the program file from where it was interrupted. This chapter shows you how to set up and use a processor input interrupt (PII).
9-1
Writing PII Ladder Logic

Follow these rules when writing ladder logic for a PII program file: Store the PII program in a ladder file. Make sure the input condition (to cause the interrupt) doesnt occur faster than the execution time of the PII program. If a second input condition occurs before the interrupt program has finished executing for the first input condition, a PII overlap occurs and the processor sets a minor fault bit at S:10/12. The timing for a PII is as follows:

1 ms to switch to the PII task PII ladder logic execution time 1 ms to return to executing the control program
Since you need to allow at least 1 ms to run your PII logic, define a PII time of at least 3 ms to help prevent PII overlaps. Be aware that the processors watchdog timer continues to run while running a PII program. A PII can detect an event within 100 s; however, you must allow at least 3 ms between successive PII events.
Note
If the interrupt occurs during the execution of an instruction, the processor stops executing the instruction, scans the interrupt file once to completion, then resumes executing the instruction. In effect, execution of a PII is transparent to program execution time unless you program too many too often. Too many PIIs too often can cause the watchdog timer to time out or cause excessively long program scans. Consider the following guidelines when you create your PII: Do not use 2-slot addressing when using PIIs. Do not use 1771-IG or -IGD, 8- and 16-point TTL modules for the PII. Use the 1771-IQ16 input module instead. Since the modules input delay filter is selectable, you can set the delay to 0 or about 200 s. Avoid using a block-transfer module in the processor-resident rack with a PII configured because you could miss an input pulse while a block-transfer of data is in progress. If you need to use block-transfers, however, make sure that a PII input pulse is at least 400 s which causes the block-transfer not to affect the PII.
9-2
Online editing affects the performance of a PII routine. A PII cannot interrupt the processor while it is managing its memory due to the online edits being made. The PII input must be on for an amount of time slightly greater than the actual time required to complete the online edits. If not, the PII does not execute. Clear S:51 in one of two ways:

using a CLR instruction (see the example on page 9-5) placing a MOV (move) instruction on the last rung in the PII file. Move a 0 into S:51 to reset the PII bits before finishing the PII file. If S:51 is not cleared, a PII overlap bit is set on that status page, causing a minor fault.
Note
9-3
PII Application Examples

You can use a PII program in one of two ways, counter mode or bit transition mode. These are described below.
Using Counter Mode

Using counter mode, you make use of the New Platform PLC-5 processor's internal counter. Configure the PII with a preset value so that the hardware counts your input condition and then runs the PII when the preset equals the accumulated value. The actual PII ladder logic then only needs to contain the output that you want to occur.
Using Bit Transition Mode

Using bit transition mode, you configure the PII to occur every time the input condition is true (versus counting x input conditions and then running the PII). To get the same result as counter mode, you would have to include a counter in your PII ladder program to count the input events, and then set the output when the counter reaches the preset value. Bit Transition Mode Example For example, you want to count tablets as they leave the production line at a rate of 100 tablets per second. The machinery packs 100 tablets per package. Assume an optical switch detects each tablet. The PII program must: Count 100 tablets per group Set an output at the 100th tablet Reset the counter for the next group
9-4
C5:0.CU U CTU COUNTER UP Counter Preset Accum C5:0 DN Output C5:0 RES CLR CLEAR Destination S:51 C5:0 100 0 DN CU
Output
The output image bit remains set until the next count.
9-5
Setting Up a PII
To set up a PII, you need to: Store the configuration information of the PII program in the processor status file Create the ladder file and enter the ladder logic
Use the processor configuration screens to enter this information. PII configuration changes are not put into effect until the processor goes from Program to Run or Test mode. Also, if the input word number specified (S:47) is not in the local rack or if there is not an input module in the slot addressed, a minor fault bit (S:10/11) is set at mode transition. For more information on using the processor configuration screens to enter this information, see the processor configuration chapter in the PLC5 A.I. Series Software Reference manual.
Configuring the PII

To configure a PII, you need to specify the information shown in the table below:
PII Characteristic: program file number module group Status Description: File Word: S:46 S:47 Enter the number of ladder file that contains the PII program. Enter the assigned rack number and I/O group number of the input to monitor (for example 21 for rack 2, group 1). Do not enter the address. For each module group bit (specified in S:47 above): Enter 0001 (1 in hexadecimal) to monitor the bit Enter 0000 (0 in hexadecimal) to ignore the bit. Each module group (specified in S:47) has a bit used wen controlling a PII through bit transition. For a false to true transition to count (bit trigger), enter 0001 (hexadecimal). For a true to false transition to count (event trigger), enter 0000 (hexadecimal).
bit mask
S:48
compare value
S:49
9-6
PII Characteristic: down count
Status Description: File Word: S:50 Enter a preset value to determine how many instances of a condition will occur before the interrupt. Valid range is 0 32,767. Enter a 0 or 1 if you want the interrupt to occur every time. For example, in the PII Application Example on page 9-4, you would enter 100 in S:50.
For more information on setting these values on the Processor Configuration screen, see the processor configuration chapter in the PLC5 A.I. Series Software Reference manual.
Block Transfers Used Within a PII

You can use the PII for a block transfer to remote I/O in New Platform PLC-5 processors. Remote block-transfer instructions in a PII cause the processor to resume executing lower priority ladder programs and STIs while waiting for the block transfer to complete. If you want the PII to run to completion before returning to your main logic program, include a UID (User Interrupt Disable) and UIE (User Interrupt Enable) instruction pair in your PII program file. Place the block-transfer instruction inside of a UID/UIE pair.
9-7
Monitoring a PII
When the PII is generated, the processor updates the PII Return Mask and the PII Accumulator in the status file. Use the processor status screen to monitor PIIs. For information on using the processor status screen, refer to the PLC-5 A.I. Series Software Reference manual. The PII related status addresses are described below.
PII Return Mask

The PII return mask (S:51) displays the bit transitions that caused the interrupt. You can then use this information to condition other rungs in your ladder program. Note If one of these bits is already set (that is, a previous interrupt set the bit), the processor sets a minor fault (S:10/12) to indicate a possible PII overlap. If you want to monitor this overlap, make sure the last rung in your PII program clears this return mask in the status file.
PII Accumulator
The PII Accumulator (S:52) displays the number of conditions that occurred before the interrupt. This value should match the value in the counter field of your configuration information. If these values do not match: The interrupts are not executing when they are supposed to You are trying to count too many events The events are happening too quickly to count
PII Scan Times

The processor stores the scan times of the PII routine in: Last scan time S:55 Maximum scan time S:56
9-8
Writing a Fault Routine
10

You can write a fault routine that the processor runs when it detects a major fault. If your processor faults, you can tell the processor to interrupt the current program, run your fault routine, resetting the conditions for running your process. Then you can have the processor continue with the original program. This chapter shows you how to set and write a fault routine and how to protect your processor from powering up in run mode after a power loss.
10-1
Using Fault Routines

You can use a fault routine to specify how a processor responds to a major fault. You can also use a fault routine to provide protection from powering up in run mode when the processor recovers from a power loss.
Responses to a Major Fault

When the processor detects a major fault, the processor immediately interrupts the current program. If a fault routine exists (specified in S:29 as a fault routine), the processor runs that fault routine program. Depending on the type of fault, the processor: returns to the current ladder program file if the processor can recover from the fault enters fault mode if the processor cannot recover from the fault
For example, the following rung includes an instruction which causes a major fault:
A B Causes a major fault C
] [
In the example above, the processor runs the fault routine after detecting the fault. If the fault routine resets the faulted bits, the processor returns to the next instruction in the program file following the one that faulted (instruction B) and continues executing the remainder of the rung. If you do not program a fault routine for fault B, the processor immediately faults. The bits in word 11 of the processor status file indicate the type of major fault. The following table describes the fault associated with each bit.
10-2
This bit in S:11: Indicates this type of major fault: 00 01 02 03 04 05 corrupted program file (see fault codes 1019 in the table on page 10-4) corrupted address in ladder program (see fault codes 2029 in the table on page 10-4) programming error (see fault codes 3049 in the table on page 10-4) processor detected an SFC fault (see fault codes 7179 in the table on page 10-4) processor detected an error when assembling a ladder program file (see fault code 70 in the table on page 10-4); duplicate LBLs found startup protection fault . The processor sets this major fault bit when powering up in Run mode if the user control bit S:26/1 is set. If your fault routine does not reset this bit, the processor inhibits startup. peripheral device fault usergenerated fault; processor jumped to fault routine (see fault codes 09 in the table on page 10-4) watchdog faulted system is configured wrong (see fault codes 80-88 in the table on page 10-4) recoverable hardware error MCP does not exist or is not a ladder or SFC file PII file does not exist or is not a ladder or SFC file STI file does not contain ladder logic or does not exist fault routine does not contain ladder logic or does not exist faulted program file does not contain ladder logic
06 07 08 09 10 11 * 12 * 13 14 15
* This fault applies to New Platform PLC-5 processors only.
Major Fault Codes

The following table lists major fault codes. The processor stores the fault code in word 12 of the processor status file.
10-3
This fault code: Indicates this fault: 00 09 10* 11* 12 13 14 15 16 17 18 19* 20 21 22 23 24 30 31 32 33 34 35 36 37 38 39* 40 reserved for userdefined fault codes runtime data table check failed bad user program checksum bad integer operand type, restore new processor memory file bad mixed mode operation type, restore new processor memory file not enough operands for instruction, restore new processor memory file too many operands for instructions, restore new processor memory file corrupted instruction, probably due to restoring an incompatible processor memory file cant find expression end; restore new processor memory file Missing end of edit zone; restore new processor memory file download aborted you entered too large an element number in an indirect address you entered a negative element number in an indirect address you tried to access a non-existent program file you used a negative file number, you used a file number greater than the number of existing files, or you tried to indirectly address files 0, 1, or 2 you tried to indirectly address a file of the wrong type you tried to jump to one too many nested subroutine files you did not enter enough subroutine parameters you jumped to an invalid (nonladder) file you entered a CAR routine file that is not 68000 code you entered a negative preset or accumulated value in a timer instruction you entered a negative time variable in a PID instruction you entered an outofrange setpoint in a PID instruction you addresses an invalid module in a block transfer, immediate input, or immediate output instruction you entered a return instruction from a nonsubroutine file FOR instruction with missing NXT the control file is too small for the PID, BTR, BTW, or MSG instruction
The fault is:
Recoverable the fault routine can instruct the processor to clear the fault and then resume scanning the program. A fault routine executes when any of these faults occur.
Non-recoverable the fault routine will be executed but cannot clear major fault bit 2.
Recoverable
Non-recoverable Recoverable
10-4
This fault code: Indicates this fault: 41* 42 43* 44 NXT instruction with missing FOR you tried to jump to a non-existent label file is not an SFC error using SFR. This error occurs if: you tried to reset into a simultaneous path you specified a step reference numer that is not found or is not tied to a step (it is a transition) the previous SFR to a different step is not complete 45 46 69 70 71 72 73 74 75 76 77 78 79 80 invalid channel number entered reserved the processor detected duplicate labels the processor tried to start an SFC subchart that is already running the processor tried to stop an SFC subchart that isn't running the processor tried to start more than the allowed number of subcharts SFC file error detected the SFC has too many active functions SFC step loops back to itself the SFC references a step, transition, subchart, or SC file that is missing, empty, or too small the processor cannot continue to run the SFC after power loss you tried to download an SFC to a processor that cannot run SFCs you incorrectly installed a 32point I/O module in a 1slot configuration (Original PLC-5 processors) you have an I/O configuration error (New Platform PLC-5 processors) you illegally set an I/O chassis backplane switch by setting both switch 4 and 5 ON illegal cartridge type for selected operation. This error also occurs if the processor doesn't have a memory module, but the backplane switches are set for a memory module. Make sure the backplane switches are correct (set switch 6 ON and switch 7 OFF if the processor doesn't have a memory module). user watchdog fault error in userconfigured adapter mode block transfer memory module bad memory module is incompatible with host
The fault is:
81 82*
83* 84* 85* 86*
10-5
This fault code: Indicates this fault: 87* 88 scanner rack list overlap Scanner channels are overloading the remote I/O buffer; too much data for the processor to process. If you encounter fault code 88, review the guidelines for assigning racks in the Allen-Bradley documentation that came with your processor. Specifically, make sure you: group together 1/4-racks and 1/2-racks of each logical rack. Do not intersperse these with other rack numbers. if using complementary I/O addressing, treat complementary rack addresses individually when grouping racks; primary rack numbers are separate from complement rack numbers. 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 200 201 Sidecar module extensive memory test failed. Call your Allen-Bradley representative for service sidecar module undefined message type sidecar module requesting undefined pool sidecar module illegal maximum pool size sidecar module illegal ASCII message sidecar module reported fault, which may be the result of a bad sidecar program or of a hardware failure sidecar module not physically connected to the PLC-5 processor sidecar module requsted a pool size that is too small for PC command (occurs at power-up) sidecar module first/last 16 bytes RAM test failed sidecar module-to-processor data transfer faulted processor-to-sidecar module transfer failed sidecar module end of scan transfer failed the file number specified for raw data transfer through the sidecar module is an illegal value the element number specified for raw data transfer through the sidecar module is an illegal value the size of the transfer requested through the sidecar module is an illegal size the offset into the raw transfer segment of the sidecar module is an illegal value sidecar module transfer protection violation; for PLC-5/26, -5/46, and 5/86 processors only ControlNet output transfer missed ControlNet input data missed
3
The fault is:
Recoverable
10-6
This fault code: Indicates this fault: 202 203 204 205 ControlNet diagnostic data missed ControlNet schedule transmit data overflow ControlNet configuration too complex for the PLC-5 processor ControlNet configuration exceeded PLC-5 bandwidth
The fault is:
* This fault applies only to New Platform PLC-5 processors. Note If the PLC5 processor detects a fault in the fault routine (double fault condition), the PLC5 goes directly to fault mode without completing the fault routine.
10-7
Programming a Fault Routine

If you choose to program a fault routine, first examine the major fault information recorded by the PLC5 and decide whether to do the following before the PLC5 processor automatically goes to fault mode: Set an alarm Clear the fault Shutdown in an orderly manner
Upon detecting a major fault, the processor immediately suspends the program file it was running and, if programmed, runs the fault routine file once to completion. If the processor does not run a fault routine, or the fault routine does not clear the fault, the processor automatically switches to fault mode.
Set an Alarm
You may need an alarm to signal when a major fault occurs. Put this rung first in your fault routine program and combine it with a counter.
alarm output
You can also set an alarm in your fault routine to signal when the fault routine clears a major fault.
Clearing the Fault

If you decide to clear the fault in the fault routine, place the ladder logic for clearing the fault at the beginning of the fault routine. You can compare the fault code with a reference. Compare the Fault Code with a Reference Identify the possible major faults and then select only those your application will let you safely clear. These are your reference fault codes.
10-8
From the fault routine, examine the major fault code that the processor stores in S:12. Use an FSC instruction to compare the fault code to the reference file that contains acceptable fault codes (wordtofile comparison). If the processor finds a match, the FSC instruction sets the found (.FD) bit in the specified control structure. Use a CLR instruction to clear the fault in S:11. Then jump to the end of the fault routine to quickly complete running the fault routine. In the drawing below, #N10:0 is the reference file.
R6:0 RES FSC FILE SEARCH/COMPARE Control Length Position Mode Expression S:12 = #N10:0 R6:0 CLR CLEAR Dest S:11 0 10 JMP R6:0 20 0 ALL ER DN EN
] [
FD
10 ] LBL [
TND
END
10-9
The processor completes the scan of the fault routine. If the routine clears S:11, the processor returns to the program file and resumes program execution. If the fault routine does not clear S:11, the processor executes the rest of the fault routine and goes into FAULTED mode. Note If the fault routine clears the major fault, the processor completes the fault routine and returns to the next instruction in the program file after the one that contained the faulted instruction. The remainder of the rung with the faulted instruction is executed as if the rung were false. It appears that the fault never occurred. The cycle of recurring fault routine execution continues until you correct the major fault.
Using Shutdown Logic

Shutdown programming considerations should include the following: Store initial conditions and reset other data to achieve an orderly startup later. Monitor the shutdown of critical outputs. Use looping if needed to extend the single fault routine scan time up to the limit of the logic processor watchdog timer so your program can confirm that critical events took place.
Testing a Fault Routine

To test a fault routine, use a JSR instruction to the fault routine. Send a fault code as the first parameter of the JSR instruction. The processor stores the fault code in status word 12 and sets the corresponding bit in word 11. You may detect and set your own faults using fault codes 09 or by using the processordefined fault codes 1280.
10-10
Setting Up a Fault Routine

You can write multiple fault routine programs and store them in multiple fault routine files, but the logic processor runs only one fault routine program when the PLC5 detects a major fault. The number of the fault routine the PLC5 runs is stored in word 29 of the processor status file. Typically, you enter a fault routine file number with the programming software and change the specified fault routine file from the ladder program. To set up a fault routine, you need to: Enable the fault routine Change the specified fault routine from ladder program, if necessary Create the program file and enter fault routine logic
Enabling a Fault Routine

To enable a fault routine, store the program file number (31999), of the file that contains the fault routine logic, in word 29 of the processor status file. When the processor encounters a major fault, the processor runs the fault routine logic to handle the fault. If you do not specify a program file number, the processor immediately enters fault mode after detecting a fault.
Changing the Fault Routine from Ladder Logic

You can change the specified fault routine from ladder logic by copying a new fault routine file number into word 29 of the processor status file. The following drawing shows an example program for changing the fault routine file number.
MOV MOVE Source Dest 12 S:29
10-11
Be sure not to corrupt the program-file number of the fault routine, nor use the same file for any other purpose. If the file number you specify results in a nonexistent fault routine, the processor immediately enters fault mode after detecting a fault. Unexpected machine operation may result with damage to equipment and/or injury to personnel.
Clearing a Major Fault

You can clear a major fault with one of the following methods: Use the programming software to clear the major fault. For more information about using the programming software to clear major faults, see the PLC5 A.I. Series Software Reference manual. Note Turn the keyswitch on the PLC5 processor from REM to PROG to RUN.
Clearing a major fault does not correct the cause of the fault. The PLC5 processor might continue to repeat the fault cycle until you correct the cause(s) for the major fault.
10-12
Setting PowerUp Protection

You can set your processor so that after a power loss the processor does not come up in run mode. Bit 1 in word 26 of the processor status file sets powerup protection. The table below shows the states for this bit.
If S:26/1 is: Set (1) Reset (0) Then after power loss: the processor scans the fault routine before returning to normal program scan the processor powers up directly at the first rung on the first program file
Set word 26, bit 1 manually from the Processor Status screen (see the PLC5 A.I. Series Software Reference manual), or you can latch this bit through ladder logic. When set, the processor scans the fault routine once to completion after the processor recovers from a power loss. You can program the fault routine to determine whether the processors status will let the processor respond correctly to ladder logic and whether to allow or inhibit the startup of the processor.
Allowing or Inhibiting Startup

Bit 5 of status word 11 controls whether the processor can start up after a power loss. After a power loss, the processor automatically sets this bit. The table below shows how you can change this bit from your fault routine.
If the Fault Routine Makes S:11/5: Set (1) Reset (0)
Then: the processor faults at the end of scanning the fault routine; leave this bit set to inhibit startup. the processor resumes scanning the processor memory file; reset this bit to allow startup
Note
You can use JMP and LBL instructions to scan only the portion of the fault routine associated with a particular fault or powerup condition.
10-13
Using Adapter Mode
11
Using Adapter Mode

An Original PLC-5 processor in adapter mode can communicate with the local I/O chassis and with a supervisory processor. A New Platform PLC-5 processor can scan local I/O and remote I/O and communicate with a supervisory processor. If you have your processor configured for adapter mode, use this chapter for information on how a PLC5 processor transfers data.
11-1
Using Adapter Mode

Adapter mode communication allows you to connect independent programmable controllers via the remote 1771 I/O communication network for distributed control. You can monitor status between the supervisory PLC-5 processor and the adapter PLC-5 processor at a consistent rate. That is, the throughput of the remote I/O communication network is unaffected by programming terminals and other noncontrol related communications, such as message instruction transmissions, on the DH+ link.
Supervisory processor remote I/O link
Adapter mode processor
1771 I/O DL40 message display
11-2
Using Adapter Mode
Operating in Adapter Mode

In adapter mode: Your PLC5 processor appears to the supervisor as a remote I/O adapter

in a 8 or 16slot chassis for an Original PLC-5 processor in a 4, 8, 12 or 16slot chassis for a New Platform PLC-5 processor
Your PLC5 processor transfers I/O data and status data using discrete transfers and block transfers An Original PLC-5 processor scans ladder logic, monitors and controls its own local I/O A New Platform PLC-5 processor scans ladder logic, monitors and controls its local I/O and remote I/O simultaneously (due to the different channel configurations) Your PLC5 processor provides concurrent communication over Data Highway Plus
If the supervisory processor is a PLC3 processor, the 1775S4A or 1775S4B scanner must be series B, revision A or later.
Configuring an Original PLC-5 Processor for Adapter Mode

When you configure your processor for adapter mode, you set switch assemblies SW1 and SW2, as described in the 1785 PLC5 Family Programmable Controllers Hardware Installation Manual (AllenBradley Publication 17856.6.1). Follow these steps to configure your processor: 1. 2. Select adapter mode on switch assembly SW1. Assign a rack address (rack number 0-77 octal) on switch assembly SW2. (The rack number range is determined by the processor type of the supervisory processor which can be a PLC-3, PLC-5 or PLC-5/250 processor.) The supervisory processor uses this address to reference the adaptermode processor. Specify the simulated chassis size, either a half or full rack, and the corresponding first I/O group on switch assembly SW2. The chassis size and first I/O group determine the number of discrete data words (4 words for a half rack, 8 words for a full rack) the processor transfers to and from the supervisory processor during the supervisory processors remote I/O scan.
3.
11-3
The actual size of the chassis has no bearing on the simulated size of the chassis. Note 4. In adapter mode, the processor reserves rack 3 I/O image tables (I:30-37 and O:30-37) for I/O communication with the supervisory processor.
If you use 1/2slot addressing with a 16slot I/O rack, you need to use rack 3 I/O image tables of the adapter mode processor for backplane communication with local I/O. In this case, create an adapter image file. (See page 11-9 in this chapter)
Configuring a New Platform PLC-5 Processor for Adapter Mode

To configure communications for a New Platform PLC-5 processor, use the Processor Configuration and Channel Configuration screens. The default channel for adapter mode is 2A. To configure your New Platform processor, see the PLC5 A.I. Series Software Reference manual.
11-4
Using Adapter Mode
Transferring Discrete I/O and Block Data

There are three methods for transferring data in adapter mode: Discrete I/O transfer (using rack 3) Discrete I/O transfer (using an adapter image file) Block transfer
The processor performs the transfer of discrete I/O and block data in the same way. The processor scans the processor memory file to read inputs and control outputs. The processor scans local I/O and block data during the I/O scan and the I/O update is synchronous to the program scan. The drawing below shows how the processor transfers discrete I/O in adapter mode.
Adapter Mode Processor Remote I/O

Adapter
Other Racks x y
Housekeeping
Supervisor Scanner Remote I/O Buffer Local I/O Remote I/O Scan Local Rack read inputs write outputs read inputs
1-3 ms typical
Immediate I/O IOT (x) IIN (y)
write outputs
Program Scan
x y I/O Scan
End
11-5
The adapter processor and the supervisory processor automatically transfer discrete data between themselves via the supervisory processors remote I/O scan. During each remote I/O scan: if the supervisory processor is an Original PLC-5, it transfers either 4 or 8 words (depending on whether the adapter processor is configured as half rack or full rack) of its output image table to the corresponding input image file of the adapter processor. If you are using a New Platform processor, it transfers 2, 4, 6 or 8 words depending on whether the adapter processor is configured as a 1/4, 1/2, 3/4 or full rack) if the adapter processor is an Original PLC-5, it transfers 4 or 8 words of its output image file to the corresponding input image table of the supervisory processor. If you are using a New Platform processor, it transfers 2, 4, 6 or 8 words depending on whether the adapter processor is configured as a 1/4, 1/2, 3/4 or full rack.
The following drawing shows the transfers between the supervisory output image table and the adapter input image file, and between the adapter output image file and the supervisory input image table.
11-6
Using Adapter Mode
Supervisory Processor Word 17 14 13 10 07 04 03 *0 1 2 Supervisory Processor PLC-2 0X0-0X7 3 Output Image PLC-3 OXX0-OXX7 4 Table PLC-5 O:X0-O:X7 5 6 7 Supervisory Processor Word 17 14 13 10 07 04 03 *0 1 2 Supervisory Processor PLC-2 1X0-1X7 3 PLC-3 IXX0-IXX7 Input Image 4 PLC-5 I:X0-I:X7 Table 5 6 7 00 00
Adapter-Mode Processor I:30 - I:37 (or adapter image file) 17 14 13 10 07 04 03 00
Input Image File
Adapter-Mode Processor O:30 - O:37 (or adapter image file) 17 14 13 10 07 04 03 00
Output Image File
* Word 0 in an Original PLC-5 processor is reserved for block transfer and status; if you are using a New Platform PLC-5 processor, bits 00-07 are available for user data
Note
If data from the supervisory processor is intended to control outputs of the adapter processor, the ladder logic in the adapter processor must move the data from the adapter processors input image table (I/O rack 3 or the adapter image file) to its output image table (local I/O) with XIC and OTE instructions for bit data or MOV and COP instructions for word data. If you want the supervisory processor to read data from a data file in the adapter processor, ladder logic in the adapter processor must move that data to the adapter processors output image table (I/O rack 3 or the adapter image file) for transfer to the supervisory processor.
11-7
Programming Discrete Data Transfers

For the supervisory processor to read data from the adapter processor, you have to make sure the adapter processor moves the correct data into the output image file (or the adapter image file) for the adapter processor. For the adapter processor to use data from the supervisory processor, the adapter processor has to move incoming data from its input image file.
Using Rack 3
Rack 3 is the default discrete transfer file for Original PLC-5 processors. If you are using a New Platform processor, you can use any file for discrete transfer, including rack 3. Typically, each output instruction in one processor should have a corresponding input instruction in the other processor. The rack number determines the addresses you use: The ladder logic in the supervisory processor uses the rack number (0-77 octal) of the adapter processor. (The rack number range is determined by the processor type of the supervisory processor which can be a PLC-3, PLC-5 or PLC-5/250 processor.) Condition the ladder logic with bit 10 octal (if using rack 3 I/O image). When set, this bit indicates a communication failure between the adapter and supervisory processors. The ladder logic in the adapter processor uses I:031-037 for input data and O:031037 for output data, unless you specify a special adapter image file. To specify rack 3 for New Platform PLC-5 processors, use input I:024 and output 0:024 decimal; the processor interprets these as I:030 and O:030 in octal.
11-8
Using Adapter Mode
Creating an Adapter Image File - Original PLC-5 Processors

If you use 1/2slot addressing in a 16slot chassis, you need rack 3 for scanning local I/O on the adapter processor. In this case, you can create an adapter image file for transferring data. Before you create an adapter image file, make sure these conditions are true: The PLC5 processor is in adapter mode. The adaptermode processor is in a 1771-A4B I/O chassis. You are using 1/2slot addressing. You have not inhibited rack 3 by setting the rack inhibit bit 3 in processor status word 27
To create the adapter image file, create a 16word integer file. This file must be 16 words regardless of whether you use 4word or 8word transfers. This file must be a unique integer file, for use only as an adapter image file. Words 0-7 are used for output; words 8-15 are used for input. Bits are numbered in decimal 0-15 for each word. To tell the processor which file is the adapter image file, enter the file number in word 25 of the processor status file. You enter this file number on the Processor Status screen. For more information about the Processor Status screen, see the section on using status data in the Troubleshooting and Diagnostics chapter of the PLC5 A.I. Series Software Reference manual. Condition the ladder logic with bit 8, word 0 of the adapter image file. When set, this bit indicates a communication failure between the adapter and supervisory processors.
Do not program block transfers to a supervisory processor if you created an adapter image file. For more information about block transfers, see page 11-14 in this chapter.
Creating an Adapter Image File - New Platform PLC-5 Processors

To create an adapter image file for a New Platform processor, use the channel configuration screen. You will need to specify an input sourcethe starting address for adapter input, and an output sourcethe starting address for adapter output. For both the input source and the output source, enter a data table file number and a starting element number in decimal. The following table shows two examples of input source and output source entries.
11-9
Sample Entry input source output source input source output source 010:050 011:050 012:016 012:000
Starting Address adapter inputs start at N10:50 adapter outputs start at N11:50 adapter inputs start at N12:16 adapter outputs start at N12:0 and end at N12:15
The processor determines the number of words used by the file(s) according to the size of the chassis:
Chassis Size: 1/4 1/2 Word Length: 2 4 Chassis Size: 3/4 full Word Length: 6 8
For more information on configuring a channel for adapter mode, see the PLC5 A.I. Series Software Reference manual.
Transferring Bits between Supervisory (PLC-2) and Adapter Processors

The drawing below shows ladder logic for transferring bit 17 of the supervisory processors output image word 7 and bit 16 of the adapter processors output image word 5. The X represents the adapter processors rack number; rack 3 is the simulated rack for the adapter processor. This example assumes 1slot or 2slot hardware addressing. The supervisory processor is a PLC-2 processor.
Transferring Bits Using Rack 3 in the Adapter Processor
Supervisory Processor (PLC-2) 0X7 17 1X5 16 Adapter Processor (PLC-5) I:037 17 O:035 16
11-10
Using Adapter Mode
When the supervisory processor sets its output image bit 0X7/17, input image bit I:037/17 in the adapter processor is automatically set. In the same way, when the adapter processor sets output image bit O:035/16, input image bit 1X5/16 in the supervisory processor is automatically set. The drawing below shows ladder logic if you created an adapter image file because you need rack 3 for local I/O. This example uses N51 as the adapter image file.
Transferring Bits Using Your Own Adapter Image File
Supervisory Processor (PLC-2) 0X7 17 1X5 16 Adapter Processor (PLC-5) N51:15 15 N51:05 14
For Original PLC-5 processors, words 0-7 in the integer file represent output, words 815 represent input. For New Platform PLC-5 processors, input source and output source entries determine input and output words.
Determining the Status of the Adapter Processor

Supervisor Adapter Adapter processor sends to Supervisory processor
The supervisory processor receives status bits (see the table below) from the adapter mode processor in word 0 of the input image table for the rack that the adapter processor is emulating:
This status bit of the adapter being set: Octal 10 15 Decimal 8 13 data not valid Adapter processor is in Program or Test mode Indicates this Condition:
The supervisory processor should monitor the rack fault bits for the rack the adapter processor is emulating to determine the status of the remote I/O link.
11-11
Determining the Status of the Supervisory Processor

Supervisor Adapter Supervisory processor sends to Adapter processor
The PLC5 processor in adapter mode sets status bits (see the table below) in I:030 (or word 0 of the adapter image file) of the adapter processors data table. These bits tell the adapter mode processor the status of the supervisory processor and the integrity of the remote I/O communication link.
Status Bits of the Supervisory Processor Set in the Adapter Processors Data Table This bit being set: Rack 3 Input Adapter Input Image Table Image File (octal) (decimal) 10 11 8 9 the adapter processor detects a communication failure or receives a reset command from the supervisory processor the adapter processor receives a reset command from the supervisory processor (processor in Program or Test mode) the adapter processor is powering up; this bit is reset with the first communication from the supervisory processor the adapter processor detects a communication failure (for example, no communication activity on the remote I/O communication link within the last 100 msec.) Indicates this Condition:
13 15
11 13
11-12
Using Adapter Mode
Programming Considerations for Using Adapter Mode

In a distributed control system where your process is controlled by several independent programmable controllers, you must make sure that your program considers the status of the PLC-5 processors and the integrity of the communication link by using the status bits that the supervisory and adapter mode processor provide for each other (see the tables on pages 11-11 and 11-12). For example, how should your process respond if: there is an incremental degradation of the systems control due to the loss of one of the programmable controllers the supervisory processor is in Program mode and someone manually activates a valve normally controlled by the supervisory processor the adapter processor faults
The adapter processor can monitor the status of the supervisory processor by examining the status bits in the first word of the data being transferred from the supervisory processor (see page 11-12). The supervisory processor can monitor the status of the adapter processor by examining the status bits in the first word of the data being transferred from the adapter processor (see page 11-11). The supervisory processor can also monitor the rack fault bits for the rack the adapter is emulating to determine the integrity of the remote I/O communications between the supervisor and the adapter processors. For more information on rack fault bits, see the PLC5 A.I. Series Software Reference manual.
11-13
Programming Block Transfers - Original PLC-5 Processors

To transfer blocks of data between an adapter processor and a supervisory processor, the adapter processor must have a BTW instruction to respond to the BTR from the supervisory processor (and a BTR to respond to the supervisory processors BTW). For example, when the supervisory processor enables a BTR instruction, the adapter processor responds by enabling a BTW instruction. The supervisory processor controls the transfer; the adapter processor responds to the request. The drawing on the following page shows an example of block transfer programming between an adapter and supervisory processor.
11-14
Using Adapter Mode
Example: Adapter/Supervisor Block Transfer Programming for an Adapter Processor in Rack XX and a PLC-3 Supervisory Processor
Supervisory Processor (PLC-3) Adapter-mode Processor 1771 I/O Chassis Remote I/O Link Set for Rack XX
BTR BLOCK TRANSFER READ 0XX Rack 0 Group 0=LOW Module FB001:0000 Control Data File FB002:0000 Length 0
BTW BLOCK TRANSFER WRITE 3 Rack 0 Group 0 Module N7:15 Control Block Data File N7:200 BT Length 8 Continuous Y
BTW BLOCK TRANSFER WRITE 0XX Rack 0 Group 0=LOW Module FB001:0000 Control Data File FB003:0000 Length 0
BTR BLOCK TRANSFER READ 3 Rack 0 Group 0 Module N7:10 Control Block Data File N7:100 BT Length 40 Continuous Y
Addressing Tips for Block Transfers

The following table lists some addressing tips for programming block transfers between an adapter processor and a supervisory processor.
11-15
BTR/BTW Parameter: BTR/BTW in Supervisor: Rack PLC2/30: PLC3: PLC5/25: must be 0 must be 0 1-7 octal 0-77 octal 0-7 octal
BTR/BTW in Adapter: image rack 3
Group, module Length Continuous
must be 0 number of words transferred
yes (PLC5 and PLC5/250 only) yes
!
Note
To guarantee the correct destination of block transfer data, program only one set of bi-directional block transfers between the supervisory and adapter processors.
If you are using an Original PLC-5 processor, set the supervisory processors communication rate for remote I/O to 57.6K baud. If you have a New Platform processor, you may be able to use 115K or 230K baud depending on what the other device supports. Remember that block transfers between adapter and supervisory processors transfer data between data table addresses. If you want to transfer local I/O data of the adapter mode processor to a supervisory processor or if you want to transfer data from the supervisory processor to local I/O of the adapter mode processor, you must use block transfer instructions within the adapter processor to move the data in or out of the data file used in the adapter block transfer instruction. The following drawing shows data transfers from a supervisory processor to an adapter processor and to a local block transfer module, and vice versa.
11-16
Using Adapter Mode
Example: Block Transfer from Supervisory Processor (PLC-3) to Adapter Processor to Local Block Transfer Module and Vice Versa Supervisory Processor (PLC-3) Adapter-mode Processor in Supervisory Processor's Remote I/O Rack 2 BT Module in Local I/O Rack 0, I/O Group 2 Module 0 * Local BT over chassis backplane Data File N7
BTW BLOCK TRANSFER WRITE Rack 2 Group 0 Module 0=LOW Control FB001:0000 Data File FB002:0000 Length 0 BTR BLOCK TRANSFER READ Rack 3 Group 0 Module 0 Control Block N7:10 Data File N7:100 BT Length 40 Continuous Y
Block Transfers over Remote I/O Link Data File FB002 0000
N7:100
0039 Data File FB003 0000
N7:139
BTW BLOCK TRANSFER WRITE Rack 0 Group 2 Module 0 Control Block N7:15 Data File N7:100 BT Length 40 Continuous Y
To BT Module *
//
BTR BLOCK TRANSFER READ Rack 2 Group 0 Module 0=LOW Control FB001:0000 Data File FB003:0000 Length 0 BTW BLOCK TRANSFER WRITE Rack 3 Group 0 Module 0 Control Block N7:20 Data File N7:150 BT Length 8 Continuous Y
//
BTR BLOCK TRANSFER READ Rack 0 Group 2 Module 0 Control Block N7:25 Data File N7:150 BT Length 8 Continuous Y
N7:150
From BT Module *
0007
N7:157
If you transfer block data with a supervisory processor, you cannot use 1/2slot addressing with a 1771-A4B chassis because the adapter processor needs the rack 3 I/O image table for block transfer communication.
Do not try block transfers to a supervisory processor when the adapter processor uses rack 3 for scanning local I/O (when you create your own adapter image file). Using rack 3 addresses under this condition will result in unpredictable machine operation with possible damage to equipment or personnel.
11-17
Example Ladder Logic

The following figures show example ladder logic for block transfers between an adapter processor and a supervisory processor.
Supervisory Processor (PLC2/30, PLC3, PLC5, or PLC5/250)

Enter the following parameters in the block transfer instructions in the supervisory processor: set the length to 0 set the continuous bit for continuous operation (PLC5 and PLC5/250 only) use the remote I/O rack number for which you configure the adapter processor use 0 for the group and module numbers condition the use of BTR data with a data valid bit (see the table on page 11-11)
11-18
Using Adapter Mode
Example Block Transfer in PLC2/30 Supervisory Processor

BTR Done Bit 120 06 BTW Done Bit 120 07 Store Bit 020
BLOCK TRANSFER WRITE EN 07 DATA ADDR 030 MODULE ADDR 200 BLOCK LENGTH 0 120 DN 140-237 FILE
Store Bit L
Store Bit U
07 Store Bit
BLOCK TRANSFER READ DATA ADDR 031 MODULE ADDR 200 BLOCK LENGTH 0 240-337 FILE
020
EN
06 120
DN
BTR Done Bit Data Valid Bit 120 120 06 10

FILE TO FILE MOVE COUNTER ADDRESS 033 POSITION 0 FILE LENGTH 64 FILE A: 240-377 FILE R: 400-477 RATE PER SCAN 64
06
PLC-5 adapter-mode processor in rack 2
11-19
Example Block Transfer in PLC3 Supervisory Processor

BTR Done Bit B1:0 15 BTR BLOCK XFER READ RACK 2 GROUP 0 MODULE 0 #B1:0 CNTL DATA #B2:0 0 LENGTH BTW BLOCK XFER WRITE RACK 2 GROUP 0 MODULE 0 #B1:0 CNTL DATA #B3:0 0 LENGTH
LE DN ER
Read Request B1:0 17
LE DN ER
BTR Done Bit B1:0 15
Data Valid Bit I:020 10 MVF FILES FROM A TO R #B2:0 SOURCE #B4:0 DESTIN C5 COUNTER ALL MODE 64 LENGTH 0 POSITION
EN DN ER
11-20
Using Adapter Mode
Example Block Transfer in PLC5 Supervisory Processor

BTR BLOCK TRNSFR READ RACK 2 GROUP 0 MODULE 0 CONTROL BLOCK N7:10 DATA FILE N7:100 LENGTH 0 CONTINUOUS Y BTW BLOCK TRNSFR WRITE 2 RACK 0 GROUP 0 MODULE CONTROL BLOCK N7:15 DATA FILE N7:200 LENGTH 0 CONTINUOUS Y BTR Error Bit N7:10 12 BTW Error Bit N7:15 12 BTR Error Bit N7:10 12 Data Valid Bit I:020 10 COP COPY FILE SOURCE DESTIN LENGTH
EN DN ER
EN DN ER
BTR Enable Bit N7:10 U 15 BTW Enable Bit N7:15

U
15
#N7:100 #N7:200 64
11-21
Example Block Transfer in PLC5/250 Supervisory Processor

BR020:0 BW020:0 BTR BLOCK TRNSFR READ RACK 002 GROUP 0 MODULE 0 CONTROL BLOCK BR020:0 DATA FILE 1BTD1:0 0 BT LENGTH CONTINUOUS BT TIMEOUT YES 3 EN DN ER
/
EN
/
EN
BR030:0 BW030:0
/
EN
/
EN
BTW BLOCK TRNSFR WRITE RACK 002 GROUP 0 MODULE 0 CONTROL BLOCK BW020:0 1BTD2:0 DATA FILE 0 BT LENGTH CONTINUOUS BT TIMEOUT YES 3
EN DN ER
BTR Error Bit Data Valid Bit BR020:0 I:020 EN 10

FILE ARITH/LOGICAL 1R0:0 CONTROL 64 LENGTH POSITION 0 MODE ALL DESTIN #1N0:0 EXPRESSION 1BTD1:0 EN DN ER
11-22
Using Adapter Mode
Adapter Processor (PLC5/15, 5/25)

Enter the following parameters in the block transfer instructions in the adapter processor: Use 3 for the rack, 0 for the group, and 0 for the module Set the continuous bit for continuous operation Condition the use of BTR data with status bits from the supervisory processor
Example Block Transfer for PLC5 Processor in Adapter Mode
BTR BLOCK TRNSFR READ RACK 3 GROUP 0 MODULE 0 CONTROL BLOCK N7:10 N7:100 DATA FILE 40 LENGTH Y CONTINUOUS BTW BLOCK TRNSFR WRITE RACK 3 GROUP 0 MODULE 0 CONTROL BLOCK N7:15 N7:200 DATA FILE 8 LENGTH CONTINUOUS Y
EN DN ER
EN DN ER
BTR Error Bit N7:10 12 BTW Error Bit N7:15 12 I:030 I:030 I:030 I:030 10 11 12 15 BTR Error Bit N7:10 12
COP COPY FILE SOURCE DESTIN LENGTH
BTR Enable Bit N7:10 U 15 BTW Enable Bit N7:15 U 15
Status Bits
#N7:100 #N7:200 40
11-23
Adapter Processor (New Platform Processors)

If you have a New Platform PLC-5 processor, you do not need to use ladder logic; you can configure the adapter channels from the channel configuration screens. See the PLC5 A.I. Series Software Reference manual.
11-24
Using Scanner Mode
12
Using Scanner Mode

A PLC5 processor in scanner mode transfers discrete I/O and block data with local and remote I/O chassis. If you have your processor configured for scanner mode, refer to this chapter for information on how a PLC5 processor in scanner mode transfers data. This chapter also gives information on how to handle I/O rack faults for local and remote I/O in scanner mode.
Operating in Scanner Mode

In scanner mode, the processor scans the processor memory file to read inputs and control outputs. The processor scans local I/O during the I/O scan which is synchronous to the program scan. The processor scans remote I/O during a separate scan which is asynchronous to the program scan (but updates the data table from the remote I/O buffer synchronously to the program scan).
Configuring an Original PLC5 Processor for Scanner Mode

When you configure your processor for scanner mode you use switch assembly SW1, as described in the 1785 PLC5 Family Programmable Controllers - Hardware Installation Manual (AllenBradley publication 17856.6.1). Select scanner mode on switch assembly SW1.
Configuring a New Platform PLC5 Processor for Scanner Mode

To configure a New Platform processor for scanner mode, use the Processor Configuration screen. For more information on configuring your processor, see the PLC5 A.I. Series Software Reference manual.
12-1
Transferring Discrete Data

The processor scans local I/O synchronously to the program scan. The drawing below shows how the processor scans local I/O and transfers discrete data.
Remote I/O Rack 3

Adapter
Housekeeping
x y
Immediate I/O IOT (x) IIN (y) read inputs write outputs
1-3 ms typical
Adapter
Rack 2
Remote I/O Buffer Local I/O
Program Scan
Rack 1
Adapter
Local Rack
read inputs write outputs
x y Remote I/O Scan I/O Scan
End
The processor: Presents all discrete I/O data synchronously to the program scan. Scans discrete I/O data in the local I/O chassis synchronously to the program scan. Scans discrete I/O data in remote I/O chassis asynchronously to the program scan. The remote I/O scan transfers discrete I/O data between remote I/O adapters in I/O chassis and the remote I/O buffer in the processor. Performs housekeeping once per program scan:

Original PLC-5 processor: 3 ms maximum; typically 1.5 ms New Platform PLC-5 processor: 4.5 ms
12-2
Using Scanner Mode
Transferring Block Data

The processor transfers blocks of data to and from its local and remote I/O chassis when operating in scanner mode. The processor performs block transfers asynchronously to the program scan. The processor also interrupts the program scan asynchronously to momentarily access BTW and BTR data files. The processor performs one remote block transfer per addressed rack per remote I/O scan. The drawing below shows how the processor handles transferring block data to local and remote I/O.
Remote I/O Scan Housekeeping Q = Queue A = Active Buffer BT
One transfer per remote I/O scan
Remote I/O 2-slot addressing Rack 4

Adapter
Q A
Requests BTR or BTW Data
*
BT Requests
* Interrupt from STI or Fault Routine
Q
Adapter
BTR or BTW Data
1-slot addressing
One transfer per remote I/O scan One transfer per remote I/O scan
A Q A
Rack 2 and 3
*
BTRequests BTR or BTW Data
*
BT Requests
Program Scan
2-slot addressing Rack 1
Adapter
One transfer per remote I/O scan
Q A
BTR or BTW Data
BT Requests
Q Local Rack 0 Multiple Block Transfers A *
BTR or BTW Data
End I/O Scan I/O Scan
12-3
Queued Block Transfer Requests

If your ladder program requests more than one block transfer to or from the same I/O chassis in the same program scan, the processor queues the requests. Original PLC-5 processors can handle up to 17 requests per chassis; New Platform processors can handle up to 128 remote block transfer requests. After the processor queues the requests, an Original PLC-5 processor runs the block transfers in the order they are requested. The only exception is a block transfer request in a fault routine or STI (see the drawing on page 12-6). Since a New Platform processor can request many block transfers to a single chassis at the same time, the adapter device chooses the order in which the block transfers execute. The exception is a block transfer request in a fault routine, STI or PII (see the drawing on page 12-8). The processor has an active area. The processor places a block transfer in the active area when the processor takes the request off the queue. The processor places a block transfer request directly in the active area only if the queue is empty.
Block Transfers to Local I/O

Block transfers to local I/O follow these procedures: Block transfer requests are queued for the addressed local I/O rack. The active buffer handles all block transfer modules whose block transfer instructions were enabled in the program scan continuously via the queue scan in the order the requests were queued. The processor momentarily interrupts program scan when the active buffer performs a block transfer request to access the block transfer data file. Block transfers can finish and the done bit can be set anytime during the program scan.
The processor runs all enabled block transfers to local I/O continuously as each block transfer request enters the active buffer. The processor does not wait for the I/O scan to queue the requests.
Block Transfers to Remote I/O

Block transfers to remote I/O follow these procedures: Block transfer requests are queued for each addressed remote I/O rack. Each active buffer transfers one data block per remote I/O scan. The processor momentarily interrupts program scan when the active buffer performs a block transfer request to access the block transfer data file.
12-4
Using Scanner Mode
If program scans are two or three times longer than remote I/O scans, the processor can run two or three remote block transfers per program scan and interrupt the program scan two or three times.
Block Transfers in Fault Routines or Selectable Timed Interrupts (STIs)

If the processor runs a fault routine or a selectable timed interrupt (STI) that contains block transfers, the processor performs these block transfers immediately upon completing any block transfers currently in the active buffer, ahead of block transfer requests waiting in the queue. The block transfers in a fault routine or an STI should only be between the processor and local I/O.
The program scan stops when an Original PLC-5 processor runs a fault routine or STI with a block transfer instruction to a remote chassis. The delay for a block transfer could be unacceptable for your application. However, for a New Platform PLC-5 processor, the MCP resumes processing while the PII or STI is waiting for the block transfer to complete.
12-5
Block Transfer Sequence Original PLC-5 Processors

The drawing below shows the sequence the processor follows to run a block transfer in an Original PLC-5 processor. (If you are using a New Platform processor, see page 128.)
1, 7 Ladder Program
Request
2 Q17 Buffer for 17 BT Requests
Pair of buffers per assigned rack address
6 STI
Priority Request Data Data Acknowledgement and Incoming Data Request and Outgoing Data 3a, 3b, 5 Active BT area
Data Files
4a, 4b I/O Chassis
The following steps describes the numbered sections in the drawing above. 1. 2. Ladder logic enables the block transfer. The processor places the block transfer request in the queue, or in the active buffer if the queue is empty. (If the queue is full, the request is ignored until the next scan.)
12-6
Using Scanner Mode
3.
If the block transfer is a: a. BTW: The processor interrupts the program scan momentarily to transfer data from the BTW file to the active buffer. The active buffer transfers the request and outgoing data to the local I/O module or to the remote I/O adapter. BTR: The active buffer sends the block transfer request to the local I/O module or remote I/O adapter. In the same local block transfer update or in the next remote I/O scan, the active buffer receives the block transfer acknowledgment and incoming data. The processor interrupts the program scan momentarily to transfer incoming data to the BTR file one word at a time; therefore, some ladder logic could execute in between word transfers to the BTR file. We recommend that you buffer your BTR data with a fileto file move or a copy instruction using a BTR done bit to condition the rung if you need file integrity of the data.
b.
4.
If the block transfer is to: a. b. Local I/O: The processor continuously runs block transfer requests for all local I/O modules in the order the processor queues the requests. Remote I/O: The processor runs one block transfer request for one block transfer module per rack address per remote I/O scan.
5. 6.
The processor clears the active buffer and the active buffer accepts the next request after the buffer receives a confirmation of a valid read or write. When the processor enables a fault routine or STI, the processor runs any block transfer program in the fault routine or STI ahead of any block transfer requests in the queue, as soon as the active buffer completes any block transfer currently in the active buffer. The program scan is stopped until the STI or fault routine block transfer is complete. The block transfer process runs asynchronously to the program scan, so data can change during a program scan.
7.
12-7
Block Transfer Sequence New Platform PLC-5 Processors

The drawing below shows the sequence the processor follows to perform a block transfer in a New Platform PLC-5 processor.
1, 7 Ladder Program
Request
2 Block Transfer processing
Holding area
6 STI PII
Priority Request 3a, 3b, 5 Active BT area Acknowledgement and Incoming Data
Data Data Files Data
Request and Outgoing Data
4a, 4b I/O Chassis
The following steps describes the numbered sections in the drawing above. 1. 2. Ladder logic enables the block transfer. The processor examines the block transfer request. If a request already exists for the slot, the processor places the request in the Holding area.
12-8
Using Scanner Mode
3.
If the block transfer is a: a. BTW: The processor interrupts the program scan momentarily to transfer data from the BTW file to the active buffer. The active buffer transfers the request and outgoing data to the local I/O module or to the remote I/O adapter. BTR: The active buffer sends the block transfer request to the local I/O module or remote I/O adapter. In the same local block transfer update or in the next remote I/O scan, the active buffer receives the block transfer acknowledgement and incoming data. The processor interrupts the program scan momentarily to transfer incoming data to the BTR file one word at a time; therefore, some ladder logic could execute in between word transfers to the BTR file. We recommend that you buffer your BTR data with a fileto file move or a copy instruction using a BTR done bit to condition the rung if you need file integrity of your data.
b.
4.
If the block transfer is to: a. b. Local I/O: The processor continuously runs block transfer requests for all local I/O modules in the order the processor queues the requests. Remote I/O: The processor runs one block transfer request for one block transfer module per rack address per remote I/O scan.
5.
The processor clears the active buffer and the active buffer accepts the next request from the Holding area after the buffer receives a confirmation of a valid read or write. When the processor enables a fault routine, STI or PII, the processor runs any block transfer program in the fault routine, STI or PII ahead of any block transfer requests in the holding area, as soon as the active buffer completes any block transfer currently in the active buffer. The program scan is stopped until the STI or fault routine block transfer is complete. The block transfer process runs asynchronously to the program scan, so data can change during a program scan.
6.
7.
Block Transfer Sequence with Status Bits

The following explanations describe how the ladder logic and the I/O scanner handle block transfers with status bits.
12-9
Ladder logic: Detects that the rung containing a block transfer is enabled Sets the enable bit (.EN, bit 15) Detects the status of the read/write bit (.RW, bit 07) Places the block transfer in the active buffer if the queue is empty; the processor sets the start bit (.ST, bit 14) and begins the transfer Places the block transfer in the queue if the active buffer is not empty; the processor sets the enabled waiting bit (.EW, bit 10)
If the queue is full, block transfer requests may not occur in the order the ladder logic requests the transfers. The processor sets the enabled waiting bit (.EW, bit 10) when the request enters the queue. I/O scanner: Transfers the request to or from the I/O chassis after the request reaches the active buffer Detects whether the module responds; if the module does not respond, the processor sets the no response bit (.NR, bit 09) If there is no response and the timeout bit (.TO, bit 08) is reset, the processor re queues the request until the watchdog timer times out (4 seconds). If there is no response and the .TO bit is set, the scanner retries the request one more time before setting the .ER bit. If the request is a:

BTW: transfers the data to the module BTR: moves data from the module to the BTR data file one word at a time
Sets the done bit (.DN, bit 13) upon completion of a valid transfer; sets the error bit (.ER, bit 12) if there were errors Checks the status of the continuous bit (.CO, bit 11); if set and no error occurred, the scanner requeues the block transfer Notifies the active buffer to accept the next request
For a list of block transfer error codes, see the Allen-Bradley documentation that came with your processor.
12-10
Using Scanner Mode
Block Transfer Timing: Original PLC-5 Processors

The time to complete a block transfer in an Original PLC-5 processor depends on: Instruction run time Waiting time in the queue Transfer time
Instruction Run Time

The time in milliseconds it takes the processor to perform a block transfer instruction depends on these formulas:
Write: 310 + 11.2Q + 5.4W Read: 250 + 11.2Q
where: Q represents the number of queued block transfer requests to the same I/O chassis with the continuous bit set W represents the number of words to transfer
Waiting Time in the Queue

The waiting time in the queue is the sum of the transfer times yet to occur before the block transfer request (for which you are calculating time) to the same I/O chassis.
Transfer Time
The transfer time in milliseconds between the active buffer and the module starts when the processor sets the start bit and ends when the processor sets the done bit. The transfer time depends on these formulas:
Write 0.9 + 0.1W 13 + 30C + 0.3W 13 + 21.3C + 0.3W Read 0.9 + 0.1W 9 + 30C + 0.3W 9 + 21.3C + 0.3W
local
local remote (57.6K baud)
remote (57.6K baud) remote (115K baud)
remote (115K baud)
where: C represents the number of remote I/O chassis W represents the number of words to transfer
12-11
Block Transfer Timing: New Platform PLC-5 Processors

The time to complete a block transfer in a New Platform processor depends on: Instruction run time Waiting time in the queue Transfer time
Instruction Run Time

The time it takes the processor to perform a block transfer instruction is the same for a read or a write: 450 microseconds.
Waiting Time in the Holding Area

The waiting time in the holding area is the sum of the transfer times yet to occur before the block transfer request (for which you are calculating time) to the same I/O chassis.
Transfer Time
The transfer time in milliseconds between the active buffer and the module starts when the instruction sets the start bit and ends when the instruction sets the done bit. The transfer time depends on this formula (and is the same for a read or a write):
local remote (57.6K baud) remote (115K baud) 0.9 + 0.1W 4 + 8C + 0.3W 4 + 4.6C + 0.15W
where: C represents the number of remote I/O chassis W represents the number of words to transfer
12-12
Using Scanner Mode
When the Processor Detects a Major Fault

In general, if the processor detects a hardware fault or other runtime error, it sets a major fault bit and stops scanning I/O and the program. The outputs remain in their last state or they are deenergized, based on how you set the last state switch in the I/O chassis (1771A1B, A2B, A3B, A4B). Note In the PLC5 processors local chassis, outputs are reset - regardless of the last state switch setting - when one of the following occurs: Processor detects a run-time error You set a status file bit to reset a local rack You select program or test mode To decide how to set this switch, evaluate how the machines in your process will be affected by a fault. For example, how will the machine react to outputs remaining in their last state or to outputs being automatically deenergized? What is each output connected to? Will machine motion continue? Could this cause the control of your process to become unstable? To set this switch, see the 1785 PLC5 Family Programmable Controllers - Hardware Installation Manual (AllenBradley Publication 17856.6.1).
12-13
When a Resident Local I/O Rack Faults

The chassis that contains the PLC5 processor is the resident local I/O rack. If a problem occurs with the chassis backplane, the input and output data table bits for the resident local I/O rack are left in their last state. The processor sets a minor fault and continues scanning the program and controlling I/O. Your ladder program should monitor the I/O rack fault bits and take the appropriate recovery action (covered later in this chapter).
If a resident local I/O rack fault occurs and you have no recovery methods, the input image table and outputs for the faulted rack remain in their last state. Injuries to personnel and damage to machinery may result.
12-14
Using Scanner Mode
When a Remote I/O Rack Faults

In general, when a remote I/O rack faults, the processor sets an I/O rack fault bit and then continues scanning the program and controlling I/O. The outputs in the faulted rack remain in their last state or they are deenergized, based on how you set the last state switch in the I/O chassis (1771A1B, A2B, A3B, A4B).
If outputs are controlled by inputs in a different rack and a remote I/O rack fault occurs (in the inputs rack), the inputs are left in their last non-faulted state. The outputs may not be properly controlled and injuries to personnel and damage to machinery may result. Make sure you have recovery methods in place.
12-15
Recovering from a Resident Local I/O or Remote I/O Rack Fault

In the PLC5 processor, you can monitor I/O rack faults using PLC5 status bits and then recover from the fault using a fault routine or ladder logic.
Using I/O Status File Bits to Monitor Rack Faults

There are two types of status bits used to display information about your I/O system: global status bits and the I/O status file. Using Global Status Bits The global status bits are set if a fault occurs in any one of the logical racks. See the table below to determine the number of bits.
Processor: New Platform Orig. PLC5/10, 5/12, 5/15 PLC5/25 PLC-5/11, -5/20 PLC-5/30 PLC5/40 PLC5/60, -5/80 Possible Logical Rack Bits: 4 8 4 8 16 24
Each bit represents an entire rack, no matter how many chassis make up a rack. (Remember that you can have up to four chassis configured as quarter racks to make up one logical rack.) These bits are stored in the lower eight bits of status file words 7 and 27 for Original processors and words 7, 32 and 34 for New Platform processors. For more information on global status bits, see the PLC5 A.I. Series Software Reference manual. Using the I/O Status File The I/O status file is used to monitor the racks in your I/O system. This file contains 2 words of status bits for every rack configured in your system. The data file number that contains this I/O information is stored in word 16 (low byte) of the status file. You must enter this information on the Processor Status screen (Original PLC-5) or the Processor Configuration screen (New Platform).
12-16
Using Scanner Mode
For more information on the I/O status file, see the PLC5 A.I. Series Software Reference manual.
Using Fault Routine and Ladder Logic to Recover

You may want to configure an I/O rack fault as a minor fault if you have the appropriate fault routine and ladder logic to perform an orderly shutdown of the system. You can program ladder logic in several ways to recover from a I/O rack fault. These methods are: Usergenerated major fault Reset input image table Fault zone programming
Usergenerated Major Fault Using this method, you jump to a fault routine when a remote I/O rack fault occurs. In other words, if the status bits indicate a fault, you program the processor to act as if a major fault occurred (that is, jump to the fault routine). You then program your fault routine to stop the process or perform an orderly shutdown of your system. When the processor executes the endoffile instruction for the fault routine, a usergenerated major fault is declared. For more information on fault routine programming, see Chapter 10- Writing a Fault Routine. Reset Input Image Table With this method, you monitor the status bits and, if a fault is detected, you program the processor to act as if a minor fault occurred. After the status bits indicate a fault, use the I/O Status screen to inhibit the remote rack that faulted. You then use ladder logic to set or reset critical input image table bits according to the output requirements in the nonfaulted rack. If you reset input image table bits, during the next I/O update, the input bits are set again to their last valid state. To prevent this from occurring, your program should set the inhibit bits for the faulted rack. The global inhibit bits control the input images on a rack by rack basis; the partial rack inhibit bits control the input images on a 1/4 rack basis. This method requires an extensive and careful review of your system for recovery operations. For more information on inhibiting I/O racks, see the PLC5 A.I. Series Software Reference manual.
12-17
Fault Zone Programming Using fault zone programming, you disable sections of your program with MCR (Master Control Reset) zones. Using the status bits, you monitor your racks; when a fault is detected, you control the program through the rungs in your MCR zone. With this method, outputs within the MCR zone must be nonretentive to be deenergized when a rack fault is cleared. For more information on the MCR instruction and MCR zones, see the Instruction Set Reference.
12-18
Programming Through a Serial Port
13

New Platform PLC-5 processors have a serial port that can be used to connect the processor to a terminal that supports ASCII DF1 protocol or to any device that can send or receive ASCII characters. This serial port can operate in two modes: System Mode and User Mode. In System Mode, you can connect to terminals, modems and 1770KF2 series B modules. In User Mode, you can connect to ASCII terminals, modems, bar code readers, dataliners, etc. This chapter gives you an overview of the different ways you can program through a serial port on a New Platform processor: System Mode

Pointtopoint DF1 slave
User Mode
For more information on these communication options, see the Data Highway/Data Highway Plus Protocol and Command Set (AllenBradley Publication 17706.5.16).
13-1
System Mode
In system mode, the processor interprets a command from the other device. Use system mode when you need to communicate with other devices on a Data Highway link. In system mode, you can send data to a device using the message instruction or as an ASCII string using the ASCII write instructions. (For more information on these instructions, see the PLC5 A.I. Series Instruction Set Reference manual.) Using system mode, you can use either of the following protocols: Pointtopoint (or DF1) DF1 slave
PointToPoint
Pointtopoint is a basic serial protocol used when you need: Singledevice to singledevice connection Twoway simultaneous transmission needed
DF1 Slave
The processor can function as a slave in a master/slave serial communication network. Master/Slave communications use a multidrop link with all nodes interfaced through modems. There may be from 2 to 256 nodes simultaneously connected to a single link. One node is designated as the master, and it controls who has access to the link. (For example, a master can be a PLC5/250, 1771KE/KF or 1771KGM). All other nodes are slaves and must wait for permission from the master before transmitting. The master can send and receive messages from all nodes on the link and to nodes on other Data Highway links connected to the multidrop, but a slave can only respond to the master.
13-2
User Mode
In User mode, all received data is put into a buffer. In order to access this data, you use ASCII instructions in your ladder program. Likewise, using ASCII instructions in your ladder program, you can then send ASCII string data to a processor or other device. Note In User Mode, only ASCII instructions can be used; if you try to use a message instruction that references the serial port, the error (.ER) bit is set.
13-3
Changing Modes
You can configure channel 0 of the processor to change communication modes in two ways: Directly - through the Channel Configuration screen Remotely - by defining communication mode change characters that another device can send. You define the ASCII control characters to get the processors attention and then switch modes.
For more information on switching modes, see the PLC5 A.I. Series Software Reference manual.
13-4
Index
Index
A
Adapter Mode block transfer examples..................... 11-18 block transfers................................... 11-14 configuring ......................................... 11-3 operating............................................. 11-3 transfer data........................................ 11-5 transfer status.................................... 11-12 Addressing frequently used files ............................ 7-14 I/O image.............................................. 7-6 indexed ............................................... 7-10 indirect ................................................. 7-8 logical................................................... 7-2 mnemonics ........................................... 7-4 symbolic ............................................. 7-12 Alarm fault routine ........................................ 10-8 Application Program Development Model ... 2-1 STI ..................................................... 12-5 timing for New Platform ................... 12-12 timing for Original............................ 12-11 Branches...................................................... 5-7 execution time....................................... 5-8 nested ................................................... 5-7
C
Clearing a Major Fault.................... 10-8, 10-12 Compare Fault Code to Reference .............. 10-8 Constructing Rungs ..................................... 5-5 Converting Machine Statements to Ladder Logic .................................................... 5-2, 5-6
D
Data Block................................................... 6-3 organizing ............................................ 6-4 user-defined .......................................... 6-3 Data File organizing ............................................ 6-4 types of ................................................. 7-2 Data Storage bit ......................................................... 6-3 concepts................................................ 6-1 data block ............................................. 6-3 element ................................................. 6-2 file ........................................................ 6-2 sub_element.......................................... 6-3 type....................................................... 6-2 user-defined .......................................... 6-3
B
Bit (data file) ............................................... 6-3 Block Transfer........................................... 11-5 addressing......................................... 11-15 examples........................................... 11-18 fault routine ........................................ 12-5 local I/O.............................................. 12-4 programming .................................... 11-14 queued requests................................... 12-4 remote I/O .......................................... 12-4 scanner mode...................................... 12-3 sequence (New Platform) .................... 12-8 sequence (Original)............................. 12-6
Index-i
Design Specification checking for completeness................... 3-13 detailed analysis............................. 2-2, 3-5 example ................................................ 3-2 functional.............................................. 2-2 program development model ................. 2-1 writing functional specification ............. 3-3 DF1 Slave .................................................. 13-2 Digital I/O example instructions ............................. 5-3 Discrete I/O transfer data ............................... 11-5, 11-8 Drawing An SFC ......................................... 4-6
remote I/O rack recovery ................... 12-16 File Boundary ............................................ 7-10 Files data storage........................................... 6-2 frequently used.................................... 7-14 Functional Specification............................... 2-2 writing .................................................. 3-3
G
Gapping....................................................... 6-4 Global Status Bits .................................... 12-16 GOTO definition ............................................ 4-11 rules.................................................... 4-11 GOTOs and Labels ...................................... 4-5
E
Element (data file) ....................................... 6-2 Event_Driven Interrupts........................ See PII Execution Time............................................ 5-8
I
I/O discrete I/O data transfer ............ 11-5, 11-8 image address ....................................... 7-6 status file........................................... 12-16 Indexed Address ........................................ 7-10 Indirect Address........................................... 7-8 Instructions arranging ..................................... 5-5, 5-10 examples............................................... 5-3
F
Fault Routine ............................................... 2-8 alarm .................................................. 10-8 block transfer ...................................... 12-5 changing specified file ...................... 10-11 clearing a fault .................................... 10-8 compare fault code .............................. 10-8 power_up protection.......................... 10-13 programming ...................................... 10-8 setting up .......................................... 10-11 shut down logic................................. 10-10 startup............................................... 10-13 testing ............................................... 10-10 Faults local I/O rack .................................... 12-14 major (types of) ................................... 10-3 major fault codes................................. 10-3 remote I/O rack ................................. 12-15
L
Labels definition ............................................ 4-11 rules.................................................... 4-11 Ladder Logic branch................................................... 5-7 PII......................................................... 9-2 shut down ......................................... 10-10
Index-ii
Index
writing .................................................. 5-5 Local I/O Rack faulting ............................................. 12-14 Logic branch................................................... 5-7 writing .................................................. 5-5 Logical Address........................................... 7-2 mnemonic............................................. 7-4
ladder logic........................................... 9-2 monitoring ............................................ 9-8 program flow ...................................... 3-11 setting up .............................................. 9-6 Placing Instructions ................................... 5-10 Point-to-Point ............................................ 13-2 Power_Up Protection fault routine ...................................... 10-13 Power_Up Routine program flow ...................................... 3-11 Processor Input Interrupt ...................... See PII Processor Status File STI settings........................................... 8-3 Processor Type............................................. 1-1 Program Flow application examples........................... 3-12 considering program features .............. 3-11 Programming Features............................... 3-11
M
Machine Statements converting to logic ......................... 5-2, 5-6 Main Control Program.......................... 2-2, 2-4 configuring ........................................... 2-6 disabling ............................................... 2-6 execution .............................................. 2-4 monitoring ............................................ 2-7 using interrupt programs....................... 2-8 Major Faults clearing............................................. 10-12 codes................................................... 10-3 detecting ........................................... 12-13 responses ............................................ 10-2 Memory Gapping......................................... 6-4 Mnemonic Addressing................................. 7-4 Multiple Main Programs See Main Control Program
R
Remote I/O Rack faulting ............................................. 12-15 recovering from fault ........................ 12-16 Rung creating................................................. 5-5 definition .............................................. 5-2 writing .................................................. 5-5
O
Organizing Data .......................................... 6-4
S
Scanner Mode block transfer ...................................... 12-3 configuring .......... 12-1, 12-2, 12-11, 12-12 operating............................................. 12-1 transferring data ................................. 12-2 Selectable Timed Interrupt................... See STI
P
PII ...................................................... 2-8, 3-11 application examples............................. 9-4 bit transition mode ......................... 9-4, 9-6 counter mode ........................................ 9-4
Index-iii
Selection Branch................................... 4-3, 4-9 Serial Port changing modes .................................. 13-4 DF1 slave communications.................. 13-1 point_to_point communications .......... 13-1 System mode....................................... 13-1 User mode........................................... 13-1 SFC building blocks...................................... 4-1 drawing................................................. 4-6 GOTOs and labels........................ 4-5, 4-11 path....................................................... 4-2 scan sequences .................................... 4-11 selection branch ............................. 4-3, 4-9 SFR instruction ................................... 4-12 simultaneous branch..................... 4-4, 4-10 special structures................................... 4-6 step ....................................................... 4-1 step actions ........................................... 4-2 transition............................................... 4-2 SFR Instruction.......................................... 4-12 Shut Down Logic ..................................... 10-10 Simultaneous Branch ................................... 4-4 post scan mode.................................... 4-10 SoftLogix 5 ................................................ 7-13 Specification, design example ...................... 3-2 Startup Fault Routine ............................... 10-13 Status File....................................... 7-15, 12-16 Step (SFC) ................................................... 4-1
Step Actions................................................. 4-2 STI ..................................................... 2-8, 3-11 block transfer ...................................... 12-5 program flow ...................................... 3-11 setting up .............................................. 8-3 setup in processor status file .................. 8-3 Structure Names ........................................ 7-13 Sub_Element................................................ 6-3 Symbol....................................................... 7-12 System Mode ............................................. 13-2
T
Time_Driven Interrupts ....................... See STI Timing block transfer for New Platform ........ 12-12 block transfer for Original................. 12-11 Transition (SFC).......................................... 4-2 Types (data storage) ..................................... 6-2
U
User Mode ................................................. 13-3
W
Writing branch logic .......................................... 5-7 rung logic.............................................. 5-5
Index-iv

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PLC-5

December 1997 Supersedes Doc. ID 9399-L5PG-04.17.95

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PLC-5 A.I. Series Software Reference

PLC-5 A.I. Series Software Reference

PLC-5 A.I. Series Programming Guide

How to Use This Manual

Planning Programs for Your Application

Planning Programs for Your Application

PLC-5 A.I. Series Programming Guide

Planning Programs for Your Application

PLC-5 A.I. Series Programming Guide

Using Main Control Programs

How the Processor Interprets the MCPs

Planning Programs for Your Application

PLC-5 A.I. Series Programming Guide

Configuring Main Control Programs

Specifying The Order of Main Control Programs

Disabling Main Control Programs

Planning Programs for Your Application

Monitoring Main Control Programs

PLC-5 A.I. Series Programming Guide

Using Interrupt Programs

Designing Programs for Your Application

Designing Programs for Your Application

PLC-5 A.I. Series Programming Guide

Drill Motor LS1 N.O.

Held Open LS5 N.O.

Designing Programs for Your Application

Creating the Functional Specification

PLC-5 A.I. Series Programming Guide

AUTO operator starts cycle

LS1 wood in position

LS4 hole drilled

TMR1 dwell timer done

LS2 station home

LS5 wood ejected

Designing Programs for Your Application

Creating the Detailed Analysis

LS3 closes LS4 closes timer done LS3 opens

PLC-5 A.I. Series Programming Guide

When This Happens: LS2 opens

Designing Programs for Your Application

ladder file initialization

AUTO operator starts cycle ladder file 3 action name conv_frwd

LS4 hole drilled

LS5 wood ejected

PLC-5 A.I. Series Programming Guide

Designing Programs for Your Application

Entering the Program

PLC-5 A.I. Series Programming Guide

Process Sequence MCP

LS4 hole drilled

Ladder Logic for Outputs MCP

Designing Programs for Your Application

Using Other Processor Programming Features

At a specified time interval

Selectable Timed Interrupt (STI)

PLC-5 A.I. Series Programming Guide

Examples of Special Programming Applications

Designing Programs for Your Application

Checking for Completeness

SFC Building Blocks