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i h xin dnh bi ny cho cc bn mun tm hiu v cch m phng c bn bng cch vit testbench vi ModelSim, ti h xin nhn mnh

l c bn v khng c nh ma ru qua mt th. u tin bn phi ci t ModelSim hin nay c cc bn dnh cho sinh vin min ph. Cc bc c th tm v download y. http://model.com/content/modelsim-pe-student-edition-hdl-simulation Cc bn c th khc nhau v giao din v mt s tnh nng, th vin, nhng cn bn cch lm khng khc nhau. Sau khi ci t xong, chng ta thc hin nh sau: Bc 1: Khi ng ModelSim c giao din sau

Bc 2: Vo File/New/Project

Project Location: chn th mc lu project (Ch rng vic to mt th mc mi cng phi dng ModelSim. Nu bn to th mc mi thng thng t WINDOWN th sau ny s khng chy m phng c - xem hnh sau)

Project Name: G tn project (phi trng vi tn file top m bn tnh m phng) Default Library Name: cc bc c nguyn y ti h lm mt encoder_16_4. Nhn OK

Bc 3: Sau khi Nhn OK - c khung sau:

Create new file: To file mi. Add Existing file: Thm file c sn (v d: bn vit file verilog sn v u , bn ch cn copy file vo th mc m bn to project, bn vo y thm file vo) y ti h to file mi

File name: Tn file Add file as type: Chn loi file cn to Folder: C Top Level Nhn OK. Trong ca s WorkSpace xut hin file cn to vi trng thi ? (ngha l cha c tng hp, kim tra).

Nu cn to thm file khc th lm li bc 3. Xong ta Close sang bc 4. Bc 4: Vit RTL code - Nhp i chut vo tn file trong ca s Workspace s hin ra ca s edit vit RTL code.

Bc 5: Compile thit k - Nhp chut phi vo tn file va vit code xong. Chn Compile Selected: Ch kim tra file chn. Compile All: Kim tra tt c cc file trong ca s workspace.

Bc 6: Sa li (nu c). Nu c li, ModelSim s hin dng ch thng bo. Nhp i chut vo n tm v tr li v sa.

Sa v Compile li cho n khi c dng thng bo successful mu xanh

Th l chng ta hon thnh phn vit RTL code v compile thit k trong ModelSim. Bi sau ti h s hng dn mt mn m phng n gin, d lm d xi. Verilog simulatorFormal Verification
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Sun, 25/04/2010 - 06:45

#1
phi_thien_dao

Offline Last seen: 3 weeks 1 day ago Joined: 15/04/2010

Re:ModelSim - Cn bn v ngon - Mi cc bc cng xi

Bi 2: Vit TestBench v m phng

Sau khi to xong mt project, vit RTL code v compile. Khu tip theo l chng ta m phng kim tra. V d c thc hin y l encoder_16_4, ng ra s ch v tr ca ng vo c tch cc v nu c hn hai ng vo bng 1 th ng ra bng 0. Bng gi tr ca encoder_16_4:

Trc ht y l RTL code ca encoder_16_4:

module encoder_16_4( enable, // tin hieu cho phep binary_out, // 4 bit ngo ra encoder_in // 16-bit ngo vao

); //ngo vao input enable; input [15:0] encoder_in; //ngo ra output [3:0] binary_out; //kieu ngo ra reg [3:0] binary_out; //chuong trinh chinh always @ (enable or encoder_in) begin binary_out = 0; if (enable) begin case (encoder_in) 16'h0002 : binary_out = 4'd1; 16'h0004 : binary_out = 4'd2; 16'h0008 : binary_out = 4'd3; 16'h0010 : binary_out = 4'd4; 16'h0020 : binary_out = 4'd5; 16'h0040 : binary_out = 4'd6; 16'h0080 : binary_out = 4'd7; 16'h0100 : binary_out = 4'd8; 16'h0200 : binary_out = 4'd9; 16'h0400 : binary_out = 4'd10; 16'h0800 : binary_out = 4'd11; 16'h1000 : binary_out = 4'd12; 16'h2000 : binary_out = 4'd13; 16'h4000 : binary_out = 4'd14; 16'h8000 : binary_out = 4'd15; endcase end end endmodule
m phng kim tra ta thc hin nh sau:

Bc 1: To testbench Nhp chut phi vo vng trng ca ca s Workspace. Chn Add to project/New file

Ca s Create Project File xut hin

in tn file (tb_encoder_16_4) v chn loi file cn to (verilog). Nhn OK. Ca s edit xut hin v chng ta g file testbench vo

y l ni dung file testbench (vit c bn theo hng dn topic Help me vit testbench)

module tb_encoder_16_4; //ngo vao gan gia tri test reg enable; reg [15:0] encoder_in; //ngo ra quan sat wire [3:0] binary_out; //goi module test encoder_16_4 encoder( enable, // tin hieu cho phep binary_out, // 4 bit ngo ra encoder_in // 16-bit ngo vao ); //phan gan gia tri test initial begin enable = 1'b0; encoder_in = 16'h0001; #500 enable = 1'b1; #200 encoder_in = 16'h0002;

#200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in #200 encoder_in end endmodule

= 16'h0004; = 16'h0008; = 16'h0010; = 16'h0020; = 16'h0040; = 16'h0080; = 16'h0100; = 16'h0200; = 16'h0400; = 16'h0800; = 16'h1000; = 16'h2000; = 16'h4000; = 16'h8000; = 16'h1010;

Bc 2: Compile file testbench (nh compile file RTL code)

Xut hin dng bo successful l xong

Bc 3: Chy m phng Trong ca s Workspace chn th Library, chn mc work ta s thy hai file c compile nh sau

Nhp i chut vo dng c tn file testbench bt u chy m phng. Sau khi nhp i chut ta c kt qu nh sau

Trong hnh trn, bn phi ta thy hai dng c ch Loading bo ti thnh cng hai file bao gm file thit k encoder_16_4 v file testbench tb_encoder_16_4. Bc 4: Chnh khong thi gian cho mt ln chy m phng T bc ny, ti h ch cch chy m phng theo tng khong thi gian chng ta c th d dng quan st. Xem hnh sau bit ch chnh khong thi gian cho 1 ln chy m phng (ti h chnh 1000us mc nh l 100us)

Bc 5: Bt ca s tn hiu Signals vo View/Signals

Ca s sau xut hin

Trong ca s Signals v Add/Wave hin th cc tn hiu trong thit k ln ca s chy dng sng Wave

Bc 6: Chy dng sng Ca s Wave

Bm nt RUN (khoang trn mu vng) chy dng sng. Mt ln bm dng sng s chy 1 khong thi gian bng khong thi gian chng ta thit lp

Bc 7: Xem kt qu Ta thy kt qu m phng ng thit k :silly: :silly: :silly: Chc mt ngy p


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Wed, 02/03/2011 - 14:41

#2

kathykg

Offline Last seen: 52 weeks 8 hours ago Joined: 02/03/2011

V: Re:ModelSim - Cn bn v ngon - Mi cc bc cng xi

Bc phi_thien_dao i ! Em bt u dung VDHL vit chng trnh m phng mch cng m cha vit v lm nh th no?..Em thy ca Bc hay...Bc hng dn hoc c fike g cho em xin c ko?..Cm n Bc phi_thien_dao. Top


Sun, 06/03/2011 - 06:55

#3
rockuall Offline Last seen: 3 weeks 4 days ago Joined: 11/01/2011

V: Re:ModelSim - Cn bn v ngon - Mi cc bc cng xi VHDL & Verilog v cn bn iu ging nhau as hardware design language. VHDL is older language with strictly rules nn vit s di dng hn nhiu. Bn nn hc v Verilog hn bi v EDA tools such as compiler, logic synthesis, and place and route tools support Verilog nhiu hn. Vi System Verilog which is combined Verilog and borrowed from Verification language such as Specman-E c th c ng dng rng ri hn in the future. Top


Sat, 26/11/2011 - 16:03

#4
langtu Offline Last seen: 21 weeks 2 days ago Joined: 01/12/2009

V: ModelSim - Cn bn v ngon - Mi cc bc cng xi Bac phithiendao chem nghe "a" qua. Rt hu ich cho cac ban mi hoc v ASIC hay FPGA! Mong bac chem nhiu hn anh em thm nh. Top


Sun, 18/03/2012 - 21:30

#5
hbtien (not verified)

V: ModelSim - Cn bn v ngon - Mi cc bc cng xi Cm n bn vit bi ny, n rt hu ch cho mnh v mnh mi tp tnh vo ngh h, mong s nhn c nhiu cao chiu hn ca bn^^

Have funny day!!