Proceedings of the 2010 18th IEEE/IFIP International Conference on

VLSI and System-on-Chip

27 29 September 2010 Computer Science School, Complutense University of Madrid

IEEE Catalog Number: CFP10LSI-DVD ISBN: 978-1-4244-6470-8

2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Welcome Message
Welcome to the IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC) 2010 held in Madrid, Spain. VLSI-SoC 2010 is the 18th in a series of international conferences sponsored by IFIP TC 10 Working Group 10.5, IEEE CEDA and CASS that explores the state-of-the-art and the new developments in the field of Very Large Scale Integration (VLSI), System-on-Chip (SoC) and their designs. Previous conferences have taken place in Edinburgh, Trondheim, Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier, Darmstadt, Perth, Nice, Atlanta, Rhodes and Florianopolis. The purpose of VLSI-SoC is to provide a forum to exchange ideas, and show industrial and research results in the fields of VLSI/ULSI Systems, SoC design, VLSI CAD and Microelectronic Design and Test. This edition special emphasis is given to the research area of Energy efficiency of computing and Green computing. As for the technical meeting, VLSI-SoC2010 was a resounding success: 199 papers were submitted, of which 60 papers were accepted for oral presentation at the symposium (a 30% acceptance rate). With poster papers, a total of 82 papers will be presented at the symposium and published in the proceedings. The final technical program consists of 41 full presentations and 19 short presentation in 16 oral sessions and 22 posters in 2 poster sessions, as well as 1 PhD Forum session. The technical program of GLSVLSI2010 has two parallel sessions to allow longer presentations and discussions; a total of 12 normal sessions covering topics such as VLSI circuits, testing CAD, low power and emerging technologies/post-CMOS have been included. VLSI-SoC 2010 starts off Monday, September 27th, in the morning and concludes on Wednesday, September 29th, in the evening. It includes an exciting set of four invited speakers on a broad range of issues related to VLSI and SoC design evolution, as well as emerging nano-electronics and bio-inspired technologies. On Monday, our two keynote speakers are Prof. Subhasish Mitra (Stanford University) and Dr. Sani Nassif (IBM), who will be presenting the latest trends on VLSI design-for-testability and future technology roadmap prospective for IC design. Then, on Tuesday, Prof. Giovanni De Micheli (EPFL) will present the different components of forthcoming nanosystems, which include re-thinking the underlying devices, circuits, architectures and applications. Finally, on Wednesday, Prof. Nikil Dutt (U.C. Irvine) will present novel abstractions for neural circuits and frameworks for modeling, simulating and analyzing spiking neural networks. In addition, the technical program includes two invited special session on Green Computing and on Manycore Architectures to deepen on the technical aspects of the special topic emphasis of this years edition, as well as a PhD/GOLD special luncheon session on Tuesday were renown scientists will present to PhD students and young faculty members their views and good practices to have a successful career in academia and industry. We would like to thank all the Track Chairs, the members of the Technical Program Committee and the additional reviewers, who have made possible the high technical quality of the VLSI-SoC program Moreover, the other members of the Organizing Committee should be thanked for providing excellent service with respect to publication, registration and publicity of the event. Overall, we trust that VLSI-SoC 2010 will meet your highest expectation of quality and technical advancement as reflected in these Proceedings and presentations, and we hope to see you all in Madrid. David Atienza General Chair Jos L. Ayala, Andrea Acquaviva and Rajesh Gupta Program Chairs II

Organization Committee
General Chair David Atienza, EPFL, Switzerland Program Chairs Jos L. Ayala, Complutense University of Madrid, Spain Andrea Acquaviva, Politecnico di Torino, Italy Rajesh Gupta, UCSD, USA Special Sessions Chairs Ayse K. Coskun, Boston University, USA Luca Benini, University of Bologna, Italy Local Arrangements Chair Katzalin Olcoz, Complutense University of Madrid, Spain Publication Chairs Jos I. Hidalgo, Complutense Universtity of Madrid, Spain Ricardo Reis, UFRGS, Brazil Finance Chair Fernando Rincn, Univ. of Castilla La-Mancha, Spain Publicity Chair Praveen Raghavan, IMEC, Belgium PhD Forum Chairs Matthew Guthaus, UCSC, USA Andreas Burg, ETHZ, Switzerland Steering Committee Manfred Glesner, TU Darmstadt, Germany Salvador Mir, TIMA, France Ricardo Reis, UFRGS, Brazil Michel Robert, Univ. Montpellier, France Luis M. Silveira, INESC ID, Portugal Event Management Grupo Pacfico

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Program Committee
Low-Power and ThermalAware Design Track Chairs: Low-Power and ThermalAware Design Track Members: Chi-Ying Tsui, Hong Kong Univ. of Science and Tech., Hong Kong Alberto Macii, Politecnico di Torino, Italy Naehyuck Chang , Seoul National University, Korea Pai Chou, University of California Irvine, USA Yung-Hsiang Lu, Purdue University, USA Volkan Kursun , HKUST, Hong Kong Subreviewers Hailong Jiao, HKUST, Hong Kong Hong Zhu, Oxford Brookes University, UK Yanan Sun, The University of Maryland, USA Subhasish Mitra, Stanford University, USA Matteo Sonza Reorda, Politecnico di Torino, Italy Gabriel Caffarena, CEU, Spain Joan Figueras, UPC, Spain Sachin Sapatnekar, University of Minnesota, USA Biplab Sikdar, Bengal Engineering and Science University, India Nicola Nicolici, McMaster University, Canada Gizopoulos Dimitrios, University of Piraeus, Greece

CAD and Tools, Testability and Design for Test Track Chairs: CAD and Tools, Testability and Design for Test Track Members:

Subreviewers Abhik Mukherjee, Bengal Engineering and Science University, India Ignacio Herrera-Alzu, Politecnica University of Madrid Pablo Ituero, Politecnica University of Madrid Debasis Mitra, Florida Institute of Technology, USA Digital Signal Processing and Mario Vigliar, DPControl, Italy Image Processing IC Design Christos Bouganis, Imperial College London, United Kingdom Track Chairs: Digital Signal Processing and Ilker Hamzaoglu, Sabanci University, Turkey Image Processing IC Design Giancarlo Raiconi, Universit degli Studi di Salerno, Italy Ioannis Sourdis, TU Delft, Netherlands Track Members: Todor Plamenov Stefanov, LIACS, Netherlands Athanassios Skodras, EAP, Greece John McAllister, Queens University Belfast, UK Taeweon Suh, Korea University, Korea Changjian Gao

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Deep Submicron Design and Modeling Issues Track Chairs: Deep Submicron Design and Modeling Issues Track Members:

Subreviewers Shih-Lien Lu, Intel, USA Dimitris Bakalis, University of Patras, Greece Haridimos Vergos, University of Patras, Greece Abdulkadir Akin, EPFL, Switzerland Onur Ulusel, Sabanci University, Turkey Arnaldo Azevedo, TU Delft, Netherlands Haykel Ben Jamaa, CEALETI, France Milos Stanisavljevic, EPFL, Switzerland Sorin Cotofana, TU Delft, Netherlands Vasilis Pavlidis, EPFL, Switzerland Nishant Patil, Stanford University, USA Minas Nikolaos, IMEC, Belgium Frank K. Gurkaynak, ETH, Switzerland Alexandre Schmid, EPFL, Switzerland Kirsten Moselund, IBM, Switzerland Subreviewers Jaemin Kim, IMEC, Belgium Nor Zaidi Haron, TU Delft, Netherlands Yao Wang, TU Delft, Netherlands Pavel Poliakov, IMEC, Belgium Seyab Khan, TU Delft, Netherlands Salvador Mir, TIMA Laboratory, France George-Jie Yuan, Hong Kong Univ. of Science and Tech., Hong Kong Jiun-Lang Huang, National Taiwan University, Taiwan Manh Anh Do, Nanyang Technological University, Singapore Mohamad Sawan, cole Polytechnique de Montral, Canada Jerzy Dabrowski, Linkopings University, Sweden Diego Vazquez-Garcia, CSIC, Spain Jose Silva-Martinez, Texas A&M University, USA Subreviewers Soon-Jyh Chang, National Cheng-Kung University, Taiwan Ali Naderi, cole Polytechnique de Montral, Canada Ching Chuen Jong, Nanyang Tech. University, Singapore Hao-Chiao Hong, National Tsing Hua University, Taiwan Gabriel Rincon-Mora, Georgia Tech., USA Mona Safi-Harb, cole Polytechnique de Montral, Canada Robert Chebli, University of Glasgow, UK Tien Bui, Concordia University, Canada
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Analog and Mixed-Signal IC Design Track Chairs: Analog and Mixed-Signal IC Design Track Members:

New Applications Track Chairs: New Applications Track Members:

Vamshi Krishna Manthena, Nanyang Technological University, Singapore Onabajo Marvin, Texas A&M University, USA Chirn Chye Boon, Nanyang Technological University, Singapore Manuel J. Barragan, University of Seville, Spain Francisco Moya, University of Castilla-la-Mancha, Spain Wei-Chung Cheng, Food and Drug Administration, USA Cesar Sanchez, IMDEA, Spain Pablo Garcia del Valle, Complutense University of Madrid, Spain Francisco J. Rincon, Complutense University of Madrid, Spain Qinru Qiu, Binghamton University, USA Iva Bogdanova, EPFL, Switzerland Massimo Poncino, Politecnico di Torino, Italy Qing Wu, Binghamton University, USA Subreviewers Javier Vzquez, University of Castilla-la-Mancha, Spain David Villa, University of Castilla-la-Mancha, Spain Flix J. Villanueva, University of Castilla-la-Mancha, Spain Franco Fummi, University of Verona, Italy Jiun-Lang Huang, National Taiwan University, Taiwan Nicola Bombieri, University of Verona, Italy Graziano Pravadelli, University of Verona, Italy Pablo P. Sanchez, University of Cantabria, Spain Valeria Bertacco, University of Michigan, USA Michael Hsiao, Virginia Tech, USA Xiaoqing Wen, Kyushu Institute of Technology, Japan Subreviewers Giuseppe Di Guglielmo, University of Verona, Italy Valerio Guarnieri, University of Verona, Italy Rawan Abdel-Khalek, University of Michigan, USA Sara Vinco, University of Verona, Italy Chia-Lin Yang, National Taiwan University, Taiwan Mirko Loghi, University of Verona, Italy Luigi Di Guglielmo, University of Verona, Italy Francesco Stefanni, University of Verona, Italy Debapriya Chatterjee, University of Michigan, USA Valerio Guarnieri, University of Verona, Italy Andrew DeOrio, University of Michigan, USA

Prototyping, Validation, Verification, Modeling and Simulation Track Chairs: Prototyping, Validation, Verification, Modeling and Simulation Track Members:

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Yuan Xie, Pennstate University, USA Digital systems and architectures Track Chairs: Giuseppe Desoli , STMicroelectronics, USA Dennis Sylvester, University of Michigan Ann Arbor, USA Digital systems and architectures Track Members: Elio Guidetti, STMicroelectronics, Italy Davide Pandini, STMicroelectronics, Italy Helen Li, Polytechnic Institute of New York University, USA Murali Srinivasan, EPFL, Switzerland Tajana Simunic, UC San Diego, USA Subreviewers Shervin Sharifi, UC San Diego, USA Matt Fojtik, University of Michigan Ann Arbor, USA Ciprian Seiculescu, EPFL, Switzerland Gyouho Kim, University of Michigan Ann Arbor, USA Bharan Gridhar, University of Michigan Ann Arbor, USA Mingoo Seok, University of Michigan Ann Arbor, USA Alex Orailoglu , UC San Diego, USA Georgi Gaydadjiev, TU Delft, Netherlands Leonel Sousa, IST/INESC-ID, Portugal Chun Jason Xue, City University of Hong Kong, Hong Kong Cristina Silvano, Politecnico di Milano, Italy Peter Petrov, University of Maryland, USA Dionisios Pnevmatikatos, Technical University of Crete, Greece Luigi Carro, UFRGS, Brazil

New Architectures and Compilers, Reconfigurable Systems Track Chairs: New Architectures and Compilers, Reconfigurable Systems Track Members:

Subreviewers Dimitris Theodoropoulos, TU Delft, Netherlands Samuel Anto, IST/INESC-ID, Portugal Gianluca Palermo, STMicrolectronics, Italy Giovanni Mariani, Swiss University, Switzerland Carlo Brandolese, Politecnico di Milano, Italy Catalin Ciobanu, TU Delft, Netherlands Leandro Fiorin, University of Lugano, Switzerland System-on-Chip Design Track Samar Abdi, Concordia University, Canada Fadi Kurdahi, UC Irvine, USA Chairs: System-on-Chip Design Track Martino Ruggiero, EPFL, Switzerland Mladen Berekovic, TU Braunschweig, Germany Members: Gabriela Nicolescu, Ecole Polytechnique de Montreal, Canada Chen Liu, Florida International University, USA Zebo Peng, Linkping University, Sweden Jose Luis Risco, Complutense University of Madrid, Spain
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3-D Integration and Physical Design Track Chairs: 3-D Integration and Physical Design Track Members

Subreviewers Tim Kranich, TU Braunschweig, Denmark Jelena Trajkovic, UC Irvine, USA Zhaozhou Meng, Florida International University, USA Muhammad S. Khairy, Cairo University, Egypt Kiarash Amiri, University of California, USA Syed Abbas Ali Shah, TU Braunschweig, Denmark Avesta Sasan, UC Irvine, USA Pollawat Thanarungroj, Florida International University, USA Yusuf Leblebici, EPFL, Switzerland Fabien Clermidy, CEA Leti Minatec, France Maud Vinet, IBM, USA Alexandre Valentian, CEA, France Igor Loi, University of Bologna, Italy Pratibha Singh, Sematech, USA Thomas Brunschwiler, IBM, Switzerland Frank K. Gurkaynak, ETH, Switzerland

Subreviewers Mohammad Reza Kakoee, University of Bologna, Italy Preeti Panda, Indian Institute of Technology Delhi, India Logic and High-Level Srinivas Katkoori, University of South Florida, USA Synthesis Track Chairs: Saraju Mohanty, University of North Texas, USA Logic and High-Level Madhu Mutyam, Indian Institute of Technology Madras, India Synthesis Track Members: Prabhat Mishra, University of Florida, USA Luciano Lavagno, Politecnico Di Torino, Italy Nirav Dave, MIT CSAIL, USA Olivier Coudert Francisco J Cazorla, BSC, Spain Embedded Systems Design and Real-Time Systems Track Roberto Gioiosa, BSC, Spain Chairs: Ryo Sugihara, University of California San Diego, USA Embedded Systems Design and Real-Time Systems Track Eduardo Quiones, BSC, Spain Jose M. Moya, Politecnica University of Madrid, Spain Members: Mohammad Abdullah Al Faruque, University of Karlsruhe, Germany Davide Quaglia, University of Verona, Italy Bodhi Priyantha, Microsoft, USA Alex Veidenbaum, University of California Irvine, USA Special Session Track Chairs: Ayse K. Coskun, Boston University, USA Luca Benini, University of Bologna, Italy

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Keynote Talks
Keynote Talk 1 Date/Time Location Speaker Robust System Design for Scaled CMOS and Beyond Monday, 27 September 2010 / 09:00 10:00 Auditorium Prof. Subhasish Mitra, Stanford University

Summary

Complex electronic systems are an indispensable part of all our lives. The impacts of malfunctions in these systems continue to increase as systems become more complex, interconnected, and pervasive. Robust system design is required to ensure that future systems perform correctly despite rising levels of complexity and increasing disturbances. Hardware failures are especially a growing concern because:

Existing validation and test methods barely cope with todays complexity. For coming generations of silicon ICs, several failure mechanisms, largely benign in the past, are becoming visible at the system-level. Emerging nanotechnologies are inherently prone to high rates of imperfections. Nevertheless such technologies are being seriously explored to build highly energy-efficient systems of the future. This talk will address these outstanding challenges, ranging from immediate concerns blocking progress today to major obstacles in exploratory nanotechnologies, as described below: Thorough validation and test despite enormous complexity. Tolerance and prediction of hardware failures. Correct circuit operation in emerging nanotechnologies prone to imperfections.

Biography

Prof. Subhasish Mitra leads the Robust Systems Group in the Departments of Electrical Engineering and Computer Science of Stanford University. Before joining Stanford, he was a Principal Engineer at Intel Corporation. Prof. Mitras research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His X-Compact technique for test compression is used by more than 50 Intel products, and has influenced major CAD tools. The IFRA technology for post-silicon validation, created jointly with his student, was characterized as a breakthrough in the Communications of the ACM. His work on the first demonstration of imperfection-immune carbon nanotube VLSI circuits, jointly with his students and collaborators, was selected by NSF as a Research Highlight to the US Congress, and was highlighted as a significant breakthrough by the Semiconductor Research Corporation and the MIT Technology Review. Prof. Mitras major honors include the Presidential Early Career
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Award for Scientists and Engineers, the highest U.S. honor bestowed on early-career outstanding scientists and engineers, ACM SIGDA Outstanding New Faculty Award, Terman Fellowship, IEEE CAS/CEDA Pederson Award for the IEEE Trans. CAD Best Paper, IEEE/ACM Design Automation Conf. Best Paper, and the Intel Achievement Award, Intels highest corporate honor. Prof. Mitra also serves on DARPAs Information Science and Technology Board as invited member.

Keynote Talk 2 Date/Time Location Speaker

Resilience: The Looming Technology Hurdle Monday, 27 September 2010 / 13:30 14:30 Auditorium Dr. Sani Nassif, IBM

Summary

CMOS technology has faced and overcome many hurdles to achieve the amazing products that we see all around us today, from cell phones to smart cars and medical devices to incredibly fast supercomputers. These continuing innovations in technology, devices, circuits, systems, and design tools have enabled a rate of improvement that is unprecedented. Early on, there was much talk about sub-micron transistors and how scaling will stop at 1.25micron, then we had a giant crisis about wire delay, and most recently another one with leakage power. Sub-wavelength lithography is one of the current hurdles, but it appears that the industry sees a clear way through this crisis as well. As we scale further, however, a new challenge looms: Resilience. Resilience is the ability of circuits to operate in spite of challenges like noise, difficult environmental conditions, aging and manufacturing imperfections. These factors conspire to cause transient or permanent errors that are indistinguishable from traditional hard faults typically caused by defects during fabrication. In the area of SRAM, such phenomena have existed for the last three or four technology nodes, but significant investments in this area have indeed allowed continued system level scaling with ever larger on-chip memories. Given that no new technology is ready to take over the role that Silicon has provided for so long, it is likely that we will continue to live with and scale Silicon technology for at least the coming ten to fifteen years. This means that there is an urgent need for research and development in this resilience area to avert the problems certain to arise with increased defect rates. This keynote will outline this problem, show a roadmap that can help motivate and quantify work, and suggest some ideas for possible solutions.

Biography

Sani Nassif received his Bachelors degree with Honors from the American University of Beirut in 1980, and his Masters and PhD degrees from Carnegie-Mellon University in 1981 and 1985 respectively. He worked for ten years at Bell Laboratories on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. He joined the IBM Austin Research Laboratory in January 1996 where he is presently managing the tools and technology department, which is focused on design/technology coupling and includes activities in: model to hardware matching, simulation and modeling, physical design, statistical modeling, statistical technology characterization and similar areas. Sani has authored numerous conference and journal publications, and delivered many tutorials at top conferences. He has received four Best Paper awards, and authored invited papers to ISSCC, IEDM, ISLPED, HOTCHIPS, and CICC. He is an IEEE Fellow, a member of the ACM and AAAS, and has a total of 44 patents. Sani is a member of the IBM Academy of Technology, and has received the Penrose award (given to one outstanding graduate from the American University of Beirut), the Distinguished Member of Technical Staff award from Bell Labs, two Research Accomplishment Awards from IBM, and the SRC Mahboob-Khan Outstanding Mentor awards from the SRC.
Keynote Talk 3 Date/Time Location Speaker Nanosystems: Devices, Circuits, Architectures and Applications Tuesday, 28 September 2010 / 09:30 10:30 Auditorium Prof. Giovanni De Micheli, EPFL

Summary

Much of our economy and way of living will be affected by nanotechnologies in the decade to come and beyond. Mastering materials at the molecular level and their interaction with living matter opens up unforeseeable horizons. This talk deals with how we will conceive, design and use nanosystems, i.e., integrated systems exploiting nanodevices. Whereas switching circuits and microelectronics have been the enablers of computer and communication systems, nanosystems have the potentials to realize innovative computational fabrics whose applications require broader hardware abstractions, extended software layers and with a much higher complexity level overall. The abstraction of computation, the nanosystem architecture, the technological feasibility envelope and the multivariate design optimization problems pose challenging and disruptive research questions that this talk will address.

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Biography

Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He also chairs the Scientific Committee of CSEM, Neuchatel, Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983). His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis, hw/sw codesign and lowpower design, as well as systems on heterogeneous platforms including electrical, micromechanical and biological components. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 400 technical articles . He is, or has been, member of the technical advisory board of several companies, including Magma Design Automation, Certess, Coware and STMicroelectronics. Prof. De Micheli is the recipient of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He is a Fellow of ACM and IEEE. He received the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000. He received the 1987 D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS, two Best Paper Awards at the Design Automation Conference, in 1983 and in 1993, and a Best Paper Award at the DATE Conference in 2005. He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1987-2001). He is and has been Chair of several conferences, including DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989). He is a founding member of the ALaRI institute at Universita della Svizzera Italiana (USI), in Lugano, Switzerland, where he is currently scientific counselor.
Keynote Talk 4 Towards Reverse Engineering The Brain: Modeling Abstractions and Simulation Frameworks Wednesday, 29 September 2010 / 10:00 11:00 Auditorium Prof. Nikil Dutt, U.C. Irvine

Date/Time Location Speaker

Summary

Biological neural systems are well known for their robust and power-efficient operation in highly noisy environments. Biological circuits are made up of low-precision, unreliable and massively parallel neural elements with highly reconfigurable and plastic connections. Two of the most interesting properties of the neural systems are its self-organizing capabilities and its template architecture. Recent research in spiking neural networks has demonstrated interesting principles about learning and neural computation. Understanding and applying these principles to
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practical problems is only possible if large-scale spiking neural simulators can be constructed. Recent advances in low-cost multiprocessor architectures make it possible to build large-scale spiking network simulators. In this paper we review modeling abstractions for neural circuits and frameworks for modeling, simulating and analyzing spiking neural networks.
Biography

Nikil D. Dutt is a Chancellors Professor at the University of California, Irvine, with academic appointments in the CS and EECS departments. He received a B.E.(Hons) in Mechanical Engineering from the Birla Institute of Technology and Science, Pilani, India in 1980, an M.S. in Computer Science from the Pennsylvania State University in 1983, and a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign in 1989. He is affiliated with the following Centers at UCI: Center for Embedded Computer Systems (CECS), California Institute for Telecommunications and Information Technology (Calit2), the Center for Pervasive Communications and Computing (CPCC), and the Laboratory for Ubiquitous Computing and Interaction (LUCI). Professor Dutts research interests are in embedded systems, electronic design automation, computer architecture, optimizing compilers, system specification techniques, distributed systems, formal methods, and brain-inspired architectures and computing. He is a coauthor of seven books: High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992, Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration, Kluwer Academic Publishers, 1999, Memory Architecture Exploration for Programmable Embedded Systems, Kluwer Academic Publishers, 2003, SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits, Kluwer Academic Publishers, 2004, Functional Validation of Programmable Embedded Architectures: A Top-Down Approach, Springer-Verlag, 2005, On-chip Communication Architectures: Current Practice, Research and Future Trends, Morgan Kaufman/Elsevier Systems-on-Silicon Series, 2008, and Processor Description Languages: Applications and Methodologies, Morgan Kaufman/Elsevier Systems-on-Silicon Series, 2008. Professor Dutts research has been recognized by Best Paper Awards at the following conferences: CHDL89, CHDL91, VLSI Design 2003, CODES+ISSS 2003, CNCC 2006, ASPDAC 2006, and IJCNN 2009; and Best Paper Award Nominations at: WASP 2004, DAC 2005, and VLSI Design 2006. He has also received a number of departmental and campus awards for excellence in teaching at UC Irvine.

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Special Sessions
Special Session 1 Date/Time Location Green Computing Tuesday, 28 September 2010 / 14:00 16:00 Aula 7 (1st floor)

Session Summary

Green computing research is gaining more attention every year due to the substantial increase in the energy costs of computing and the resulting environmental effects. This session offers a comprehensive discussion on key research problems in green computing and provides a rich portfolio of recent high-impact solutions proposed by industry and academia. The first talk by T. Chilimbi (Microsoft Research) discusses opportunities for lowering the computing cost by improving the energy efficiency of data center software and hardware running an industrystrength web search engine. R. Gioiosa (Barcelona Supercomputing Center) demonstrates the evolution of power consumption in supercomputing in his talk, and provides on hardwaresoftware co-design solutions for exascale computing era. In the third talk, E. Kursun (IBM TJ Watson Research Center) gives an overview of the recent power and thermal trends in multicore systems, and points out novel directions for power management and scheduling to improve energy efficiency. In the final talk of the session, D. Brunelli (University of Trento) focuses on sensing and monitoring techniques for greening buildings, and presents case studies of green computing architectures leveraging connected sensing systems and networks.

Session Program

(1) Greening Web Search using Energy-Efficient Software and Hardware Trishul Chilimbi, Microsoft Research, USA Trishul Chilimbi is a senior researcher at Microsoft Research leading the Runtime Analysis & Design (RAD) research group, which is part of Microsofts Research in Software Engineering (RiSE) organization. He joined Microsoft Research after receiving his Ph.D from the University of Wisconsin at Madison in 1999. His areas of interest include programming languages, compilers, runtime systems, computer architecture, and parallel and distributed systems. He is currently focused on improving the performance and energy-efficiency of web services both from a client and data center perspective.

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(2) Towards Sustainable Exascale Computing Roberto Gioiosa, Barcelona Supercomputing Center, Spain Roberto Gioiosa is a research scientist at Barcelona Supercomputing Center (BSC). Roberto received his PhD on High performance computing clusters from the University of Rome Tor Vergata in 2002. Prior to coming to BSC, he was graduate student at Los Alamos National Laboratory (LANL) from 2004 to 2005, working on High Performance Computing (fault tolerance and performance analysis) in the PERCS project. Roberto started at BSC as Postdoc in 2006; at BSC he worked on Operating Systems for High Performance Computing Clusters and optimization for future processor architectures. From 2008 to 2009 he was a post-doc at IBM TJ Watson Research center, in the BlueGene group. He went to BSC in September 2009. Since 2006 Roberto has also been an external collaborator of the System Programming Research Group at the University of Rome Tor Vergata.

(3) Trends and Techniques for Energy Efficient Architectures Eren Kursun, IBM T. J. Watson Research Center, Yorktown Heights, USA Eren Kursun is a Research Staff Member at IBM Research T.J. Watson Center, where she has been involved in research projects and test-sites focusing on power/temperature management and technology-aware design for microprocessor architectures. Dr. Kursun has published on energy-efficient and technology-aware microprocessor design; she received the best paper award in IEEE International Conference on Computer Design and IEEE Micro Top Picks. Dr. Kursun received her B.Sc. degree in Electrical and Electronics Engineering from Bogazici University; M.Sc. and Ph.D. degrees in Computer Science from the University of California, Los Angeles.

(4) Smart Distributed Sensors for Adaptive Green Services Davide Brunelli, University of Trento, Italy Davide Brunelli is Assistant Professor at University of Trento. He received his PhD degree in Electrical Engineering from the University of Bologna in 2007. He collaborated with ETH, the Swiss Federal Institute of Technology in Zurich in a joint research project on scavenger design for WSN, focused on maximum power transferring from solar cell. Davide has been a scientific consultant for TELECOM ITALIA LAB for developing Wireless Sensor Networks (WSN) for Smart Home Environments in 2006 and on Electronic systems for Ambient Intelligence in 2008. His research interests are energy scavenging for wireless sensor networks, the development and optimization of low-power and low-cost WSN, optimizations of algorithms for WSN communication, and new standards exploration (IEEE802.15.4, Zigbee, ULP Bluetooth) with particular emphasis on energy efficiency, management on buildings, and green computing.

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Special Session 2 Date/Time Location

Manycore Architectures Wednesday, 29 September 2010 / 14:00 15:30 Aula 7 (1st floor)

Session Summary

Multicore computing is rapidly becoming manycore computing as the number of cores on a chip is increasing at exponential pace dictated by Moore's law. This special section focuses on two key issues in manycore design and management, namely interconnect design and workload allocation. The first talk by A. Joshi (Boston University) presents a vertically integrated approach for designing energy-efficient on-chip and off-chip communication networks. The second talk, by R. David (CEA LIST) discusses workload allocation of complex applications in manycore systems, and presents a framework for load balancing and task allocation supporting various execution models. Finally, in the third talk, F. Angiolini (INoCs) focuses on novel design automation technologies for synthesizing network-on-chips with performance and power constraints.
Session Program

(1) Designing Energy-Efficient Communication Networks for Manycore Systems Ajay Joshi, Boston University, USA Ajay Joshi is an Assistant Professor in the ECE department at Boston University. Prior to joining Boston University, he received his PhD from Georgia Institute of Technology and then worked as postdoctoral researcher at Massachusetts Institute of Technology. His research interests include on-chip/off-chip communication, low-power high-speed digital design and error-correcting codes. (2) SESAM Extension For Fast MPSoC Architectural Exploration And Dynamic Streaming Applications Raphal David, CEA LIST, France Raphal David is in charge of Embedded Computing Laboratory at the CEA LIST. He received his Ph.D. degree in computer engineering after designing the DART reconfigurable processor, from the University of Rennes I, France, in 2003. He has joined the CEA LIST in a post-doctoral position to study reconfigurable architectures benefits to reduce power consumption of embedded systems. Since 2004 he has proposed dynamic execution models for programmable and reconfigurable multi- and many-core systems to support variable execution conditions resulting from technology or data-dependent applications. He is now in charge of the MPSOC design team in CEA LIST and explores the architectures design space to support such advanced execution models. He is also involved in the implementation of dynamically reconfigurable processors for image processing and low power design.
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(3) Synthesizing On-Chip Interconnects Federico Angiolini, iNoCs, Switzerland Federico Angiolini received the M.S. degree (summa cum laude) in electrical engineering from the University of Bologna, Bologna, Italy, in 2003, and Ph.D. in the Department of Electronics and Computer Science, University of Bologna, in 2008. He is currently holding the position of VP of Engineering at iNoCs. He is focusing his research on memory hierarchies, multiprocessor embedded systems and Networks-on-Chip.

Technical Papers
Monday, 27 September 2010

Session 1: Systems-On-Chip and Networks-on-Chip Design Session 2: Prototyping, Verification and Modeling Poster Session 1 Session 3: Analog and Mixed Signal IC Design Session 4: Digital Signal Processing and Image Processing IC Design

Tuesday, 28 September 2010

Session 5: Digital System Design and Architectures Session 6: Circuits and Systems for New Applications Session 7: Special Session 1 Green Computing Session 8: Logic Synthesis, Testability and Design for Test

Wednesday, 29 September 2010

Session 9: Architectures for DSP and Video Processing Applications Session 10: Deep Submicron Design Session 11: Special Session 2 Manycore Architectures Session 12: Low Power Circuit Design Session 13: Physical Design for 3D Integration and Communication Systems Session 14: New Architectures for Reconfigurable Systems-on-Chip and Multiprocessor Systems-on-Chip

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