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II
Abstract
Using Au-Si wafer bonding and LLO (Laser Lift-Off) techniques, an
LED (Light Emitting Diode) GaN epi-layer was successfully transferred
onto a Si substrate. After the wafer bonding, a KrF excimer laser was
used to separate the GaN layer from the grown sapphire substrate. The
Raman spectra results show that the initial compressive stress level of the
GaN epi-layer was relieved after transferring. According to Kozawas
relation, we got the relationship between the biaxial stress and various Au
bonding layer thickness ranging from 7 m to 40 m. The maximum
compressive stress relief, 290 MPa, in the transferred GaN thin film
occurred at the largest Raman peak position shift of 10 m Au layer (red
shift, 1.79 cm
-1
). The transferred GaN epi-layer was further processed
for use in a thin-GaN LED device. The L-I-V curve results indicate a
forward voltage of 3.4 Volts, and a luminance intensity of 204 mcd at 20
mA.
A detail stress evolution during thin-GaN LED fabrication was
studied, and then the lighting intensity with different biaxial in-plane
stress was also measured. We proved that we can avoid QCSE
(Quantum Confined Stark Effect) efficiently by relieving the compressive
stress. And the order of compressive stress relief can be controlled by
changing the process parameters. The non-linear parabolic relation of
the QW (Quantum Well) band gap with the stress level was also
mentioned by .


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III
Table of Contents

Chinese Abstract I
English Abstract II
Table of Contents
List of Figures
List of Abbreviations

Chapter 1 Introduction 1
1-1 Historical review of Nitrides compound 2
1-2 Substrate substitution technology 3
1-3 Piezoelectric and spontaneous polarization field in GaN thin film 6
1-4 Raman scattering examination for thin film stress 10
1-5 Outline of this dissertation 11

Chapter 2 Experimental Technique 12

Chapter 3 Results and Discussions 19
3-1 Thin-GaN LED fabrication by Au-Si wafer bonding 20
3-2 Stress evolution of GaN epi-layer 23
3-3 Raman measurements for transferred GaN thin film 27
IV
3-4 Stress change by different bonding temperature 32
3-5 Stress effect on optical properties of GaN epi-layer and
lighting performance 33

Chapter 4 Summaries 51

Appendixes 54
Appendix A. Effect of Cu Content on Interfacial Reactions between
Sn(Cu) Alloys and Ni/Ti Thin Film Metallization 54

Appendix B. Fabrication Low-loss Hollow Optical Waveguides via
Amorphous Silicon Bonding Using Dilute KOH Solvent 75

Appendix C. The Novel Asymmetric UBM Structure Applying to
Micro-level Alignment Accuracy 83


References 94

Vita 99


V
List of Figures

Fig. 2-1 The entire metal configuration 16

Fig. 2-2 The process flowchart of thin-GaN LED devices
fabrication

17

Fig. 2-3 The final LED chip device 18

Fig. 2-4 Raman spectrum of GaN on sapphire 18

Fig. 3-1 Transferred GaN thin film on the Si substrate by In-In
bonding

37

Fig. 3-2 Binary phase diagram of Au-Si 38

Fig. 3-3 The flowchart of Au-Si reaction during bonding
process

39

Fig. 3-4 SEM cross-sectional image of continuously uniform
Au-Si bonding layer

40

Fig. 3-5 Lighting image of transferred thin-GaN LED chip 41

Fig. 3-6 L-I-V characteristics for the thin-GaN LED 42

Fig. 3-7 SEM image of n-side GaN surface after LLO 43

Fig. 3-8 Stress evolution of the GaN epi-layer during the
substrate transferring

44

Fig. 3-9 The (a) Raman peak position and (b) biaxial in-plane
stress vs. Au bonding layer thickness while bonding
temperature is 420 J


45

Fig. 3-10 The illustration of bending transferred GaN thin film
on Si

46
VI

Fig. 3-11 Raman mapping results corresponding with the (a)
smooth GaN surface and (b) GaN surface with cracks

47

Fig. 3-12 The (a) Raman peak position and (b) biaxial in-plane
stress vs. Au bonding layer thickness while bonding
temperature is 380 J


48

Fig. 3-13 (a) PL spectrum with various stress state in GaN thin
film F(b) the relation between Energy band gap and
in-plane stress level of the transferred GaN epi-layer


49

Fig. 3-14 (a) Luminous intensity vs. biaxial in-plane stress and
its relation F (b) the illustration of band structure
deformation induced by stress change


50





















VII
List of Abbreviations

EDX Energy-dispersive x-ray spectroscopy

EL Electroluminescence

EQE External quantum efficiency

IQE Internal quantum efficiency

LED Light emitting diode

L-I-V
Light intensity current voltage


LLO Laser lift off

MOCVD Metal-organic chemical vapor deposition

MQW Multiple quantum well

PL Photoluminescence

QCSE Quantum confined stark effect

SEM Scanning electron microscope

SQW Single quantum well






1
Chapter 1 GIntroduction
Energy production and consumption is one of the most serious
challenges confronting human at the beginning of the 21
st
century. The
environment, political, and economic consequences of energy use are
obviously in the consumers pay for utilities. The world in particular
faces enormous challenges, as growth in energy demand is expected to
outstrip domestic production well in the future. [1]
General lighting is estimated to consume approximately 20% of
electricity. So, how to substantially increase the efficiency of lighting is
very important on the issue of energy consumption. Light emitting
diodes (LEDs) of solid state lighting has attracted serious attention, since
it could potentially provide much higher lighting efficiency than the
current lighting sources, such as, tungsten incandescent and fluorescent
lamp. The first advantage of LED is its efficiency. In theory,
semiconductors-based LEDs can have 100 % efficiency conversion from
the electrical energy to optical energy. [2] Unlike other lighting
technologies (e.g. incandescent and fluorescent), it has fundamental
limitations to the efficiency. The second major advantage is that LED
technology has much longer life time. By experiments, the operating
lifetimes of LEDs are over 100,000 hours. This is vastly longer than
other man-made light sources and this can reduce the total cost of the
light source in the world.
Yet, the current state-of-the-art LED technology is far from wild
general lighting use. Many challenges remain to be solved before LEDs
2
attain significant lighting market occupancy. Improving the
performance of LEDs is the main subject of this work. This chapter will
provide an introduction to LED technology, thin-GaN LEDs fabrication,
stress effect and piezoelectric field in LED devices.

1-1 Historical review of Nitrides compound
At early 1960s, there is a flurry of interest in visible light-emitting
semiconductor devices. The debut report of the practical LED was
published by N. Holonyak et al. [3] The very first production of LEDs
were based on GaAsP and GaP semiconductors, whose efficiency was
less than 1 %. However, from this promising start, LED development
has become a steady progression of new innovations. LEDs are formed
from compound semiconductor materials. The simplest structure of
LED epi-layers contains one electron-rich layer, one hole-rich layer and
one active layer. The electrons and holes make a recombination in the
active layer and radiating the photons.
Recently, this kind of solid-state lighting has attracted serious
attention, since it could potentially provide much higher lighting
efficiency than the current lighting sources, such as tungsten incandescent
and fluorescent lamp. The current approach of developing solid-state
lighting source is using GaN-based LED to pump the suitable phosphors
and emitting white light. [4,5] GaN and its alloy compounds with AlN
and InN form a direct wide band gap semiconductor of great promise for
optoelectronic and high power application. The band gaps of
3
nitrides are from visible to ultraviolet spectra. As we know, there
are 1.9 eV, 3.4 eV and 6.2 eV for InN, GaN and AlN, respectively. [6]
Because of these wide band gap and strong band strength, nitrides are
suitable for blue or green light emission devices. They also can stand
the higher temperature and hostile environment for future electronic
devices.

1-2 Substrate substitution technology
Generally, the GaN films are widely grown on sapphire (Al
2
O
3
)
substrates because of its low cost and transparency. However, due to the
large lattice mismatch (13 %) in comparison between GaN epi-layer and
sapphire substrate, it will result in poor crystal quality and severe
cracking on epilayers. Also, the relatively poor thermal conductivity of
sapphire substrate has been recognized to be the main limitation for the
application of high-brightness LED. Many researchers had tried to look
for a suitable substrate or improve growth processes for solving the above
problems. A function on growing GaN on Si substrate was reported. It
provides better thermal dissipation and versatile electrical supports for
LED devices. [7,8] Besides, we also can easily integrate high-quality
optoelectronic devices with Si integrated-circuit devices, like ESD
(electrostatic discharge) by fully-developed semiconductor technology.
Yet, there is very large lattice constant mismatch between GaN and Si
substrate and it will lead to the limitation for lighting due to serious
dislocations formation. Another alternative approach to transfer GaN
4
epi-layer onto a thermal conductive substrate is using the wafer bonding
technique and LLO (Laser lift-off). [9-11] Many researchers had shown
that replacing the sapphire substrate with higher thermal conduction
substrate, LED devices can sustain higher input power. If electrically
conductive materials were chosen for the new substrates, such as, metal
[10] or heavy-doped Si [9,11], we can fabricate the vertical structure LED
devices. The vertical type LED is more attractive then the common
planar one because of better efficient epi-layer area utilized and the better
current spreading. So, comparing to the conventional wire-bonding
LED, this substrate substitution technology, which is called thin-GaN
device, has been proven that it can promote the better electrical and
optical properties. The major advantages of thin-GaN LED are better
current spreading and thermal dissipation. And we can also make the
downward light be reflected by a reflection metal layer.
Wafer bonding technology has been extensively used for
optoelectronic devices, and it is also not a new application. In an early
red GaAs-LED structure, spontaneous emission is assumed isotropic and
approximately half of light goes toward substrate. Those photons can be
easily absorbed, if the substrate has lower bandgap energy than the active
region. In order to achieve high-brightness LEDs, a transparent
substrate (GaP) was directly bonded and then removed the original
substrate to enhance the light extraction. [12] To date, this technique is
also applied for GaN-based LED to fabricate high-brightness LEDs.
After wafer bonding process, a pulsed laser was used to enter
5
through transparent sapphire substrate and thermally separate GaN from
the grown sapphire substrate. The major mechanism of LLO process is
that the GaN/sapphire interface absorbs the laser energy and cause
thermal decomposition of GaN. The decomposition products are Ga
metallic particles and N
2
gas. As we know, the bonding energy for AlN,
GaN and InN are 11.52, 8.92 and 7.72 eV/mol, respectively. They are
relatively high compared to other compounds. [13] These high
bond energies result in the higher melting temperatures and good thermal
stability of the GaN compounds. So in LLO process, we notice that this
decomposition reaction would result a very high temperature at
GaN/sapphire interface. The in-situ interfacial temperature could be as
high as 900 . [ J 14] So, a key for a successful process of substrate
transferring is the wafer bonding. The bonding layer must be strong
enough to sustain high temperature process of LLO. The advantage of
Pd-In bonding system, which is adopted by Wong, is that it can produce a
high temperature bonding under a low temperature process. The
resultant Pd-In intermetallic compound phase has a melting point of 664
. [ J 9] In our experiments, Au-Si binary eutectic bonding system is
chosen for the same reason. And in the first part of this thesis, I will
discuss in depth the mechanism of Au-Si bonding applying for thin-GaN
LEDs.



6
1-3 Piezoelectric and spontaneous polarization field in GaN
thin film
The critical issue of LED entering into the commercial use is its
lighting efficiency. So, besides the novel outer packaging, the intense
works bring forth a relatively good quality of GaN films is also very
important. Further studies can help us to explore the more confusing
and ambiguous physical phenomenon for these Nitrides compounds.
Akimova et al. first found the emission peaks demonstrated an anomalous
blue shift along with increasing temperature by means of
electroluminescence (EL) for an AlGaN/InGaN/GaN SQWs. [15] This
phenomenon is widely reported by many other researchers, and to be
generally called as the s-shaped emission shifts. Eliseev et al. have
induced a band-tail model with a Gaussion-like distribution of the density
of state and described this abnormal behavior, and named it as
temperature-induced blue shift. [16] Another interesting phenomenon
which is energy difference between the emission line and the absorption
edge, referred to as the Stokes shift. Chichibu et al. have reported the
emission mechanism of InGaN/GaN SQW and MQW by means of EL
and electroabsorption (EA). [17] The significant energy blue shift
between EL and EA spectra is observed as well as a function of Indium
mole fraction. Their result of the stress in QWs will induce
piezoelectric field about 1.4 MV/cm of In
025
Ga
0.75
N single QW LED.
Martin et al. also have established a clear linear dependence of the
Stoke s on the peak emission energy, and proposed that an existence of
7
highly Indium-rich quanum dot within a phase segregated alloy. [18] A lot
of researchers ascribed this Stoke s shift to the quantum confined stark
effect (QCSE) or band filling of localization states of the excitons. It
has been reported that the localized excitions play an important role for
the light emission mechanism in the InGaN based MQWs or InGaN/GaN
heterostructure devices. [16] As above references mentioned, the internal
field will strongly influence the optical and electrical properties for
-nitrides compound such as QCSE for InGaN/GaN MQWs structure.
The QCSE is ascribed to a strong internal field contained in the
heterostructure which is originated from the piezoelectric polarization and
the spontaneous polarization. The former is due to the lattice mismatch
induced strain for heterostructure and the latter term is ascribed to the
asymmetry wurtzite crystal structure. Bernadini et al. [19] have
reported about the spontaneous polarization, piezoelectric constants and
dynamical charges of III-nitrides material by using the Berry-phase
approach. In the absence of external field, the intrinsic
polarization-induced field is as large as few MV/cm order by Bernadini
prediction. Such strong field may evidently influence the optical
properties of III-nitrides based structure. Some authors believe that the
strong intrinsic electric field contained in the quantum well will cause the
electron and hole-wave function overlap separated, and finally decrease
the optical oscillator strength. [20] If the in-well field becomes so large
that may sweeps the carriers away from the quantum well, and the
exciton will be field-ionized. Then the performance of the
8
optoelectronic devices is degraded due to that strong electric field. So,
how to measure the strength of the field is an interesting issue in the field
of the nitride-based alloys.
For InGaN-like alloy, Takeuchi et al. [21] have estimated the
piezoelectric effect in InGaN/GaN quantum well by mean of
bias-dependent photoluminescence. They determined that the
magnitude of piezoelectric field is 1.2 MV/cm for InGaN/GaN quantum
well and identified the direction of this field is oriented from surface to
the substrate. And the build-in piezoelectric field will lead to QCSE and
a smaller effective band gap. So, in this work, a detail relation between
stress and effective band gap will be further studied after stress level
measurement.
To sum up the above theoretical and experimental results for
III-nitrides based semiconductors. We can get some results about
polarization-induced field for III-nitrides based materials. (1) Most of
the experimentally reported values of field strength are smaller than the
theoretical prediction; (2) the direction of field is already determined for
InGaN/GaN QWs structure; (3) for AlGaN and InGaN epilayer, the
electric field is originated by the contribution of spontaneous polarization
and that of piezoelectric polarization, respectively, and (4), the strain
subjected to InGaN/GaN heterostructure is always compressive strain.
Nevertheless, all research groups in the world focus the variant sort
strain subjected to epilayer and how to reduce the strain effect from the
viewpoint of growth process. McIntosh et al. [22] have deposited
9
AlInGaN in the different composition range by MOCVD on (0001)
sapphire substrate. By changing the quaternary composition, the band
gap and lattice constant can be adjusted in order to attain AlInGaN/InGaN
lattice matched or strain relax structure. But strain change induced by
fabrication process is very seldom discussed. Generally,
MOCVD-grown GaN epi-layer on the sapphire substrate is known to
have a high compressive stress due to the large lattice mismatch and CTE
mismatch between sapphire substrate and GaN. [23-26] The compressive
stress will cause the distortion of energy band gap and the charge
separation in the quantum wells. As the previous section, wafer bonding
and LLO are two main processes in thin-GaN LED fabrication. And
these two processes usually accompanied thermal variation. This
thermal variation will induce the strain change and also change the
internal piezoelectric field. During the operation of GaN LED devices,
the internal piezoelectric field also normal to the quantum well plane and
would cause quantum-confined stark effects. As a result, two effects
occurred. One is red shift in light emitting at increasing forward current
injection. The other is that the degradation of external quantum
efficiency (E.Q.E). We believe that the distortion of the GaN energy
band structure will strongly affect the LED device performance such as
the recombination efficiency, emission peak wavelength, and threshold
current. So, the stress-state of the transferred GaN is an important issue
to study for the thin-GaN LED technology.

10
1-4 Raman scattering examination for thin film stress
As we know, the magnitude of these stresses depends on the
geometry of the films. But it is very hard to get the stress value directly.
So, most researchers use finite element simulations of the stress
generation during processing. Unfortunately, simulations may give a
distorted image of the real situation if they are not properly validated.
Raman spectroscopic is one of the few techniques that can be used for
this validation. However, it is still generally impossible to obtain
quantitative or even precise absolute stress state value from Raman data
without assumptions or simulations. The complete spectroscopic
information often needed to compute an arbitrary stress is almost never
available. So, a typical method of analysis is that using the difference
between two different stress-state materials. In our system, we get the
original Raman data first and then get another data after processing.
And we can calculate the stress change during this process by the
simplest assumption made is biaxial stress (
yy xx
+ ). There is
usually a linear relation between the stress and Raman frequency shift
( ). The slope is known to the elastic constant of Raman scattering
and the relation is described as Y . While tensile stress ( 0 > )
will result in a negative frequency shift, and compressive stress ( 0 < ) in
a positive shift. In summaries, Raman spectroscopy can help us to catch
the vibration of atom bonding induced by stress state change. By this
character, Raman spectroscopy has contributed a great deal to the
advances in the -nitrides field. [27] In the second part of this thesis, we
11
discuss about the relationship between in-plane biaxial stress at different
bonding conditions by Raman spectroscopy and also investigate the stress
evolution of transferred GaN thin film in thin-GaN LED process.

1-5 Outline of this dissertation
Light emitting diode technology is at the forefront of a revolution in
the lighting industry. But the potential efficiency and reliability of these
devices are unmatched for mass commercial use. So, in this work, we
studied the possibility of Au-Si wafer bonding applying for thin-GaN
LED fabrication and tried to improve LEDs lighting performance by
controlling the process parameter. The reminders of this dissertation
present researches about Au-Si bonding mechanism and stress evolution
of transferred GaN epi-layer. The stress evolution theory will be further
verified by compressive stress relief measurement of transferred GaN thin
films. Biaxial in-plane stress was plotted with various Au bonding
thickness and energy band gap of GaN epi-layer.













12
Chapter 2 GExperimental Technique
In this thesis, the thin-GaN LED devices are fabricated by Au-Si
eutectic wafer bonding and LLO process. As we know, the melting
point of Au(Si) solid solution phase depends on the their compositions.
So, the melting point of Au(Si) solid solution phase can be estimated
from the Au-Si phase diagram by knowing the composition. The major
phase of Au-Si bonding interface could bare melting point even over
1100 C and very stable. This advantage is like Pd-In bonding system.
Besides, Si is chosen not only its high thermal dissipation, but also
segment easier than other metal substrates.
First, AlInGaN MQWs LED epi-layer structure was grown on a
sapphire substrate by metalorganic chemical vapor deposition (MOCVD).
Then, a Ni/Au p-GaN contact layer was deposited on the p-GaN layer by
E-gun process and followed by an annealing process to achieve a
low-resistance contact. The annealing temperature is 500 for 2 J
minutes in ambient air. For the thin-GaN structure, a reflective layer, Al,
is needed to reflect the downward emitting light through the top p-type
contact. After the Al reflection layer deposition, the bonding
metallization, Ni/Au, was deposited on the top of the Al layer. Ni serves
as an adhesion and barrier layer and Au layer is used for the Au-Si wafer
bonding. The thickness of Au layer is varied stepwise from 7 m to 40
m. The entire metal configuration is illustrated in Fig. 2-1.
A heavy doped (111) Si (P
+
, 10
-3
Ocm, 625 m) is used to bond
with the GaN wafer. To perform the wafer bonding process, the Si
13
wafer was cleaned by the standard organic acid solution to ensure the
cleanness of Si bonding surface. Wafer bonder (EVGroup, model 501)
was used to perform Au-Si bonding. The bonding temperature and
pressure were 420 and 5 MPa, respectively. The bonding time was J
30 minutes. Here, we also do another contrast experiment with bonding
temperature 420 , and other conditions are the same to check the stress J
difference induced by temperature effect. The detail Au-Si reaction
mechanism will be described at the following chapter and this method has
been successfully demonstrated to be a suitable for thin-GaN LED
fabrication. [28]
After GaN/Si wafer bonding, KrF excimer laser (JPSA-IX120i, 248
nm, 25 ns) was used to strip the initial sapphire substrate. The energy of
single laser pulse is 600 mJ/cm
2
and the irradiation size is 1 1 mm
2
.
The laser pulse with high energy was irradiated into transparent sapphire
substrate and proceeds thermal decomposition reaction. Then, the GaN
epi-layer can be separated from the sapphire substrate and transferred
onto the Si substrate. The transferred GaN epi-layer was processed into
thin-GaN LED device. The process flowchart of thin-GaN LED devices
fabrication is shown in Fig. 2-2. After LLO process, the residual
metallic Ga droplets on the n-GaN surface of the transferred GaN
epi-layer were etched away by the dilute HCl acid solution (10 Vol %).
Then, HDP (High Density Plasma) etcher was used to remove the top
un-doped GaN layer and define the chip area. This step can avoid the
possible damage occurred at LLO process and remove the high
14
electric-resistance layer. The chip area is about 350 350 m
2
. Finally,
100 100 m
2
Ti/Al/Ti/Au n-type contact pad was produced on the
n-GaN epi-layer. The final LED chip structure is shown in Fig. 2-3.
We realize that the stress state of the transferred GaN epi-layer will
influence not only energy band gap, but also both electrical and optical
characteristics. In the process of the layer transferring, the stress level
of the GaN layer will be affected, and then also eventually affects the
LED performance. For the purpose to characterize the stress level on
the transferred GaN epi-layer, Raman spectroscopy was used to analyze
the GaN epi-layer. We first attempted to take a reference scan of the
GaN on sapphire (Fig. 2-4), and then scanned again after GaN epi-layer
transferring process. Our system operates in the -1 order using a 250
mm focal length and a 3000 line/mm grating with 488 nm incident light.
This result in a resolution of our Renishaw in Via Raman instrument
being 0.46 cm
-1
/pixels. The mapping operation is limited by the laser
spot size which has been measured to be approximately 1 m. Further
details on this Raman system can be found at its companys website. [29]
By analyzing the Raman shift (E2 mode) change, the biaxial in-plane
stress level of the transferred GaN epi-layer can be obtained.
For analyzing the stress level distribution on GaN surface, a further
2-D Raman map scan technique was used. Every part of GaN surface
was scanned by Raman spectroscopy in short duration and then each
wavenumber value was gotten. By averaging each Raman peak position
at each point on GaN surface, the reasonable values for the nominal stress
15
in the sample could be obtained.
Then low temperature photoluminescence (PL) spectra were
obtained by a PL system with cw 325 nm He-Cd laser as excitation light
source. The PL examination can help us to find the wavelength change
during thin-GaN LED fabrication. After thin-GaN LED chip process,
the LED chips were also examined by luminescence intensity current
(L-I) measurement for the purpose to find the relationship between the
optical performance and stress state in GaN epi-layer.

















16














Fig. 2-1 The entire metal configuration











Sapphire
Au
Ni (300)
Al (1500)
GaN
Ni/Au (50/50)
17




Fig. 2-2 The process flowchart of thin-GaN LED devices fabrication




Sapphire
Sapphire
GaN
Metallization
Substrate
Metallization
Substrate
scan
Wafer bonding Laser lift-off
Chip definition
GaN
Transferred thin-GaN
Substrate
Metallization
p-GaN
active layer
n-GaN
undoped buffer
Substrate
Metallization
p-GaN
active layer
n-GaN
Substrate
Metallization












Remove buffer layer
HDP etching
n-GaN
p-GaN
18

n-GaN
active layer
p-GaN
P-contact
Si
Au-Si bonding layer
n-contact

Fig. 2-3 The final LED chip device




Our GaN
0
2000
4000
6000
8000
10000
12000
14000
425 475 525 575
Wavenumber
C
o
u
n
t
s

Fig. 2-4 Raman spectrum of GaN on sapphire


19
Chapter 3 GResults and Discussions
This chapter is divided into five parts G1. Thin-GaN LED fabrication
by Au-Si wafer bonding, 2. Stress evolution of GaN epi-layer, 3. Raman
measurements for transferred GaN thin film, 4. Stress change by different
bonding temperature, 5. Stress effect on optical properties of GaN
epi-layer and lighting performance.
In part 1, the detail Au-Si bonding mechanism and the feasibility of
Au-Si bonding applying for thin-GaN LED fabrication were described.
The basic electrical and optical performance was also measured.
In part 2, the whole stress evolution in the process of layer
transferring from the viewpoint of thermal change was described.
In part 3, the biaxial in-plane stress was measured and calculated by
Raman measurement. The surface stress distribution was also shown by
Raman mapping scan technique.
In part 4, a similar experiment with different bonding temperature
was designed and tried to find the evidence to support the inference of
stress evolution in part 2.
In part 5, PL instrument was used to measure energy band gap of
GaN epi-layer. The energy band gap was sketched with various biaxial
in-plane stress states in GaN thin film and found their relation. By
wavelength measurement, we proved that we can avoid QCSE by
controlling stress level of GaN epi-layer. And the better lighting
performance was also gotten at less stress state of GaN thin film by L-I
measurement.
20
3-1 Thin-GaN LED fabrication by Au-Si wafer bonding
We talked about that the LLO is the key process of the thin-GaN
LED fabrication at the previous section. Thus, GaN LED epi-layer can
be separated from the sapphire substrate and transferred onto the Si wafer.
But here, the decomposition reaction of GaN would only occur at a
temperature above 900 . So, during LLO process, the in J -situ temperature
at the GaN/sapphire interface should be over 900 at least, which is also J
confirmed by other people s thermal simulation result. [30] Under such
high process temperature at the GaN/sapphire interface, the bonding layer
could be potentially affected (remelting or degraded), since the bonding
layer is only several microns away from the GaN/sapphire interface. If
any melting or phase change occurs in the bonding layer during LLO
process, the GaN epi-layer would not be smoothly transferred onto the
thermal substrate.
Fig. 3-1 shows the transferred GaN epi-layer on the Si substrate by
using In-In bonding layer. Clearly, we can observe that the transferred
GaN epi-layer seriously fractured on the Si substrate. We speculate that
the In-In bonding layer could be melting during LLO process, which
caused the cracking of the transferred GaN epi-layer. So, the key for a
successful transferring of the GaN epi-layer on thermal substrates relies
on a good thermal stable wafer bonding layer. The bonding layer has to
sustain the LLO process. For this purpose, many bonding systems are
adopted by other researchers in the world. The main-stream choices are
AuSn, Pd-In, and metal brazing, such as, Ni-Ni or Cu-Cu. [9-11] Wong in
21
Berkeley reported Pd-In bonding system and its advantage is that it can
produce a bonding layer with a high melting temperature under a low
temperature process. The resultant bonding layer mainly is the Pd-In
intermetallic compound phase having a melting point of 664 . At this J
work, we first investigated the feasibility of the fabrication of a thin-GaN
LED structure by using Au-Si bonding system. Au-Si eutectic bonding
has been widely used for the Si die attachment and MEMS packaging as
well. [31-33] From Au-Si binary phase diagram in Fig. 3-2, The Au-Si
system consists of a simple eutectic point at 363 and the composition J
of 3.2 wt.% of Si. [34] Around this eutectic point, the curve is very sharp
and steep. So Au-Si bonding has the similar merit with the Pd-In
bonding system; it can achieve a thermal stable bond layer with high
melting point (over 650 ) under relatively low processing temperature, J
e.g., 400 . Also, Au has the best ductility among all metal elements. J
The Au bonding layer would absorb the thermal stress caused during the
wafer bonding and LLO process. So, a low residual stress level on the
transferred GaN epi-layer could be obtained.
The flowchart of Au-Si reaction is described below and shown in
Fig. 3-3. During the bonding process, we promote the temperature to
420 , which is higher than the eutectic point. Si atoms first dissolved J
into the Au bonding layer. Once the local composition of the Au layer
near the Au/Si interface reached the Au-Si eutectic composition, (i.e.,
97Au3Si), then eutectic liquid Au-Si alloy would form. Typically, it
only takes less than one minute to form the liquid Au-Si alloy. Then,
22
eutectic Au-Si liquid would wet the Si/Au interface and produce an
uniform eutectic liquid Au-Si interfacial layer. Once eutectic liquid
Au-Si interfacial layer formed in the bonding process, Si atoms would
continuously dissolve into eutectic liquid Au-Si bonding layer due to the
concentration gradient of Si in the AuSi liquids. The continued
dissolution of Si atoms make some craters form in the Si interface, then
the AuSi liquids fill into theses craters, and then the Si atoms keep
dissolving due to the infinite source of Si. Due to the sharp curve
around the eutectic point in Au-Si phase diagram, we know that with a
little incremental Si content, the melting point of the Au-Si alloy would
dramatically increase. Consequently, with a slight increasing of Si
content in the eutectic liquid Au-Si bonding layer, a high-melting
bonding layer would achieve. As seen in Fig. 3-4, SEM cross-sectional
image show that a continuously uniform Au-Si bonding layer formed at
the interface. Dark phase particles at the bonding layer were identified
to be Si precipitates by EDX (Energy-dispersive x-ray spectroscopy)
analysis. The composition of Au and Si is 68 wt.% and 32 wt.%,
respectively in position A. This Au-Si composition is Si-rich
comparing with eutectic point. It proves that the excess of Si atoms
precipitate out during cooling process. And the position B has the
standard Au-Si eutectic composition (Au G96.24 wt.% FSi G3.76 wt.%).
The L-I-V characteristics were measured by semiconductor
characterization measurements (Keithley 4200). Fig. 3-5 displays the
lighting image of thin-GaN LED chip on Si and Fig. 3-6 shows the
23
luminance intensity current voltage (L-I-V) characteristics of our
thin-GaN LED chip. For the 14 mil chip, the forward voltage is 3.4 V at
20 mA. This electrical property is similar with the conventional LED
and slightly lower than the previous reported values for thin-GaN LED
structures. [10] In addition, this co-planar LED structure exhibits a high
luminance intensity of 204 mcd at 20 mA. For 40-mil large chip, the
forward voltage is 7 V at 350 mA, and luminous intensity is 520 mcd.
The forward voltage is clearly higher than the conventional large size
LEDs. We speculate that the high I-V characteristic should be caused
by the following possible reasons Gdamage of p-GaN contact at bonding
process, electrical behavior of Au-Si alloy, bad contact interface between
n-GaN and n-electrodes caused by LLO. By our observation in Fig. 3-7,
n-GaN surface will become very rough after LLO. We believe that is
because laser energy is not very uniform. When we scan sample, some
areas are scanned repeatedly, but some are just only once. That will
make the different damage depth and form the rough imprint during LLO,
and then also influence the following HDP etching process and
n-electrode pads fabrication. So, we think the most major key issue is
the un-uniform laser energy at LLO. Here, we can also observe the
saturation phenomena occurred at only 350 mA due to bad electrical
property.

3-2 Stress evolution of GaN epi-layer
The above Au-Si bonding process is shown to be a feasible wafer
24
bonding technique for the fabrication of thin-GaN LEDs. However, the
stress level of the GaN epi-layer transferred onto the Si substrate is
another important issue that needs to be evaluated. This high stress
level would result in the possible formation of defects, peeling, and
cracking, which would eventually degrade the internal quantum
efficiency and reliability of the resultant LEDs. Bykhovski et al. had
reported that stress in the GaN epi-layer not only affects the energy band
gap, but also influences both the electrical and optical characteristics of
the GaN epi-layer. [35] So, it is very important to investigate the thin
film stress variation of the transferred GaN epi-layer by using Au-Si
bonding.
It has been reported that the compressive stress level of
MOCVD-grown GaN epi-layer on the sapphire substrate is in the range
of 450 ~ 650 MPa at the thickness range from 50 m to 2 m. [36] The
compressive stress in the GaN epi-layer attributes to two parts: intrinsic
stress and extrinsic stress. The intrinsic stress comes from the lattice
mismatch between the GaN epi-layer and the sapphire substrate. As for
the extrinsic stress, it mainly results from the thermal stress caused by
CTE mismatch between the GaN layer and the sapphire substrate
(a
GaN
=5.610
-6
K
-1
and a
Sapphire
=7.610
-6
K
-1
) [37] during cooling after
MOCVD deposition process. As the MOCVD-grown GaN epi-layer
cooling from the process temperature of MOCVD, 1000 , to room J
temperature, a compressive stress will be established due to CTE
mismatch between GaN and sapphire.
25
As mentioned in the experimental parts in chapter 2, to transfer the
GaN epi-layer onto a Si wafer, the MOCVD-grown GaN epi-layer would
go through a series of thermal treatments. Therefore, the GaN epi-layer
would experience different stress states during the fabrication process of
the thin-GaN LED structure. As seen in Fig. 3-8, the stress evolution of
the GaN epi-layer during the substrate transferring is illustrated.
According to Kozawa s result, we assume that the GaN epi-layer grown
on the sapphire substrate has a compressive stress of about 620 MPa at
the thickness of 4 m. As mentioned previously, 620 MPa compressive
stress is composed of two contributions: (1) lattice constant mismatch and
(2) thermal stress, i.e., CTE mismatch between the GaN layer and the
sapphire substrate. The thermal stress part can be simplified and
estimated by the following equation G

( )
GaN GaN sap
Y T
.
(1)

Where
. sap
(7.6 ppm) and
GaN
(5.6 ppm) are the CTE of the
sapphire substrate and the GaN layer, ?T is 975
o
C, and Y
GaN
is Young s
modulus of GaN. Plug in the necessary parameters into the equation (1),
then, the thermal stress part in the MOCVD-grown GaN epi-layer is
obtained to be about 370 MPa. So, the compressive stress induced by
lattice constant mismatch part is about 250 MPa.
During the Au-Si wafer bonding process, the pair of GaN and Si
wafers will be heated up to 400 . Hence, the compressive stress in the J
26
GaN epi-layer will be relieved by 150 MPa due to the relief of thermal
stress. In other words, as the GaN wafer bonded with Si wafer at 400
o
C,
the stress-level of the GaN epi-layer could be about 470 MPa. While the
temperature of bonded sapphire/GaN/Si samples cooled down to room
temperature, the stress of the GaN epi-layer is mainly determined by the
stress balance of the Si and sapphire wafers. Since CTE of sapphire is
larger than CTE of Si (a
Si
=2.610
-6
K
-1
) [37], Si wafer would be under a
compressive state due to the shrinkage of the bonded sapphire substrate.
During cooling from the bonding temperature (420
o
C), the GaN epi-layer
would only gain very little compressive stress with the presence of Si
wafer. Once the sapphire substrate was removed by LLO process, the Si
wafer would expand back to the normal state at room temperature. The
expansion of Si wafer provides a tension force to reduce the compressive
state of the GaN layer. The tensile force exerted on the GaN epi-layer
by the Si substrate is ( )
GaN Si GaN
Y T , where
Si
is the CTE of Si and
?T = 400
o
C. Plug in all necessary parameters, the stress relieved by the
tension of the Si substrate is about 235 MPa. So, the residual stress
level in the transferred GaN epi-layer on Si substrate is about 235 MPa
(470-235). From above discussion, we conclude that the stress of the
transferred GaN epi-layer can be adjusted by the following two factors G(1)
the bonding temperature, which relieve the thermal stress of the GaN
epi-layer on sapphire. (2) the tension force provided by the smaller CTE
transferring substrate, i.e., Si in this case.

27
3-3 Raman measurements for transferred GaN thin film
As the introduction of chapter 1-4, Raman spectrum was used to
analyze the stress-state of the GaN epi-layer. The shift of Raman peak
position reveals the stress level of the GaN layer. Kozawa et al. had
correlated the stress level of the GaN epi-layer and the measured Raman
shift ( ) by the following relation G
GaN
2 . 6 . [36] According to
this relation, the stress state of the GaN epi-layer can be obtained by
Raman spectrum analysis. Fig. 3-9(a) shows the Raman peak position
vs. various bonding layer thickness ranging from 7 m to 40 m.
Raman peak position of the initial GaN layer on sapphire is examined to
be 568.61 cm
-1
. We found that the Raman peak position of the GaN
epi-layer has red shift to the short wave-number region after transferring
the GaN epi-layer on Si substrate. From Kozawa s analysis, red shift
implies the relief of the compressive stress state in the GaN epilayer.
Using Kozawa s relation,
GaN
2 . 6
, the stress level of the
transferred GaN epi-layer with different Au bonding thickness can be
obtained. Fig. 3-9(b) shows the magnitude of the compressive stress
relief vs. Au bonding layer thickness. The maximum compressive stress
relief in the transferred GaN thin film occurred at the largest Raman peak
position shift of 10 m Au layer (red shift, 1.79 cm
-1
). The maximum
compressive stress relief is about 290 MPa. This value is almost half of
the reported value of as-grown GaN epi-layer. The relief of the
compressive stress of the transferred GaN layer is mainly due to the
replacement of the initial grown sapphire substrate by Si substrate.
28
From the discussion in the previous section, we note that the stress
relief by the layer-transferring process is about 385 MPa. Yet, from our
Raman spectrum, the stress relief at the 7 m Au thickness is only about
125 MPa. Here, we realize that the effect of the Au bonding layer on
the stress-state of the GaN layer can not be ignored. We believe that the
Au bonding layer has two functions on the stress-state of GaN epi-layer
during the process of GaN epi-layer transferring. The first effect is the
thermal stress effect contributed from the Au bonding layer. CTE of Au
(1410
-6
K
-1
) is much larger than GaN. Therefore, the Au bonding layer
could also cause the compressive stress in the GaN epi-layer after the
sapphire substrate being removed. So, the Au bonding layer could exert
a compressive stress on the GaN epi-layer during the cooling after wafer
bonding process. The structure bends toward the Au layer, as depicted
in Fig. 3-10, where ? is the radius of curvature, L is the length, W is the
width, and t is the thickness of layer. The stress distribution for
heteroepitaxial structures can be formulated using the following equations
for force balance, momentum balance, and equal lattice constants at the
interface.

N
i
i
F
1
0 (2)

( )

1
]
1

+
N
i
i
j
i j i
i i
t t F
R
w t E
1 1
2
1
3
0
12
(3)

29
( ) ( )

+
+ +
+
+
+
1
1
1
1 1
1
1
2
1
N
i
i i
i i
i
i i
i
i i
t t
R wt E
F
wt E
F
(4)

Then, we combine these equations and get the modified Stony s equation.

1
2
2
1
6 1 t
t Y


,
_

(5)

Where Y is the Young s modulus and ? is the Poisson ratio. For Au
layer, we divided two parts to discuss. Case 1 Gthe stress of Au induced
by Si. We can simplify the equation (5) to
Si
Au
Si
t
t

6
2
. So, the strain of
Si is proportional with the thickness of Au layer square. Because the
ratio of Au thickness with Si thickness is very small, so we can infer that
Si substrate almost doesn t deform. And the curvature of this system
will not change obviously. Case 2 Gthe stress of GaN induced by Au.
Similarity, we drive the equation (5) to
GaN
Au
GaN
t
t Y

6 1
2

,
_

. In this
equation, Y, ? are constants, and the curvature, ?, is also the constant by
the discussion of case 1. So, the stress of GaN induced by Au can be
neglected and all induced by Si substrate while thickness of Au is small.
As Au thickness increases, the thickness effect will appear, and the stress
of GaN is function of Au thickness square.
We can observe the quadratic curve while Au bonding layer is over
30
10 m. However, at the initial Au bonding thickness, we found that the
stress relief increased with the Au thickness. On the other hand, we also
speculate that the second function of the buffering effect plays the
dominant role for the compressive stress in the GaN layer. Au has the
best ductility among all metal elements. So, the Au layer could serve as
a stress-buffer layer. We believe that the Au bonding layer could absorb
the thermal stress caused by the sapphire during the wafer bonding and
LLO process. With thicker Au bonding layer, more residual stress level
on the transferred GaN epi-layer can be relieved. At Au bonding
thickness ranging 10 m to 40 m, the thermal stress effect would
become dominant. With thicker Au thickness, the buffer effect saturated.
The stress level of the GaN epi-layer was mainly influenced by the
thermal stress from the Au layer. At 10 m Au layer, the stress relief
reaches the maximum, which means that the optimal balance of the
buffering and thermal stress effects.
In addition, 2-D mapping scan of Raman examination is used for
observation of the transferred GaN surface stress state. The detail
Raman peak image is obtained and can be calculated to standard
deviation. According to the previous discussion, we can know that the
larger standard deviation of measured Raman peak shift, the stress state
of GaN layer vibrates violently. It implies that the quality of the GaN
surface is worse. The hollow circle points in Fig. 3-9(a) show the
standard deviation of the measured Raman peak position versus Au
bonding layer thickness. The tendency shows that the values of standard
31
deviation are higher while the bonding Au thickness is thinner, and the
values become smaller while Au bonding thickness is over 10 m. It
means that the transferred GaN epi-layer has better film quality with
thicker Au bonding layer. The quality degradation of the GaN epi-layer
after layer transferring process might be caused by (1) micro-cracks
during the LLO process to separate the GaN epi-layer with the sapphire
substrate. (2) the rough n-GaN surface after LLO. The micro-cracks
in the GaN epi-layer could be resulted from the high local temperature at
GaN/sapphire interface during laser separation. Thicker Au layer could
prevent the formation of those micro-cracks due to their buffer effect and
better thermal conduction to avoid high local temperature accumulation at
GaN/sapphire interface. Another possible explanation for this behavior
is that Au-Si bonding layer will form many craters and voids due to the
quick dissolution of Au atoms into Si. By Bokhonov s study, a large
amount of Au atoms will dissolve into Si after long reaction duration and
form the craters and voids. [38] This phenomenon is also observed by our
experiments. These craters and voids form under the GaN thin film will
make transferred GaN layer to cave-in. The caved GaN surface make
non-mirror face and increase the vibration of Raman peak position. In
our experiments, the thicker Au layer isn t yet consumed completely.
So, the craters and voids did not form easily. In addition, Micro-cracks
might be induced by LLO process, which also can be observed by the
different mapping results in the same sample. Fig. 3-11(a) is the Raman
mapping result corresponding with the smooth GaN surface. Fig. 3-11(b)
32
is the one corresponding with the GaN surface which has the cracks.
Both they are the same sample in different areas. The deep yellow color
in the second figure shows the lower Raman peak position and also
means the higher compressive stress relief. The same finding is
observed on other samples. We believe that it is because the cracks
induced by LLO will assist to relieve the compressive stress, even though
they will also make the film quality degraded.

3-4 Stress change by different bonding temperature
To prove the deduction of stress evolution in section 3-2, we design
an experiment with different bonding temperature, 380
o
C, and also
measured the in-plane biaxial stress on transferred GaN layer. In Fig.
3-12, this is Raman peak position vs. Au bonding layer like Figure 3-8.
We can observe the same tendency but lower Raman peak shift, 1.56 cm
-1
.
And then, the lower amount of compressive stress relief, 255 MPa, can be
obtained. This value is slightly smaller than 290 MPa, which is relieved
while the bonding temperature is 420 . This result obeys the J
deduction at section 3-2. The lower bonding temperature leads two
effects to reduce the compressive stress relief. One is induced by
sapphire upon heating process, and the other is induced by Si at cooling
process. Initially, the compressive stress in the GaN epi-layer will be
relieved by 150 MPa due to the relief of thermal stress at heating process.
Now, the value downs to 134 MPa at lower bonding temperature. On
the other hand, the tension force induced by expansion of Si wafer at
33
cooling process will also be reduced (235 MPa 211 MPa). By these
two reasons, we get the lower compressive stress relief at lower bonding
temperature, and make sure we can change the biaxial in-plane stress by
controlling process temperature.

3-5 Stress effect on optical properties of GaN epi-layer and
lighting performance
Low temperature photoluminescence (PL) spectra were obtained by
a PL system with 325 nm He-Cd laser as excitation light source and help
us to analyze the luminescent band gap change with various stress level in
the transferred GaN epi-layer on Si. The relation between band gap and
in-plane stress level of the transferred GaN epi-layer are shown in Fig.
3-13. As expected, the energy band gap increased due to the relief of
the compressive stress. By Takeuchi s study, the build-in piezoelectric
field will lead to QCSE and a smaller effective band gap. [21] According
to their calculation that the strain-induced piezoelectric field in the case
of the 13% indium content induces a redshift of about 240 meV for the 5
nm thick quantum well, i.e. the deformation potential of GaN (the relation
between the piezoelectric field parallel to the c-axis and the band gap
energy) is found to be 240 meV. In our case, 85 meV is estimated the
largest blueshift will be observed as the internal strain was relieved. In
spite of no reaching the theoretical value, 240 meV, but this blue shift
will be contributive to decrease the QCSE induced by growth process is
expectable. By this finding, it is possible that we can change the
34
build-in piezoelectric field successfully and alleviate the QCSE for
further improving the lighting performance by controlling the stress state
in the transferred GaN thin film. About the relation between Eg and
biaxial in-plane stress at room temperature, the tendency of increasing
energy bandgap will be eased off while gradually increasing the
compressive stress relief. Unlike the linear relation in the tensile region
of the GaN layer reported by Zhao [39], who reported a linear
relationship with a coefficient of 21.1
t
3.2 MeV/GPa. We found a
non-linear parabolic dependence of the QW band gap with the stress
level G

) ( 84 . 1 8 . 0 56 . 2
2
eV Eg +

The parabolic curve means that the increasing tendency of energy
band gap will be eased with the larger biaxial in-plane stress. It seems
that there is another mechanism to lead to red shift except piezoelectric
field change. Because the measured biaxial in-plane stress is described
as the compressive stress relief in our system, so we believe that the
change of lattice constant induced by tensile stress is not considered. As
we know, the larger tensile stress will lead to the larger lattice constant
and also make the smaller energy band gap generally. This deformation
effect will compete with the blue shift phenomena induced by
piezoelectric field change.
For the purpose to study the lighting performance, luminescence
35
intensity current (L-I) values were measured and sketched the relation
chart with biaxial in-plane stress, as shown in Fig. 3-14(a). We can find
the better lighting intensity with larger biaxial in-plane stress, and also
find their relation G

2
0034 . 0 0856 . 1 59 . 2 + I

As the description in chapter 1, the general GaN epi-layer grown on
sapphire substrate suffers a compressive stress and causes QCSE induced
by internal piezoelectric field. The QCSE makes energy band structure
of GaN epi-layer distortion. While energy band structure deforms,
wavelength will change (red shift) and lighting efficiency (internal
quantum efficiency) will be degraded at the same time. That is because
the original direct bandgap structure becomes the indirect bandgap
structure. So, the recombination of electrons and holes need waste the
extra kinetic energy. During the fabrication of thin-GaN LED devices,
the internal piezoelectric field, which is normal to the quantum well plane,
will be efficiently eliminated with the relief of compressive stress. And
then the band structure backs to the direct bandgap structure. So,
wavelength will tend to blue shift and lighting efficiency will increase
without extra energy loss. And as a result, the more compressive stress
relief leads to the better lighting performance. Fig. 3-14(b) is the
illustration of band structure deformation induced by stress change. So,
we successfully get better lighting performance by producing the lower
36
stress state of transferred GaN epi-layer.























37







Fig. 3-1 Transferred GaN thin film on the Si substrate by In-In bonding










GaN epi-layer
In bonding layer
38







Fig. 3-2 Binary phase diagram of Au-Si







363
39





Fig. 3-3 The flowchart of Au-Si reaction during bonding process







Si dissolves into Au layer to
form AuSi from the defects
on the Si surface.
AuSi (97Au3Si) eutectic
liquids formation.
Si precipitations
The Au layer totally becomes
AuSi alloy and Si continues
to dissolve into AuSi liquids.
420J
RT
Heating
Cooling
Si
Si
Au
Si
RT
Au
Si
Au
Si
AuSi molten alloy
While cooling to RT, the
surplus Si atoms precipitate
out.
420J
420J
40








Fig. 3-4 SEM cross-sectional image of continuously uniform Au-Si
bonding layer







GaN
Sapphire
Si
Au-Si alloy
Si precipitate
A
B
41






Fig. 3-5 Lighting image of transferred thin-GaN LED chip



42


(a) 14 mil chip


(b) 40 mil chip

Fig. 3-6 L-I-V characteristics for the thin-GaN LED


43









Fig. 3-7 SEM image of n-side GaN surface after LLO








44




Fig. 3-8 Stress evolution of the GaN epi-layer during the substrate
transferring



GaN
Sapphire
GaN
Sapphire
Au
Si
GaN
Sapphire
Au
Si
Si
GaN
Au
Sapphire
Si
GaN
Au
620 MPa compressive stress
in MOCVD-grown GaN
layer.
(a) (b) (c)
(d)
(e)
At 420J Au-Si bonding
temperature, 470 MPa
compressive stress in GaN
epi-layer.
After cooling down to R.T., Si
is under compression due to
the shrinkage of the sapphire
substrate
After the sapphire is
eliminated, Si would expand
to the normal state at R.T.
The stress state of the GaN
layer is released by G(1) Re-heat
at the wafer bonding process.
(2) The tensile stress from the
Si substrate.
45
(a)

(b)

Fig. 3-9 The (a) Raman peak position and (b) biaxial in-plane stress vs. Au
bonding layer thickness while bonding temperature is 420 J

46








Fig. 3-10 The illustration of bending transferred GaN thin film on Si








GaN (5.6E-6)
Au (14.2E-6)
Si (2.6E-6)
e
L
W
t
1
t
2
t
3
47

(a)

Peak
568
567.895
567.789
567.684
567.579
567.474
567.368
567.263
567.158
567.053
566.947
566.842
566.737
566.632
566.526
566.421
566.316
566.211
566.105
566
7 msmooth


(b)

Peak
568
567.895
567.789
567.684
567.579
567.474
567.368
567.263
567.158
567.053
566.947
566.842
566.737
566.632
566.526
566.421
566.316
566.211
566.105
566
7 m crack


Fig. 3-11 Raman mapping results corresponding with the (a) smooth GaN
surface and (b) GaN surface with cracks




100 m
100 m
48
(a)


(b)


Fig. 3-12 The (a) Raman peak position and (b) biaxial in-plane stress vs.
Au bonding layer thickness while bonding temperature is 380 J
49
(a)

(b)

Fig. 3-13 (a) PL spectrum with various stress state in GaN thin film F(b) the
relation between Energy band gap and in-plane stress level of the
transferred GaN epi-layer
50



(a)

(b)





Fig. 3-14 (a) Luminous intensity vs. biaxial in-plane stress and its relation F
(b) the illustration of band structure deformation induced by stress change




-
-
+
+
GE
1 G E
2
51
Chapter 4 GSummaries
Light emitting diode technology is expectable to make a tremendous
impact on the lighting industry, even the whole human life. However, in
order for the true potential of this technology to be realized, some
significant hurdles must be overcome. The focus has been on improving
the efficiency of light emitting diodes for use. So, this dissertation
concentrates on three parts G(1) Au-Si wafer bonding technique applying
for thin-GaN LED fabrication F(2) Stress analysis and measurement of
GaN epi-layer, and (3) lighting characterization of transferred GaN thin
film by controlling stress state.
Thin-GaN LED demonstrates a better fabrication method, which has
better thermal dissipation and higher lighting area utilities. Au-Si wafer
bonding technique is successfully used on thin-GaN LED fabrication in
this work and also proven that it is a feasible bonding system with high
thermal stability for sustaining the following LLO process. The L-I-V
results show that the better electric and optical properties comparing with
the conventional wire bonding LED. And we also describe clearly
Au-Si bonding kinetic and thermodynamic mechanism in the process of
wafer bonding.
The detail stress evolution of GaN epi-layer in layer transferring
was also described. As mentioned in the experimental parts in chapter 2,
to transfer the GaN epi-layer onto a Si wafer, the MOCVD-grown GaN
epi-layer would go through a series of thermal treatment. Therefore, the
GaN epi-layer would experience different stress states during the
52
fabrication process of the thin-GaN LED structure. So, we sketched the
in-situ stress change by the viewpoint of thermal stress. And from our
discussion, we realized that the stress of the transferred GaN epi-layer can
be adjusted by the following two factors G(1) the bonding temperature,
which relieve the thermal stress of the GaN epi-layer on sapphire. (2)
the tension force provided by the smaller CTE transferring substrate, such
as, Si. Whatever the compressive stress relief in (1) or tensile stress in
(2), both of them will make the stressed GaN epi-layer tend to less stress
state in the process of thin-GaN LED fabrication. We also set up a
contrast experiment with different bonding temperature in order to prove
our deduction about stress evolution. The lower bonding temperature
has also been proven that it leads the lower compressive stress relief.
The absolute stress level in transferred GaN was hard to be gotten.
So, we used Raman spectroscopy to examine the biaxial in-plane stress
(compressive stress relief). According to Kozawas relation, we got the
relationship between the biaxial stress and various Au bonding layer
thickness ranging from 7 m to 40 m. The maximum compressive
stress relief in the transferred GaN thin film occurred at the largest
Raman peak position shift of 10 m Au layer (red shift, 1.79 cm
-1
). The
maximum compressive stress relief is about 290 MPa. Besides, we also
tried to explain about the influence coming from bonding Au layer
modified Stonys equation.
The QCSE induced by internal piezoelectric field was known as a
big limitation for high internal quantum efficiency development. So
53
finally, the lighting intensity with different biaxial in-plane stress was
measured, and we proved that we can avoid QCSE efficiently by
relieving the compressive stress. And the order of compressive stress
relief can be controlled by changing the process parameters in thin-GaN
LED fabrication. It is very important and novel finding! The
non-linear parabolic relation of the QW band gap with the stress level
was also mentioned by ) ( 84 . 1 8 . 0 56 . 2
2
eV Eg + .
The thin-GaN fabrication by Au-Si wafer bonding system with
various bonding conditions is a promising technique that has several
advantages, including the high stability process, eliminates QCSE by
controllable process and improving the lighting performance. It could
be potentially used for the high-brightness white nitride-based lighting
LEDs in the future.


















54
Appendixes
There are three parts in appendixes. All of them are branches of
my Ph. D researches and they are very interesting and important. First
is the study of the effect of Cu content on interfacial reactions between
Sn(Cu) alloys and Ni/Ti thin film metallization. Second is the study of
fabricating low-loss hollow optical waveguides via amorphous silicon
bonding using dilute KOH solvent. The third study is the novel
asymmetric UBM structure applying to micro-level alignment accuracy.
The details are listed as below.

Appendix A. Effect of Cu Content on Interfacial Reactions
between Sn(Cu) Alloys and Ni/Ti Thin Film Metallization
In the advanced IC (Integrated Circuits) packaging, the thin-film
metallization is commonly used as UBM (Under Bump Metallization) on
the chip side to bond small C4 solders balls. [40] Yet, the fast
consumption of the limited metal thin layer due to the reaction with
Sn-bearing solders is always a concern for the reliability of solder joints.
[41-43] Tri-layer Cu/Ni(V)/Al UBM has successfully used as flip-chip
UBM for many years. No spalling was observed after 40 minutes
reflowing, when it reacted with the eutectic SnPb solder. [44] However,
when the eutectic SnPb solder was replaced with Sn-rich Pb-free solders,
spalling in tri-layer Cu/Ni(V)/Al UBM was found after several reflows.
[45] Therefore, it is a challenging task to develop a thin film UBM
without spalling for flip-chip Pb-free solder bumps.
55
In previous study by Wang, the spalling of Ni thin film was found to
be prevented if a Cu reservoir was introduced into the structure of C4
(Controlled Collapse Chip Connections) solder joints during the soldering
reaction. [46] The Cu reservoir could be the incorporated Cu particles
inside the solder or the Cu pad in the package side. The major role of
Cu reservoir was a source to provide Cu atoms to form a layer Cu-Sn
compound on Ni thin film, which was believed to be the key for the
prevention of spalling.
Some reports have demonstrated that the small amount of Cu
additives can improve the Pb-free solders mechanical properties, such as,
fatigue, creep, and tensile strength. [47-49] So, it seems inviting us to
understand the role of Cu additives in the interfacial reaction between
Cu-bearing Pb-free solders and Ni thin film metallization. It will also be
interesting to study that will the limited Cu additives in Cu-bearing
Pb-free solders have the same effect as the Cu reservoir. In this study,
nine dilute Sn(Cu) were used to study the effect of the variation of Cu
content on the interfacial reaction between Sn(Cu) alloys and the Ni thin
film.

Experimental Procedures
The Ni/Ti metallization was deposited on an oxidized Si wafer by
E-beam evaporation process. The Ti layer is for the adhesion purpose
and the Ni layer is simulated to the wettable metal bond pad. The
thickness of Ti and Ni are 500 and 2000 , respectively. 99.99 %
56
purity of Sn and Cu purchased from Alfa AESAR Inc. were used to
prepare nine SnCu alloys, which range 0, 0.2, 0.6, 1, 1.4, 1.8, 2.2, 2.6,
and 3.0. To produce accurate composition of SnCu alloys, weight Sn
and Cu in desired weight percentage by a digital balance (SCALTEC
SBC31), then, place them into evacuated and sealed quartz tubes. Heat
quartz tubes to a constant temperature of 900 C in a furnace for 150
hours. During the heat treatment, swirled quartz tubes to evenly mix the
metal elements. After the heat treatment, quartz tubes were quickly
quenched by water cooling. Cut 2 mg of each of nine alloys and melt
them under the flux ambient to produce a spherical solder ball.
The reflowing process steps are in following. Right amount of flux
was poured into a stainless beaker. Put the beaker on a hot plate and
maintain the flux at a constant temperature of 250 C. The Si wafer
coated with Ni/Ti metallization was cut into 2 2 cm square pieces.
Those Si pieces were immersed into the heated flux for 30 seconds to
clean the Ni surface. Then, 2 mg solder balls were placed on the top of
Si pieces. As solder ball touched Ni surface, the molten solder started
spreading and reacting with Ni/Ti metallization. Five different reaction
times were carried out for each composition, which are 30 sec, 1 min, 5
min, 10 min, and 20 min.
After certain reflowing time, Si chips were removed from flux and
cooling in the air for one minute, then they were cleaned by alcohol in an
ultrasonic machine. To perform the SEM examination, mount
reflowed-samples by the epoxy resin. First, the epoxy mounted samples
57
were cut by a diamond saw and abraded by coarse sandpapers. Then,
samples were finished by 0.3 m Al
2
O
3
powder polishing. Before SEM
observation, samples were slightly etched by light acid (10% H
2
SO
4
) for
10 seconds to delineate the morphology of the compound layer.

Results
Fig. 1 shows the cross-sectional SEM images of interfacial reactions
between low Cu-content Sn(Cu) alloys and Ni thin film. As seen in Fig.
1(a) and (b), the original Ni thin film could not be observed at the
interface after 30 seconds reflowing. We believe that the Ni thin film
was completely consumed by the formation of the Ni-Sn compound layer
and, then, spalled into the molten solder. It is striking that, as shown in
Fig. 1(c), a layer of interfacial compound was found to reside at the
interface, as Ni thin film reacted with Sn0.6Cu for 30 seconds. It
implied that 0.6 wt% of Cu content could defer the on-set time of spalling
to longer reaction time. Using EDX analysis, the compound layer was
determined to be the Ni
3
Sn
4
compound phase dissolved with Cu. The
Cu in (Ni,Cu)
3
Sn
4
intermetallic compound layer should attribute to the
Cu content in the molten solder. Yet, we found that spalling occurred
after 5 minutes reflowing, as shown in Fig. 1(d). The big separated
Ni-Sn grains on the Ti surface indicated the occurrence of the ripening
process.
As the Cu content in Sn(Cu) alloy increased to 1.0 wt.%, remarkably,
we found that spalling could not be observed even after 20 minutes
58
reflowing! Fig. 2 is the SEM cross-sectional images of interfacial
reaction between Sn1.0Cu and Ni thin film for different reflowing times.
The EDX analysis shows that a scallop-like Cu
6
Sn
5
compound layer
covered the original Ni thin film after 30 seconds reflowing, as seen in
Fig. 2 (a). The substantial portion of the initial Ni thin film remained
un-reacted. With prolonged reflowing, the growth of the interfacial
compound layer was very sluggish. After 20 minute reflowing, EDX
results show that a thin Ni thin film layer still can be observed and
covered by a (Cu, Ni)
6
Sn
5
intermetallic compound layer. Interestingly,
the morphology and size of the scallop-like compound grains show no big
change during the reflowing process, as seen in Fig. 2. It indicates that
ripening did not occur in compound grains.
Fig. 3 is the cross-sectional SEM images of interfaces between
Sn1.8Cu/ Ni thin film for different reflowing times. Spalling did not
occur in the initial 5 minutes reflowing. As the reflowing was
prolonged to 10 minutes, the ripening process occurred and the resultant
big compound grains started departing from the Ti surface, as seen in Fig.
3(c). Fig. 4 is the SEM cross-sectional images of the interfacial reaction
between Sn3.0Cu and Ni thin film. Unlike the scallop-type compound
layer of other Sn(Cu) alloys after 30 seconds reflowing, the morphology
of interfacial layer of Sn3.0Cu is relatively flat. In addition, the primary
Cu
6
Sn
5
compound phase was observed in the solder, as indicated by black
arrows in Fig. 4(a) and 4(b). After one minute reflowing, the primary
Cu
6
Sn
5
compound precipitates inside the solder were greatly reduced.
59
We believe that the primary Cu
6
Sn
5
compound particles in the solder
were quickly expensed by the growth of the compound layer.
Coalescence or ripening between primary Cu-Sn compound particles and
interfacial compound layer were the two possible processes for the
consumption of the primary Cu
6
Sn
5
particles. After 5 minutes reflowing,
big chunk of compound grains were found at the interface and about
departing from the surface of Ti layer, as seen in Fig. 4(c). The average
thickness of compound layer is estimated to be about 4.2 m. In the Fig.
4(d), clearly, we can observe that the chunky Cu
6
Sn
5
compound grains
are floating upward in the solder after 20 minutes of reflowing.
Table one is a summary for the on-set time of spalling versus
different Sn(Cu) alloys. The on-set time of spalling strongly depends on
the Cu concentration in the Sn(Cu) alloys. The initial small amount of
Cu additives deferred the on-set time of spalling to longer reflowing time.
Amazingly, no spalling can be found for the Sn1.0Cu alloy. As Cu
content in the Sn(Cu) alloys are over 1.0 wt%, the spalling backed to
occur. Note that in region of high Cu-content alloys, the more Cu
additives, the earlier spalling occurred.

Discussions
(1) Review of spalling phenomenon
The typical picture of the spalling process in the Cu thin film is
illustrated in Fig. 5. First, the Cu thin film was completely converted to
a scallop-appearing compound layer after a short soldering reaction, as
60
shown in Fig. 5(a). Then, the ripening process occurred among
scallop-like compound grains; the bigger scallop-like compound grains
grew at the expense of smaller scallop-like compound grains. [2] Due to
the mass conservation, the incremental of the bigger grain in radius, dr
1
,
was smaller than the decrease of smaller compound grain in radius, dr
2
.
Thus, a small portion of the Ti surface was exposed to the molten solder,
as shown in Fig. 5(b). As a result, unstable triple junctions of three
interfacial energies, i.e., ?
Ti/Solder
, ?
Ti/compound
, and ?
Solder/compound
, occurred as
indicated by three arrows in Fig. 5(c). The unbalanced interfacial
energies at the triple junctions led to the shape transformation from
semi-spherical grains to spherical grains, as seen in the dash circle in Fig.
5(c). The spherical compound grains had very little contact with the Ti
surface, so, they tend to float into the molten solder due to the gravity
effect. The resultant high interfacial energy between the Ti surface and
the molten solder caused the dewetting of the molten solder on the Ti
surface, as shown in Fig. 5(d).
From the review above, we recognize that the ripening process,
which caused the exposure of the Ti surface to the molten solder, is the
key step for the occurrence of spalling. In the present study, we found
that the Cu additives in Sn could defer or prevent the spalling of the Ni
thin film during the soldering reaction. So, we believe that the Cu
additives in solders should have a strong influence on the repining
process in the interfacial compound layer. In the following, we will first
discuss the influence of Cu additives on the interfacial reaction between
61
Sn(Cu) alloys and Ni thin film and, then, lead to the possible mechanism
of the spalling deferring.
(2) Formation of interfacial compounds on Ni thin film
SEM cross-sectional results have shown that a layer of Cu-Sn
compound formed on the Ni thin film, as the Ni thin film reacted with
Sn(Cu) alloys having Cu content over 0.6 wt.%. A similar finding on
the bulk Ni substrate was reported by Kao. [50,51] It is plausible that Kao
explained this finding well by using the diffusion paths in the Sn-Cu-Ni
isotherm. Here, we found that it also can be interpreted by the concept
of the Cu solubility limit in Sn. Fig.6 is the enlarged Sn corner of the
Sn-Cu-Ni ternary phase diagram calculated by Zeng et al. [52,53].
According to this diagram, the solubility limit of Cu in Sn is estimated to
be about 1.1 wt%, which is close to the experimental value, 1.5 wt%,
reported from Steen. [54] The slight discrepancy between experimental
and calculation values could be due to the difference in temperature. It
is of interesting that with little additional Ni in Sn, as indicated by a black
dot in Fig. 6, the Cu solubility limit is greatly reduced to about 0.6 wt%.
In the very early stage of the soldering reaction, Ni would dissolve
into the local region of the molten solder near the interface of Ni thin film
before the formation of the Ni-Sn compound. As pointed out earlier, the
presence of little Ni dissolution in the liquid Sn would cause the reduction
of the Cu solubility limit to be around 0.6 wt.% at 250 C. Therefore,
for Sn(Cu) alloys having the Cu content over 0.6 wt.%, the Cu
concentration near the Ni surface became over-saturated. The access Cu
62
would instantaneously precipitate out as a Cu-Sn compound layer on the
Ni interface to meet the Cu solubility limit under the presence of Ni.
Consequently, an instant Cu concentration difference would be
established between the Ni interface and the bulk of molten Sn(Cu) alloys
and generate a Cu flux from solder to Ni interface. As long as sufficient
Ni dissolution could be maintained near the interface of the Ni side, the
Cu atomic flux would exist and the Cu-Sn compound layer would grow.
Yet, during the formation of Cu-Sn compound layer on Ni side, the Ni
dissolution could be incorporated into the formation of the Cu-Sn
compound and formed a Cu-Ni-Sn ternary compound. The decreasing
Ni dissolution at the Ni surface could diminish the Cu atomic flux toward
the Ni interface. The Cu flux would resume, if the Ni dissolution could
be replenished by the diffusion of Ni through the Cu-Sn compound layer
from Ni thin film. So, we believe that Cu flux from solder to Ni
interface could likely to be an on-and-off process rather than a continuous
process. It really depended on the Ni diffusion rate in the Cu-Sn
compound and the thickness of Cu-Sn compound on the Ni side.
Fig. 7 is a plot of thickness of interfacial compound layers versus the
square root of reflowing time for Sn(Cu) alloys with Cu content over 0.6
wt%. Two growth stages are observed. In the first minute reflowing,
the compound growth rate did not show much difference for all alloys.
To interpret it, first, we realize that for Sn(Cu)alloys having Cu content
over the Cu solubility limit in Sn at 250 C, the primary Cu
6
Sn
5
solid
phase will coexist with the Cu-saturated liquid Sn(Cu) alloy at 250 C.
63
The ratio between the liquid and solid phases depends on the composition.
So, during the early soldering reactions at 250 C, the interfacial reactions
mainly occurred between the Cu-saturated Sn(Cu) liquid and Ni thin film.
Therefore, a similar reaction behavior could be expected for Sn(Cu)
alloys having Cu content over 10 wt.%. After one minute of reflowing,
beside Sn1.0Cu, the thickness of Cu-Sn compound layers increased
dramatically, because the primary Cu
6
Sn
5
compound particles started
participating the growth of the interfacial Cu-Sn compound layer. It is
worthy of note that an incubation time was needed for the primary Cu
6
Sn
5

compound particles to participate the interfacial compound growth. It is
not understood yet.
Another interesting point is that we found that the compound growth
of Sn1.0Cu was very slow in the late reflowing stage. The sluggish
Cu-Sn compound formation could be because that no primary Cu-Sn
would exist in the molten solder of Sn1.0Cu during the soldering reaction.
After one minute reflowing, 1.1 m Cu-Sn compound layer consumed
about 0.3 wt.% 0.4 wt.% of Cu content in the molten solder. The Cu
content in the liquid solder was reduced to be very close with the Cu
solubility limit under the presence of Ni. Hence, the formation of Cu-Sn
compound on the Ni thin film was very slow in the late stage of
reflowing.
(3) Kinetics of Cu-Sn formation on Ni thin film in the initial
reflowing stage
In Fig. 7, the compound growth showed a linear relation with the
64
square root of reflowing time in the initial reflowing. It implied that the
formation of Cu-Sn compound might be controlled by a diffusion process
in the initial reflowing stage. We realize that the Cu in the Sn(Cu)
alloys was the only source for the formation of the Cu-Sn compound
layer on Ni thin film. Hence, two sequential processes were
indispensable for the formation of Cu-Sn compound layer; they were the
precipitation of Cu-Sn compound on the Ni interface and the
transportation of Cu to the Ni interface by the liquid diffusion.
Assuming the precipitation of Cu-Sn compound on the Ni interface was a
fast and a constant-rate process, the formation of Cu-Sn compound on the
Ni thin film could be limited by the Cu liquid diffusion process in the
molten solder.
The initial Cu flux from the molten solder toward the Ni interface
can be simply obtained by calculating the growth rate of the Cu-Sn
compound layer on the Ni interface. So, the Cu flux can be expressed as:

J
Cu
= L?f
Cu
N
0
/ tM
Cu

Where, L is the thickness of compound layer, ?is the density of
Cu
6
Sn
5
(8.27 g/cm
3
), f
Cu
is the Cu weight fraction in Cu
6
Sn
5
, N
0
is
Avogadro number, t is the reflowing period, and M
Cu
is the molecular
weight of Cu. In the initial growth period, 0.8 micrometers of
compound layer formed in the first minute of reflowing. Plug in the
compound thickness and the reflowing time, the Cu flux for the initial
65
growth period is about 2.4x10
17
atoms/cm
2
s.
Using the quasi-steady-state approximation, the Cu flux can also be
expressed as J=D
dX
dC
. As discussed previously, the Cu concentration
difference, 0.5 wt.% (1.1-0.6 wt.%), established between the molten
solder and the Ni interface was considered to be the driving force for the
Cu flux in the initial reflowing stage. To obtain the concentration
gradient, the distance for the Cu concentration difference should be
determined. Since the exact distance for the Cu concentration difference
is unknown, here, we estimate the average Cu concentration gradient by
dividing the Cu concentration difference with the height of the solder cap,
200 m. Plug in the number of the Cu concentration gradient and Cu
diffusivity in Sn, 10
-5
cm
2
/s [55], into the flux equation, we can obtain the
magnitude of Cu flux from solder to the Ni interface to be about 1.6 x10
17

atoms/cm
2
s, which is very close with the experimental number of Cu
flux calculated previously. So, we believe that the kinetic behavior of
Cu condensing flux in the initial reflowing period could be described by
the Cu solubility difference between the molten solder and the Ni
interface. In the late reflowing period, the primary Cu
6
Sn
5
compound
phase in the solder was involved in the growth of the interfacial
compound layer. Thus, the growth behavior of the interfacial compound
layer in the late stage was very different with that in the initial stage.

(4) Spalling deferring mechanism
We have realized that the ripening process among the compound
66
grains played the key role for the occurrence of spalling. One can
postulate that if the ripening flux of shrinking smaller compound grains
could be compensated by the condensing Cu flux from the molten solder,
Ti surface will not expose to the molten solder. Then, spalling could be
prevented. The ripening flux for semi-spherical Cu
6
Sn
5
compound
grains was equated by Tu [43]:


Where, D is the diffusivity of Cu in the molten solder, O is the molar
volume of Cu
6
Sn
5
, ? is interfacial energy per unit area between Cu
6
Sn
5

and molten solder, C
0
is the equilibrium concentration of Cu in solder, R
is the gas constant, T is the temperature,

is the mean separation


between grains, and r is the mean grain radius.
To evaluate the repining flux in the initial reflowing stage, materials
properties are given as O=117.87 cm
3
/mole, reflowing temperature is 523
K, and R=8.3 Joule/mole K. We take the Cu equilibrium concentration
in Sn about 1.1 wt%. The Cu diffusivity in Sn is 10
-5
cm
2
/s. The mean
grain radius is estimated about 1.5 m after 30 seconds reflowing. Also,
we use the same approximation of the interfacial energy per unit area
between Cu
6
Sn
5
and molten solder and the separation length taken by
Kim. Substitution of all parameters into the ripening equation, the
repining flux of the initial reflowing was obtained to be about 3.8x10
17

atoms/cm
2
s. Strikingly, we found that it is in the same order with the
condensing Cu flux from the molten solder to the Ni interface in the early
LRT
DC
J
3
0
2


67
stage of reflowing. The correspondence between the ripening flux and
the condensing Cu flux sustains our postulation that the ripening flux
could be compensated the Cu flux from solder.
For Sn(Cu) alloys having Cu content less than 0.6 wt.%, no Cu
concentration difference would develop between the molten solder and
the Ni interface. Therefore, the Cu condensing flux was absent or too
mall to compensate the ripening flux among compound grains. As a
result, the ripening process and spalling would occur in the interfacial
compound grains within one minute reflowing. For Sn(Cu) alloys
having Cu content over 1.0 wt%, spalling did not occur in the first minute
of reflowing because the ripening process was hindered by the Cu flux.
So far, we can consistently explain the mechanism of spalling
retarding in the initial reflowing stage. Yet, with longer prolonged
reflowing, the mechanisms for the absence of spalling in the case of
Sn1.0Cu and the occurrence of spalling in the high Cu-content alloys,
such as, Sn1.8Cu, Sn2.2Cu, Sn3.0Cu, are still not very clear to us. Here,
possible interpretations are provided in the following. For the high
Cu-content alloys, Sn1.8Cu, Sn2.2Cu, Sn3.0Cu, the thickness of the
Cu-Sn compound layer increased dramatically after one minute reflowing,
because the primary Cu
6
Sn
5
compound particles in the solder participated
the growth of the interfacial Cu
6
Sn
5
compound layer. When all the
primary Cu
6
Sn
5
compound particles were quickly consumed by growing
the interfacial Cu-Sn compound layer, a quasi-equilibrium state was
maintained between the molten solder and the compound interface. No
68
net Cu flux would exist toward the compound interface. So, the
ripening process would proceed and spalling would occur after one
minute reflowing.
In the case of Sn1.0Cu, since the Cu content is just about the Cu
solubility limit at 250 C, no primary Cu-Sn compound phase co-existed
with the molten solder during the soldering reaction. So, in the late
soldering reaction, the growth of interfacial compound layer was very
sluggish, which only expensed the Cu content in the molten solder.
Owing to the relatively thin Cu-Sn compound layer, Ni could diffuse
through the Cu-Sn compound layer. The constant presence of Ni on the
surface of interfacial (Cu,Ni)
6
Sn
5
compound layer would have strong
effects on the ripening flux among interfacial (Cu,Ni)
6
Sn
5
compound
grains in couple aspects. First, it would persistently induce Cu flux
toward the Ni side, therefore, the ripening process among interfacial
(Cu,Ni)
6
Sn
5
compound grains would be retarded constantly. Secondly,
the Ni on the surface of interfacial compound grains would block the
dissolution of Cu into the molten solder, since Ni has a much lower
dissolution rate than Cu has in the solders. Hence, the ripening flux
among the interfacial (Cu,Ni)
6
Sn
5
compound grains would be diminished.
Coupling the two effects above, we believe that the constant exist of Ni
on the surface of the interfacial compound layer is the key for the absence
of spalling.

Summary
69
We have found that the Cu additives in Sn can defer or prevent the
occurrence of spalling in Ni thin film during the reflowing process. For
the Cu content in Sn(Cu) alloys below 0.6 wt%, the spalling quickly
occurred after 30 seconds of reflowing. Spalling was not observed in
Sn0.1Cu after 20 minutes of reflowing. The mechanism of spalling
prevention is proposed. The presence of Ni at the interface caused the
reduction of Cu solubility near the Ni interface. The reduction of Cu
solubility resulted a Cu concentration gradient between solder and Ni
interface, which induced a condensing Cu flux from solder to the Ni thin
layer. The condensing Cu flux was calculated to be in the same order
with the ripening flux from smaller compound grains to larger compound
grains. We tend to conclude that the condensing Cu flux compensated
the ripening flux, therefore ripening process in compound grains was
hindered. Then, spalling was deferred or prevented.
For the high Cu-content Sn(Cu) alloys, a large Cu condensing flux
from solder to Ni interface prevented spalling in the compound layer at
the initial one minute of reflowing. The condensing Cu flux was due to
the ripening process between Cu-Sn compound precipitates and the
interfacial Cu-Sn compound layer. After one minute reflowing, the
Cu-Sn particles in solder quickly consumed. The ripening process
proceeded in the compound grains at the interface, then spalling backed
to occur.



70

















Figure 1
Figure 2

(c)
Sn0.6Cu
Si
30 seconds reflowing
Sn0.6Cu
Si
(d)
5 minute reflowing
(a)
Sn
Si
(b)
Sn0.2Cu
Si
30 seconds reflowing 30 seconds reflowing
10 gm
(Ni,Cu)
3
Sn
4

(Ni,Cu)
3
Sn
4

10 gm
(b)
Sn1.0Cu
Si
Sn1.0Cu
Si 10 gm
(a)
(c)
Sn1.0Cu
Si
(d)
Sn1.0Cu
Si
30 seconds reflowing
10 minutes reflowing
20 minutes reflowing
1 minutes reflowing
(Cu,Ni)
6
Sn
5

10 gm 10 gm
71
Figure 3
Figure 4
1 minutes reflowing
Sn3.0Cu
Si
(a)
Sn3.0Cu
Si
(c)
10 gm
Sn3
S
(
Sn3.0Cu
(d)
10 gm
30 seconds reflowing
10 minutes reflowing 20 minutes reflowing
Primary Cu
6
Sn
5
phase


Primary Cu
6
Sn
5
phase


10 gm 10 gm
Spalling Cu
6
Sn
5

Spalling Cu
6
Sn
5


1 minutes reflowing
Sn1.0Cu
Si
10 gm
Sn1.8Cu
(a)
Si
Sn1.8Cu
(a)
Si
10 gm
10 minutes reflowing
30 seconds reflowing
(c)
Sn1.8Cu
Sn1.8Cu
10 gm
10 gm
10 gm
Si
Si
Sn1.8Cu
(b)
(d)
(Cu,Ni)
6
Sn
5

1 minutes reflowing
20 minutes reflowing
72




























Figure 5



J, Ripening flux
?X
(a)
metal film
Compound layer
solder
Ti layer
(d)
solder
(c)
?
Ti/Solder

?
Solder/compound

?
Ti/compound

(b)
Ti layer
Ti layer
Floating compound
grains
73



















Figure 7


0
1
2
3
4
5
0 5 10 15 20 25 30 35
Square root of reflowing time (s
1/2
)
T
h
i
c
k
n
e
s
s

o
f

i
n
t
e
r
f
a
c
i
a
l

c
o
m
p
o
u
n
d

(

)
Ni Cu
1.1 wt.%
Figure 6
0.6 wt.%
Sn1.0Cu
Sn1.8Cu
Sn2.6Cu
Sn3.0Cu
74








Table 1 spalling on-set time for different Sn(Cu) alloys














Sn Sn0.2Cu Sn0.6Cu Sn1.0Cu Sn1.4Cu Sn1.8Cu Sn2.2Cu Sn3.0Cu
30sec
1min V V
5min V V V
10min V V V V V V
20min V V V V V V V
75
Appendix B. Fabricating Low-loss Hollow Optical Waveguides
via Amorphous Silicon Bonding Using Dilute KOH Solvent

Introduction
Wafer bonding techniques become increasingly important in the
packaging and assembly of sophisticated micro-electro-mechanical-system
(MEMS). Various bonding methods have been reported, for example:
clamped fusion bonding, direct-bonded fusion bonding, local fusion
bonding, anodic bonding and ultrahigh-vacuum bonding [56-60]. Because
of the flexibility and compatibility of the bonding methods, there is a
growing interest in the wafer direct bonding using adhesive. Recently, we
have demonstrated a semiconductor hollow waveguide formed by
omni-directional reflector (SHOW-ODR) [61]. However, owing to the
rough surface of the amorphous silicon deposited by chemical vapor
deposition, the conventional direct bonding technique can not be applied.
In Ref. 61, the amorphous silicon thin films in the SHOW-ODR were
bonded by epoxy. Although, there was a 1-m air gap between the
bonded wafers, the characterization results of the SHOW-ODR show that
low propagation loss of 1.7dB/cm has been demonstrated for the TE and
TM modes. This value approached that for practical integrated-optic
applications where the maximum propagation loss of 1 dB/cm is required.
Low polarization dependent loss which is below 0.1 dB also shows that
the SHOW-ODR can be used to fabricate the polarization-independent
components. However, in Ref. 61, the air-gap between the bonded wafers
76
may induce a significant propagation loss. To reduce the gap between the
bonded wafers, in this study, we propose a novel wafer bonding
technique using diluted KOH (DKOH). We also use this technique to
demonstrate the SHOW-ODR. This method is suitable to be applied for
the wafer bonding process where low-temperature treatment is required.

Sample preparation
The concept and the design of SHOW-ODR have been reported
elsewhere [61]. Figure 1 shows the mode pattern simulated by
finite-difference time-domain method where the refractive index of Si
and SiO
2
was 3.48 and 1.48, respectively. The thickness of each layer is
designed to be quarter wavelength at 1.55 m. The photonic bandgap of
the omni-directional reflector is calculated to be between 1190-1720 nm.
It indicates that the SHOW-ODR can be used for a large bandwidth. We
can also observe that the light can be confined in the air core. To fabricate
the samples, some straight trenches were defined and etched by
photolithographic process and inductive coupled plasma (ICP) on a (100)
Si-wafer. The width of the trenches was varied from 3.5 m to 9 m for
different waveguide designs. The depth of the trenches was 2.0 m. After
fabricating trenches on Si wafer, plasma enhanced chemical vapor
deposition (PECVD) technology was used to deposit six-pair of Si/SiO
2
multilayers on the (100) Si-wafer. The thickness of Si and SiO
2
is 0.111
and 0.258 m, respectively. There, the wafers were cleaned in standard
Radio Corporation of America (RCA) process for 15 min at 70
o
C. After
77
rinsing with de-ionized (DI) water, the wafers were dried by baking at
100
o
C for 5 min. Diluted KOH (2%) liquid layer applied on both
trenched ODR Si and flat ODR Si wafers. Here, note that the top of ODR
Si wafer sample is PECVD grown amorphous Si. Then, two ODR Si
Wafers were pre-bonded together by using a wafer bonder (EVG, 501).
The bonding pressure is 0.5 MPa and the bonding temperature and time
are 10 minutes, respectively. The pre-bonded wafers were annealed at
200
o
C for two hours. To examine the bonding interface between two
wafers, the sample was polished mechanically on the edge of the sample.
Figure 2(a) shows the SEM cross-section image on a SHOW-ODR. The
detail bonding interface was shown in figure 2(b). The bonding thickness
is measured to be about 0.38 m, which is much smaller than the bonding
interface using epoxy.

Result and Discussion
As seen in the SEM cross-sectional image of the SHOW-ODR in
figure 2(a), an air core was surrounded by omni-directional reflectors,
which contain six Si/SiO
2
pairs. Hence, light can be confined in the air
core. To characterize the SHOW-ODR, a broadband light source with a
bandwidth from 1520 to 1620nm was directly coupled into the
SHOW-ODR using a standard single-mode fiber. The far-field image of
the output mode profile was shown in figure 3. The result indicates that
the light is well confined in the SHOW-ODR.
The reaction of KOH solutions with the silicon surface had been
78
studied greatly [62,63]. As the hydroxyl ions, OH
-
, contacts with Si
surface, the oxidation of the silicon starts to occur.
Si + 2OH
-
? SiO
2
(OH)
2
2-
+ 4e
-
(1)
Four electrons from each oxidized Si-atom are injected into the
conduction band of the silicon. Attracted by the negatively charged
complex silicon, SiO
2
(OH)
2
2-
, the electrons remain near the Si wafer. In
combination with the SiO
2
(OH)
2
2-
ions, they build up an electrolytic
dipole layer. Finally, the electrons react with water
4e
-
+ 4H
2
O? 4(OH)
-
+ 2H
2
(2)
Thus, the overall KOH etching scheme
Si + 2OH
-
+ 2H
2
O? SiO
2
(OH)
2
2-
+ 2H
2
(3)
We use the external pressure and heating to remove water and H
2

between the two wafers. After the treatment of the external pressure and
the heating, we consider the soluble complex SiO
2
(OH)
2
2-
is
resolidifications. A bonding layer was found between the two six-pair
Si/SiO
2
multilayer. The strength of bonding is strong enough to stand for
the stress due to the mechanical polishing of the edge of the
SHOW-ODR.
To achieve successful wafer bonding, three major parameters should
be considered: KOH concentration, reaction time, and external pressure.
According our experience, KOH concentration and the pressure should be
larger than 2% and 0.5Mpa, respectively. And the proper bonding time is
about 10 minutes. From the literatures, dilute HF solution has been used
to the bond amorphous silicon [64]. The annealing temperature and time
79
is around 450
o
C and 24hours, respectively. Additionally, As
+
-ion
implantation is also required in the method. In our study, the pre-bonding
temperature (70
o
C) and the thermal treatment (200
o
C) are much less than
the bonding temperature by dilute HF solution. The present fabrication
process with low temperature shows better advantages over existed wafer
bonding process.

Conclusion
We have successfully demonstrated a novel fabrication process for
SHOW-ODR by directly bonding two amorphous silicon layers with
DKOH solution. The result shows that the input light was strongly
confined inside the air core. The bonding and heat treatment temperature
of this process is below 200
o
C, which enables any integrated-optics
requiring a low-temperature process. Besides, fabrication of the air-core
of the SHOW-ODR can also be applied in the process of the micro fluidic
channel for the biological applications.








80











Figure 1 Mode pattern simulated by finite-difference time-domain
method where the refractive index of Si and SiO
2
was 3.48 and 1.48,
respectively.





Si
OD
OD
Si
Air core
81






(a)






(b)
Figure 2(a) SEM images of the cross-section of the bonding interface of
the SHOW-ODR. An air core was surrounded by omni-directional
reflectors which were formed by six Si/SiO
2
pairs on Si-wafer, applied
pressure 0.6 Mpa. (b) Cross-section image of bonded interface taken by
SEM, applied pressure 0.5 Mpa.

air
Si substrate
Si
Bonding
Si/SiO
2

Si/SiO
2
ODR
Si/SiO
2
ODR
Bonding layer
Si
Si
82










Figure 3 Far-field image of the output optical field of the SHOW-ODR.
The optical field dimension is about 5 m 2.5 m.









Full image
5m
2.5m
83
Appendix C. The Novel Asymmetric UBM Structure Applying
to Micro-level Alignment Accuracy

Introduction
In the advanced micro-optical system, micro-electromechanical
system (MEMS), and optoelectronics, often, chips need to be assembled
together. How to achieve an accurate alignment among these chips is
the most critical issue for a successful system. Now, active alignment
method and passive alignment method are usually mentioned. The
active alignment method is usually using pick and place machine and
the epoxy-type polymers are the major bonding agents. The alignment
accuracy can be accomplished as good as around several micrometers.
However, this so-called active alignment method is very time-consuming
and high cost. On the other hand, passive alignment method is widely
used by solder self-alignment ability due to lower the surface energy
between molten solder and under bump metallization (UBM). The most
advantage is its simple process and can reach a robust assembly process,
simultaneously. But there are also some hardly-controlled problems on
current passive alignment method. In this work, we propose a novel
assembly process, which utilizes solder self-alignment and asymmetric
UBM structure to achieve a robust assembly process. Finally, getting
more highly accurate alignment is assisted by mechanical stop even for
multi-chips systems.
Replacing the use of high-accuracy pick and place machine, the
84
fine alignment is obtained easily just during the solder reflow process, if
we use the solder self-alignment technology. Now that flip-chip
technology is widely used in IC packaging. Self-alignment is the key
feature for flip-chip assembly, which results from the minimization of the
surface tension of molten solder bumps. Fig. 1 depicted the process of
self-alignment of flip-chip joint. Firstly, the top solder bump is not in
the center position of the bottom bond pad. As the top solder bump
melts, the molten solder will spontaneously wet on the surface of metal
bond pad. Nevertheless, this wetting process simultaneously create
more surface area of molten solder, as the triple line of the spreading
molten solder is advantage. To lower the total surface energy, the top Si
chip should move along with the triple line to the center position of the
bottom bond pad. This phenomenon leads to the equilibrium state
depicted by Youngs equation (1), and forms a spherical liquid cap on the
solid, as shown in Fig. 2. The wetting angle, ?, is determined by three
interfacial tension, ?
vl
, ?
ls
, ?
sv
.

( )
vl sv ls
/ cos
(1)

Where ? is the interfacial tension and the subscript L, V, and S
indicate the liquid, ambiance, and solid, respectively. Youngs equation
can describe the relationship of surface tension among different interface
elegantly. Many researches are investigated the wetting behavior when
different solders wet onto different UBM. And those results will be the
85
important references for us to choose appropriate solder.
The minimization of the total surface energy is the key point for
self-alignment. The asymmetric joint scheme is due to different widths
of metallization lines, which are patterned on both chips by using lift-off
process. This novel structure can supply a continuous pulling force,
moreover, another inverse pulling force or mechanical stop at another
side. This continuous pulling force can avoid the original vibration of
molten solder and get better alignment accuracy.

Experimental Procedures
First, we will fabricate mechanical stops on Si chip. Defining the
L shape pattern by photolithography technology, and then send into
ICP ] Inductive Coupled Plasma ^ for dry etching the cubic Si pillar.
Fig. 3 shows the schematic of asymmetric structure. The size of the
top metal pad and bottom metal are 300 m and 600 m, respectively.
They were fabricated by photolithography process. The chip are about
1cm 1cm. The Ti/Ni/Au metal bond pads are produced by the
electron-beam evaporation and lift-off process. The thickness of Ti, Ni
and Au is 500 , 2000 and 1000 , respectively. Then, we did the
solder bumping by manual process. First, we cut 0.2 mg SnPb solder
pieces and reflow them at a flux ambient to produce 600 m diameter
solder balls. The solder balls were placed on the pre-fluxed small metal
bond pads, then reflowed chip at 250 for 1 minute. The sold J er will
from a hemispherical shape by tend to minimize the surface energy. To
86
assembly two chips, we used edge-to-edge to roughly align two chips in
position. Then, send these two contact chips into the reflow oven to
perform metallic bonding process at 250 . Fig J . 3 and Fig. 4 are side
view and top view of as-bonded sample, respectively. SEM image and
OM images are shown in Fig. 6 ~ Fig. 8.

Results and Discussions
First, we performed a simple test to check the self-alignment ability
of the symmetric UBM structure. Theoretically, the two opposite metal
bond pads should perfectly align to each other due to the minimization of
surface energy. Yet, in Fig. 4, we found that 10 m mis-alignment
occurred in our SEM cross-section observation, which is about 3.3%
inaccuracy. During the reflowing process, we noticed that ting vibration
in the top Si chip can be detected. As the temperature cooled down
below the melting point of SnPb solder, 183 , the Si chip has a finite J
chance to have misalignment position with the bottom Si chip. So, we
believe that the misalignment was mainly caused by the vibration of the
molten solder bumps. It is very hard to be overcome.
Fig. 5 illustrates how the asymmetric structure works during bonding
process. Fig. 5(a) shows the un-bonded state. When the two chips
were placed into contact by rough edge-to-edge, the tip of solder bump
would contact the edge portion of the large bottom bond pad. As the
temperature increased to 250 , J the solder ball melts and wets on the
bottom large bond pad, as shown in Fig. 5(b). As we know, to lower the
87
total energy of the system, the total surface area of the molten solder
bump should keep in a minimum magnitude. Therefore, if there are no
mechanical stops in our structure, the small top bond pad should be
positioned to the center of the large bottom bond pad. Fig. 5(c) shows
the final force balance by three competitive surface tensions, ?
VL
, ?
LS
, ?
SV
,
respectively. By further analyzing, ?
VL
and ?
LS
are the surface tensions
coming from the tendency that the molten solder ball want to reduce its
surface area. ?
SV
is the force that pulling molten solder expansively by
its wet ability onto UBM. The results of three forces competing, two
chips will closer and upper chip will move to the right in the center of
bottom chip, as shown in Fig. 5(d), i.e. lose the function of vibration
avoiding. If we can give the corresponding pulling force at the other
side simultaneously in order to maintain the asymmetric solder structure,
either using another asymmetric structure or mechanical stop, like Fig. 3.
This restore force, which is responsible for final alignment, will make the
submicron alignment possible.
With mechanical stops, the asymmetrical surface tension will exert a
force to bring the top stop to intimately contact with the bottom stop.
The created force was the key to achieve the fine alignment. Then, the
alignment position of two chips can be maintained thought out the entire
cooling process. These experimental results are shown in Figure 6 and 7.
The ultimate alignment of two chips is determined by pulling forces
against lithographically located mechanical stops. We can find the
relative position of mechanical stops. Hence, the final alignment will
88
not be affected by the joint process. Another advantage of this
asymmetrical structure is that we can accomplish two dimensional
alignment accuracy by creating two L-shape mechanical stops on the two
assembling chips. But it should be very careful that the addition of
frictions accompany with enlarge the contact area between mechanical
stops and UBM interface.
Here we replace the common used mechanical stop type, combining
fiber and V-groove structure, by L-shape structures. Besides omit the
complex processes, and use widely for other alternative substrates.
Because of specific orientation, Si substrate can easily be etched the
V-groove structure. But for more and more micro-optical systems, or
optical-electronics, Si is no longer the best choice. Several III-V
semiconductors, piezoelectric materials, and glass-like materials can not
create the V-groove like Si. So, dry or wet etching process onto these
varieties for building perpendicular walls seems all-purpose. By the
way, some optoelectronic or micro-optics systems are bonded containing
multiple chips. The asymmetrical solder joint can provide a robust and
low-cost assembly process with high accurate self-alignment at one time.
In the case of IC packaging, flux is required for the solder reflowing
process to assure the occurrence of self-alignment and a good quality of
solder joints. However, for the packaging of optoelectronic devices,
fluxing will cause massive flux residue and deteriorate the function of
devices. So, developing a fluxless process is also an important
technology for optoelectronic packaging. In order to avoid using flux,
89
two major methods are chosen. One is trying to use AuSn solder, and
the other is changing the atmosphere. Here, we try an alternative
atmosphere, such as N
2
, Vacuum, or forming gas to eliminate the
oxidation on the surface of molten solder. Moreover, Different solders
or UBMs will lead to different magnitudes of surface tension. So, a
suitable wettable metallization also is a prerequisite for a good wettability.
How to get the basic datum of relationship of wetting behavior between
various solders and UBMs is a very fascinating research in the future.

Conclusions
IBM first introduced the C4 (controlled collapse chip connection)
technology about four decades ago, which involves fabricating a fusible
bump on the IC pads and placing the chips in an inverted position on
matching bonding pads of the substrate and reflowing the solder. Now,
we use the similar method to proceed to our experiments and not only for
IC packaging, but also applied to optoelectronics, MEMS, and
micro-optical system, which need higher aligned requirement. From
several decades ago to now, as we seen, the basic concept has not
changed at all.
In this work, we demonstrate the ability to reach ultrahigh 3-D
alignment precision by novel asymmetric UBM structure. By way of
this novel structure, all the modern packaging materials bonding
including the flip-chip technology can be accomplished perfectly.

90








Fig. 1







(a) (b) (c)
Fig. 2









c ^
sv
^
ls
^
vl Ambiance
Liquid
Solid
91




Fig. 3















Fig. 4








Y
X
92





(a) (b) (c) (d)
Fig. 5 (a~d)








Fig. 6




10 m
35 m
10 m
35 m
93






Fig. 7









Fig. 8



94
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64. Q. Y. Tong, Q. Gan, G. Hudson, G. Fountain, P. Enquist, R. Scholz
and U. Gosele, Appl. Phys. Lett., vol. 83, 4767 (2003).






99
Vita

1. Education
National Central University, Jhongli City, Taiwan (R. O. C.)
B.S., Chemical Engineering, June 1999

National Central University, Jhongli City, Taiwan (R. O. C.)
Master, Chemical and Materials Engineering, June 2002
Thesis GSolid-Liquid Equilibrium of Binary Pairs and Ternary
Mixture of m-Chlorophenol, p-Chlorophenol and tert-Butanol.

National Central University, Jhongli City, Taiwan (R. O. C.)
Ph. D., Chemical and Materials Engineering, June 2007
Thesis GStudy of Au-Si Wafer Bonding for Thin-GaN Light
Emitting Diodes Fabrication

2. Skills and Interests
Proficient with semiconductor processing techniques including
microlithography, materials deposition, dry etching and wet etching,
etc.
Proficient with wafer bonding of homogenous or heterogeneous
materials including anodic bonding, metal bonding, eutectic bonding
and fusion bonding.
Proficient with soldering technologies including Pd-free solder
100
development and interaction study.
Proficient with LED devices technology including chip processing and
the following measurement of electrical and optical characterization.

3. Publications
S. C. Hsu, S. J. Wang, and C. Y. Liu, Effect of Cu Content on
Interfacial Reactions between Sn(Cu) Alloys and Ni/Ti Thin-Film
Metallization, J. Electronic materials, vol. 32, 1214-1221, (2003).
S. S. Lo, H. K. Chiua, C. C. Chena, S. C. Hsu, and C Y Liu,
Fabricating low-loss hollow optical waveguides via amorphous
silicon bonding using dilute KOH solvent, Photonics Technology
Letters,vol.17 (12), 2592-2594 (2005).
T. M. Her, L. S. Lee, S. C. Hsu, Solid-liquid equilibria of mixtures
containing tert-butanol, m-chlorophenol, and p-chlorophenol and
development of adductive crystallization processes, Fluid Phase
Equilibria, vol. 237, 152-161, (2005).
M. Her, L. S. Lee, S. C. Hsu, Using Aniline as an Adductive Agent
for Separartion of an m-Chlorophenol + p-Chlorophenol Mixture, J.
Chin. Inst. Chem. Engrs., Vol. 36, No. 2, 285-297, (2005).
S. S. Lo, C. C. Chen, S. C. Hsu, and C. Y. Liu, "Fabricating a hollow
optical waveguide for optical communication applications" IEEE
Journal of Microelectromechanical Systems, Vol. 15, No. 3, 584-587,
(2006).
S. C. Hsu, C. Y. Liu, Fabrication of thin-GaN LED structures by
101
Au-Si wafer bonding, Electrochemical and Solid-State Letters, Vol. 9,
No. 5, pp. G171-G173, (2006).
Chien-Chieh Lee, Chih-Ming Wang, S. K. Huang, J. Y. Chang,
Gou-Chung Chi, S. C. Hsu, and C. Y. Liu, Fabrication and tolerance
reduction of a Si-based pickup module for optical storage, Opt. Eng.
Vol. 45, 074601 (Jul. 2006).
S. C. Hsu, B. J. Pong, W. H. Lee, C. Y. Liu, Thomas E Beechem III,
and Samuel Graham, Stress relaxation of the GaN layer transferring
by Au-Si wafer bonding, pending.
S. C. Hsu, B. J. Pong, W. H. Lee, C. Y. Liu, Thomas E Beechem III,
and Samuel Graham, Stress analysis of transferred thin-GaN light
emitting diode by Au-Si wafer bonding, pending.
S. C. Hsu, B. J. Pong, W. H. Lee, C. Y. Liu, Thomas E Beechem III,
and Samuel Graham, Stress effect on optical properties of transferred
thin-GaN light emitting diode, pending.
\@ N B B A t L ] h ~Z A s - Q
K (Apr. 2005)


4. Conferences
H. T. Chiew, S. C. Hsu, and C. Y. Liu, Effects of Ni and Cu Additive
on Electromigration in Sn Solder Lines, The 133
rd
Annual Meeting
of the Minerals, Metals, and Materials Society, (2004)
S.C. Hsu, S.J. Wang and C.Y. Liu, Metallic wafer and chip bonding
for LED packaging, The 5
th
CLEO/Pacific Rim, (December 15-19,
102
2003), The Grand Hotel, Taipei, Taiwan
S. C. Hsu, C. Y. Liu, Fabrication of thin-GaN LED structure by using
Au-Si wafer bonding, 2005 SPIE, Fifth International Conference on
Solid State Lighting conference in San Diego, USA, (31 Jul ~ 04 Aug,
2005).
S. C. Hsu and C. Y. Liu, Stress Analysis of Transferred Thin-GaN
Light Emitting Diode by Au-Si Wafer Bonding, 2006 Electronic
Materials Conference, Pennsylvania State University, USA, (28 ~ 30
Jun, 2006)


5. Patents

O
MQ W O MQ X oH
MQ-

1 Z TAIWAN I222910
C. Y. Liu
S. C. Hsu
S. J. Wang

92 ~
2
u@
X c
TAIWAN I249452
C. Y. Liu
J. Y. Chang
C. J. Lee
S. C. Hsu
94 ~
3 Solder Composition USA RCA
C. Y. Liu
S. C. Hsu
S. J. Wang
pending
4 oG s y k TAIWAN I248222
C. Y. Liu
S. C. Hsu
94 ~
5 oG s y k TAIWAN I246784
C. Y. Liu
S. C. Hsu
95 ~
103
6 oG s y k TAIWAN I253770
C. Y. Liu
S. C. Hsu
C. L. Lin
Y. S. Lin
95 ~
7
LIGHT EMITTING
DIODE AND
MANUFACTURING
METHOD THEREOF
USA RCA
C. Y. Liu
S. C. Hsu
pending



6. Contact information

Tel G886-3-4227151 # 34228 FFax G886-3-4254974
E-mail Gs1344008@cc.ncu.edu.tw