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A Method Based on Petri Nets and a Matrix Model to Implement Recongurable Logic Controllers
Celso F. Silva, Camilo Quintns, Member, IEEE, Antonio Colmenar, Manuel A. Castro, Fellow, IEEE, and Enrique Mandado, Life Member, IEEE

AbstractThis paper presents a method to implement recongurable logic controllers (RLCs) using a new matrix model to describe Petri nets (PNs). The method obtains the general equations and directly translates them into a hardware description language (HDL) to congure a eld-programmable gate array (FPGA). To achieve a generalized model in a comprehensible way, several PN examples including timers, counters, and hierarchical subnets are described in detail. The working principles and robustness of the method are validated by simulating each example and by their practical implementation in an RLC. Index TermsField-programmable gate arrays (FPGAs), hardware design languages, industrial control, matrix equations, Petri nets (PNs).

I. I NTRODUCTION OGIC controllers have commonly been implemented until now using programmable logic controllers (PLCs), and several methods have been used to describe their behavior. These methods can be based on ladder diagrams [1], Petri nets (PNs) [2], the sequential function chart (SFC) [3], etc. In particular, PNs provide a unied model for both sequential (only one state being active at a time) and concurrent logic controllers (several states can simultaneously be active) [4] including synchronization, shared resources, mutual exclusions, and dispatching. These properties are difcult to handle without using PNs. Useful tutorials describing PN fundamentals are available in [5][7]. Logic controllers based on PNs are usually implemented by means of a program executed in a sequential way using a programmable processor such as a PLC. However, due to the special advantages of PNs relating to the specication of logic controllers, they can be implemented using sequential hardware without using a programmable processor [8]. Fixed-architecture standard off-the-shelf integrated circuits (medium-scale integrated or large-scale integrated) and application-specic integrated circuits have been used until now
Manuscript received January 28, 2009; revised August 16, 2009; accepted November 2, 2009. Date of publication January 8, 2010; date of current version September 10, 2010. C. F. Silva is with the Department of System Engineering and Automation, University of Vigo, 36310 Vigo, Spain (e-mail: csilva@uvigo.es). C. Quintns and E. Mandado are with the Department of Electronic Technology, University of Vigo, 36310 Vigo, Spain. A. Colmenar and M. A. Castro are with the Electrical and Computer Engineering Department, Spanish University for Distance Education (UNED), 28040 Madrid, Spain. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIE.2009.2038946

to carry out the implementation of logic controllers. However, due to the wired nature of these kinds of circuits, complex logic controllers are difcult to implement. The development of congurable digital integrated circuits over the last decade, such as eld-programmable gate arrays (FPGAs) [9], [10], has allowed the introduction of new ways of implementing logic controllers. Several studies have been carried out to implement logic controllers using FPGAs [1], [2], [11]. These controllers, called recongurable logic controllers (RLCs) [12], are more exible and cheaper than PLCs due to their great logic resource capacity, recongurability, and running speed [13]. However, from a practical point of view, it is worthwhile to note that the design method is the same when implementing an RLC and a PLC [14]. To achieve this, it is necessary to use a unied electronic design automation tool including different description, compilation, debugging, hardware conguration, and testing tasks [15]. During the description stage, a data structure is necessary, following a mathematical model easily joined to the graphic project editor. Then, an algorithm translating the data structure into a hardware description language (HDL) code, for example, very high speed integrated circuit HDL (VHDL) [4], [16], is needed in the case of an RLC. Many efforts have been made to describe logic controllers with an HDL code exploiting the characteristics of some wellknown design methods [17]. In the case of PNs, there are several PN-to-VHDL translators, but they are usually based on the interpretation of a pseudocode or on a rule-based formal language [2], [18]. In addition, these modeling methods do not follow a mathematical notation on which one can work and which may directly be translatable to VHDL. Moreover, the translators based on intermediate languages, which constitute an additional step, complicate the transformation of the system model into a VHDL code. On the contrary, a more universal mathematical model does not add more complexity than that of the represented system [19]. Furthermore, it is easier to generate a mathematical notation from the graphic editor than to generate a pseudocode requiring a greater abstraction level. This paper presents a method to implement logic controllers, described by means of a PN, using a new matrix model in such a way that the requirements are easily carried out by an RLC. Matrix models [5] have mainly been used in the past to optimize the necessary resources [20] or to determine the PN behavior through simulation, implementing it by means

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of a sequential programmable processor [21]. In contrast, the new matrix model is expressly designed to provide a structure dening the PN from which the controller state equations, synthesizable with the FPGA hardware, can directly be obtained. Moreover, any model dening a logic controller must facilitate the utilization of timers and counters. These elements are essential to allow the automation of any industrial process, and therefore, the matrix model is extended to include them. In Section II, the denition, general equations, and structure of the PN matrix model and its implementation as an RLC are described. Section III contains a basic example that is analyzed and simulated to demonstrate the method application. Section IV deals with the aspects needed to be taken into account when timers and counters are included in the requirements, and the previous example is modied to show the necessary theoretical and practical changes. Practical results, conguring an RLC based on a Cyclone FPGA [22] for the different examples, are shown in Section V. In Section VI, the model is enhanced to include subnets, showing how the matrix model is easily extended to achieve the global matrices of the whole system. Finally, conclusions are summarized in Section VII. II. M ETHOD D ESCRIPTION AND I MPLEMENTATION This section presents the general denition of the matrix model elements and shows how a set of logic equations describing the PN behavior is achieved. The method presented in this paper is focused on binary or safe (1-bounded) PNs, with extensions such as inhibitor arcs [5] and without effective conicts. A dispatching subroutine can be used in conict resolution [21]. Alternatively, a xed priority can be used (a xed priority is used in this context because it is simpler [23] and because an effective conict constitutes a bad design). The logic equations specify the evolution between the current and next states without either glitches or extra clock cycles. Then, the method to obtain the VHDL code showing the proposal process organization, in a graphical way, is described. Finally, an example of a platform implementing an RLC is analyzed. A. Denition of the PN Matrix Model To describe logic controller behavior using a PN, it is necessary to establish an interpretation dening the transition ring conditions and the actions to be generated. This kind of PN is called a control-interpreted PN (CIPN) [6], [8] and constitutes a class of nonautonomous PNs in the same way as I/O placetransition PNs [24] and signal-interpreted PNs are used to formally specify control algorithms for PLCs [25], and fuzzy PNs are used as a controller [26]. A CIPN is synchronized, safe, and deterministic [6] and is the kind of PN used in this paper. The actions are associated with places, and the transitions are associated with events (input and output logic functions) and with pulse outputs. The specications with SFC are treated as a special form of CIPN. The terms and denitions that are used by the PN matrix model implementing a logic controller are shown in Table I. The dimensions of the model matrices are shown in Table II.

TABLE I N OTATION D EFINITIONS

TABLE II D IMENSION OF THE D OT-M ATRIX M ODEL

B. General Equations and Structure of the Matrix Model From the PN, the following matrices are obtained. 1) Preincidence T I and postincidence T O matrices TI : m n T O : m n. (1) (2)

A 1 in the ij position of the T I matrix indicates that there is an arc from place j to transition i, and a 1 in the ij position of the T O matrix indicates that there is an arc from transition i to place j. 2) Input map matrix E and output map matrix A E = ( E1 A = ( A1 E2 A2 Eh ) : 1 h Aq ) : 1 q. (3) (4)

3) Transition logic matrix F = ( f1 f2 fm ) : 1 m. (5)

Matrix F is constituted by input, output, and internal conditions associated to transitions.

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4) Current marking matrix CP matrix N P CP = ( cp1 N P = ( np1 cp2 np2

and next marking (6) (7)

cpn ) : 1 n npn ) : 1 n.

A 1 in position i of CP indicates that the pi place is marked. In the same way, a 1 in position i of N P indicates that the pi place will be marked in the next clock event. From the matrices dening the PN, the nal equations are found in accordance with the following sequence. First, the P T matrix is calculated as P T = CP T I t (8)

Fig. 1.

Processes implementing a PN.

where the operator between two matrices A1n and Bnm means that each term c1,j of the resulting matrix C1m corresponds to the AND operation & of the products a1,i & bi,j that are not null (with i being from 1 to n and j being from 1 to m). The P T matrix indicates the places that must have a token to activate a transition. Then, the matrix T specifying the transitions to be activated is calculated T = F & P T = F & CP T I t . After that, the F T I matrix is obtained F T I = F T I. (10) (9)
Fig. 2. Block diagram of the logic controller hardwaresoftware platform.

This matrix is used to obtain the P P staying matrix establishing the conditions to be fullled so that the state of any marked place remains unchanged P P = CP & F T I. Now, the transition evolution matrix T T O is obtained T T O = T T O. (12) (11)

Then, the logic operation OR | between the T T O matrix and the P P matrix is carried out to obtain the next marking matrix N P , taking into account that a certain place may already be marked (P P ) or newly marked (T T O) N P = T T O |P P = (T T O)| CP & (F T I) . (13)

Fig. 1 shows the process organization implementing the PN from the aforementioned equations. The different processes are the following. 1) ConditionsCalc: This is a combinational process (5) calculating the logic conditions that activate the transitions. 2) StateCalc: This is a combinational process (14) calculating the next marked state from the present one and taking into account the logical functions of the transitions, which were calculated in the previous process. 3) StateUpdate: This is a process being synchronized by the clock, where the markings and outputs are updated. The outputs are directly calculated from the N P signals (15) and are memorized at the same time as the CP ones. Although this method of calculating the outputs does not follow traditional solutions, it has the advantages of saving one clock cycle and guaranteeing that all output signals are activated at the same time, thereby preventing intermediate output values because of the delays of the combinational circuit of the logic equation (15). C. RLC Implementation To implement an RLC, a hardwaresoftware platform is needed. In the implementation presented in this paper (Fig. 2), the software includes a PN design tool called HPetriNets [27] and the design tool of the particular FPGA being used in the project. The most important task of the HPetriNets is the translation of a PN into a VHDL description in a transparent way. The hardware is an FPGA-based card and a set of digital and analog I/O cards (Fig. 3). It not only implements the automation task but is also combined with a software tool providing simulation and monitoring capabilities.

The general equation, depending on the initial denitions in Table I, is N P = (F & CP T I ) T O | CP & (F T I) .
t

(14)

Finally, the output equation corresponding to matrix A is given by the next marking and the output activation matrices A = N P XA (15)

where the operator between two matrices A1n and Bnm means that each term c1,j of the resulting matrix C1m corresponds to the OR operation | of the products a1,i & bi,j that are not null.

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TABLE III (Continued.) C P ROGRAM G ENERATING THE VHDL C ODE F ROM THE M ATRIX M ODEL

Fig. 3.

RLC photography including the FPGA (left) and the I/O card (right). TABLE III C P ROGRAM G ENERATING THE VHDL C ODE F ROM THE M ATRIX M ODEL

Using the HPetriNets graphic interface, the PN is dened and translated into the matrix model in accordance with the method previously described. The code generator converts the matrix model into a VHDL description using the data ow modeling and takes into account the hardware constraints. Table III shows an example of a C language program generating the VHDL code. A synthesis using fewer resources can be obtained if a VHDL structural description is used [28], [29], particularly if specic components are designed, instead of directly implementing places and transitions of the PN [30]. However, nowadays, it

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Then, the matrix T (9) specifying the transitions to be activated is calculated T = ( t1 t2 t3 t4 ) = F & P T = F & CP T I t T = ( f1 f2 f3 f4 ) & ( cp1 cp2 cp3 cp4 & cp5 ) T = (f1 & cp1 f2 & cp2 f3 & cp3 f4 & cp4 & cp5 ). After that, the F T I intermediate matrix matrix (11) are obtained 1 0 F T I = F T I = ( f1 f2 f3 f4 ) 0 0 F T I = ( f1 f2 f3 f4 f4 ) (10) and the P P 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1

P P = CP & F T I P P = ( cp1 cp2 cp3 cp4 cp5 ) & ( f1 f2 f3 f4 f4 )

Fig. 4. PN example.

P P = (cp1 & f1 cp2 & f2 cp3 & f3 cp4 & f4 cp5 & f4). Now, the transition evolution matrix (12) is obtained, as shown in the equation at the bottom of the page. Then, the logic operation OR | between the T T O matrix and the P P matrix is carried out to obtain the next marking matrix N P (13) t4 (cp1 & f1 ) t1 (cp2 & f2 ) t N P = T T O | P P N P = t1 (cp3 & f3 ) . t (cp & f ) 2 4 4 t3 (cp5 & f4 ) Therefore, the nal equations to the next marking for the PN example in Fig. 4 are the following: np1 = t4 (cp1 & f1 ) = (f4 & cp4 & cp5 ) (cp1 & f1 ) np2 = t1 (cp2 & f2 ) = (f1 & cp1 ) (cp2 & f2 ) np3 = t1 (cp3 & f3 ) = (f1 & cp1 ) (cp3 & f3 ) np4 = t2 (cp4 & f4 ) = (f2 & cp2 ) (cp4 & f4 ) np5 = t3 (cp5 & f4 ) = (f3 & cp3 ) (cp5 & f4 ). Finally, the output matrix A is given by the next marking and the output activation matrices (15) 0 0 1 1 A = N P XA = ( np1 np2 np3 np4 np5 ) 1 0 0 0 0 1 A = ( A1 A2 ) = ( np2 | np3 np2 | np5 ) .

is not worth making an effort to use component-based models because there is no problem with the number of logic elements (LEs) that are integrated into the FPGA. When developing HPetriNets, it was taken into account that the monitoring and testing of the hardware-congured application is necessary. Therefore, a VHDL le describing a monitor and communication software module is included in the project. This module provides information to the graphic interface about how the implemented controller is working. Fig. 2 shows this module in addition to its connection with the rest of the HPetriNets elements. Using the VHDL PN le and the VHDL monitor le, the FPGA Design Tool creates a project taking into account the device that has been selected. The project is compiled and analyzed, and nally, the hardware is congured. III. I MPLEMENTATION E XAMPLE To demonstrate an actual application of the matrix model method described in Section II, the PN in Fig. 4 is used. The PN representation follows the PN Standard Graphical Notation guidelines [31]. In this example, the number of places is n = 5, the number of transitions is m = 4, and the T I and T O matrices, given by (1) and (2), are, respectively 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 TI = TO = . 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0

T T O = T T O = ( t1

t2

t3

0 0 t4 ) 0 1 f1 & cp1

1 0 0 0

1 0 0 0

0 1 0 0

0 0 1 0

T T O = ( t4

t1

t1

t2

t3 )

T T O = ( f4 & cp4 & cp5

f1 & cp1

f2 & cp2

f3 & cp3 )

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TABLE IV VHDL DATAFLOW D ESCRIPTION OF THE PN IN FIG . 4

Fig. 5. Simulation result using the Altera Quartus II.

Thus, following the diagram in Fig. 2, the code generator, which is carried out by the general algorithm in Table III, provides the specic VHDL description of the PN in Fig. 4 according to the hardware structure in Fig. 1. This VHDL code is shown in Table IV, adding the sE synchronized inputs in the StateUpdate process to minimize the risk of race conditions. These inputs should be evaluated to prevent PN evolution after an RST signal is applied. From (14), this value is obtained F & CP T I t = 0 sE. (16)

its complexity. Moreover, for the same reason, if the input signal speed is similar to the clock one, the net performance is guaranteed because of the correct synchronization of the different VHDL processes with the same clock event. This fact is demonstrated in Fig. 5, showing a particular situation where the conditions to simultaneously activate several transitions are true. When places 3 and 4 are active (cp3 and cp4) and f 3 (E2 & E3) is true, place 5 is activated (cp5). Due to the fact that f 4 (E1) and f 1 (E1) are true, a ring sequence through the whole net occurs (places 1, 2, and 3) until place 5 is activated again. This way, any possible stability problems are avoided. After the rst rising edge of the clock system following a reset deactivation, the sEi synchronization signals in Table IV are not valued Ei signals until a rising edge of the clock, and thus, f i signals are not updated. This is only in the interim between the end of the reset and the rising edge. At this point, it is important to highlight that all of the previous characteristics (a high-speed response to the input variations in only one clock cycle with a correct synchronization avoiding stability problems and output glitches) can be only achieved if an RLC is implemented instead of a PLC. Thus, the advantages of logic controllers based on an FPGA (RLCs) over logic controllers based on a programmable processor (PLCs) are clearly shown. IV. T IMERS AND C OUNTERS Time events, which consist of timers and counters, are essential to allow the automation of any industrial process. Thus, any implementation of a logic controller must facilitate their utilization. To include timers and counters, the matrix model, described in Section II, must be modied, and the matrices that are dened in Table V must be added. To illustrate the implementation using an FPGA, the previous example is modied to include a timer. Similarly, the same example is modied to illustrate what changes must be incorporated to the VHDL code implementing a counter. Timers and counters are not included in the PN general theory, so it must be extended. To achieve this, a model with a control subsystem and a data subsystem including counters and timers is used. It is important to point out that this model is different from the theoretical model of timed PNs [5], [6].

Fig. 5 presents the simulation results using the Altera Quartus II software [32] to implement the PN example in Fig. 4, described in VHDL according to the previously described method. A Cyclone FPGA has been used as a target device for the synthesis. This example uses 14 LEs, which are the minimal resources needed to carry out a synchronous implementation. Despite the fact that this example is not very complex, it demonstrates the correct performance of the model description without output deadlocks, traps, and glitches. Notice that only one clock cycle is needed to evaluate the ring transition conditions, to activate the new places, and to establish the new outputs, even if several places must concurrently be activated, such as places 2 and 3. As just one clock is used, the time spent to update the whole net is constant and independent of

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TABLE V D EFINITION OF THE N EW M ATRICES

Fig. 7.

Processes implementing a PN with timers.

can generate a 1-ms and/or 1-s time base, depending on the time scale implementing the different processes. All timers used in the PN must be triggered in such a way that the controller only uses the essential timers without any subsequent optimization method. This characteristic of the PN constitutes an important difference with the SFC [33]. The basic structure of the PN description in Fig. 1 is extended to that in Fig. 7 using the same methodology but including the processes carrying out the timing generation. The structure in Fig. 1 has an independent process that tests fi signals of the transition ring conditions. These signals are combined with the transition input place states by means of the following equation to generate the pulses that establish the timer initial contain (LD):
Fig. 6. PN example in Fig. 4 including the TM0 timer.

A data subsystem time can be used to specify timing relations between places or transitions in any position and not solely between adjacent ones. In this paper, timers are used in a way similar to that in SFC; however, they must explicitly be triggered by means of the PN transition pulse outputs. In the SFC methodology, every step is associated with an elapsed time variable that can be used within the rest of the chart to monitor step activation [33]. Counters are used in a way similar to that in SFC; however, they must be initialized by means of the PN transition pulse outputs. A. Timers Timers are triggered by means of transition pulse outputs, which are indicated by / characters [34], instead of by special actions associated with places [6]. The PN in Fig. 6 uses the retriggerable TM0 timer with the / TM0 := 5 s pulse. The timing end is checked with TM0, equivalent to TM = 0. Due to the fact that the hardware main clock may have different frequencies, an appropriate frequency divisor value must be included in the hardware constraints before the automatic VHDL code is generated. Using this information, the system

T M _LD = T XT M _LD = (F & P T ) XT M _LD . (17) It must be highlighted that the TimersUpdate process that implements (17) depends on the fi and cpi signals, in the same way that the StateCalc process calculates npi . Regarding the example in Fig. 6, the load condition of the TM0 timer is obtained by substituting (9) and the timer loading matrix XT M _LD in (17). The following timer equation is obtained in this way: T M _LD = ( f1 & cp1 f2 & cp2 f3 & cp3 f4 & cp4 & cp5 ) 0 0 1 0 0 T M _LD = f3 & cp3 . (18)

The transition logic equation matrix (5) is now converted into the following to add the timer output as a new controller input: F = E1 E3 E 2 & E3 E1 & TM0 . (19)

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TABLE VI VHDL D ESCRIPTION OF THE C ONTROLLER I NCLUDING THE TM0 T IMER

Fig. 8. PN example including the CT0 counter.

3) The TimersUpdate process establishes all the timers preselection time (P T ). It includes the vTM# auxiliary variable and a call to the TC_Load procedure with the global signal TM#_LD. Any TC_Load call can modify the vTM# variable, but only the last value is taken into account when it is stored in the TM#_PT preset time signal (# represents 0 in this case). The ConditionsCalc process in Table IV is modied to include the TM# signals generating the transition ring conditions. The StateCalc and StateUpdate processes in Table IV remain unchanged. Each time a new triggering condition for the same timer is included in the PN, a new TC_Load code line is generated. The auxiliary variable vTM# is used to reset the TM#_PT signal (when vTM# is 0) and to make sure that only the last value is taken into account (as the timer is undertaken in a parallel process). With this method, the automatic code generation is simplied, and a possible collision is avoided when several transitions simultaneously try to preset the same timer. This way, the robustness of the result is guaranteed if a bad design is carried out.

B. Counters Table VI contains the VHDL code describing the PN depicted in Fig. 6 according to the block diagram in Fig. 7. This code comprises three new processes, as well as the three included in Table IV (which are slightly modied). 1) The Timer_TM# process, Timer_TM0 in this case, is automatically added to the code when a timer is included in the project. This is a retriggerable timer because it triggers each time the associated transition is red. 2) The DivisorMc process provides the time base clkMcS, which is used for timing generation. The accuracy of the process can be improved using an alternative description [35]. Counters can be included in a PN in a way similar to that of timers, and the method to obtain the VHDL code is also similar. Fig. 8 shows the basic example in Fig. 4 including the CT0 counter. To set the counter value using f 0, a new place and transition are added. In this case, the counter is set to 0 with the pulse action CT0 := 0, it is increased with CT0 := CT0 + 1 and CT0 := CT0 + 2, and its state is checked with CT0 < 4. The fi signals of the transition ring conditions are combined with the transition input place states to be able to generate pulses establishing the initial content of any counter. This way, the block diagram in Fig. 1 is transformed into that in Fig. 9, including the processes and signals implementing the counter.

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TABLE VII VHDL D ESCRIPTION OF THE C ONTROLLER I NCLUDING THE CT0 C OUNTER

Fig. 9. Processes implementing a PN with the CT0 counter.

Table VII contains the VHDL code describing the PN depicted in Fig. 8 according to the block diagram in Fig. 9. This code comprises two new processes, as well as the three included in Table IV (which are slightly modied). 1) The Counter_CT# process, Counter_CT0 in this case, is automatically added to the code when a counter is included in the project. 2) The CountersUpdate process establishes the counters preset value (P V ) and the counters up/down value (U D). The CountersUpdate process includes the vCT# auxiliary variable and a call to the TC_Load procedure with the global signal CT#_LD. Any TC_Load can modify the vCT# variable, but only the last value is taken into account when it is stored in the CT#_PV preset value signal (# represents 0 in this case). It must be highlighted that this process depends on the fi and cpi signals, in accordance with CT _LD = T XCT _LD = (F & P T ) XCT _LD . (20) signal CT#_UD. Any TC_UpDn can modify the vCT# variable that it is stored in the CT#_UDV up/down value signal (# represents 0 in this case). This process depends on the fi and cpi signals, in accordance with CT _U/D = T XCT _U/D = (F & P T )XCT _U/D . (22)

The application of this equation to the example in Fig. 8 is carried out by substituting (9) and the counter loading matrix XCT _LD in (20). This way, the load condition of the CT0 counter given by (21), shown at the bottom of the page, is obtained. The CountersUpdate process also uses the vCT# auxiliary variable and calls to the TC_UpDn procedure with the global

CT _LD = ( f0 & cp0

f1 & cp1

f2 & cp2

f3 & cp3

1 0 0 f4 & cp4 & cp5 ) 0 0 0 (21)

CT _LD = f0 & cp0

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The application of this equation to the example in Fig. 8 is carried out by substituting (9) and the counter up/down updating matrix XCT _U/D in (22). This way, the up/down condition of the CT0 counter given by (23), shown at the bottom of the page, is obtained. Now, the transition logic equation matrix (5) is extended to F = ( E1 E3 E2 & E 3 E1 & [CT0 < 4]) (24)
Fig. 10. Performance test of the PN example in Fig. 6 conguring the FPGA.

to incorporate the logic condition, which depends on the value (an integer) of the counter output CT0. This means that the value of the counter output is handled as an input The ConditionsCal process in Table IV is modied to include the CT# signals generating the transition ring conditions. The StateCalc and StateUpdate processes in Table IV remain unchanged, except for the associate code to the f 0 condition and place 0 (Fig. 8). Each time a new loading condition for the same counter is included in the PN, a new TC_Load code line is generated because, in general, different values must be loaded. The auxiliary variable vCT# is used to reset the CT#_PV signal (when vCT# is 0) and to make sure that only the last value is taken into account (as the counter is undertaken in a parallel process). With this method, the automatic code generation is simplied, and a possible collision is avoided when several transitions simultaneously try to load the same counter. This way, the robustness of the result is guaranteed if a bad design is carried out. The same thing does not happen when increasing/decreasing the counter content, since several simultaneous counting actions may have to be carried out on the same counter from different transitions, as in the example in Fig. 8. Thus, the TC_UpDn procedure, shown in Table VII, accumulates the value, which is passed as a parameter into vCT0. It must be observed that an OR logic function is not suitable to solve this problem, since it is not possible to distinguish between an independent counting and a simultaneous one. Due to this, (23) is separated, and each term of the OR logic function is passed as a parameter to each line generated using the TC_UpDn procedure, as the up/down values are generally different. V. E XPERIMENTAL R ESULTS To validate the simulation results of the logic matrix model and its translation to VHDL code, as described in Section II,

Fig. 11. Performance test of the PN example in Fig. 8 conguring the FPGA.

an actual RLC based on a Cyclone FPGA has been used (Fig. 3). A logic analyzer has been used to test the signals involved in the different examples described before. The practical results depicted in Fig. 10 correspond to the PN in Fig. 6 including the TM0 timer. The system starts to operate after placing the RST signal at 0. When the E1 input signal is placed at 1, the f 1 ring occurs, and places 2 and 3 are activated. Following on, when E3 is valued 1, place 4 is activated, and place 2 is deactivated, which means that places 3 and 4 are active at this moment. When E2 and E3 are worth 1, the TM0 timer is triggered, and the system has to wait for TM0 to end. When starting the transition in the f 3 condition, the ring sequence f 3, f 4, f 1, f 2, f 3 cannot happen. Fig. 11 shows how the CT0 counter in Fig. 8 works. The CT0_UD signal has been connected to the A3 output, only for testing. When this signal is active and several simultaneous res happen, all of the operations over the counter are accumulated. Notice that when the counter value is 3 and f 2 and f 3 are true, the counter nal value is established at 6. This is due to the fact that it takes into account two operations: transition with f 2

CT _U/D = ( f0 & cp0

f1 & cp1

f2 & cp2

f3 & cp3

0 0 1 f4 & cp4 & cp5 ) 1 0 0 (23)

CT _U/D = (f2 & cp2 )|(f3 & cp3 )

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Fig. 13.

Preincidence and postincidence matrices including a subnet.

As mentioned before, the procedure starts obtaining p1 1 0 = 0 0 p1 0 0 = 0 1 p2 0 1 0 0 p2 1 0 0 0 r3 0 0 1 0 r3 1 0 0 0 p4 0 0 0 1 p4 0 1 0 0 p5 0 0 0 1 p5 0 0 1 1 t1 t2 t3 t4 t1 t2 t3 t4 (25)

T IH
Fig. 12. PN example including a subnet.

increases the content by 1 and transition with f 3 increases it by 2. VI. E XTENDING THE M ATRIX M ODEL TO H IERARCHICAL PNs The complexity of many industrial processes implies that, in general, their behavior cannot be described with just one PN because they would be too big to be handled and understood [36], [37]. This problem can be solved using a top-down decomposition methodology to develop a model including subnets. In PN literature, top-down decomposition is usually referred to as renement and can be dened in static or dynamic form [38]. The PNs described in this section follow the static integration mechanism where a PN can contain another PN model (subnet). This integration is obtained by place substitution, where a place is seen as a macroplace, which can also include other macroplaces, supporting a multilevel hierarchical integration schema. In this section, the matrix model described in Section II is extended to a hierarchical PN to integrate the matrix model of a net into another one. Fig. 12 shows a main PN including four transitions (mH = 4) and four places plus a subnet (macroplace) named LOAD (nH = 5). The subnet is also made up of three places (nL = 3) and two transitions (mL = 2). To achieve a matrix model from the two models (one of the main net and another of the subnet), the general matrices T I and T O must be obtained from the specic T I and T O matrices of each net. Then, the general equations will be solved by applying the method described in Section II. Moreover, it is obvious that the matrices of each net are also built following the same method but considering the subnet included in the main net as if it was a place. In the PN example in Fig. 12, subnet 3 (LOAD) is considered to be place 3, but a different symbol and the name r3 is used. The procedure to obtain the general matrices of the whole design is described next by means of the example in Fig. 12.

T OH

of the main net (high level H) and

of the subnet (low level L), which have already been dened. The T IH and T OH matrices of the main net are now extended with the elements of the T IL and T OL subnet matrices to obtain T I and T O global matrices using the following steps. 1) The r3 column dening the output and input connections to the subnet is extracted from the T IH and T OH matrices, respectively, of the high-level net. 2) The T IL and T OL matrices are added to T IH and T OH , respectively, at the end position (mH+1 , nH ). Now, the new matrices T I and T O of the whole net have the suitable dimensions [(mH + mL ) (nH 1 + nL )]. 3) The r3 column extracted from T IH is overwritten at the last column of the extended matrix T I (Fig. 13, r3 p3 r3 ). The same operation is carried out with the column extracted from T OH to complete the column nH of T O (Fig. 13, r3 p1 r3 ). 4) The remaining elements of the general T I and T O matrices are padded with 0. At this point, the nal step is to extend the general matrices E, A, F , CP , and N P by adding the subnet matrices to the net ones as follows: E = ( EH A = ( AH EL ) AL ) (27) (28) (29) (30)

F = (f1 , f2 , . . . , fmH , rf1 , rf2 , . . . , rfmL ) CP = (cp1 , cp2 , . . . , cpnH , rcp1 , rcp2 , . . . , rcpnL )

N P = (np1 , np2 , . . . , npnH , rnp1 , rnp2 , . . . , rnpnL ). (31)

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Consequently, when the general matrices are obtained, the process to achieve the nal equations is the same as that shown in Section II. Although, in this method, subnets are used as places, they cannot have any associated action in the main net. This is due to the fact that when the subnet state is activated, it really corresponds with the rst place in the subnet, which is the place specifying the action that must be carried out. It is important to highlight the fact that, as the two models are mixed into only one, the process to obtain the VHDL code from this global model is greatly simplied because this solution follows the general scheme in Fig. 1. VII. C ONCLUSION Due to the exible hardware architecture of real FPGAs, nowadays, it is worthwhile to implement FPGA-based logic controllers. Nevertheless, useful, robust, and economical design methods are necessary. This paper has described a new logic controller design and implementation method using CIPNs and FPGA recongurable integrated circuits. The presented method has provided, from the matrix structure dening the PN, controller state equations directly synthesizable with FPGA hardware. Due to the hardware structure implementing the controller, an optimum running speed has been achieved because only one clock cycle is necessary to obtain the next PN state. This method has utilized a generic algorithm to obtain the specic VHDL code describing each PN. Thus, the use of VHDL templates, hiding the automation method, has been avoided. The method has been presented through several examples of increasing complexity including important elements such as timers and counters, being used in many logic controllers. To facilitate complex logic controller management, the matrix model has also been generalized to incorporate subnets, obtaining a unique global matrix model. The results have been validated by simulation before their practical implementation, and the VHDL code of each example has been used to congure an RLC based on a Cyclone FPGA. Using this method, PLC users can implement RLCs using the same design methods, and they do not need an in-depth knowledge of the RLC hardware. R EFERENCES
[1] J. T. Welch and J. Carletta, A direct mapping FPGA architecture for industrial process control applications, in Proc. IEEE Int. Conf. Comput. Des., 2000, vol. 1, pp. 595598. [2] J. M. Fernandes, M. Adamski, and A. J. Proena, VHDL generation from hierarchical Petri net specications of parallel controllers, Proc. Inst. Elect. Eng.Comput. Digit. Tech., vol. 144, no. 2, pp. 127137, Mar. 1997. [3] M. Adamski, SFC, Petri nets and application specic logic controllers, in Proc. IEEE Int. Conf. Syst., Man, Cybern., 1998, pp. 728733. [4] J. Pardey and M. Bolton, Logic synthesis of synchronous parallel controllers, in Proc. IEEE Int. Conf. Comput. Des., 1991, pp. 454457. [5] T. Murata, Petri nets: Properties, analysis and applications, Proc. IEEE, vol. 77, no. 4, pp. 541580, Apr. 1989. [6] R. David and H. Alla, Discrete, Continuous and Hybrid Petri Nets. Berlin, Germany: Springer-Verlag, 2005. [7] R. Zurawski and M. Zhou, Petri nets and industrial applications: A tutorial, IEEE Trans. Ind. Electron., vol. 41, no. 6, pp. 567583, Dec. 1994.

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Celso F. Silva received the Industrial Engineering degree from the University of Vigo, Vigo, Spain, in 1987. Since 1987, he has been a Researcher and an Electrical and Computer Engineering Educator with the Department of System Engineering and Automation, University of Vigo. His research interests are in programmable control systems. He is a coauthor of books about programmable logic controllers, including Autmatas Programables y Sistemas de Automatizacin (Barcelona, Spain: Marcombo, 2009) with two editions.

Manuel A. Castro (M87SM93F08) received the Industrial Engineering degree and the Ph.D. degree in engineering from the Escuela Tcnica Superior de Ingenieros Industriales/Madrid Polytechnic University, Madrid, Spain. He is an Electrical and Computer Engineering Educator with the Spanish University for Distance Education (UNED), Madrid, Spain. For ve years, he was with in the Digital Equipment Corporation, Madrid, Spain, as a Senior Systems Engineer. He was a Researcher in different projects, ranging from solar power system and advanced microprocessor system simulation to telematics and distance learning systems, acting now as a Senior Technical Coordinator. He served as UNEDs New Technologies Vice Rector, Information Services Center Director, Research Vice Director, and Academic Affairs Vice Director of the Engineering School, acting now as Head of the Electrical and Computer Engineering Department. He has published various technical books and articles in journals and conference proceedings. His research interests focus on system applications of simulation techniques, distance learning applications, and computer-aided electrical engineering. Dr. Castro is a member of the IEEE Education Society Administrative Committee (20052010) and the Founder of the Spanish Chapter of the IEEE Education Society. He is a Board Member of the Spanish International Solar Energy Society Committee.

Camilo Quintns (M05) received the B.S. degree in electrical engineering from the University of Vigo, Vigo, Spain, in 1997, the M.S. degree and the Ph.D. degree in electrical engineering from the Spanish University for Distance Education (UNED), Madrid, Spain, in 2005 and 2008, respectively. From 1997 to 2001, he was in the industrial electronics eld, particularly in electrical power generation. Since 2000, he has been a Researcher and an Assistant Professor with the Department of Electronic Technology, University of Vigo. His research interests are in analog and digital mixed circuits applied to instrumentation and control systems.

Enrique Mandado (S68M69LM09) received the B.S. degree in electronic engineering from the Polytechnic University of Madrid, Madrid, Spain, in 1969 and the Ph.D. degree from the Polytechnic University of Barcelona, Barcelona, Spain, in 1976. From 1969 to 1978, he was an Electronic Application Engineer with Miniwatt (Philips), Barcelona, Spain. In 1979, he joined the University of Vigo, Vigo, Spain, where he is currently a Full Professor of electronics with the Department of Electronic Technology and the Director of the Institute for Applied Electronics, developing electronic systems for control and measurement. He is the author or a coauthor of ten books about electronics, including Programmable Logic Controllers and Logic Devices (London, U.K.: Prentice-Hall, 1996), Sistemas Electrnicos Digitales (Barcelona, Spain: Marcombo, 2008) with nine editions, and Autmatas Programables y Sistemas de Automatizacin (Barcelona, Spain: Marcombo, 2009).

Antonio Colmenar received the Industrial Engineering degree and the Dr.Eng. degree from the Escuela Tcnica Superior de Ingenieros Industriales/Spanish University for Distance Education (UNED), Madrid, Spain. He is an Electrical and Computer Engineering Educator with the Electrical and Computer Engineering Department, Spanish University for Distance Education. He worked for 14 years in different levels of education in Spain and Nicaragua. He was a Researcher on various projects, ranging from solar power systems to distance learning systems. He has published various technical books and articles in journals and conference proceedings. Dr. Colmenar is a member of the Association for the Advancement of Computing in Education (AAEC) and the Spanish group of the International Solar Energy Society (ISES).