Ecl 302 Electronic Circuits - I and Simulation Lab

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SYMBOLS AND PIN DIAGRAMS
Electronic Circuits I Lab
Vidyaa Vikas College of Engineering and Technology
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Page no-2
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CIRCUIT SIMULATION USING ORCAD SIMULATION TOOL -------------------------------------------------------------------------------------
Procedure for Circuit simulation: 1. Choose ORCAD capture icon from the program window. 2. In file, select new and then project. 3. Enter the name of the project, create the new project using A/D or mixed modeling and specify the location. 4. Create PSPICE project as a blank project. 5. In the schematic window click on the right most corners to select the tools. 6. Select the place part tool to select the components that are specified circuit diagram. 7. Place the components on the schematic page as given in the circuit diagram. 8. Select place wire tool to connect the components as per the circuit diagram. 9. Place the junctions where ever it is necessary. 10. Select the place ground tool to place ground as needed in the circuit diagram. 11. Select the voltage / level marker from the tool bar and place as per the requirement and save the project. 12. Choose new simulation profile and name the simulation profile. 13. Select edit simulation settings from the tool bar and make the necessary simulation settings. 14. Select Run PSPICE option and obtain the results. 15. Adjust the run to time by selecting edit simulation settings for proper results.
Note: 1. Simulation of mandatory. all the experiments using ORCAD tool is
2. The above said procedure should be followed in common to all the experiments given in the syllabus formulated by Anna University Coimbatore.
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Page no-3
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STUDY OF DIFFERENT TYPES OF BIASING OF ACTIVE CIRCUITS (BIASING OF BIPOLAR JUNCTION TRANSISTOR - BJT) ----------------------------------------------------------------------------------Aim: To Study and simulate the different biasing techniques of Bipolar Junction Transistor (Fixed bias and voltage divider bias). Components required: S.No 1 2 Theory: The process of raising the strength of a weak signal without any change in its general shape is called faithful amplification. The key factor for achieving this faithful amplification is biasing. Biasing the circuit should ensure the following conditions, 1. Proper zero signal collector current. 2. Minimum proper BaseEmitter voltage (VBE) at any instant. 3. Minimum proper CollectorEmitter voltage (VCE) at any instant. (VCE does not fall below 0.5 V for Germanium and 1V for silicon) Conditions (1) and (2) ensure that base-emitter junction shall remain properly forward biased and (3) ensure that base-collector junction shall remain reverse biased at all times. The fulfillment of these conditions will ensure that the transistor works over the active region of the output characteristics i.e., between saturation to cutoff region. Methods of Transistor Biasing: 1. Base resistor or fixed bias. 2. Self bias or voltage divider bias Base Resistor or Fixed biasing technique: In this method, a high resistance RB (several 100 Kilo ohms) is connected between the base and positive end of supply for NPN transistor and between base and negative end of supply for PNP transistor. Hence zero signal Base current is provided by VCC and its flows through RB. Since base is positive with respect to emitter, the base emitter junction is forward biased. The required value of zero signal base current IB can be made to flow by selecting the proper value of base resistor RB. Description PSPICE Simulation Tool PC System Range Type Quantity -
Figure 1.1.1: CE amplifier circuit with fixed bias Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
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Page no-4
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(A) Circuit Arrangement for Base resistor or fixed biasing technique:
Circuit Design: Design a common emitter amplifier circuit with base resistor biasing method for the given specifications
=100
VCC = 15V S S S =+1 = 100+1 = 101 = IC / = 210-3 / 100 = 0.02 mA ----
VBE = 0.6V
VCE = 8V
IC = 2 mA
=S1
We know that, IB IB IB
To find RB and RC: VCC RB = IB RB + VBE = (VCC - VBE) / IB = (15-0.6) / 0.0210-3 RB VCC RC = 720 K
= IC RC + VCE. = VCC - VCE / IC = (15-8) / 210-3
RC
= 500
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Page no-5
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Circuit Analysis for Base resistor or fixed biasing technique: From the Figure 1.1.1 It is required to find the value of RB so that the required collector current flows in the zero signal conditions. Let IC be the required zero signal collector current. Therefore IB = I C / --------(1)
Where, is the current amplification factor for CE configuration. Considering the closed circuit A-B-E-N-A and applying KVL, VCC = IB RB + VBE RB = (VCC - VBE) / IB --------(2)
Eqn. (2) can be rewritten as, RB = VCC / IB; since VCC >> VBE Stability factor(s): S= + 1 Advantages of Base Resistor Method: 1. The biasing circuit is very simple as only one resistance RB is required. 2. Biasing conditions can easily be set and the calculations are simple. 3. There is no loading of the source by the biasing circuit since no resistor is employed across base emitter junction. Disadvantages of Base Resistor Method: 1. This method provides poor stabilization. 2. The stability factor is very high. Self Bias or Voltage Divider Bias: This is most widely used method of providing biasing and stabilization to a transistor. In this method, two resistances R1 and R2 are connected across the supply voltage VCC and provide biasing. The emitter resistance RE provides stabilization. The name Voltage Divider comes from the voltage divider form by R1 and R2. The voltage drop across R2 forward biases the base-emitter junction. This causes the base current and hence collector current flows in the zero signal condition. VBE can be Neglected
Circuit Analysis for Self Bias or Voltage Divider Bias: To find collector Current (IC): I1 = VCC / R1 + R2 VB = VCC R2 / R1 + R2 ------(1) (2)
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Page no-6
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Design a common emitter amplifier circuit with Voltage Divider biasing method for the given specifications
VCC = 10 V
IE =1mA
S=7
hfe = 100
VCE = 5V
VE = 1V
To find RC: VCC IC RC RC = IC RC + VCE + IE RE = IC RC + VCE + VE = VCC - VCE - VE = (VCC - VCE - VE) / IC = (10 5 1) / 110-3 RC = 4 K To find VB: VB = VBE + VE = 0.7 + 1 = 1.7 V VB S = 1.7 V = (1+ ) (1+ (RB / RE)) 1+ + (RB / RE) Solving the above equation we get, S RB = 1+ (RB / RE) = (S-1) RE = (7-1) *(1103) RB =6K -----------(VE=IE RE)
To find R1 and R2: VB R1 + R2 RB R1 + R2 = VCC R2 / R1 + R2 = VCC R2 / VB = R1 R2 / R1 + R2 = R1 R2 / RB --------------------(1) (A) (2) (B)
From the Equations A and B, (LHS = RHS) VCC R2 / VB R1 = R1 R2 / RB = RB VCC / VB = (6103) * 10 / 1.7 R1 We know that, RB = R1 R2 / R1 + R2 = 35.29 K
Exp.No: RB = R1 R2 / R1 + R2 VBE = VB - VE VB = VBE + VE VB = VBE + IE RE IE = VB VBE / RE (Or) IC = VB VBE / RE
Page no-7 ------(3) VE = IE RE
Date:
----
(4) IE IC (IE = IC + IB (IB Negligible))
Considering Eqn. (4) IC does not depend upon . Though IC depends upon VBE but in practice VB >> VBE so that IC is practically independent of VBE. Thus IC in this voltage divider bias circuit is almost independent of transistor parameters and hence good stabilization is ensured.
Fig 1.1.2: CE amplifier circuit with Voltage divider bias
To find Collector Emitter Voltage Applying KVL to the Collector side, VCC = IC RC + VCE + IE RE VCE = VCC - IC RC - IE RE VCE = VCC - IC (RC+RE) Stabilization (S):
(VCE):
---------
IE IC
In this circuit excellent stabilization is provided by RE VB = VBE + IC RE --------IE IC If collector Current (IC) increases due to rise in temperature, causes the voltage drop across emitter resistance RE to increase. As voltage drop across R2 is independent of IC therefore, VBE decreases. This in-turn causes IB to decrease which in-turn restore IC to the original value. Stability Factor(S) = (1+ ) (1+ (RB / RE)) 1+ + (RB / RE) Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No: Sub. RB = 6 K
Page no-8 and R1 = 35.29 K

3 3
Date:
in above equation,
610 = 35.2910 * R2 / 35.29103 + R2 Solving the above equation we get, R2 = 7.3 K To find CC and CE: CC = XCC = Zi / 10 Zi = R1 ll R2 ll hie h
ie
7K
=h
fe
re
re = VT / IE = 2610-3 / 110-3 = 26 h
ie
= 100 26 = 2.6 K ----/ 10 R1 ll R2 = R1 R2 / R1 + R2 = 35.29K *7.3K 35.29K +7.3K =6K

3
XCC = R1 ll R2 ll hie / 10 =6K XCC CC ll 2.6 K
XCC= 0.182 K = 1/ 2f CC = 1/ (23.141000.18210 ) = 8.7410-6 = 8.74 f CC XCE XCE CE CE 10 f = Z0 /10 = R =R

E
XCE = 1/ 2f CE
E
/ 10
/ 10 = 100
= 1/ (23.14100100) = 16 f
Exp.No: Note: R2 = 0.1 RE To find load resistance: RL = VCC VE / 2 IE
Page no-9
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To find the value of coupling capacitor: CC = 1/ 2f XCC Where, XCC = Zi / 10 = R Zi = R1 ll R2 ll h h

ie ie in
/ 10
=h
fe
re -------(VT = 26mV)
re = VT / IE
To find the value of bypass capacitor: CE = 1/ 2f XCE Where XCE= R

E
/ 10
Description Preparation Performance Viva Voce Record Total Staff Signature
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the biasing of Bipolar Junction Transistor in base resistor bias method and voltage divider bias method were studied and verified the same by using PSPICE circuit simulation tool. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
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Page no-10
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Design a common source JFET amplifier in self biased condition for the given specifications ID =1.5 mA VDS= 10V IDSS = 0.5mA VP = - 2V VDD= 12 V
To find VGS: ID 1.510-3 (1.5/5) = IDSS {1- (VGS / VP)} 2 = 510-3 {1+ (VGS / 2)} 2 = 1+ (VGS / 2) ----- (1.5/5) = 0.55
Solving the above equation we get, VGS To find VS: VGS VGS VS To find RS: RS RS = VS / I S = VS / I D = 0.9 / 1.510-3 RS To find RD: VDD VDD 12 RD RD To find CC: XC1 = RG / 10 = 1106 / 10 XC1 XC1 CC1 CC1 CC1 = 0.1M = 1/ 2f CC1 = 1/ 2f XC1 = 1/ (23.141000.1106) = 0.015 f = CC2 = 0.015 f = CC2 0.01 f ----RG=1M (To make the gate current negligible) = ID RD + VDS + IS RS = ID RD + VDS + VS = 1.510-3 RD +10+0.9 = (12 -10.9) / 1.510-3 = 0.73 K -----(VS = IS RS) = 0.6 K -----(IS = ID) = VG - VS = - VS = - 0.9 V = 0.9 V -----(VG = 0) = - 0.906 V
Solving the above equation,
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Page no-11
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STUDY OF DIFFERENT TYPES OF BIASING OF ACTIVE CIRCUITS (BIASING OF JUNCTION FIELD EFFECT TRANSISTOR - JFET) ----------------------------------------------------------------------------------Aim: To Study and simulate the different biasing techniques of Junction field effect Transistor (Fixed bias and voltage divider bias). Components required: S.No 1 2 Description PSPICE Simulation Tool PC System Range Type Quantity -
Theory: Generally, field effect transistors output characteristics are controlled by input voltage, thus field effect transistor is classified as a voltage controlled device. This behavior of the FET represents the clear difference from the BJT (Current controlled device). FET is classified into two types, 1. Junction Field Effect Transistor (JFET) 2. Metal Oxide Semiconductor Field Effect Transistor (MOSFET). A JFET is a three terminal semiconductor device in which current conduction is by one type of carrier i.e. electrons or holes. JFET Biasing: For the proper operation of n-channel JFET, gate must be negative w.r.t. source. This can be achieved either by inserting a battery in the gate circuit or by a circuit known as biasing circuit. Biasing of JFET is the most likely one due to the reason that batteries are costly and require frequent replacement. Biasing Circuit: The biasing circuit uses supply voltage VDD to provide the necessary bias. There are two most commonly used biasing methods are 1. Self bias 2. Voltage divider bias / Potential divider bias. Self-Bias Method: Figure 1.2.1 shows the self bias method. The resistor RS is the base resistor. The DC component of drain current flowing through RS produces the desired bias voltage. The capacitor CS bypasses the AC component of the drain current.
Exp.No: To find CS: XCS XCS CS
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= RS / 10 = 0.6103 /10 = 60 = 1/ 2f XCS = 1/ (23.1410060)
CS To find RL:
= 26 f 15 f
Gain (A) = gm (RD ll RL) Required gain: 10 RL = 4.7 K
Exp.No: Circuit Analysis: To find RS: Voltage across RS, VS = ID RS
Page no-13
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Figure 1.2.1: Common Source JFET Amplifier in Self Biased Condition To find VS: Since the gate current is negligibly small, the gate terminal is at D.C ground i.e, VGS = 0 VGS VGS VGS = VG - VS = 0 - ID RS = - ID RS -----(VG = 0)
Thus bias voltage VGS keeps gate negative w.r.t. source. Operating point: The operating point (i.e, zero signal ID and VDS) can be easily determined. Since the parameters of the JFET are usually known, zero signal ID can be calculated from the following relation ID Also VDD VDS To find CC: XC1 XC1 CC1 To find CS: XCS CS To find RL: Gain (A) = gm (RD ll RL) = RS / 10 = 1/ 2f XCS = RG / 10 = 1 / 2f CC1 = 1 / 2f XC1 -----RG=1M (To make the gate negligible) = IDSS {1- (VGS / VP)} 2 = ID RD + VDS + IS RS = VDD - ID (RD + RS) -----(ID IS)
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Page no-14
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Design a common source JFET amplifier in Voltage divider biased condition for the given specifications ID=2.5mA VDS= 8V IDSS =10mA VP = -5V VDD= 30 V R1=1 M R2=500K
To find VGS: ID 2.510-3 (2.5/10) = IDSS {1- (VGS / VP)} 2 = 1010-3 {1+ (VGS / 5)} 2 = 1+ (VGS / 5) ---- (2.5/10) (2.5/10)1/2
Solving the above equation we get, VGS To find V2: V2 = VDD R2 / R1+ R2 = (30500103) / (106+500103) V2 To find RS: V2 10 RS RS = VGS + IS RS = -2.5 + 2.510-3 RS = (10 + 2.5) / 2.510-3 =5K ----(IS = ID) = 10 V = - 2.5 V
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Page no-15
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Voltage divider bias or potential divider bias: Figure 1.2.2 shows potential divider method of biasing a JFET. The circuit is very much similar to that of biasing the transistor. The resistors R1 and R2 form a voltage divider across drain supply VDD. The voltage V2 across R2 provides the necessary bias.
Figure 1.2.2: Common Source JFET Amplifier in Voltage Divider Method Circuit Analysis: To find V2: V2 Now V2 VGS = VDD R2 / R1+ R2 = VGS + ID RS = V2 - ID RS ----(ID = IS)
The circuit so designed that ID RS is larger than V2 so that VGS is negative. This provides correct bias voltage. The operating point can be found by ID And VDD VDS = (V2 - VGS) / RS = ID RD + VDS + IS RS = VDD - ID (RD + RS)
To find the value of coupling capacitor: XCC1 RG CC1 = RG / 10 = R1 R2 / R1 + R2 = 1/ 2f XC1
To find the value of Source capacitor: XCS CS = RS / 10 = 1/ 2f XCS
Exp.No: To find RD: VDD 30 30 17 RD RD XCC1 RG XCC1 CC1 CC1 XCS
Page no-16
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= ID RD + VDS + IS RS = 2.510-3 RD + 8+9 = 2.510-3 RD = 13 / 2.510-3 = 5.2 K = RG / 10 = R1 R2 / R1 + R2 = 333.33 K = 33.33 K = 1/ 2*3.14*100*33300 = CC2 = 0.04 f 0.01 f = RS / 10 = 5000 / 10
To find the value of coupling capacitor:
To find the value of Source capacitor:
XCS Cs Cs
= 500 = 1/ (2*3.14*100*500) = 3.2 f 4.7 f
Exp.No:
Page no-17
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the biasing of Junction Field Effect Transistor in base resistor bias method and voltage divider bias method were studied and verified the same by using PSPICE circuit simulation tool.
Exp.No:
Page no-18
Date:
Circuit Diagram:
Design: Output requirements: Mid-band voltage gain of the amplifier = 50. Selection of transistor: Select transistor BC 107 since its minimum guaranteed h the required gain (=50) of the amplifier.
FE
(=100) is more than
Details of BC 107: Type: NPN silicon, application: In audio frequency. Max. Ratings Nominal Ratings : VCB= 50V : VCE= 5 V VCE= 45 V IC= 2mA VBE=6 V IC= 100mA h FE = 100 to 500
DC biasing conditions: VCC= 12V IC= 2mA VRE= 10% of VCC=1.2V Design of RC VRC = IC RC = 4.8 V RC = VRC / IC = 4.8 / 210 RC =2.4 K 2.2 K
-3
VRC= 40% of VCC=4.8V VCE= 50% of VCC= 6V Design of RE VRE = IE RE= 1.2 V RE = VRE / IE = 1.2 / 210-3 ---RE =600 620 IC=IE
Design of voltage divider R1 and R2 I B = IC / h = 210-3 / 100 = 20 A
FE
IB = 20 A
Exp.No:
Page no-19 AMPLIFYING CIRCUITS
Date:
(A) SIMPLE COMMON EMITTER AMPLIFIER CONFIGURATION GAIN & BANDWIDTH
--------------------------------------------------------------------------------------------------Aim: To design, simulate and set up a simple Common Emitter (CE) amplifier using bipolar junction transistor and to plot its frequency response. Components Required: S.No 1 2 3 4 5 6 7 8 9 Theory: RC Coupled CE amplifier is widely used in audio frequency applications in radio and TV receivers. It provides current, voltage and power gains. Base current controls the collector current of a CE amplifier. A small increase in base current results in a relatively large increase in collector current. Similarly small decrease in base current causes large decrease in collector current. The emitter-base junction must be forward biased and the collector-base junction must be reverse biased for the proper functioning of an amplifier. In the circuit diagram, NPN transistor is connected as a common emitter ac amplifier. R1 and R2 are employed for the voltage divider bias of the transistor. Voltage divider bias provides independence from the variation in . The input signal V in is coupled through CC1 to the base and output voltage is coupled from collector through the capacitor CC2. is Z The input impedance of the amplifier is Z = RC
in
Description Transistor Capacitors Resistors Power Supply Bread Board Signal Generator CRO Probe Connecting wires
Range(s)
Type
Quantity
= R1 ll R2 ll r
and output resistance
out
Procedure: 1. Test all the components using a multimeter. Set up the circuit and verify dc biasing conditions. To check the dc biasing conditions, remove input signal and capacitors in the circuit. 2. Connect the capacitors in the circuit and apply a sinusoidal signal from signal generator to the circuit input. Observe the input and output waveforms on the CRO screen simultaneously. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No:
Page no-20
Date:
Assume the current through R1 =10 IB and that through R2 = 9 IB to avoid loading the potential divider by the base current. VR2 = Voltage across R2 = VBE + VRE VR2 = VBE + VRE = 0.7 + 1.2=1.9V - (1) Also VR2 = 9 IB R2 = 1.9 V 9 IB R2 = 1.9 V R2 = 1.9 / 92010 R2 = 10.6 K
-6
VR1 = Voltage across R1 = VCC - VR2 VR1 = VCC - VR2 = 12 1.9 = 10.1V -- (1) Also VR1= 10 IBQ R1 =10.1V 10 IBQ R1 = 10.1 V R1 = 10.1 / 102010-6 R1 = 50 K --------------(3) (4) 47K pot. ---- (2) From (1) and (2) (LHS = RHS)
----- (2)
From (1) and (2) -
(LHS = RHS)
10 K
Design of RL
(Av = -(r c r e))
Where r c = RC ll RL
re = 25 10-3 / IE = 2510-3 / 210-3 = 12.5 re = 12.5 Sine the required gain= 50, substituting we get RL = 845 . Use 820 . Design of coupling capacitors CC1, CC2 and CC3 XC1 at the lowest frequency (say 100Hz), should be equal to one-tenth or less of the series impedance being driven by the signal passing through the capacitor. Here the relevant impedance is R in.
Then XC1 R Here R

in
in
/10. re ---. . (5)
Similarly, XC2 Rout /10. Where Rout = RC Then XC2 240 CC2 = 1/ 2fL XC2 = 1/ (23.14100240) CC2 = 6.6 f 10 f
= R1 ll R2 ll h
FE
Where re = 12.5 R
Sub all the values in equation (5), we get

in
= 1.1K . Then XC1 110 CC1 = 1/ 2fL XC1
= 1/ (23.14100110) CC1 = 14 f 15 f
Design of Bypass capacitors CE To bypass the lowest frequency (say 100Hz), XCE should be equal to one-tenth or less of the resistance RE. XCE RE /10; CE 1/ 2fL XCE = 1/ (23.1410062) CE = 2.6 f use 10 f
Exp.No:
Page no-21
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3. Keeping the input amplitude constant vary the frequency of the input signal from 0 Hz to 1 MHz. Measure the output amplitude corresponding to different frequencies and enter it in tabular column. 4. Plot the frequency response characteristics on a semi-log graph sheet with gain on Y-axis and log (f) on X-axis. Mark log (fL) and log (fH) corresponding to 1/ 2 times of the maximum gain. 5. Calculate the bandwidth of the amplifier using the expression BW = fH - fL. 6. Remove the emitter bypass capacitor CE from the circuit and repeat the steps 3 to 5 and observe that the bandwidth increases and gain decreases in the absence of CE. Circuit Analysis for simple common emitter amplifier in Voltage Divider Bias: To find collector Current (IC): I1 = VCC / R1 + R2 VB = VCC R2 / R1 + R2 RB = R1 R2 / R1 + R2 VBE = VB - VE VB = VBE + VE VB = VBE + IE RE IE = VB VBE / RE (Or) IC = VB VBE / RE ---(4) IE IC (IE = IC + IB (IB Negligible)) ---VE = IE RE ---------(1) (2) (3)
Considering Eqn. (4) IC does not depend upon . Though IC depends upon VBE but in practice VB >> VBE so that IC is practically independent of VBE. Thus IC in this voltage divider bias circuit is almost independent of transistor parameters and hence good stabilization is ensured. To find Collector Emitter Voltage Applying KVL to the Collector side, VCC = IC RC + VCE + IE RE VCE = VCC - IC RC - IE RE VCE = VCC - IC (RC+RE) Stabilization (S): In this circuit excellent stabilization is provided by RE VB = VBE + IC RE --------IE IC If collector Current (IC) increases due to rise in temperature, causes the voltage drop across emitter resistance RE to increase. As voltage drop across R2 is independent of IC therefore, VBE decreases. This in-turn causes IB to decrease which in-turn restore IC to the original value. Stability Factor(S) = (1+ ) (1+ (RB / RE)) 1+ + (RB / RE) Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology --------IE IC
(VCE):
Exp.No:
Page no-22
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Model Graph: frequency response with out CE
Model Graph: frequency response with CE
Exp.No: Note: R2 = 0.1 RE To find load resistance: RL = VCC VE / 2 IE
Page no-23
Date:
To find the value of coupling capacitor: CC = 1/ 2f XCC Where, XCC = Zi / 10 = R Zi = R1 ll R2 ll h h

ie ie in
/ 10
=h
fe
re -------(VT = 26mV)
re = VT / IE
To find the value of bypass capacitor: CE = 1/ 2f XCE Where XCE= R

E
/ 10
Exp.No: Observation:
Page no-24
Date:
V
S.No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency in Hz With CE Vo in Volts Gain (A) = 20 log(VO / V in)
in
With out CE Vo in Volts Gain (A) = 20 log(VO / V in)
Exp.No:
Page no-25
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the simple Common Emitter (CE) amplifier using bipolar junction transistor was designed, simulated and its frequency response were plotted. Bandwidth of the amplifier with CE Bandwidth of the amplifier with out CE = fH - fL = = fH - fL =
Exp.No:
Page no-26
Date:
Design a common source JFET amplifier in self biased condition for the given specifications ID =2 mA VDS= 10V VD= 45 % of VDD = 5.4 V VGS = - 2V VDD= 12 V gm = 2.5 Gain(A)=10
Select RG = 1M To find VS: VGS VGS -2 VS To find RS: RS
to make current negligible.
= VG - VS = - VS = - VS =2V = VS / I S RS = VS / I D = 2 / 210-3
------
(VG = 0)
------
(IS = ID)
RS To find RD: VD RD
=1K = ID RD = VD / I D = 5.4 / 210-3
RD To find RL:
=2.7 K
Gain (A) = gm (RD ll RL) Required gain: 10 RL To find CC: XC1 = RG / 10 = 1106 / 10 XC1 XC1 CC1 CC1 CC1 = 0.1M = 1/ 2f CC1 = 1/ 2f XC1 = 1/ (23.141000.1106) = 0.015 f = CC2 = 0.015 f = CC2 0.022 f ----RG=1M (To make the gate current negligible) = 4.7 K
Exp.No:
Page no-27 AMPLIFYING CIRCUITS
Date:
(B) COMMON SOURCE AMPLIFIER CONFIGURATION GAIN & BANDWIDTH --------------------------------------------------------------------------------------------------Aim: To design, simulate and set up a Common Source (CS) amplifier using junction field effect transistor and to plot its frequency response. Components Required:
S.No 1 2 3 4 5 6 7 8 9 Theory: Transistor Capacitors Resistors
Description
Range(s)
Type
Quantity
Power Supply Bread Board Signal Generator CRO Probe Connecting wires
Junction field effect transistor (JFET) is unipolar voltage controlled device. The drain current is controlled by the voltage at gate. Like BJTs, JFET amplifiers can also be set up in three configurations namely Common Drain, Common Source and Common Gate. Common Source configuration is similar to common emitter configuration of BJT.. JFETs can be biased as voltage divider bias or self bias. A self bias circuit maintains drain current and gm relatively constant. Constant gm results in a constant voltage gain. The design of the circuit is done in such a way that the gate to source junction is reverse biased. The reverse biased junction provides high input impedance. The applied input voltage slightly changes the gate potential and in turn, the drain current varies. The output voltage varies with the drain current. The following expression can be sued to find the gain in dB.
Gain = 20 log (VO / V
in)
Exp.No: To find CS: XCS XCS CS
Page no-28
Date:
= RS / 10 = 1103 /10 = 100 = 1/ 2f XCS = 1/ (23.14100100)
CS
= 16 f 15 f
Circuit Diagram:
Model Graph:
Exp.No: Circuit Analysis: To find RS: Voltage across RS, VS = ID RS
Page no-29
Date:
Figure 1.2.1: Common Source JFET Amplifier in Self Biased Condition To find VS: Since the gate current is negligibly small, the gate terminal is at D.C ground i.e, VGS = 0 VGS VGS VGS = VG - VS = 0 - ID RS = - ID RS -----(VG = 0)
Thus bias voltage VGS keeps gate negative w.r.t. source. Operating point: The operating point (i.e, zero signal ID and VDS) can be easily determined. Since the parameters of the JFET are usually known, zero signal ID can be calculated from the following relation ID Also VDD VDS To find CC: XC1 XC1 CC1 To find CS: XCS CS To find RL: Gain (A) = gm (RD ll RL) = RS / 10 = 1/ 2f XCS = RG / 10 = 1 / 2f CC1 = 1 / 2f XC1 -----RG=1M (To make the gate negligible) = IDSS {1- (VGS / VP)} 2 = ID RD + VDS + IS RS = VDD - ID (RD + RS) -----(ID IS)
Exp.No:
Page no-30
Date:
Exp.No: Procedure:
Page no-31
Date:
1. Set up the circuit on the breadboard. Check the DC conditions and apply the input sinusoidal signal from signal generator to the gate. 2. Obtain the amplified output. Take the output amplitude for various frequencies for at the input. 3. Plot the frequency response curve. Find the bandwidth of the FET amplifier.
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the Common Source amplifier using Junction Field Effect Transistor was designed, simulated and its outputs were plotted. Bandwidth of the amplifier = fH - fL
Exp.No:
Page no-32
Date:
Circuit Diagram: TWO STAGE RC COUPLED AMPLIFIER
Model Graph:
Exp.No:
Page no-33 TWO STAGE RC COUPLED AMPLIFIER
Date:
--------------------------------------------------------------------------------------------Aim: To design, set up and study a two stage RC coupled CE amplifier using Bipolar Junction Transistor. Components Required: S.No 1 2 3 4 5 6 Transistor Capacitors Resistors Bread Board Signal Generator CRO Description Range(s) Type Quantity
Theory: More stages of RC coupled amplifiers can be used in cascade to increase the voltage gain of an amplifier. A two stage amplifier provides an overall voltage gain of A1 and A2 are the gains of first and second stages respectively. Since each stage provides a phase inversion, the final output is in-phase with the input. The input impedance of the second stage is in parallel with RC of the first stage. The voltage gain A1 of the first stage is: A1 = RC ll Zin (Second stage) / re Where Zin (Second stage) = R1 ll R2 ll h A2 = RC ll RL / re Procedure: 1. Test all the components using multimeter and make the connections as per the circuit diagram. 2. Apply a sinusoidal signal from the function generator to the circuit input. Observe the input and output waveforms on the CRO screen simultaneously. 3. Keeping the input amplitude constant, vary the frequency of the input signal from 0 Hz to 1 MHz. Measure the output amplitude corresponding to different frequencies and enter the values in tabular column. 4. Plot the frequency response characteristics on a semi log graph sheet with gain on Y-axis and log (f) on X-axis. Mark log (fL) and log (fH) corresponding to 1/ 2 of the maximum gain. 5. Calculate the bandwidth of the amplifier using the expression BW = fH - fL. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
FE
re
The Voltage gain A2 of the second stage is:
Exp.No: Design:
Page no-34
Date:
Output requirements: Mid band voltage gain of the amplifier = 100 Selection of Transistor: Select transistor BC 107 since its minimum guaranteed hFE equals the required gain (=50) of the amplifier. Assume the gains A1 = 50 and A2 = 2 since A= A1 A2. DC biasing conditions: VCC = 12 V IC=2mA VRC = 40% of VCC =4.8 V VRE = 10% of VCC =1.2 V VCE = 50% of VCC =6 V Design of first stage: Design of RC VRC = IC RC = 4.8 V RC = VRC / IC = 4.8 / 210 RC =2.4 K 2.2 K
-3
Design of RE VRE = IE RE= 1.2 V RE = VRE / IE = 1.2 / 210-3 ---RE =600 620 IC=IE
Design of voltage divider R1 and R2 I B = IC / h

FE
= 210-3 / 100 = 20 A
IB = 20 A Assume the current through R1 =10 IB and that through R2 = 9 IB to avoid loading the potential divider by the base current. VR2 = Voltage across R2 = VBE + VRE VR2 = VBE + VRE = 0.7 + 1.2=1.9V - (1) Also VR2 = 9 IB R2 = 1.9 V 9 IB R2 = 1.9 V R2 = 1.9 / 92010 R2 = 10.6 K
-6
VR1 = Voltage across R1 = VCC - VR2 VR1 = VCC - VR2 = 12 1.9 = 10.1V -- (1) Also VR1= 10 IBQ R1 =10.1V 10 IBQ R1 = 10.1 V R1 = 10.1 / 102010-6 R1 = 50 K 47K pot. ---- (2) From (1) and (2) (LHS = RHS)
----- (2)
From (1) and (2) -
(LHS = RHS)
10 K
Design of RL From A1 A1 = RC ll Zin (Second stage) / re Where Zin (Second stage) = R1 ll R2 ll h

-3 -3 FE
----re
-3
(3) (4)
-----
re = 25 10 / IE = 2510 / 210 = 12.5 re = 12.5 Substituting the R1, R2, h (3). Finally we get A1 = 50 (approx.)
FE
and re values in equation (4) and solve the equation
Exp.No:
Page no-35
Date:
Exp.No:
Page no-36
Date:
Gain of the CE amplifier is given by the expression A2 = AV = (RC ll RL) / re If the required gain = 2, substituting the values and solving the above equation, We get, RL = 23 22
Design of coupling capacitors CC1, CC2 and CC3 XC1 at the lowest frequency (say 100Hz), should be equal to one-tenth or less of the series impedance being driven by the signal passing through the capacitor. Here the relevant impedance is R in. Then XC1 R Here R
in
in
/10. re ---. . (5)
Similarly, XC2 Rout /10. Where Rout = RC Then XC2 240 CC2 = 1/ 2fL XC2 = 1/ (23.14100240) CC2 = 6.6 f 10 f (Take CC2 = CC3)
= R1 ll R2 ll h
FE
Where re = 12.5 get R
Sub all the values in equation (5), we

in
= 1.1K . Then XC1 110
CC1 = 1/ 2fL XC1 = 1/ (23.14100110) CC1 = 14 f 15 f
Design of Bypass capacitors CE To bypass the lowest frequency (say 100Hz), XCE should be equal to one-tenth or less of the resistance RE. XCE RE /10; CE 1/ 2fL XCE = 1/ (23.1410062) CE = 2.6 f use 10 f
Exp.No:
Page no-37
Date:
Page no-38
Date:
V
S.No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency in Hz Vo in Volts
in
Gain (A) =20 log(VO / V in)
Exp.No:
Page no-39
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the two stage RC coupled CE amplifier using Bipolar Junction Transistor was designed and its outputs were obtained.
Gain of the first stage Gain of the second stage Bandwidth of the amplifier Electronic Circuits I Lab
= = =
Exp.No: Circuit Diagram:
Page no-40
Date:
Model Graph:
Exp.No:
Page no-41
Date:
COMPLEMENTARY SYMMETRY CLASS B PUSH PULL POWER AMPLIFIER --------------------------------------------------------------------------------------------------Aim: To design, simulate and set up a Complementary Symmetry Class B Push Pull Power Amplifier using bipolar junction transistor and to plot its output characteristics. Components Required:
S.No 1 2 3 4 5 Transistors Capacitors Resistors Diodes
Description
Range(s)
Type
Quantity
Power Supply Bread Board
6 7 8 9 Theory:
Signal Generator CRO Probe Connecting wires
Class B operation means that the Q point is located at cut off region hence collector current flows only for 180 of the input cycle. A complementary symmetry circuit uses two transistors NPN and PNP with identical characteristics. Both the transistors are connected as emitter follower with emitters connected together. The name push pull comes from the fact that one transistor drives current through the load in one direction (pushing) while the other drives current in opposite direction (pulling). The dc bias keeps transistors near cut off region. During the positive half cycle of the input, base of NPN transistor T2 is driven positive relative to its emitter. This makes the transistor ON. At the same time, other transistor remains in OFF state. A current determined by the supply voltage and load resistor gets established in the output circuit. During the negative half cycle of the input, transistor T1 becomes ON and T2 becomes OFF state. Now, output current flows in the opposite direction. Voltage developed across RL is like the input voltage. Diodes are functioning as compensating diodes to avoid thermal run away. Procedure: 1. Set up the circuit as shown in figure after testing all the components. Observe the output waveform on the CRO screen. 2. Set the frequency of input signal at 1 KHz and load impedance at 8 in power meter. Take the reading on the power meter for different values of load impedance. Plot load impedance versus output power. Note the impedance for which output power is Maximum. This is the value of optimum load. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No: Design:
Page no-42
Date:
Output requirements VO = 50mW DC biasing conditions +VCC= 12 V -VCC= -12V VCE1 = VCE2 = 6V P
dc
= 0.5 mW.
Selection of RL: the output of an audio amplifier is usually connected to a loud speaker whose impedance is normally 8W. Take RL = 8.2 . Design of RC P
dc
= IC2 R = 78 mW = VCC - VCE =12V - 6V = 76 RC = 76 8.2 = 67.8 . Use 62 , 2W

FE
Then IC = 78 mA IC (RC+ RL) RC+ RL Then
Design of R Base current of the transistors IB = IC / h
= 78 mA / 40 = 1.95 mA.
We can see from the circuit VCC (-VEE) = 2VR + 2VD where VR is the potential across the resistor R and VD is the diode drop. Then VR = 11.3 V Assume the current through RS is 10IB so as to avoid loading of the biasing network by the base currents. Then R = VR / 10IB = 579 . Use 560 Selection of coupling capacitors CC1 and CCC2 Since the frequency of interest is in the audio range, Take CC1 = CCC2 = CCC3 = 10 F Observation:
S.No 1 2 3 4 5 6 7 8 9 10 Electronic Circuits I Lab
Resistance in
Power in mW
Exp.No:
Page no-43
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the Complementary Symmetry Class B Push Pull Power Amplifier using bipolar junction transistor was designed, simulated and its outputs were plotted. Optimum Load =.. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No:
Page no-44
Date:
Circuit Diagram for Half Wave Rectifier:
Circuit Diagram for Full Wave Rectifier:
Exp.No:
Page no-45
Date:
CHARACTERISTICS OF HALF WAVE AND FULL WAVE RECTIFIERS ---------------------------------------------------------------------------------------------Aim: To study the characteristics of half wave and full wave rectifier and plot its output characteristics. Components Required: S.No 1 2 3 4 5 6 7 8 9 10 Theory: Rectifier changes ac to dc and it is an essential part of a power supply. The unique property of a diode permitting the current to flow only in one direction is utilized rectifiers. Half wave rectifier: Mains power supply is applied at the primary of the step down transformer. The entire positive half cycles of the stepped down ac supply pass through the diode and the entire negative half cycles get eliminated. For a half wave rectifier, V rms = V m / 2; Where, Resistors Diodes Bread Board Step down transformer Voltmeter Ammeter CRO Probe Connecting wires Power meter Description Range(s) Type Quantity
VDC = V V rms VDC Vm
= rms value of input = Average value of the input = Peak value of output
1/2
Ripple factor r = ((V values.
rms
/ VDC 2) 1)
. It can be seen that r=1.21 by substituting the
Exp.No: Model Graph:
Page no-46
Date:
Exp.No: Full wave rectifier:
Page no-47
Date:
During the +ve half cycles of secondary voltage, the diode D1 is forward biased and D2 is reverse biased. Then current flows through the diode D1, load resistor (RL) and upper half of the transformer winding. During ve half cycles, diode D2 becomes forward biased and D1 becomes reverse biased. Then current flows through the diode D2, load resistor (RL) and lower half of the transformer winding. Load current in both the cases is in same direction. For a full wave rectifier, V
rms
=V
/ 2
VDC = 2V V rms VDC Vm
Where,
= rms value of input = Average value of the input = Peak value of output
1/2
Ripple factor r = ((V values. Procedure:
rms
/ VDC 2) 1)
. It can be seen that r=0.48 by substituting the
1. Wire the half wave rectifier circuit after testing all the components using a multimeter. 2. Switch ON mains supply. Observe the transformer secondary voltage waveform and output voltage waveform across the load resistor, simultaneously on the CRO screen. Note down the peak values. 3. Calculate the ripple factor using the expression. 4. Repeat the above steps to full wave rectifier circuit.
Exp.No: Observation: Half Wave Rectifier:
Page no-48
Date:
Without Filter
S.No 1
Amplitude in volts
Time in mS
With Filter
S.No 1
Amplitude in volts
Time in mS
Full Wave Rectifier:
Without Filter
S.No 1
Amplitude in volts
Time in mS
With Filter
S.No 1
Amplitude in volts
Time in mS
Exp.No:
Page no-49
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the characteristics of half wave and full wave rectifier were studied and its output characteristics were drawn.
Ripple factor of half wave rectifier = Ripple factor of full wave rectifier = . Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No: Circuit Diagram:
Page no-50
Date:
Model Graph:
Exp.No:
Page no-51
Date:
SERIES VOLTAGE REGULATOR USING TRANSISTORS ---------------------------------------------------------------------------------------------Aim: To design, simulate and set up a series voltage regulator using transistors and to plot its output characteristics.
Components Required:
S.No 1 2 3 4 5 6 7 8 Theory: Transistor Resistors
Description
Range(s)
Type
Quantity
Bread Board Zener Diode Power supply Voltmeter Multimeter Connecting wires
Figure shows a simple series voltage regulator using a transistor and Zener diode. The circuit called a series voltage regulator because the load current passes through the series transistor Q1 as shown in figure. The unregulated DC supply is fed to the input terminals and the regulated output is obtained across the load. The Zener diode provides the reference voltage. Operation: The base voltage of transistor Q1 is held to a relatively constant voltage across the Zener diode. For example, if 8V Zener (VZ=8V) is used the base voltage of Q1 will remain approximately 8V. V
out
= VZ - VBE
Case (i): If the output voltage decreases, the increased base-emitter voltage causes transistor Q1 to conduct more, thereby raising the output voltage. As a result, the output voltage is maintained at a constant level. Case (ii): If the output voltage increases, the decreased base-emitter voltage causes transistor Q1 to conduct less, thereby reducing the output voltage. Consequently, the output voltage is maintained at a constant level.
Page no-52
Date:
Line Regulation:
S.No 1 2 3 4 5 6 7 8 9 10
Vin (Volts)
VO (Volts)
Load Regulation:
S.No 1 2 3 4 5 6 7 8 9 10
IL (milli Amps )
VL (Volts)
Exp.No:
Page no-53
Date:
The advantage of this circuit is that the changes in Zener current are reduced by a factor . Therefore, the effect of Zener impedance is greatly reduced and much more stabilized output is obtained. Load regulation: The load regulation is the change in the regulated output voltage when the load current is changed from minimum (no load) to maximum (full load). Load regulation is denoted by LR and it is expressed as LR = VNL V Where, VNL = Load voltage with no load current V
FL= FL
Load voltage with full load current % Load Regulation = ((VNL V

FL)
/V
FL)
100
Line regulation: The line regulation is the ratio of change in output voltage to the input voltage. The % line regulation is given by,
% Line Regulation= ((Change in output Voltage) / (Change in input voltage)) 100
Procedure: Line Regulation 1. Make the connections as per the circuit diagram. 2. Remove the load resistor, vary the input voltage (Vi) and measure the corresponding output voltage (VO). 3. Plot VO versus Vi which gives line regulation curve. 4. Calculate the percentage line regulation.
Load Regulation 1. Make the connections as per the circuit diagram. 2. Keeping the input voltage constant, vary the load resistance and measure the corresponding load current and load voltage. 3. Plot the load regulation characteristics (VL versus IL). 4. Mark the no load and full load output voltages on this graph. 5. Calculate the percentage load regulation
Limitations: (i) Although the changes in Zener current are much reduced yet the output is not absolutely constant. It is because both VBE and VZ decrease with the increase in room temperature. (ii) The output voltage cannot be changed easily as no such means is provided. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No: Design:
Page no-54
Date:
A series voltage regulator is required to supply a current of 1 Amps at a constant voltage of 6V. If the supply voltage is 10V and the Zener operates in the breakdown region, design the circuit. Assume =50, VBE=0.5V and minimum Zener current = 10mA. The design steps require the determination of breakdown voltage and current limiting resistance RS. (1) Zener breakdown voltage: The collector-emitter terminals are in series with the load. Therefore, the load current must pass through the transistor.
Collector current (IC) = 1A Base current (IB) Output Voltage Vout 6 VZ = IC / = 1 / 50 = 20 mA = VZ - VBE = VZ 0.5 = 6.5 V
Hence zener diode of break down voltage 6.5 is required (2) To find the value of RS: Voltage across RS RS =V
in
- VZ
= 10 6.5 = 3.5 V = Voltage across RS / (IB + IZ) = 3.5 V / (20 + 10) mA RS = 117
Exp.No:
Page no-55
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the series voltage regulator using transistors was designed, simulated and its output characteristics were drawn.
% Load Regulation =. % Line Regulation =. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No:
Page no-56
Date:
Circuit Diagram:
Model Graph:
Exp.No:
Page no-57
Date:
SHUNT VOLTAGE REGULATOR USING TRANSISTORS ---------------------------------------------------------------------------------------------Aim: To design, simulate and set up a shunt voltage regulator using transistors and to plot its output characteristics.
Components Required: S.No 1 2 3 4 5 6 7 8 Transistor Resistors Bread Board Zener Diode Power supply Voltmeter Multimeter Connecting wires Description Range(s) Type Quantity
Theory: A Shunt voltage regulator provides regulation by shunting current away from the load to regulate the output voltage. The voltage drop across series resistance depends upon the current supply to RL. The output voltage is equal to the sum of zener voltage (VZ) and transistor base-emitter voltage (VBE). V
out
= VZ + VBE
If the load resistance decreases, the current through base of the transistor decreases. As a result, the less collector current is shunted. Therefore the load current becomes larger, thereby maintaining the regulated voltage across the load. Reverse happens should the load resistance increase. Load regulation: The load regulation is the change in the regulated output voltage when the load current is changed from minimum (no load) to maximum (full load). Load regulation is denoted by LR and it is expressed as LR = VNL V Where, VNL = Load voltage with no load current V
FL= FL
Load voltage with full load current % Load Regulation = ((VNL V

FL)
/V
FL)
100
Page no-58
Date:
Line Regulation:
S.No 1 2 3 4 5 6 7 8 9 10
Vin (Volts)
VO (Volts)
Load Regulation:
S.No 1 2 3 4 5 6 7 8 9 10
IL (milli Amps )
VL (Volts)
Exp.No: Line regulation:
Page no-59
Date:
The line regulation is the ratio of change in output voltage to the input voltage. The % line regulation is given by,
% Line Regulation= ((Change in output Voltage) / (Change in input voltage)) 100
Drawbacks: A shunt voltage regulator has the following drawbacks; 1. A large portion of the total current through RS flows through transistor rather than to the load. 2. There is a considerable power loss in RS. 3. There are problems of over voltage protection in this circuit.
Procedure: Line Regulation 1. Make the connections as per the circuit diagram. 2. Remove the load resistor, vary the input voltage (Vi) and measure the corresponding output voltage (VO). 3. Plot VO versus Vi which gives line regulation curve. 4. Calculate the percentage line regulation.
Load Regulation 1. Make the connections as per the circuit diagram. 2. Keeping the input voltage constant, vary the load resistance and measure the corresponding load current and load voltage. 3. Plot the load regulation characteristics (VL versus IL). 4. Mark the no load and full load output voltages on this graph. 5. Calculate the percentage load regulation.
Exp.No:
Page no-60
Date:
Exp.No:
Page no-61
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the shunt voltage regulator using transistors was designed, simulated and its output characteristics were drawn.
% Load Regulation =. % Line Regulation =. Electronic Circuits I Lab Vidyaa Vikas College of Engineering and Technology
Exp.No:
Page no-62
Date:
Design a Darlington pair amplifier circuit for the given specifications VCC = 12 V IE =1mA S = 10 hfe = 100 f = 50 Hz
AV 1, A1= A11 * A12 hfe1 = hfe2; Apply KVL to output loop, VCC VCE = VCE + VE = VCC / 2 = 12 / 6 = 6V VCE From equation (1), 12 VE VE RE RE S = 6 + VE = 12 6 = 6V = I E RE = VE / IE = 6 / 110 =6K
-3
A1= (hfe) 2
-----
(1)
= 6V
-----
(2)
---------
(3) (4)
-----
(5)
The Stability factor (s), = (1+ ) (1+ (RB / RE)) 1+ + (RB / RE) Solving the above equation we get, S 10 RB = 1+RB / RE = 1+RB / RE = (10-1) RE = (10-1) *(6103) RB = 54 K Vidyaa Vikas College of Engineering and Technology
Exp.No:
Page no-63 DARLINGTON PAIR AMPLIFIER
Date:
-----------------------------------------------------------------------------------------Aim: To design, simulate and test a performance of a Darlington Pair amplifier and to plot its frequency response characteristics. Components Required: S.No 1 2 3 4 5 6 7 8 9 Theory: In some occasions, the current gain and input impedance often an emitter follower are insufficient to meet the requirement. In order to increase, the overall values of circuit gain (Ai) and the input impedance, two transistors are connected in series in emitter follower configuration such a circuit is known as Darlington amplifier. Note that emitter of the first transistor is connected to the base of the second transistor and the collector terminals of the two transistors are connected together. Transistor Capacitors Resistors Power Supply Bread Board Signal Generator CRO Probe Connecting wires Description Range(s) Type Quantity
Exp.No: To find VB: VB
Page no-64
Date:
= VBE + VE = 0.7 + 6 = 6.7 V
To find R1 and R2: VB R1 + R2 RB R1 + R2 VCC R2 / VB R1 = VCC R2 / R1 + R2 = VCC R2 / VB = R1 R2 / R1 + R2 = R1 R2 / RB = R1 R2 / RB = RB VCC / VB = (54103) * 12 / 6.7 R1 We know that, RB Sub. RB = 54 K = R1 R2 / R1 + R2 in above equation,
3
---------------------
(1) (A) (2) (B)
From the Equations A and B, (LHS = RHS)
= 97 K
and R1 = 97 K
5410 = 97103 * R2 / 97103 + R2 Solving the above equation we get, R2 = 122 K To find Ci and C0: Ci Zi h re h
ie ie
120 K
= XCi = Zi / 10 = R1 ll R2 ll hie =h
fe
re
= VT / IE = 2610-3 / 110-3 = 26 = 100 26 = 2.6 K = R1 ll R2 ll hie / 10 = 54 K ll 2.6 K / 10 ----RB = R1 R2 / R1 + R2 = 54 K
XCC
XCC XCC CC
= 250 = 1/ 2f CC = 1/ (23.1450250) = 1210-6 = 12 f
Ci XC0 XC0 XC0 C0
10 f = 1/ 2f C0 = Z0 /10 = R
3 E
/ 10
= 6 10 / 10 = 600 = 1/ (23.1450600) = 5.310-6 = 5.3 f
C0
5f Vidyaa Vikas College of Engineering and Technology
Exp.No:
Page no-65
Date:
The result is that emitter current of the first transistor is base current of the second transistor. Therefore, the current gain of the pair is equal to product of individual current gains i.e., = 1 2
Here the high current gain is achieved with the minimum use of components. The biasing analysis is similar to that for one transistor except that two VBE drops are to be considered. Thus, Voltage across R2, V2 = VCC R2 / (R1 + R2) Voltage across RE, VE = V2 - 2 VBE Current through RE, IE2 = V2 - 2 VBE / RE Since the transistors are directly coupled, IE1 = IB2. Now, IB2 = IE2 / 2, IE1 = IE2 / 2. In practice, the two transistors are put inside single transistor housing and three terminals E, B and C are brought out as shown in figure. This three terminal device is known as Darlington transistor. The Darlington transistor acts like a single transistor that has high current gain and high input impedance. IE1 = IE2 / 2. Applications: When emitter follower cannot provide the required high input impedance and current gain, the Darlington amplifier is used. Procedure:
1. Set up the circuit on the breadboard. Check the DC conditions and apply the input sinusoidal signal from signal generator to the gate. 2. Obtain the amplified output. Take the output amplitude for various frequencies for at the input. 3. Plot the frequency response curve. Find the bandwidth of the FET amplifier.
Page no-66
Date:
V
S.No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Model Graph: Darlington amplifier Frequency in Hz Vo in Volts
in
Exp.No:
Page no-67
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the Darlington Pair amplifier was designed, simulated and its frequency response characteristics were drawn. Band Width of the Amplifier (BW) = fH - fL.
Exp.No:
Page no-68
Date:
Design a Class A power amplifier for the given specifications
RL = 220
Pa = 500mW = 0.5Watts
Output power
(Po) Po 8 RL
= VCC 2 / 8 RL = VCC 2 = VCC 2 = 880 = 30V
0.5 (8220) VCC 2 VCC Apply KVL to output loop, VCE
= VCC / 2 = 30 / 2 = 15V
VCE VCC VCC - VCE IL
= 15V = IL RL + VCE = IL RL = VCC - VCE / RL = (30 15) / 220 = 0.07 Amps
The Collector Power is given by, PC = VCC IL = 30 0.07 = 2 Watts The Maximum output power is given by, PO
(max)
= Vo 2 / RL = (15)2 / 220 = 1 Watts
Exp.No:
Page no-69 CLASS A POWER AMPLIFIER
Date:
-----------------------------------------------------------------------------------------Aim: To design, simulate and test a performance of a Class A power amplifier and to plot its frequency response characteristics. Components Required: S.No 1 2 3 4 5 6 7 8 9 Transistor Capacitors Resistors Power Supply Bread Board Signal Generator CRO Probe Connecting wires Description Range(s) Type Quantity
Theory: Class A Amplifiers The power amplifier is said to be class A amplifier if the Q point and the input signal are selected such that the output signal is obtained for a full input cycle. Key Point: For this class, position of the Q point is approximately at the midpoint of the load line. For all values of input signal, the transistor remains in the active region and never enters into cut-off or saturation region.
Exp.No: The input power is given by, Pin Vi Zi h re h Zi Pin The Efficiency is given by. = (PO
ie ie
Page no-70
Date:
= Vi 2 / Zi = 0.2 Volts = R1 ll R2 ll hie =h

fe
re
= VT / IE = 2610-3 / 110-3 = 26 = 100 26 = 2.6 K = 19.25 = 0.2

2
/ 19.25 = 2mWatts
(max)
/ PC) 100
= (1 /2) 100 = 50 %
Exp.No:
Page no-71
Date:
When an A.C. input signal is applied, the collector voltage varies sinusoidally hence the collector current also varies sinusoidally the collector current flows for 360 (full cycle) of the input signal. In other words, the angle of the collector current flow is 360 i.e. one full cycle. The current and voltage waveforms for a class A operation are shown with the help of output characteristics and the load line, in the Figure. As shown in the Figure, for full input cycle, a full output cycle is obtained. Here signal is faithfully reproduced, at the output, without any distortion. This is an important feature of a class A operation. The efficiency of class A operation is very small. Procedure: 1. Test all the components using a multimeter. Set up the circuit and verify dc biasing conditions. To check the dc biasing conditions, remove input signal and capacitors in the circuit. 2. Connect the capacitors in the circuit and apply a sinusoidal signal from signal generator to the circuit input. Observe the input and output waveforms on the CRO screen simultaneously. 3. Keeping the input amplitude constant vary the frequency of the input signal from 0 Hz to 1 MHz. Measure the output amplitude corresponding to different frequencies and enter it in tabular column. 4. Plot the frequency response characteristics on a semi-log graph sheet with gain on Y-axis and log (f) on X-axis. Mark log (fL) and log (fH) corresponding to 1/ 2 times of the maximum gain. 5. Calculate the bandwidth of the amplifier using the expression BW = fH - fL.
Page no-72
Date:
V
S.No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Frequency in Hz Vo in Volts
in
Model Graph: Class A Amplifier
Exp.No:
Page no-73
Date:
Max. Marks 30 40 10 20 100
Marks Secured
Result: Thus the Class A amplifier was designed, simulated and its frequency response characteristics were drawn. Band Width of the Amplifier (BW) = fH - fL.
Exp.No:
Page no-74
Date:
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Exp.

SYMBOLS AND PIN DIAGRAMS

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

CIRCUIT SIMULATION USING ORCAD SIMULATION TOOL -------------------------------------------------------------------------------------

Note: 1. Simulation of mandatory. all the experiments using ORCAD tool is

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

(A) Circuit Arrangement for Base resistor or fixed biasing technique:

VCC = 15V S S S =+1 = 100+1 = 101 = IC / = 210-3 / 100 = 0.02 mA ----

= IC RC + VCE. = VCC - VCE / IC = (15-8) / 210-3

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

To find R1 and R2: VB R1 + R2 RB R1 + R2 = VCC R2 / R1 + R2 = VCC R2 / VB = R1 R2 / R1 + R2 = R1 R2 / RB --------------------(1) (A) (2) (B)

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Exp.No: RB = R1 R2 / R1 + R2 VBE = VB - VE VB = VBE + VE VB = VBE + IE RE IE = VB VBE / RE (Or) IC = VB VBE / RE

Page no-7 ------(3) VE = IE RE

(4) IE IC (IE = IC + IB (IB Negligible))

Fig 1.1.2: CE amplifier circuit with Voltage divider bias

Page no-8 and R1 = 35.29 K

= 100 26 = 2.6 K ----/ 10 R1 ll R2 = R1 R2 / R1 + R2 = 35.29K *7.3K 35.29K +7.3K =6K

XCC = R1 ll R2 ll hie / 10 =6K XCC CC ll 2.6 K

XCC= 0.182 K = 1/ 2f CC = 1/ (23.141000.18210 ) = 8.7410-6 = 8.74 f CC XCE XCE CE CE 10 f = Z0 /10 = R =R

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Exp.No: Note: R2 = 0.1 RE To find load resistance: RL = VCC VE / 2 IE

To find the value of coupling capacitor: CC = 1/ 2f XCC Where, XCC = Zi / 10 = R Zi = R1 ll R2 ll h h

To find the value of bypass capacitor: CE = 1/ 2f XCE Where XCE= R

Description Preparation Performance Viva Voce Record Total Staff Signature

Max. Marks 30 40 10 20 100

Solving the above equation,

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Exp.No: To find CS: XCS XCS CS

= RS / 10 = 0.6103 /10 = 60 = 1/ 2f XCS = 1/ (23.1410060)

Gain (A) = gm (RD ll RL) Required gain: 10 RL = 4.7 K

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Exp.No: Circuit Analysis: To find RS: Voltage across RS, VS = ID RS

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

To find the value of coupling capacitor: XCC1 RG CC1 = RG / 10 = R1 R2 / R1 + R2 = 1/ 2f XC1

To find the value of Source capacitor: XCS CS = RS / 10 = 1/ 2f XCS

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Exp.No: To find RD: VDD 30 30 17 RD RD XCC1 RG XCC1 CC1 CC1 XCS

To find the value of coupling capacitor:

To find the value of Source capacitor:

= 500 = 1/ (2*3.14*100*500) = 3.2 f 4.7 f

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

Description Preparation Performance Viva Voce Record Total Staff Signature

Max. Marks 30 40 10 20 100

Electronic Circuits I Lab

Vidyaa Vikas College of Engineering and Technology

(=100) is more than

Design of voltage divider R1 and R2 I B = IC / h = 210-3 / 100 = 20 A

= 500 = 1/ (23.14100*500) = 3.2 f 4.7 f