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Tip cn lp trnh cho FPGA t Spartan -3

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M U

Trong nhng nm gn y, k thut in t lin tc c nhng tin b vt
bc, c bit l trong nhng k thut vi in t. Khi kch thc v phc tp ca
cc h thng s ngy cng gia tng, rt nhiu cng c thit k c tr gip bi
my tnh c a vo qu trnh thit k phn cng. H tr mnh m cho
phng php thit k ny l nhng ngn ng m t phn cng HDL. Ni n HDL
tc l chng ta cp n cng ngh thit k ASIC hay cn gi l IC chuyn
dng.
nc ta, do nhu cu v cng ngh ASIC cn cha cao trong khi vic mua
sn cc DSP a nng khng phi l iu kh khn. Tnh hnh s hon ton thay i
trong tng lai khi nhu cu v bo mt, c lp v t ch cng ngh in t - vin
thng phc v cng cuc cng nghip ho v hin i ho t nc tng ln nhanh
chng. Vic ng dng rng ri cng ngh ASIC trong tng lai gn s l mt iu
c th d on trc. Do vy, vic tm hiu v cng ngh ASIC c th lm ch
cc ng dng trong cng nghip l mt vic lm hon ton cn thit. Hn th na,
nhng hiu bit su sc v cc c tnh k thut trong cng ngh ASIC khng
nhng ch c ngha ring i vi cc lnh vc in t - Vin thng, Cng ngh
thng tin ni chung m cn c ngha c bit quan trng trong lnh vc an ninh,
quc phng.
Cng ngh FPGA (Field-Programmable Gate Array) xut hin nh mt
gii php c bn cho vn tranh th thi gian v chi ph ban u thp. N cho
php ch to ngay v gi thnh sn phm thp, to nn sc cnh tranh ln trn th
trng. FPGA l mt thit b cu trc logic c th c ngi s dng lp trnh trc
tip m khng phi s dng bt k mt cng c ch to mch tch hp no. FPGA
c cng ty Xilinx gii thiu u tin vo nm 1985. Hin nay FPGA c
nhiu cng ty pht trin l AcTel, Altera, Plus Logic, AMD,
Vit Nam, trong mt s nm gn y, vic nghin cu v FPGA t c
nhng thnh tu nht nh c bit trong cc lnh vc nh x l tn hiu Raa, cc
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lnh vc bo mt in thoai.... Trn mt s din n, ngi ta gii thiu rt nhiu
v FPGA, v cng ngh lp trnh Ram tnh, cu tr nghch. Vi nhng ngi b
ra khong thi gian khng nh nghin cu v lnh vc ny th c th nhng
thng tin hon ton hnh dung ra vn , xong nhng ngi ang c nh
tm hiu th qu thc vi nhng thng tin hiu ra c th cng li phi mt
mt khong thi gian kh di.
Cun sch Tip cn lp trnh cho FPGA t Spartan -3 vi mc ch
cung cp nhng thng tin cn thit nht v cng ngh FPGA v c bit cung cp
cho cc i tng ang c nhu cu tm hiu v cng ngh ny c kh nng tip cn
mt cch nhanh chng vi cch thc lp trnh cho mt FPGA c th. Cun sch bao
gm 5 chng:
Chng I: Gii thiu v cng ngh ASIC
Chng II: Gii thiu mt s cng ngh mi lin quan n thit k ASIC hin
nay Cng ngh FPGA .
Chng III: Gii thiu bo mch Spartan-3 starter kid board v mi trng lp
trnh ISE 7.1
Chng IV: S lc v ngn ng VHDL
Chng V: Cc bi ton thit k v giao tip
Trong ngi c c th c lt qua cc chng I v II tm kim mt vi
thng tin mong mun. Chng III c bit phi quan tm v y l mt FPGA c
th. Chng IV gii thiu s lc v ngn ng VHDL, thc ra v ngn ng VHDL
c rt nhiu sch cp ti. Tuy vy, chng ta ch cn nm lng thng tin
chng ny sau c k tng bi ton chng V s gip chng ta c iu kin
hiu r hn v ngn ng. Chng V s l cc bi ton t d n kh, vi 6 bi tp
chng ta hon ton lm ch c bo mch, v v vy, vi cc bi ton bt k ch cn
cn c vo thut ton l chng ta hon ton c th trin khai thc hin c.
Do trnh cn hn ch v vy khng trnh khi nhng khim khuyt rt
mong nhn c cc kin ng gp t ngi c. Cun sch ny c s dng kh
nhiu chi tit t lun vn cao hc ca anh L Hi Triu HBK H Ni.
Tip cn lp trnh cho FPGA t Spartan -3

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CHNG I: CNG NGH ASIC

1.1. Cc hng tip cn thit k ASIC
1.1.1. Cc cng ngh lp trnh thit k ASIC
Tm tt cc cng ngh lp trnh cho ASIC c trnh by trong bng di
y.
Bng1.1. Cc c tnh cng ngh lp trnh thit k ASIC
Cng ngh lp trnh Tnh
bay hi
C th
lp trnh
Din tch ca
ASIC
in tr
(ohm)
in
dung
(pF)
Cc phn t RAM tnh C Trong
mch
Ln 1 - 2K 10 - 20
Lp trnh cu ch
nghch PLICE (PLICE
Anti-fuse)
Khng Khng Anti-fuse nh
S tranzitor
ln
300 - 500K 3 - 5
Lp trnh cu ch
nghch ViaLink
(ViaLink Anti-fuse)
Khng Khng Anti-fuse nh
S tranzitor
ln
50 - 80K 1 - 3
EPROM Khng Ngoi
mch
Nh 2 - 4K 10 - 20
EEPROM Khng Trong
mch
2xEPROM 2 - 4K 10 - 20
1.1.2. Thit k logic ASIC u vo (Logic Design Entry)
Mc ch ca thit k u vo l m t mt h thng vi in t da trn cc
cng c ca h t ng thit k in t EDA (Electronic-Design Automation). Cc
Tip cn lp trnh cho FPGA t Spartan -3

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h thng in t c xy dng da trn cc thnh phn tnh, nh l cc IC TLL.
Thit k u vo i vi cc h thng ny chnh l cng vic v cc mch v tng
hp dng gin . Gin th hin cc thnh phn c kt ni vi nhau nh th
no, chnh l lin kt ca mt ASIC. Phn ny ca qu trnh thit k u vo
c gi l u vo gin , hoc l bt gin . Mt gin mch m t mt
ASIC ging nh l mt bn thit k cho mt cng trnh xy dng.
Gin mch l mt bn v, l mt khun dng n gin chng ta c th
hiu v s dng, nhng cc my tnh cn lm vic vi cc phin bn ASCII hoc
cc tp nh phn m chng ta gi l netlist (i dy). u ra ca cng c thit k gin
chnh l mt file netlist m c cha m t ca tt c cc thnh phn trong mt
bn thit k v cc ng kt ni ca chng.
Khng phi tt c cc thng tin thit k c th chuyn thnh gin mch
hoc netlist, v khng phi tt c cc chc nng ca mt ASIC u c m t qua
thng tin kt ni. V d, gi s chng ta s dng mt ASIC lp trnh c cho mt
vi chc nng logic ngu nhin. Mt phn ca ASIC c th c thit k bng cch
s dng ngn ng lp trnh dng vn bn. Trong trng hp ny thit k u vo
cng gm c c vit m ngun. Vy iu g nu mt ASIC trong h thng ca
chng ta c cha mt PROM (Programmable Memory)? Phi chng vi m lnh l
mt phn ca thit k u vo? Vic iu hnh h thng ca chng ta chc chn l
ph thuc vo chng trnh chun ca PROM. V vy c l m lnh PROM phi l
mt phn ca thit k u vo. Mt khc khng ai coi m lnh h iu hnh c
np vo RAM trn mt ASIC l mt phn ca thit k u vo. R rng l c nhiu
dng thit k u vo khc nhau. Trong mi mt trng hp n rt quan trng
bo m l bn hon thnh ch nh cho h thng - khng ch l xy dng cu trc
chnh xc m cn bt k ai cng hiu c l h thng lm vic nh th no.
Thit k u vo l mt trong nhng phn quan trng nht ca cng ngh ASIC.
Cho n hin hay th hu ht cc thit k u vo cho ASIC vn s dng
phng php gin u vo. Do ASIC ngy cng tr nn phc tp hn, cc
phng php thit k u vo khc ngy cng tr nn ph bin. Cc phng php
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thit k u vo u c th s dng phng php ho, chng hn l mt gin ,
hoc cc tp dng text di dng ngn ng lp trnh. Vic s dng ngn ng m t
phn cng HDL (Hardware Description Language) cho mc ch thit k u vo
cho php chng ta to ra cc netlist trc tip bng cch tng hp logic. Chng ta s
cp n cc phng php thit k u vo mc thp cng vi cc u im cng
nh nhc im ca chng trong mc 2.3.
Thit k u vo bao gm cc thnh phn thit k sau:
- Thit k th vin ASIC.
- Thit k th vin cc vi mch ASIC lp trnh c (Programmable ASIC).
- Thit k phn t logic ASIC lp trnh c.
- Thit k phn t vo/ra ASIC lp trnh c.
- Thit k phn t kt ni ASIC lp trnh c.
Phn mm thit k ASIC lp trnh c:
- Thit k logic mc thp u vo (low-level design entry) s dng
VHDL: B Quc Phng M (The U.S. Department of Defence - DoD)
h tr vic pht trin ngn ng VHDL (VHSIC Hardware Description
Language) nh mt phn ca chng trnh quc gia VHSIC (Very High-
Speed IC) vo u thp k 80.
- Tng hp logic (logic synthesis): Tng hp logic cung cp lin kt gia
mt tp HDL (VHDL hoc Verilog) v mt netlist tng t nh cch m
mt b bin dch C cung cp lin kt gia m lnh chng trnh C v ngn
ng my.
- M phng (simulation): Cc k s quen vi cc h thng mu dng
kim tra sn phm thit k ca h, thng thng s dng mt th
mch mu, cho php cm cc IC v cc dy dn ln. th mch mu c
th thc hin c khi c cho php xy dng h thng t mt vi IC TTL.
Tuy nhin iu ny l phi thc t i vi thit k ASIC. Do vy hu ht cc
k s thit k ASIC u s dng phng php m phng tng ng
thay cho m hnh th mch.
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- Th nghim mc logic (test): Cc ASIC c th nghim theo hai giai
on trong qu trnh sn xut bng cch s dng cc phng php th
nghim sn xut.
1.1.3. Thit k vt l (Physical Design)
Hnh 1.1 biu din mt phn ca s thit k, l cc bc thit k vt l
i vi mt ASIC.

Hnh 1.1. Mt phn ca thit k ASIC gm c phn chia h thng, ln s
mt bng, sp xp cc phn t v cc bc nh tuyn ng kt ni.
u tin chng ta p dng vic phn chia h thng chia mt h thng vi
in t thnh cc ASIC. Trong phn ln s mt bng chng ta s nh gi kch
thc v t cc v tr lin quan ca cc khi trong ASIC (i khi cn c gi l
xp chip - chip planning). Cng thi im ny chng ta nh v khong trng cho
ng xung nhp v ngun v quyt nh v tr ca cng I/O. Vic sp xp nh
ngha v tr ca cc phn t logic cng vi s linh hot ca cc khi v khong
trng dnh cho vic ni cc phn t logic. Vic sp xp i vi thit k ma trn
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cng (gate-array) hoc phn t tiu chun (standard-cell) b tr mi mt phn t
logic vo v tr trong cng mt hng. Vic ln s mt bng v sp xp phn t
i khi c th s dng cng c CAD. Vic nh tuyn thc hin ng kt ni gia
cc phn t logic. Vic nh tuyn l mt vn rt kh v thng c phn chia
thnh cc bc ring bit c gi l nh tuyn ton cc v nh tuyn cc b.
nh tuyn ton cc xc nh cc kt ni gia cc phn t logic t ch v cc
khi s t ch u. Cn nh tuyn cc b l mc nh tuyn c th v chi tit
n tng phn t.
1.1.4. Cc cng c CAD (CAD Tools)
pht trin mt cng c CAD cn thit phi chuyn i mi mt bc trong
thit k vt l thnh cc vn c mc ch v nh hng r rng. Mc ch l
nhng g chng ta cn phi thc hin, cn nh hng l cch thc hin mc ch.
V d trong cc bc thit k vt l ASIC th cc mc ch v nh hng nh sau:
Phn chia h thng (System partitioning):
- Mc ch: Phn chia mt h thng thnh mt s cc ASIC.
- nh hng: Ti thiu ho s lng cc kt ni ngoi gia cc ASIC. Gi
cho mi ASIC nh hn kch thc cc i.
Ln s mt bng (Floorplanning):
- Mc ch: Tnh ton kch thc ca tt c cc khi v sp xp v tr ca
chng.
- nh hng: Bo m s lin kt cao gia cc khi v mt t nhin cng
gn cng tt.
Sp xp cc phn t (Placement):
- Mc ch: Sp xp vic kt ni gia cc vng v v tr ca tt c cc phn
t logic cng vi cc khi linh hot.
- nh hng: Ti thiu ho cc vng ASIC v mt kt ni.
nh tuyn ton cc (Global routing):
- Mc ch: Quyt nh v tr ca tt c cc kt ni.
- nh hng: Ti thiu ho ton b vng kt ni c s dng.
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nh tuyn chi tit (Detailed routing):
- Mc ch: Hon thnh nh tuyn tt c cc kt ni trn chip.
- nh hng: Ti thiu ho tng s di kt ni c s dng.
1.2. Thit k ASIC u vo (design entry)
1.2.1. Thit k th vin ASIC
Th vin phn t l mt phn chnh trong thit k ASIC. i vi mt ASIC
lp trnh c th mt cng ty chuyn v PLD, FPGA cung cp cho chng ta mt
th vin cc phn t lgic di hnh thc mt b kit thit k, thng l chng ta
khng c mt s la chn no v gi ca n ni chung khong vi nghn la. i
vi MGAs v CBICs chng ta c ba la chn : nh cung cp ASIC (cng ty s xy
dng ASIC cho chng ta) s cung cp mt th vin phn t, hoc chng ta c th
mua mt th vin phn t t mt nh cung cp th vin th ba, hoc chng ta c th
t xy dng th vin phn t ca chnh mnh.
S la chn u tin, l s dng mt th vin ASIC ca nh cung cp, yu
cu chng ta phi s dng mt tp cc cng c thit k c cung cp bi nh
cung cp ASIC a vo v m phng thit k ca chng ta. Tc l chng ta phi
mua cc cng c v th vin phn t. Mt vi nh cung cp ASIC (c bit cho
MGAs) cung cp cc cng c c pht trin theo yu cu.
Th vin ca nh cung cp ASIC thng thng l mt th vin o - cc phn
t ch l cc khi trng rng, nhng n bao gm thng tin b tr s mch.
Sau khi chng ta hon thnh vic b tr s mch, chng ta a ra netlist n nh
cung cp ASIC h b sung vo cc phn t o trc khi bt u sn xut chip
cho chng ta.
Cc la chn th hai v ba yu cu chng ta thc hin mt quyt nh mua
bn. Nu chng ta hon thnh vic thit k mt ASIC s dng th vin phn t m
chng ta mua, th chng ta s hu vic ch to chip c s dng sn xut
ASIC ca chnh mnh. Nhng th vin phn t nh vy thng t (c th ln n
vi trm nghn la). Tuy nhin iu ny c ngha rng vic mua mt th vin t
c th r v lu di nu chng ta sn xut nhiu hn l cc gii php khc.
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La chn th ba s pht trin mt th vin phn t theo yu cu. Nhiu cng
ty my tnh v cng ty in t ln chn phng n ny. Hu ht th vin phn t
thit k hin nay vn tip tc c pht trin theo hnh thc yu cu mc d thc
t qu trnh pht trin th vin rt phc tp v t.
Tuy nhin to ra mi phn t trong mt th vin phn t ASIC phi bao
gm cc yu t sau:
- S b tr vt l
- M hnh hot ng
- M hnh Verilog/VHDL
- M hnh tnh ton thi gian chi tit
- Chin lc th nghim, kim tra
- S mch
- Biu tng ca phn t
- M hnh ti
- M hnh nh tuyn
1.2.2. Cc vi mch ASIC lp trnh c
C hai loi ASIC lp trnh c: Thit b logic lp trnh c - PLD
(Programmable Logic Device) v Ma trn cng lp trnh c theo hng - FPGA
(Field-Programmable Gate Array). Vic phn bit gia hai loi ASIC ny cha
c chun ho. S khc nhau thc t ch l s k tha ca chng. PLDs bt u t
nhng thit b nh dng th thay th mt mt phn ca h IC TTL, v chng
c pht trin tng t nh ngi anh em FPGA ca chng, ch khc nhau v
cng ngh ch to. Trong mc ny, chng ta s coi li c hai loi ASICs u l cc
ASIC lp trnh c.
Mt ASIC lp trnh c chnh mt chip m chng ta, nh mt ngi thit k
h thng, c th t lp trnh. Chng ta tin hnh thit k u vo v m phng. Tip
theo, mt phn mm c bit to ra mt chui cc bit m t thm m rng cc kt
ni theo yu cu thc hin thit k ca chng ta - gi l tp cu hnh. Sau ,
chng ta kt ni my tnh ti chip v lp trnh cho chip tun theo tp cu hnh.
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Tuy nhin cng ngh lp trnh c th c hoc c th khng lu di. Do vy
chng ta khng th xo b nhng lp trnh trong cc ASIC lp trnh c mt ln.
V th, ngy nay ngi ta thng s dng cc loi PLD v FPGA c kh nng lp
trnh li c.
1.2.3. Cc phn t logic ASIC lp trnh c
Tt c cc ASIC (hoc PLD hoc FPGAs) u cha mt phn t lgic c bn.
l ba kiu phn t lgic c bn khc nhau: (1) B dn knh c s; (2) Bng s
tht c s; (3) Phn t logic ma trn lp trnh c. Vic la chn gia cc phn t
ph thuc vo cng ngh lp trnh.
1.2.4. Cc phn t vo/ra ASIC lp trnh c
Tt c ASICs lp trnh c u cha mt vi kiu phn t Vo/Ra (I/O) no
. Cc phn t Vo/Ra iu khin mc lgic tn hiu vo - ra ca chip, nhn v
kim tra iu kin ca cc u vo t bn ngoi, cng nh bo v tnh in cho
chip.
Sau y l cc yu cu khc nhau ca cc loi phn t Vo/Ra:
- Ngun u ra DC: iu khin tr khng ti ti u ra DC hoc tn s thp
(thp hn 1 MHz). V d cc loi tr khng ti nh LED, r le, m-t loi nh
- Ngun u ra AC: iu khin dung khng ti tc cao (ln hn 1 MHz). V
d dung khng ti cc chip logic khc, bus d liu hoc bus a ch, cp ruy bng.
- Ngun u vo DC: v d cc ngun nh chuyn mch, cm bin, hoc cc
chip logic khc.
- Ngun u vo AC: v d cc ngun nh tn hiu logic tc cao (ln hn 1
MHz) t cc chip khc.
- Ngun to xung nhp u vo: v d l ng h xung nhp h thng hoc cc
tn hiu trn bus ng b.
- Ngun cung cp u vo: chng ta cn cp ngun cho phn t Vo/Ra v cc
phn t lgic bn trong chip, m in p khng b st hoc nhiu. Ngoi ra chng ta
c th cng cn mt ngun cung cp ring bit lp trnh cho chip.
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Cc ty chn i vi phn t Vo/Ra l: s khc nhau v mc ca ngun,
tnh tng thch vi TTL, cc u vo trc tip hoc phi c iu chnh, cc u
ra trc tip hoc phi c iu chnh, phi hp tr khng, bo v qu in p, iu
khin tc trn, v qut hn ch.
1.2.5. Cc phn t ASIC lin kt ni lp trnh c
Tt c ASIC u cha cc phn t lin kt ni lp trnh c. Cu trc v s
phc tp ca cc phn t lin kt ni phn ln c xc nh thng qua cng ngh
lp trnh v kin trc ca cc phn t lgic c bn. Cht liu m chng ta dng
xy dng cc phn t lin kt ni l hp kim nhm, loi hp kim c th chu c
xp x 50 mW/1 n v din tch v dung khng l 0.2 pFcm
-1
. Cc loi ASIC lp
trnh c i u tin c xy dng s dng cng ngh hai lp kim loi; cn cc
ASIC hin nay s dng ba lp kim loi hoc nhiu hn.
1.2.6. Phn mm thit k ASIC lp trnh c
C nm thnh phn cu thnh mt ASIC: (1) Cng ngh lp trnh, (2) Phn t
lgic c bn, (3) Phn t Vo/Ra, (4) Phn t lin kt ni, v (5) Phn mm thit k
cho php chng ta lp trnh ASIC. Phn mm thit k thng l b rng buc gn
gi hn vi kin trc PLD v FPGA hn cc kiu ASICs khc.
i vi bt k ASIC no th mt nh thit k cng cn phn mm thit k u
vo, mt th vin phn t, v phn mm thit k vt l. Mi mt nh cung cp
ASIC thng bn cc b kit thit k bao gm tt c phn mm v phn cng m
mt ngi thit k cn n. Rt nhiu b kit thit k ny s dng phn mm thit k
u vo ca mt cng ty khc. Thng th ngi thit k mua lun phn mm t
nh cung cp ASIC. Phn mm ny c gi l phn mm OEM (Original
Equipment Manufacturer). Tt c cc nh cung cp ASIC u c phn mm thit k
vt l ca ring mnh - v cc phn mm thit k nh vy mi c th ph hp vi
cc gii thut tng ng vi kin trc h.
Gin u vo khng phi l phng php duy nht thit k u vo cho cc
ASIC lp trnh c. Mt s nh thit k m t vic iu khin lgic v trng thi
my di dng cc phng trnh lgic v gin trng thi. Mt gii php khc na
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cho thit k ASIC l s dng mt trong s cc ngn ng m t phn cng (HDL)
da theo mt s tiu chun. C hai dng ngn ng thng dng. Th nht l cc
phn mm c pht trin t vic lp trnh cho cc ASIC loi PLD. l ABEL,
CUPL, v PALASM, l cc ngn ng n gin v d hc. Cc ngn ng ny rt
mng trong vic m t cc my trng thi v t hp lgic. Th hai l cc ngn ng
HDL bao gm VHDL v Verilog, l cc ngn ng bc cao hn v s dng phc
tp hn nhng chng c kh nng m t hon chnh cc ASICs v c mt h thng.
Sau khi hon thnh thit k u vo v to ra mt netlist, bc tip theo l vic
m phng. C hai kiu m phng thng c s dng cho thit k ASIC. Kiu m
phng u tin l m phng lgic theo hot ng, chc nng, v m phng thi
gian. Cng c ny c th pht hin bt k li thit k no. Ngi thit k cung cp
cc tn hiu u vo m phng v kim tra u ra theo yu cu.
Kiu m phng th hai, l kiu thng s dng nht trong thit k ASIC, l
mt cng c phn tch - tnh ton thi gian. Cng c phn tch - tnh ton thi gian
l mt thit b m phng tnh v b qua vic cung cp cc tn hiu u vo. Thay
vo cng c phn tch - tnh ton thi gian kim tra cc ng gii hn m
lm hn ch tc hot ng - cc ng tn hiu gy ra tr ln.
1.3. Thit k logic mc thp u vo (low-level design entry)
1.3.1. Gin u vo (Schematic Entry)
Gin u vo l phng php ph bin nht ca thit k u vo i vi
cc ASIC. Cc ngn ng HDL ang thay th cho cc gin u vo mc cng
thng thng, nhng cc cng c ho mi da trn cc gin u vo ngay nay
cng ang c s dng to ra mt s lng ln cc m ngun HDL.
Cc gin mch c v trn cc sheet gin . Kch thc tiu chun ca
cc sheet gin tun theo tiu chun ANSI A-E (ch yu dng M) v ISO A4-
A0 (ch yu dng chu u). Nh trn hnh 2.2 th hin 2 hnh ging ci ci mai
v ci xng, l cc biu tng c cng nhn ca cc cng AND, NAND,
OR v NOR.
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Hnh 1.2. IEEE khuyn ngh kch thc v cc k hiu cho cc cng logic.
(a) Cng NAND; (b) Cng OR-c nht.

Hnh 1.3. Cc thut ng c dng trong cc gin mch
Cc cng c v gin u vo cho thit k ASIC tng t nh thit k bo
mch in PCB (Printed-Circuit Board). Trn mt PCB thng ch c vi trm thnh
phn hoc phn t TTL hoc cc in tr, tranzitor hoc t in, cun cm... Nu
chng ta coi mt cng logic trn mt ASIC tng ng vi mt thnh phn trn
mt PCB, th mt ASIC c ln cha hng trm ngn thnh phn nh vy. Do vy
v ton b cc phn t ca mt ASIC l iu khng tng.
1.3.1.1. Thit k theo th bc (Hierarchical Design)
Vic thit k theo th bc s lm gim kch thc v phc tp ca mt gin
u vo. Mt gin in t c th cha cc gin con. Cc gin con cng
c th cha cc gin nh hn na.
Vic la chn thit k theo th bc l c th v c tt c cc thnh
phn ca mt ASIC trn mt gin cc ln khng c th bc dng thit k phng.
i vi mt ASIC i mi c cha hng ngn hoc nhiu hn na cc cng logic
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bng cch s dng thit k phng hoc gin phng l iu khng th thc hin
c. Do vy ngi ta phi phn cp thit k cho cc gin thit k u vo.
1.3.1.2. Th vin phn t (The Cell Library)
Cc thnh phn trong mt gin ASIC thng c chn t mt th vin
cc phn t logic. Cc phn t ca th vin cho tt c cc loi ASIC i khi cn
c bit n nh l cc khi modul (module).
Hu ht cc cng ty trong lnh vc ASIC u cung cp mt th vin cc phn
t vi cc cng c bn c s dng trong gin u vo.
C hai vn cn t ra i vi cc th vin gin ASIC l khng c qui
c v t tn v khng c tiu chun dnh ring cho hot ng ca phn t.
Trong th vin cc phn t th cc cng logic l cc phn t c bn, chng hn
nh cng NAND. Trong mt thit k phn cp ASIC th mt phn t c th l mt
cng NAND, mt mch flip-flop, mt b nhn hoc thm ch c th l mt b vi x
l. Chnh v vy m chng ta thy rng cc thut ng v phn t u c chp
nhn mt cch chung chung trong mt gin u vo nhiu khi gy ra s lm ln.
Thut ng phn t c dng biu din c cc phn t c bn v c cc gin
con. Mc d chng c khc nhau trn thc t nh chng vn c mi lin quan gn
gi, v c chp nhn dng chung.
1.3.1.3. Cc tn gi (Names)
Mi mt phn t, c th l phn t c bn hoc khng phi, khi c t vo
mt gin thit k ASIC u phi c tn. Mi phn t khi s dng u dng theo
mt tn duy nht v khng c trng lp trong gin u vo mc d chng c
th l bn sao chp ca nhau t cng mt th vin.
1.3.1.4. Cc biu tng v k hiu trn gin (Schematic Icons and
Symbols)
Hu ht cc chng trnh v gin u vo u cho php ngi thit k s
dng cc biu tng c bit hoc biu tng t to. Ngoi ra cng c v gin
u vo cng thng t ng to ra biu tng cho cc gin con dng trong
cc gin mc cao hn. y c gi l cc biu tng gc hoc k hiu gc.
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Cc ng kt ni ngoi ca gin con c t ng gn thm biu tng,
thng thng l mt hnh ch nht. V d v cc biu tng v k hiu i vi
mt phn t c tn l DLAT c cho trong hnh 2.4.

Hnh 1.4. Mt phn t v cc gin con ca n. (a) Mt th vin gin
cha cc biu tng dnh cho cc phn t c bn; (b) Mt gin con cho mt
phn t DLAT, cha tn ca cc phn t c bn; (c) Biu tng cho phn t
DLAT.
1.3.1.5. Cc ng ni (Nets)
Cc gin trn hnh 2.4 c cha c cc ng ni cc b v ng ni bn
ngoi. Nh trn hnh 2.4.b ng ni cc b l n1, ni gia mt phn t AND c
tn l and1 v mt phn t OR c tn l or1. Cn ng ni ngoi l ng ni
gia mt phn t vi mt ng ni khc, trn hnh 2.4.b l n3.
thun tin cho vic t tn cc ng kt ni trong mt gin phn cp
ngi ta s dng tn tin t ca phn t t tn cho ng ni. Cc k t c
bit (nh ; / $ # ...) khng c dng t tn cho ng ni. Tuy nhin
vic t tn thng l c thc hin t ng thng qua cng c v gin u
vo. Trong cc ngn ng HDL (VHDL v Verilog) c cch t tn cho ng ni
rt chnh xc v cht ch c tiu chun trong cc kin trc phn cp.
1.3.1.6. Cc u ni (Connections)
Cc phn t c cc u cui (terminal) l cc u vo hoc u ra ca phn t
. Cc u cui (terminal) cn c bit n di cc tn nh cc chn (pin), cc
u ni (connection), hoc l cc u tn hiu (signal). Thut ng chn (pin) c
s dng rt rng ri, tuy nhin y chng ta ch yu s dng thut ng u cui
trnh nhm vi thut ng chn (pin) trong mt ASIC ng gi. Ngoi ra thut
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ng chn (pin) cn thng c dng trong gin u vo v chng trnh nh
tuyn ng ni ch yu cho cc thit k PCB.

Hnh 1.5. V d v vic s dng bus n gin ho mt gin . (a) Cc
u ni A, B, C; (b) Cc u ni A, B, C v DQ0 - DQ7...
1.3.2. Cc ngn ng thit k mc thp (Low-level Design Languages)
Trong trng hp thit k ASIC th ngn ng ny rt quan trng. C hai vn
cn cp n l: vic thay i mt gin rt kh v vn cha c tiu chun i
vi cc k hiu v thng tin gin dng lu tr trong mt netlist. iu ny c
ngha l chng ta cn phi chuyn i t thit k mc thp m bn s dng thit
k PLD thnh mt hoc nhiu thit k ASIC tng ng. Thng thng th chng ta
nhp nhiu PLD thnh mt PLD n ln hn chnh l ASIC. chnh l ngn ng
thit k mc thp chuyn i v c hiu t cc PLD sang khun dng m bn
c th s dng c trong cc h thng thit k ASIC khc.
Mt s ngn ng nh sau:
- Ngn ng ABEL: ABEL l mt ngn ng lp trnh PLD t cc d liu I/O
(Data I/O).
- Ngn ng CUPL: CUPL l mt ngn ng thit k PLD t cc thit b logic
(Logical Devices).
nh dng EDIF:
y l mt tiu chun dng trao i thng tin gia cc cng c EDA vi
nhau l nh dng trao i ln nhau trong thit k in t - Electronic Design
Interchange Format - EDIF. Phin bn hay c s dng nht l EDIF 2 0 0 do
EIA (Electronic Industries Association - Hip hi cng nghip in t) pht hnh c
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tn l Tiu chun ANSI/EIA 548-1988 - cn c gi l EDIF 1988. Hin nay
c phin bn 3.0.0 v 4.0.0. Hu ht cc cng ty trong lnh vc EDA u h tr
chun EDIF. Cc cng ty chuyn v ASIC - FPGA l Altera v Actel u s dng
EDIF nh l khun dng netlist ca h v Xilinx cng thng bo h cng
cp n vic chuyn dn khun dng XNF ca h sang khun dng EDIF.
1.4. Tng hp logic (Logic Synthesis)
Tng hp logic cung cp mt lin kt gia HDL v netlist tng t nh cch
mt trnh bin dch C cung cp lin kt gia m ngun C v ngn ng my. Tuy
nhin, vic so snh song song nh trn cung ch mang tnh tng i. C c pht
trin s dng vi cc trnh bin dch, cn HDL th khng c pht trin s
dng vi cc cng c tng hp logic. Verilog th c thit k nh mt ngn ng
m phng cn VHDL th c thit k nh mt ngn ng m t v d liu. C
Verilog v VHDL u c pht trin t u thp nin 80, trc khi n c gii
thiu nh mt phn mm thng mi dng tng hp logic. Do cc ngn ng
HDL hin nay c s dng vo mc ch khng phi nh ng ban u,
nn hin trng ca n trong tng hp logic gn ging nh cc b bin dch ngn
ng my tnh. Do vy tng hp logic buc ngi thit k phi s dng mt tp con
ca c Verilog v VHDL. Hin nay, VHDL c s dng rng ri v ch yu
Chu u, cn Verilog th c dng chnh M v Nht. Vic ny lm cho tng
hp logic l mt vn rt kh. Hin trng ca cc phn mm tng hp ging nh
vic mt ngi hc ngoi ng nhng nm nm sau mi s dng n.
Khi ni n cng c tng hp logic s dng HDL th ngi ta thng ngh n
lin quan n phn cng hn l vic tng hp logic s thc hin trn netlist. Theo
nh gi ca cc chuyn gia ASIC hc th phi 5 nm na chng ta mi hon
thin c qu trnh tng hp logic nh mong mun.
Ngi thit k s dng thit k u vo dng text hoc ho to ra m
hnh hot ng HDL khng bao gm bt k tham chiu no n cc phn t logic.
Cc s trng thi, cc m t ng dn d liu ho, cc bng s tht, cc mu
RAM/ROM, v cc gin mc cng (gate-level) c th s dng cng vi mt m
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t HDL. Mi khi hon thnh mt m hnh hot ng HDL, hai thnh phn yu cu
phi x l l: mt b tng hp logic (bao gm phn mm v ti liu i km) v mt
th vin phn t (bao gm cc phn t logic chng hn nh cng NAND, AND...)
c gi l th vin ngun. Hu ht cc cng ty phn mm tng hp ch cung cp
phn mm. Cn hu ht cc nh cung cp ASIC th ch cung cp cc th vin phn
t.
M hnh hot ng c m phng kim tra vic thit k theo tham s k
thut cn sau b tng hp logic s c s dng to ra mt netlist, mt m
hnh cu trc ch cha tham chiu n cc phn t logic. Hin nay khng c khun
dng tiu chun cho cc netlist m tng hp logic to ra, nhng ph bin nht hin
nay ngi ta vn s dng khun dng EDIF. Mt vi cng c tng hp logic cng
c th to ra cu trc HDL (nh Verilog v VHDL). Sau khi tng hp logic bn
thit k c thc hin m phng li so snh vi vic m phng hot ng trc
. Vic xp lp i vi bt k ASIC no u c th c to ra t m hnh cu
trc sinh ra thng qua qu trnh tng hp logic.
1.4.1. V d v tng hp logic
Trc ht chng ta hy tm hiu v mt v d ca tng hp logic. y cc
phn t logic u s dng cng ngh VLSI 1.0 m m. ASIC u tin c thit k
bng tay s dng cc gin u vo v mt s tay d liu. ASIC th hai s dng
Verilog cho thit k u vo v mt b tng hp logic. Bng 2.2 so snh kt qu ca
hai phng php trn. Vic tng hp ASIC theo phng php th hai cho kt qu l
ASIC nh hn 16% v tc nhanh hn 13% so vi cch tng hp bng tay.
Chng ta cng tm hiu ti sao li c vn trn. Hnh 2.6 biu din gin
mt b so snh v dn knh c thit k bng tay. Cn bn phi ca hnh 2.6 l m
ngun cng ca b so snh v dn knh c cng chc nng. Vic so snh hai kt
qu cho trong bng 2.3 ch ra l do ca phng php th hai cho sn phm c
kch thc nh hn, tc nhanh hn thm ch cn s dng nhiu phn t hn.
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Bng1.2. So snh thit k tng hp logic ASIC bng tay v tng hp logic
s dng Verilog theo l thuyt

Tr ng
dn/ns (1)
S cc phn t logic
tiu chun
S tranzitor
tiu chun
Kch thc/
mils 2 (2)
Thit k bng tay 41.6 1,359 16,545 21,877
Thit k tng hp
logic
36.3 1,493 11,946 18,322
Bng 1.3. So snh thit k tng hp logic ASIC bng tay v tng hp logic
s dng Verilog trn b so snh v dn knh trong thc t

Tr ng
dn/ns (1)
S cc phn t logic
tiu chun
S tranzitor
tiu chun
Kch thc/
mils 2 (2)
Thit k bng tay 4.3 12 116 68.88
Thit k tng hp logic 2.9 15 66 46.43


// M ngun chng trnh
// comp_mux.v
module comp_mux(a, b, outp);
input [2:0] a, b;
output [2:0] outp;
function [2:0] compare;
input [2:0] ina, inb;
begin
if (ina <= inb) compare = ina;
else compare = inb;
end
endfunction
assign outp = compare(a, b);
endmodule
Hnh 1.6. Thit k u vo bng tay v s dng Verilog
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1.4.2. VHDL v tng hp logic
Hu ht cc b tng hp logic bt buc chng ta phi tun theo mt tp cc
qui tc khi chng ta s dng mt h thng logic bo m l chng ta tng hp
tun theo ng nh trong m t hot ng ca n. Tp cc qui tc s dng theo
tiu chun VHDL IEEE h thng 9 gi tr.
- Chng ta c th s dng cc gi tr logic tng ng vi cc trng thi 1,
H, 0 v L trong bt k cch no.
- Mt vi cng c tng hp khng chp nhn trng thi logic U khi ng.
- Chng ta c th s dng cc trng thi logic Z, X, W v - trong tn
hiu v cc php gn bin theo bt k cch no. Z c tng hp thnh 3
trng thi logic.
- Cc trng thi X, W v - c x l nh cc gi tr khng bit hoc
khng quan tm.
Cc gi tr Z, X, W v c th s dng trong cc mnh iu kin chng
hn nh so snh trong cc lnh if hoc case. Tuy nhin mt vi cng c tng hp s
b qua chng v ch tun theo quanh cc bit 1 v 0. Do vy, mt thit k c
tng hp c th hot ng khc vi khi m phng nu mt tc nhn kch thch s
dng Z, X, W hoc -. Cc ng gi tng hp IEEE cung cp mt hm dnh
ring cho vic so snh l STD_MATCH.
Trong VHDL c cc m hnh tng hp nh sau:
- Khi ng v khi ng li (Initialization and Reset)
- T hp Tng hp logic trong VHDL (Combinational Logic Synthesis in
VHDL)
- Cc b dn knh trong VHDL (Multiplexers in VHDL)
- Cc b gii m trong VHDL (Decoders in VHDL)
- Cc b cng trong VHDL (Adders in VHDL)
- Logic tun t trong VHDL (Sequential Logic in VHDL)
- Thuyt minh trong VHDL (Instantiation in VHDL)
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- Cc thanh ghi dch v to xung nhp trong VHDL (Shift Registers and
Clocking in VHDL)
- Cc b cng v hm thut ton (Adders and Arithmetic Functions)
- Cc b cng/tr (Adder/Subtracter)
1.4.3. Tng hp b nh
C nhiu phng php tng hp b nh:
- S dng thnh phn logic ngu nhin flip-flop hoc b cht d liu.
- S dng cc tp thanh ghi trong datapath.
- S dng cc thnh phn RAM tiu chun.
- S dng cc b bin dch RAM.
Phng php u tin s dng cc vector ln hoc cc ma trn trong m lnh
HDL. B tng hp s nh x cc phn t ti ma trn ca cc flip-flop hoc cc
b cht d liu. Phng php ny c lp vi bt k phn mm no hoc kiu ASIC
no v d s dng nht nhng phm vi ng dng khng hiu qu. Mt flip-flop
chim din tch s dng 10 n 20 ln so vi mt cell RAM tnh c 6 tranzitor.
Phng php th hai s dng tng hp trc tip tng hp b nh thnh cc
thnh phn datapath. Phng php ny hiu qu hn phng php trc, tuy nhin
b ph thuc vo phn mm v cng ngh ASIC m chng ta s dng.
Phng php th ba s dng cc thnh phn tiu chun c cc nh sn xut
ASIC cung cp km. Phng php ny rt hiu qu nhng ph thuc vo cng ngh
ca tng hng sn xut.
Phng php cui cng, l s dng b bin dch RAM, y l phng php
hiu qu nht. N ph thuc vo kh nng ca trnh bin dch cng vi cng c tng
hp.
1.5. M phng (Simulation)
Thng thng chng ta thng s dng cc h thng mu kim tra cc thit
k ca mnh, m thng l cc th (bread-board), sau lp cc IC v u dy
trn cc th . Tuy nhin cch lm ny ch p dng i vi cc mch nh c vi
phn t dng TTL. Trong thc t, thc hin vic ny i vi mt ASIC th s
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dng th l iu khng th thc hin c. Do vy, i vi thit k ASIC, chng
ta phi dng n cc phng php m phng.
1.5.1. Phn loi m phng (Type of Simulation)
C th phn chia m phng theo loi hoc theo phng php:
- M phng hot ng (Behavioral simulation)
- M phng chc nng (Functional simulation)
- Phn tch thi gian tnh (Static timing analysis)
- M phng mc cng/logic (Gate-level/Logic simulation)
- M phng mc chuyn mch (Switch-level simulation)
- M phng mc tranzitor hoc mc mch (Transistor-level or Circuit-level
simulation)
Trn y l th t cc mc m phng t cao xung thp, cc mc ny c
chnh xc tng dn ng thi phc tp v thi gian cng tng theo.
C nhiu cch to ra mt m hnh m phng o cho mt h thng. Phng
php thng dng nht l m hnh ho cc m-ul ln ca h thng thnh mt khi
(ging nh mt hp en - black box) ch c cc u vo v ra. y chnh l m
phng hot ng (Behavioral simulation), ch yu l s dng ngn ng VHDL v
Verilog.
M phng chc nng (Functional simulation) s b qua thi gian hot ng v
cc tr trong tng m-ul m thit lp mc tr vi cc gi tr c nh (v d l 1ns
chng hn). Sau khi thc hin m phng hot ng v chc nng hon thnh, cho
kt qu tt th ngi mi kim tra thi gian hot ng ca tng khi.
Ti thi im ny, h thng c phn chia thnh cc ASIC v vic m phng
thi gian c thc hin trn tng ASIC c lp. Mt trong cc phng php m
phng thi gian l s dng phng php phn tch thi gian tnh (Static timing
analysis) trong trng hp hot ng tnh, sau tnh ton thi gian tr cho tng
phn t. Phng php ny c gi l phn tch thi gian tnh (Static timing
analysis) v n khng i hi phi to ra mt tp cc php th nghim i vi cc
ASIC ln.
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Tip theo l m phng mc cng/logic (Gate-level/Logic simulation) c th
cng c dng kim tra thi gian hot ng ca mt ASIC. Trong m phng
mc cng/logic mt cng logic hoc phn t logic (NAND, NOR hoc tng
ng) c kim tra hot ng ging nh m hnh hp en theo cc chc nng
nhng cc gi tr tn hiu u vo thay i c.
M phng mc chuyn mch (Switch-level simulation) cung cp mc chnh
xc v thi gian cao hn m phng mc cng/logic nhng khng c kh nng s
dng tr ca cc phn t logic lm tham s cho vic m phng.
Chnh xc nht v cng phc tp nht, mt nhiu thi gian nht l m phng
mc tranzitor hoc mc mch (Transistor-level or Circuit-level simulation).
Phng php ny yu cu cc m hnh tranzitor c th, m t in p phi tuyn v
cc tham s dng cung cp ca chng. Mi phng php thng i km vi mt
cng c phn mm khc nhau. Tuy nhin c th kt hp mt s phng php m
phng vo vic m phng mt ASIC.
Tip theo chng ta s gii thiu v mt s yu cu v h thng logic v m
hnh ng dng trong qu trnh m phng.
1.5.2. La chn cc h thng logic (Logic Systems)
Nh chng ta bit trong thc t, cc tn hiu s l cc mc in p (hoc
dng) tng t m thay i lin tc nh s thay i ca chng. Vic m phng s
gi s l cc tn hiu s ch l mt tp cc gi tr logic (hoc l cc trng thi logic)
t mt h thng logic. Do vy khi la chn mt h thng logic m phng rt
quan trng. Nu qu nhiu gi tr logic th s lm cho vic m phng tr nn phc
tp v tc b chm li. Nu t gi tr qu th s lm gim chnh xc ca m
phng khng phn nh ng hot ng ca phn cng.
V d v mt h thng 4 gi tr logic cho trong bng 1.4.
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Bng 1.4. H thng 4 mc logic
Trng thi logic Mc logic Gi tr logic
0 Khng (zero) Khng (zero)
1 Mt (one) Mt (one)
X Khng (zero) hoc Mt (one) Khng r
Z Khng (zero), Mt (one) hoc khng c g Tr khng cao
1.5.3. M phng logic hot ng nh th no
Hu ht cc loi m phng s u s dng m phng theo hot ng s kin
(event-driven). Khi mt nt mch thay i gi tr theo thi gian, cn gi tr mi l
mt tp c bit n di dng cc s kin. S kin c lp lch bng cch a
chng vo mt hng i s kin hoc danh sch s kin. Khi thi gian c ch
nh n, gi tr logic ca nt c thay i. S thay i tc ng n cc phn t
logic nt nh mt gi tr u vo. Tt c cc phn t logic b tc ng phi
c nh gi, vic ny c th thm cc s kin vo danh sch s kin. M
phng bo m vic kim tra thi gian hin thi, bc thi gian v danh sch s
kin dng gi cc s kin sp xy ra. i vi mi mt nt mch th m phng
bo m mt bn ghi trng thi logic v ln ca ngun hoc cc ngun cp cho
nt. Khi mt nt thay i trng thi logic th s gy ra mt s kin.
1.5.4. Cc m hnh phn t (Cell models)
C nhiu loi m hnh phn t khc nhau, l:
- M hnh nguyn thu, l m hnh sinh ra thng qua th vin ASIC v m
t chc nng v c im ca mi mt phn t logic (NAND, D flip-flop,
) s dng cc hm nguyn thu.
- M hnh VHDL v Verilog sinh ra thng qua th vin ASIC t cc m
hnh nguyn thu.
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- Cc m hnh c quyn sinh ra thng qua cc th vin dng m t cc
phn t logic nh hoc cc chc nng ln nh cc b vi x l.
1.5.5. Cc m hnh tr (Delay models)
M hnh tr phn t c dng tnh ton khong tr ca phn t logic.
Chng ta s dng thut ng m hnh thi gian (timing model) m t tr bn
ngoi cc phn t logic v m hnh tr (Delay models) m t tr bn trong mi
phn t logic. Cc thut ng ny hay c s dng ln ln v khng c chun
ho, thc t chng c mt s im khc nhau nh sau:
- Tr t chn n chn (pin-to-pin delay) l mt khong tr gia mt chn
u vo v mt chn u ra ca mt phn t logic.
- Tr chn (pin delay) l khong tr dn vo mt chn c nh ca mt phn
t logic (thng l mt u vo).
- Tr ng kt ni (net dalay) hoc tr ng dy (wire delay) l khong
tr bn ngoi ca mt phn t logic.















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CHNG II: GII THU MT S CNG NGH MI
LIN QUAN N THIT K ASIC HIN NAY

2.1. Gii thiu cng ngh FPGA
2.1.1. Gii thiu FPGA
Nh gii thiu trong chng 1 trc v mi trng thit k phn cng,
phng php thit k mch v mi quan h hu c gia ngn ng VHDL v
phn cng, trong mc ny ch c nh gii thiu v cc mch phn cng c xy
dng da trn cng ngh FPGA. y l cng ngh tin tin c nghin cu rt
nhiu v c ng dng rng ri trn th gii.
Cng ngh FPGA (Field-Programmable Gate Array) xut hin nh mt
gii php c bn cho vn tranh th thi gian v chi ph ban u thp. N cho
php ch to ngay v gi thnh sn phm thp, to nn sc cnh tranh ln trn th
trng. FPGA l mt thit b cu trc logic c th c ngi s dng lp trnh trc
tip m khng phi s dng bt k mt cng c ch to mch tch hp no.
2.1.1.1. FPGA l g?
FPGA c cng ty Xilinx gii thiu u tin vo nm 1985. Hin nay FPGA
c nhiu cng ty pht trin l AcTel, Altera, Plus Logic, AMD,
Ging nh MPGA, mt FPGA gm mt dy cc phn t ri rc c th c
kt ni vi nhau theo mt cch chung. V cng ging nh PLD, cc kt ni gia cc
phn t c th lp trnh c. Hnh 2.1. gii thiu v m hnh tng qut ca mt
FPGA. Trong c cc khi:
- Cc khi logic (logic block): cu trc v ni dung ca c gi l kin trc
ca n. Kin trc ca khi logic c th c thit k theo nhiu cch khc nhau.
Mt s khi logic c th ch l cc cng NAND 2 u vo, tuy nhin cng c th n
l mt b dn knh (multiplexer). Trong mt s loi FPGA cc khi logic c th c
cu trc hon ton ging nh PAL. Hu ht cc khi logic cha mt s loi flip-flop
h tr cho vic thc hin cc mch tun t.
Tip cn lp trnh cho FPGA t Spartan -3

27
- Cc ngun ti nguyn kt ni: cu trc v ni dung ca cc ngun kt ni
trong FPGA c gi l kin trc routing (routing architecture). Kin trc routing
gm cc on dy ni v cc chuyn mch lp trnh c. Cc chuyn mch lp
trnh c c th c nhiu cu to khc nhau. Ging nh khi logic, c nhiu cch
thit k kin trc routing.














Hnh 2.1. M t m hnh l thuyt ca mt FPGA
2.1.1.2. ng dng ca FPGA
FPGA c th s dng trong hu ht cc ng dng hin ang dng MPGA,
PLD v cc mch tch hp nh.
1. Cc mch tch hp ng dng c bit: FPGA l mt phng tin tng qut
nht thc hin cc mch logic s. Chng c bit thch hp cho vic thc hin
cc ASIC.
2. Thit k mch ngu nhin: mch logic ngu nhin thng c thc hin
bng PAL. Nu tc ca mch khng i hi kht khe th mch c th thc hin
thay th bng FPGA.
Logic
Ti
nguyn
I/O Cell
Tip cn lp trnh cho FPGA t Spartan -3

28
3. Thay th cc chp tich hp nh cho mch ngu nhin: cc mch hin ti
trong cc sn phm thng mi thng cha nhiu chp SSI. Trong nhiu trng
hp cc chip ny SSI ny c th c thay th bng FPGA v kt qu l gim din
tch ca bo mch i ng k.
4. Ch to mu: FPGA rt l tng cho cc ng dng to sn phm mu. Gi
thnh thc hin thp, thi gian ngn chnh l u im rt ln ca FPGA.
5. My tnh da trn FPGA: mt loi my tnh mi c th c ch to vi cc
FPGA c th ti lp trnh ngay trn mch FPGA. Cc my ny c mt bo mch
cha cc FPGA vi cc chn ni vi cc chip ln cn ging nh thng thng.
6. Ti cu hnh phn cng trc tuyn: FPGA cho php c th thay i theo
mun cu trc ca mt my ang hot ng. ng dng thch hp nht l nhng
FPGA c chuyn mch lp trnh c.
2.1.2. Cc loi FPGA v cng ngh lp trnh
C nhiu cch thc hin cc phn t lp trnh, cc cng ngh lp trnh hin
ang c s dng l RAM tnh, cu ch ngch (anti-fuse) EPROM tranzitor v
EEPROM tranzitor. Mc d cng ngh lp trnh khc nhau, tt c cc phn t lp
trnh u c chung tnh cht chung l c th cu hnh c trong mt trong hai trng
thi ON hoc OFF. Cc phn t lp trnh c dng thc hin cc kt ni lp
trnh c gia cc khi logic ca FPGA, cn FPGA thng thng c th hn
100.000 phn t lp trnh. C th ty thuc vo ng dng c th v c cc s lng
phn t lp trnh c th c cc c tnh khc. V mt ch to, cc phn t lp trnh
nu c th ch to theo cng ngh CMOS chun l tt nht.
2.1.2.1. Cng ngh lp trnh dng RAM tnh (SRAM)
Cng ngh lp trnh dng SRAM c s dng trong cc FPGA ca nhiu
cng ty nh Xilinx. Trong cc FPGA ny, cc kt ni lp trnh c lm bng cc
tranzitor truyn (pass-transistor), cc cng cho php truyn (pass-gate), hay cc b
dn knh (multiplexer), tt c u c iu khin bng cc nh (cell) SRAM.
Cc chip c thc hin theo cng ngh SRAM c din tch kh ln, bi v
cn t nht 5 tranzitor cho mi nh. u im chnh ca cng ngh ny cho php
Tip cn lp trnh cho FPGA t Spartan -3

29
FPGA c th ti cu hnh ngay trn mch rt nhanh v n c th c ch to bng
cng ngh CMOS chun.








Hnh 6.2. Cng ngh lp trnh dng SRAM
2.1.2.2. Cng ngh lp trnh dng cu ch nghch (anti-fuse)
Cng ngh lp trnh dng cu ch nghch (anti-fuse) c s dng trong cc
FPGA ca Actel. Tuy anti-fuse c s dng trong cc loi FPGA ny c cu to
khc nhau, nhng chc nng ca chng l nh nhau. Mt Anti-fuse bnh thng s
trng thi tr khng cao, nhng c th b bin thnh trng thi in tr thp khi
c lp trnh in th cao.
Anti-fuse ca Actel c gi l PLICE (Programmable Low-Impedance
Circuit Element). N c cu trc hnh ch nht gm 3 lp: lp di cng cha silic
mang in tch dng, lp gia l mt lp in mi, lp trn cng l poly-silic.






Hnh 2.3. Cng ngh lp trnh cu ch nghch anti-fuse PLICE ca Actel
(a) Mt ct ngang.
RAM
Cell
Dy ni Dy ni
RAM
Cell
Dy ni
Dy ni Dy ni
RAM
Cell
MUX
RAM
Cell
Dy ni
Dy ni
a. Transistor truyn dn b. Cng transistor c. B dn knh
Tip cn lp trnh cho FPGA t Spartan -3

30
(b) Cu trc cc lp cu ch nghch: + Lp in mi ONO (Oxy-Nit-Oxy)
cch in chiu dy nh hn 10nm; + Lp di mang in tch dng; + Lp trn
l Poly-Silic.
(c) Mt cu ch nghch nhn t pha trn xung ging nh mt cng tc
u im cng ngh cu ch nghch anti-fuse l din tch ca cc chip rt nh
so vi cc cng ngh khc. Tuy nhin b li cn phi c khng gian ln cho cc
tranzitor in th cao cn gi cho dng v p cao lc lp trnh. Nhc im ca
cng ngh ny l qui trnh ch to chng cn phi thay i so vi qui trnh ch to
CMOS.
2.1.2.3. Cng ngh lp trnh dng EPROM v EEPROM
Cng ngh lp trnh dng EPROM v EEPROM c s dng ch yu trong
cc FPGA ca Altera. Cng ngh ny ging nh s dng trong b nh EPROM.
Khng ging nh tranzitor COM, cc tranzitor EPROM gm hai cc, mt cc treo
(floating-gate) v mt cc chn (select-gate). Cc treo c t gia cc chn v
knh ca tranzitor, n c gi nh vy v n khng c kt ni in n bt k
mch no.

Hnh 2.4. Tranzitor dng cng ngh lp trnh EPROM v EEPROM
(a) Vi in p lp trnh cao (>12V) V
PP
cung cp ti cc mng cc in t c
nng lng nhy vo cng treo gate 1; (b) Cc in t cng gate 1 tng ln
in p gi m to cho cc transistor kho cho mc in p hot ng bnh
thng; (c) nh sng cc tm cung cp nng lng cc phn t cng gate 1
nhy v v tr c cho php transistor hot ng bnh thng.
Tip cn lp trnh cho FPGA t Spartan -3

31
u im ca tranzitor EPROM l chng c th ti lp trnh m khng cn b
nh bn ngoi. Tuy nhin khng ging nh SRAM, tranzitor EPROM khng th
c lp trnh li ngay trn bo mch (in-circuit).
Phng php dng EEPROM tng t nh cng ngh EPROM, ch khc l
din tch ca tranzitor EEPROM chim din tch gp hai ln din tch chp so vi
tranzitor EPROM v cn nhiu ngun in th hn cc loi khc.
2.1.2.4. Tm tt cc loi FPGA trn th trng
Bng 6.1. Tm tt cc h FPGA trn th trng
Cng ty Kin trc tng qut Kiu khi logic Cng ngh lp trnh
Xilink Symmetrical Array Look-up Table Static RAM
Altera Hierachical-PLD PLD Block EPROM
Actel Row-based Multiplexers-Based Anti-fuse
Plessey Sea-of-gates NAND-gate Static RAM
Plus Hierachical-PLD PLD Block EPROM
AMD Hierachical-PLD PLD Block EPROM
QuickLogic Symmetrical Array Multiplexer-Based Anti-fuse
Algotronix Sea-of-gates Multiplexers &
Based Gates
Static RAM
Concurent Sea-of-gates Multiplexers &
Based Gates
Static RAM
Crosspoint Row-based Transistor Pairs &
Multiplexers
Anti-fuse
2.1.2.5. Cc loi FPGA v gii thiu cng ngh lp trnh
C nhiu loi FPGA ca cc cng ty khc nhau, tuy nhin chng c th c
chia thnh 4 loi chnh nh sau (xem hnh 2.2):
- Cu trc mng i xng (symmetrical array)
- Cu trc hng (row-based)
- Cu trc PLD phn cp (hierachical PLD)
- Cu trc a cng (sea-of-gate)
Tip cn lp trnh cho FPGA t Spartan -3

32
2.2. Gii thiu phng php thit k ASIP cho cc h thng nhng
Mt thch thc m nhiu ngi tng cp n trong qu trnh thit k b
x l nhn c nhng kt qu tt nht c th i vi phm vi ng dng in
hnh cui cng cn t c ni chung l m t theo nhng chun nh gi. Vic
thu c kt qu tt nht c th ln lt tr thnh mt s tho hipphc tp gia
tnh tng qut ca nhng b x l v c trng vt l ca chng. Trong nhng nm
gn y, cc b vi x l c tp lnh chuyn dng - ASIP (Application-Specific
Intruction-Set Processor) c s pht trin c bit trong ngnh sn xut chip v
ang c nghin cu. Trong mc ny, ch ch yu gii thiu mt kiu kin trc v
phng php lun c dng thit k ASIPs trong phm vi cc b iu khin.
2.2.1. Gii thiu chung
Nhiu h thng nhng b hn ch v rng buc i vi gi thnh sn phm.
Gi biu hin theo hai c trng chnh : gi ca chng trnh ngun v gi ca b
x l. Do vy vic dung ho gia gi thnh sn phm v cht lng cng nh ng
dng ca sn phm rt d i vi cc nh thit k c th tm ra gii php tt nht
cho b x l tng ng vi vic thc hin mt ng dng trung bnh v cng sut
tiu th ca n. Do vy, phi chn gii php s dng b ng vi x l ASIC (co-
procesor ASIC) hoc l ng dng cn phi nng cp thnh mt b x l c kh
nng hot ng cao hn vi gi thnh ni chung cao hn.
Nn cng nghip bn dn ni chung ch yu nhm vo cc b x l m c
sn xut cho mt phm vi ng dng c bit nh cc chip DSP. Cc chip DSP
thng thng l nhng b vi x l vi nhng c tnh v nhng kin trc c bit
ch yu phc v cho vic x l tn hiu s. Tuy nhin, vic thit k chuyn bit v
cc b x l khng gii quyt c tt c cc vn . Cn nhng ng dng ph hp
vi cc c im ring ca mt b x l, th gi thnh ca b x l t hn do
ch c sn xut theo n t hng.
V mt thut ng ni chung, vic thit k ASIP chnh l vic to ra mt b vi
x l mi, vi tp lnh v kin trc c ty bin cho ph hp vi mt s nhng
ng dng chuyn bit.
Tip cn lp trnh cho FPGA t Spartan -3

33
Mc ch ca chng ta l c th ti u ha hiu qu chng trnh ngun v
kh nng hot ng ca mt ng dng cho sao cho bo m cc yu cu sau:
- Hiu qu h thng (gi thnh, kch thc chng trnh ngun, kh nng thc
hin, v in nng tiu th) bo m chp nhn c cho cc h thng nhng.
- Tu bin theo yu cu khch hng cng bn a ho cng tt.
- Gim ti a s thay i mi trng phn mm cng tt (bo m tnh tng
thch ngc ca cc phn mm).
- C th linh hot thay i trong qu trnh sn xut (c th ty bin chng
trnh, mt n lp trnh c, )
2.2.2. Cng ngh thit k ASIP
Cng ngh thit k y l vic ty bin mt b x l hin ti hn l tng
hp mt b x l mi vi mt tp lnh v kin trc mi c ti u ha cho mt
nhm cc ng dng chun dng nh gi.
2.2.2.1. S lung thit k














Hnh 2.5. S lung thit k ASIP
Chng trnh nh dng tp lnh mi
Thit k theo phn mm truyn thng
Qu trnh gia cng to tp lnh mi

Cc hm
Chui lnh
thc hin
Tu bin b vi x l vi tp lnh mi
Cp nht phn mm vi tp lnh
Tip cn lp trnh cho FPGA t Spartan -3

34
S lung thit k ASIP c cho trong hnh 2.5. Vic thit k ban u s
dng nhng phn mm c s (firmware) theo cc phng php truyn thng
(Traditional Software Design), sau mt chng trnh nh dng tp lnh mi
(New Instruction Identification) s gia cng to ra tp lnh mi chuyn bit. Ri
b x l c ty bin thng qua vic b sung cc lnh chuyn bit v ng dng
(Customize CPU). Cui cng, phn mm c s (firmware) c cp nht c th
s dng c cc lnh mi.
2.2.2.2. nh dng tp lnh mi
Tp lnh mi ni chung c mt trong s hai c trng sau. Chng hoc l mt
tin trnh con trong phn mm c s (firmware) m c s dng thng xuyn
hoc l mt chui cc lnh dng chung trong ng dng. V d v tin trnh con bao
gm cc trnh iu khin thit b (device driver), cc phn t tnh ton c bn, cc
b hn gi, v cc h iu hnh nguyn thu. V d chui cc lnh thng dng bao
gm cc lnh dch v cng (shift-and-add) thng c s dng trong cc b lc
s, vng qui khng, b chuyn i kiu d liu (ADC hoc DAC), d liu nh
dng i vi cng Vo/Ra (I/O), kim tra tn hiu.
2.2.2.3. Kin trc b x l
Phng php thit k y ph thuc vo kin trc b x l c c nh
mt tp lnh v ng dn d liu, tuy nhin vn cho php b sung cc phn t
logic iu khin v ng dn d liu mi thng qua vic lp trnh cho phn cng.
Nhng, vic ny c hon thnh m khng lm thay i kin trc ca ton b b
vi x l. Hai phng php tu bin thit k kin trc b x l c gii thiu trong
hnh 2.6 v hnh 2.7.
Nhng kin trc ny khng lm nh hng n bt k vng cm no trong
khi gii m lnh, ng dn d liu hoc bus h thng. Do vy, cc kin trc ny
ph hp vi a s cc b x l cng nghip.
Vic tnh ton chuyn bit cng c th c thc hin trn mt thit b ngoi
vi hot ng thng qua khi logic lp trnh c.
Tip cn lp trnh cho FPGA t Spartan -3

35
a. Kin trc b gii m tnh (Static decode Architecture)












Hnh 2.6. Kin trc gii m tnh (Static-Decode Architecture)
Kiu kin trc ny (hnh 2.6) ch cho php mt tp cc m lnh c xc
nh trc s c s dng cho cc lnh mi, nh vy cn phi c mt cu trc gii
m lnh hiu qu. Nu c bt k m lnh no c np vo v gii m, th tn hiu
start
i
dnh cho m lnh i c kch hot. Cng lc , b x l giao vic iu khin
ca cc tn hiu iu khin ng dn d liu n khi logic lp trnh c. Khi no
m lnh i hon thnh, n kch hot tn hiu done
i
ring, sau iu khin ngc li.
Cc lnh thc khng truy nhp n cc khi chc nng c thc hin thng qua
khi logic lp trnh c. Kin trc ny cho hiu qu thc hin tt hn, nhng li
phi chi ph nhiu cho vic nh v trc s lnh mi c th s dng khi logic
lp trnh c.
b. Kin trc b gii m ng (Dynamic decode Architecture)
Kiu kin trc ny (hnh 2.7) linh hot hn v cho php cc m lnh mi c
nh ngha trn c s ng dng. Vic gii m cc lnh mi c thc hin thng
qua khi logic lp trnh c. Khi mt lnh nh vy c np vo, b x l khng
th gii m lnh , tip theo n a ra mt tn hiu by trap bng vic gi mt
Khi gii m lnh lgic
c nh
Khi logic lp trnh c
start
i
done
i
B


c
h

n
/
K

t

h

p


Bus 1 Bus N
Khi iu khin Khi ng dn d
Cc tn hiu iu kin v d liu
Lgic c nh Lgic lp trnh
Bus
iu
khin
Tip cn lp trnh cho FPGA t Spartan -3

36
tn hiu n khi logic lp trnh c. Nu khi logic lp trnh c c th gii m
lnh , th sau lnh c kch hot. Nu lnh cha c khi logic lp
trnh c nhn dng, th n kch hot mt tn hiu by trap hng dn cho
khi gii m lnh lgic c nh khi ng qu trnh nhn dng lnh mi.












Hnh 2.7. Kin trc gii m ng (Dynamic-Decode Architecture)
2.2.2.4. Cp nht phn mm c s
Mi mt ln mt lnh mi c thc hin trong b x l, th phn mm nhng
c s li cn cp nht sa i s dng lnh mi ny. Tu thuc vo phng php
trn phn mm c s dng, c ba cch thc hin vic cp nht ny.
Th nht, nu phn mm c s l ngn ng dng ng gi hon chnh hoc
cc lnh mi ch lin quan n mt phn ca phn mm c s th ch c phn m
lnh ng gi c thay i.
Nu phn mm s dng mt chng trnh bin dch ngn ng bc cao nh C
v nu cc lnh mi c th p dng c vo cc ng dng khc, th sau cc lnh
mi c th c b sung vo chng trnh bin dch .
Khi gii m lnh lgic
c nh
Khi logic lp trnh c
trap

done

B


c
h

n
/
K

t

h

p


Bus 1 Bus N
Khi iu khin Khi ng dn d
Cc tn hiu iu kin v d liu
Lgic c nh Lgic lp trnh
Bus
iu
khin
trap'

Tip cn lp trnh cho FPGA t Spartan -3

37
Khi cc chng trnh bin dch c cp nht li tr thnh cc cng c dng
chung, th mt b tham s v kin trc mi ca b x l c th c thm vo
chng trnh bin dch tr thnh kh dng i vi cc lnh mi.
2.2.3. Hng pht trin ca ASIP
Trn y ch l mt trong s nhiu phng php lun v ng thit k v kin
trc cho cc ASIP ng dng trong cc h thng nhng. Hin nay cn c nhiu
phng php khc nghin cu v thit k ASIP. Vic tu bin ho tp lnh ca b
vi x l theo yu cu ca tng ng dng ph thuc vo ngi thit k v do n t
hng.
2.3. ng thit k phn cng/phn mm (Hardware/Software Co-Design)
Nh chng ta bit hu ht cc h thng in t ngy nay (c h thng
nhng hoc kt hp mt phn) u c cha mt phn ln cc thnh phn c s
ho, cc phn cng hot ng c chnh l nh vo cc phn mm ng dng
c ci t sn. ng thit k phn cng/phn mm chnh l s gp g mc h
thng ca phn cng v phn mm thng qua qu trnh thit k.
Hin nay vic thit k phn cng s c s pht trin gn nh tng ng
vi thit k phn mm. Cc mch phn cng c m t bng cc ngn ng lp
trnh hoc dng m hnh ho bng phn mm, v nh vy chng hon ton ph
hp v hot ng theo s iu khin ca phn mm. i khi ngi ta gi l thit k
phn cng chuyn bit. Do vy, vic thit k cc h thng s i hi ngi thit k
phi nm rt vng c phn cng v phn mm.
Mc ch ca mc ny ch gii thiu trong phm vi hp v ng thit k cc
h thng phn cng/phn mm.
Chng ta ch cp n cc bc ng thit k cc h thng phn cng/phn
mm mc cao (tc l ch ni n thun tu v mt cng ngh). y ta ch cp
n cc vn chung ch khng i su v mt vn no, nhm lm sng t s
ging v khc nhau gia cc h thng s thit k kt hp vi cc h thng t nhin
khc. Ta cng cp n cc k thut tng t nhau c p dng trong ng thit
k cc h thng phn cng/phn mm.
Tip cn lp trnh cho FPGA t Spartan -3

38
ng thit k cc h thng phn cng/phn mm l bao gm m hnh
(modeling), ng dng (validation) v cch tin hnh (implementation). M hnh x
l l cc tham s k thut mang tnh khi nim v nh ngha li v sn phm l cc
m hnh phn cng v phn mm. ng dng x l l mc ng dng c th c ca
ring h thng s lm vic nh c thit k v cch tin hnh l tin cy
v mt vt l ca phn cng (trong qu trnh tng hp) v kh nng c th lm vic
tng ng ca phn mm (trong qu trnh bin dch).
Khi cp n cc h thng nhng cc mu m hnh khc nhau v cc chin
lc th ta ch cp n hon ton phn cng (v d nh ASIC) v/hoc hon ton
phn mm (phn mm nhng chy trn nn card ISA) v chng l cc h thng ng
thit k. Do vy tt c cc m hnh h thng nhng u c kiu l thun nht
(homogeneous) hoc khng thun nht (heterogeneous). Ngoi ra cn c m hnh
ngn ng (v d nh m hnh lp trnh C chng hn) hoc cc hnh thc ho
c dng trnh din c phn cng v phn mm. Vn phn chia phn
cng/phn mm c th da vo cc tm tng phn ca m hnh thc hin tt nht
trong phn cng v tt nht trong phn mm. Vic phn chia ny do ngi thit k
thc hin da trn m hnh ban u hoc bng cc cng c CAD.
Khi s dng m hnh khng thun nht, vic phn chia phn cng v mm
thng da vo m hnh ca bn thn h thng, v cc thnh phn phn cng v phn
mm c th c biu din theo cc ngn ng tng ng. V d, phin bn th nht
ca mt sn phm c th c thm thnh phn phn mm v l do thi gian
thng mi ho v tnh linh hot nhng n th h tip theo ca sn phm th
thnh phn phn mm c th li c thc hin v l do gi thnh sn phm.
ISA c m hnh ho theo cc mc khc nhau. Tp lnh cung cp cc thng
tin cn thit v kin trc, h tr cho vic pht trin c phn cng v phn mm.
Vic t chc x l thng c m t trong ngn ng c t phn cng HDL
(Hardware Description Language) i vi mc ch tng hp thit k phn cng,
trong khi cc m hnh b vi x l (v d nh m hnh cc bus chc nng) li
thng s dng cc phng php gi lp kt hp.
Tip cn lp trnh cho FPGA t Spartan -3

39
Trong trng hp cu hnh li h thng, chng ta cn phi ch phn chia
gia m hnh ng dng ch v m hnh ch. Nhim v u tin thng ph hp
vi h thng ca ngi dng, trong khi nhim v th hai tng ng vi mc
pht trin h thng. Do vy, hai nhim v ny thng khc nhau v yu cu kt hp
thit k.
Do cc h thng ngy cng tr nn phc tp, vic ng dng l rt cn thit
bo m cc chc nng lm vic chnh xc v yu cu cc mc hot ng ng theo
m hnh hot ng ca h thng. Ngoi ra vic ng dng cng nh hng n s
hot ng chnh ca h thng. S hot ng ca cc ng dng da trn s phi hp
hot ng gia phn cng v phn mm. Mt khc cc h thng iu khin nhng
yu cu phi c phn chia cc ng dng nhng s hot ng km hiu qu cn
phi c kim tra trong tt c cc iu kin bo m an ton cho h thng.
S hot ng ca h thng phn cng/phn mm c th gii quyt nhiu tin
trnh con.
2.3.1. Phn chia phn cng/phn mm
Vic phn chia h thng thnh phn cng v phn mm l yu cu rt quan
trng v n l yu t u tin nh hng n c trng gi thnh/tnh nng ca vic
thit k. Do vy, bt k s phn chia no cng phi tnh n cc chi tit ca vic
phn chia thnh cc khi phn cng v phn mm.
Cng thc ca vic phn chia phn cng v phn mm tuan th theo nguyn
tc kt hp thit k. Trong trng hp cc h thng nhng, vic phn chia phn
cng v phn mm chnh l vic phn chia v mt vt l cc chc nng ca h
thng thnh cc ng dng c bit dnh cho phn cng v phn mm trn mt hay
nhiu b x l. C nhiu quan im phn chia cng v mm da trn cc tiu ch
nh kin trc hoc mc ch s dng...
Khi cp n mc ch chung ca h thng my tnh, th vic phn chia h
thng c thc hin theo cc chc nng logic, trong phn cng c thit k h
tr cho s hot ng ca phn mm. Vic phn chia ny thng tun theo tp lnh.
Do vy, vic la chn lnh nh hng n vic t chc phn cng v phn mm.
Tip cn lp trnh cho FPGA t Spartan -3

40
Tuy nhin khi cu hnh li h thng th vic phn chia ph thuc vo mc
u tin. i vi cc h thng ch c cc chip kiu FPGA, th vic phn chia cc
chc nng h thng li thnh cc thnh phn tng ng vi cng ngh ch to [16].
1. Quan im phn chia theo kin trc: quan im ny ch yu p dng trong
cc h thng nhng vi cc b x l hot ng v cc ng dng phn cng, kin
trc chung trong cc h thng ny l c th tham s ho nh l mt h ng x l...
l cc b x l lm vic kt hp vi cc phn cng trong cc ng dng c bit.
in hnh l cc kin trc x l ho 3-D vi ct cu phn cng h tr ring cho
k thut ho.
Giao din phn cng/phn mm c nh ngha kiu kin trc thay i m
nh hng ln n vic phn chia ny. Ch yu n s dng vic nh x kiu b nh
thng qua b x l hoc theo kiu truyn d liu.
2. Phn chia theo mc ch: Cc kin trc ng x l thng c chn
ci thin hiu qu lm vic ca h thng theo cc thut ton c bit [5, 34]. Do
vy, trong mt vi quan im phn chia a ra cch phn chia ng dng theo tc
. Do s c lp ca d liu, trong mt vi phm vi ng dng th tc khng
phi l cch phn chia tt. Nn trong cc ng dng thi gian thc c yu cu ngt
ngho v mt thi gian, vic phn chia ny t ra khng hiu qu.
3. Cc chin lc phn chia: Mt s quan nim sai v cch thc phn chia
l theo cch thc s dng cc cng c CAD. Thng thng vic xc nh phn
cng i li vi s hot ng ca phn mm theo cc chc nng thi hnh cc mc
tru tng m khng phi l c m hnh ho theo tham s h thng. Do vy
c hai quan im phn chia: l phn chia m v phn chia theo quan nim kin
trc.
Da vo kin trc c bit r, ngi ta phn chia mc h thng theo cc
chc nng m t nh vic gn nhn cho cc chc nng ca n theo s hot ng ca
phn cng hay phn mm. Gii php chnh xc nht cho vn phn chia, thm ch
trong trng hp n gin nht, cng i hi cch tnh ton cc k phc tp. Trong
mt n lc a ra m hnh ton hc v vn phn chia, th cng thc ca m
Tip cn lp trnh cho FPGA t Spartan -3

41
hnh lp trnh s nguyn IP (programming integer) v m hnh lp trnh tuyn tnh
s nguyn ILP (programming linear integer) thng c s dng hn c. Vic so
snh cc phng php m hnh ton hc v phn chia phn cng v phn mm rt
kh khn, bi v cht lng ca vic phn chia i khi cn chu s nh hng ca
gi thnh/tnh nng hot ng.
Cc phng php m phn chia c hai tng chnh l: cc phng
php xy dng chng hn nh cc cng ngh hp nhm v cc phng php lp
nh l cc lung thng tin trn mng, k thut tm kim nh phn cng ch v m
hnh lp trnh ng. Ngoi ra, hu ht cc phng php c s dng u da trn
cc phng php tm kim theo su, chng hn nh s thay i ca phng php
d on m KL (Kernighan-Lin), hoc cc phng php khc...
Cn cc phng php theo quan nim kin trc th ch yu l theo nhim v,
chc nng, tnh lin kt....
Ngoi nhng mi quan h rt mt thit gia cc chng trnh con vi nhau, th
vic phn chia cn i mt vi cc vn nh la chn gia cc yu t tnh
nng/gi thnh cng l mt bi ton kh. Trong khi cc phng php c lng tt
i vi s hot ng ca phn cng th cc tham s phn mm ni chung ph thuc
vo rt nhiu yu t...
2.3.2. Lp chng trnh thc hin (Scheduling)
Lp chng trnh thc hin c rt nhiu vn cn cp n. Cc gii thut
lp chng trnh do cc nh nghin cu ln gii khoa hc my tnh a ra theo
nhiu m hnh v quan im khc nhau p dng vo k thut thit k cc h
thng phn cng v phn mm.
Thc t, mt s gii thut lp chng trnh cho phn cng da trn cc k
thut c s dng trong phn mm v mt s phng php lp chng trnh mc
h thng - ngc li da trn cc tng xy dng phn cng.
Lp chng trnh c th hiu mt cch gn ng nh l vic gn mt kch hot
start time cho mt mt s kin trong mt tp, trong cc s kin c lin kt
thng qua mt s mi lin h (nh l tnh c lp, mc u tin,).
Tip cn lp trnh cho FPGA t Spartan -3

42
Mt s gii thut lp chng trnh c p dng vo vic thit k phn cng,
trnh bin dch v h iu hnh nh sau:
- Lp chng trnh hot ng trong phn cng: tng t nh vic thit k
ASIC bng cc ngn ng HDL.
- Lp chng trnh lnh trong cc trnh bin dch: cc trnh bin dch l cc
cng c phn mm phc tp, gm c cc thit b ngoi vi, c ch nh tuyn lm
vic ti u trn cc khun dng tc thi v cc chng trnh ph tr.
- Lp chng trnh x l trong cc h iu hnh khc nhau: chnh l vn
xc nh khi cc cc x l kch hot v gm c c ng b v ngn chn cc s c.
Cc gii thut i vi lp chng trnh x l rt quan trng i vi cc h iu hnh
v cc chng trnh thc hin di thi gian thc.
2.3.3. Nhn xt
ng thit k phn cng/phn mm l mt vn rt kh hin nay v
chnh l cc c hi th thch i vi cc nh thit k h thng. Vic s dng v s
dng li cc khi lnh phn cng v phn mm c th to ra cc sn phm vi cht
hng u (nh l v gi c, tnh nng, linh hot, ) vi thi gian thit k v pht
trin ngn hn ging nh chng vic chng ta so snh cc th h cng ngh ch to
mt mch tch hp (IC). Ch yu hin nay chng ta vn ang s dng cc cng
c CAD c sn thit k v ch to cc h thng phn cng/phn mm.
Cc nh khoa hc v cc nh thng mi vn nui hy vng vo cc phng
php v cc cng c ng thit k phn cng/phn mm tng trng v pht trin
mnh trong nhng nm ti y.
Nhn chung, ng thit k phn cng/phn mm l mt lnh vc nghin cu
rt rng, do tnh a dng ca cc ng dng, cc cch thc thit k v cng ngh ch
to cng nh hot ng.





Tip cn lp trnh cho FPGA t Spartan -3

43
Chng III. Gii thiu bo mch Spartan -3 starter kid board
v mi trng lp trnh ISE 7.1


I. Tng qut.
y l h FPGA mi nht ca Xilinx vi nhiu u im ni bt. u
tin phi k n l kh nng tch hp ca Spartan-3 t 50,000K-gate n 5 triu K-
gate. Mt s c im chnh ca Spartan-3 l:
- Gi thnh thp, tiu th in nng t.
- Mt tch hp ln n 74K trn mt phn t logic
- Tc xung nhp h thng ln n 325MHz
- 3 mc tiu th in nng (1.2V; 3.3V; 2.5V)
- C 784 chn
- Tc truyn d liu ln n 622Mbps
Bng 3.2. Mt s sn phm ca dng Spartan-3
Tn sn
phm
S cng ca
h thng
Cc phn
t logic
S hng S ct Khi
RAM
S chn
XC3S200 200K 4320 24 20 216K 173
XC3S400 400K 8064 32 28 288K 264
XC3S1000 1M 17280 48 40 432K 391
XC3S2000 2M 46080 80 64 720K 565
XC3S4000 4M 62208 96 72 1728K 712
XC3S5000 5M 74880 104 80 1872K 784
Hin nay vi dng sn phm Spartan-3 Platform FPGA Xilinx tr thnh hng
u tin trn th gii tip cn cng ngh 90nm.
Tip cn lp trnh cho FPGA t Spartan -3

44
Spartan -3 starter kid board l mt cng c hu hiu cho bt k ai ang c
nh thit k cc sn phm da trn cng ngh FPGA (Field-Programmable Gate
Array) vi mt gii php c bn cho vn tranh th thi gian v chi ph ban u
thp. N cho php ch to ngay v gi thnh sn phm thp v l mt thit b cu
trc logic c th c ngi s dng lp trnh trc tip m khng phi s dng bt
k mt cng c ch to mch tch hp no.
Trong phn ny ta ch gii thiu s qua cc chi tit c th nhn thy t giao
din b ngoi ca bo mch. Cc chi tit c th, cc c im cng nh cc vn
cn ch i vi mi thnh phn trn bo mch s c trnh by c th trong mi
ng dng sau ny.
Hnh 3.1 l hnh nh ca Spartan-3 Starter Kit Board nhn t mt trn.
Hnh 3.2 l hnh nh ca Spartan-3 Starter Kit Board nhn t mt di.
Hnh v 3.2 l hnh nh ca Spartan-3 Starter Kit Board khi ta tri trn mt
phng.




Hnh 3.1 . Spartan-3 Starter Kit Board nhn t mt trn
Tip cn lp trnh cho FPGA t Spartan -3

45



Spartan-3 Starter Kit Board: bao gm cc thnh phn vi cc c trng sau (
y ta ch gii thiu nhng thnh phn c lin quan n ng dng sau ny, chi tit
chng ta tm hiu phn Gui ca SP3 trn http://xilinx.com).
1. Khi s 1: chnh l chp iu khin chung Xc3s200ft256. Tn gi ca
n rt quan trng v chng ta s cn phi s dng sau ny khi thc hin
vic gn chn.
2. Khi s 2 v khi 3 : l Prom loi XCF02S, n c chc nng lu tr
cc cu hnh cng nh chng trnh np t trnh dch vo.
3. Khi s 5 : y l cng kt ni VGA. Spartan 3 c kh nng kt ni
vi mn hnh v hin th cc d liu bng vic thc hin qut dng qut
mnh theo phng thc qut ln lt. Chi tit v vic to nh trn mn
hnh hin th s c phn tch c th trong phn ng dng s c
cp phn sau.
4. Khi s 6,7: Cng kt ni Rs232.
5. Khi 9 : Kt ni vi bn phm hoc l chut.
6. Khi s 10 : Cc led 7 on. C th l c 4 led 7 on anot chung.
7. Khi 11: 8 chuyn mch. C th dng chn ch lm vic, hoc
cho nhng ng dng kim tra khi thit k thc hin chc nng 8 bt u
vo s.
8. Khi 12: 8 led, dng kim tra qu trnh thit k. L mt trong nhng
phng tin kim tra u ra hiu qu cc chng trnh m chng ta thit
k.
Hnh v 3.2 : Spartan-3 Starter Kit Board nhn t mt di
Tip cn lp trnh cho FPGA t Spartan -3

46
9. Khi 13: 4 nt n. Cng tng t nh 8 chuyn mch, chng ta c th
dng n chn ch lm vic cho bo mch.
10. Khi 15 : V tr cm ca b to dao ng thch anh. B to dao ng
thch anh to ra dao ng chun 50mhz. Chnh v vy, trong qu trnh
thit k, vi cc ng dng c th cn thc hin lm vic tn s ng
b no chng ta phi thc hin chia tn s trung tm ny ra t
c tn s mong mun. Thc t, chng ta hon ton c th kt ni vi
mt b to dao ng a vo t ngoi thng qua cc thnh phn kt ni
A
1
,A
2
, B
1
nh ch ra trn hnh v.
11. Khi 17 v 18: Khi ng chng trnh thng trc trong Rom. Chi tit
ny s c phn tch k khi thc hin mt chng trnh c th.
12. y chng ta cng cn quan tm n cc khi 19, 20 v 21: y l cc
thnh phn dng kt ni vi ngoi vi hoc dn tn hiu ra sau khi
thc hin x l. Cc khi ny tng ng vi cc thnh phn c k
hiu trn bo mch l A
1
, A
2
, B
1
. y l mt chi tit quan trng v cn
phi c bit quan tm v cch thc thc hin u cui s liu.Chnh v
vy khi tin hnh thc hin kt ni vi thnh phn ngoi phi quan tm
n cc mc in p cng nh cc chn tng ng ca n. tin hnh
dung chng ta xt mt cng A
1
nh sau





Th t ca cc chn t phi qua tri, vi chn s mt l chn GND, chn s
3 l chn tng ng vi in p +3.3V, chn s 2 tng ng mc +5V.
Nh vy cc chn l tr chn 1 ni t, cc chn l cn li s c kt ni
mc in p +3.3V, cc chn chn s c kt ni mc in p +5V.
13. Ngoi ra n cn mt s thnh phn khc na. d hnh dung hn
chng ta c th quan st hnh v di y m t cc thnh phn c
kt ni vi XC2s300.

Hnh 3.2 Cng kt ni ngoi vi A
1
Tip cn lp trnh cho FPGA t Spartan -3

47




Hnh 3.3: S khi cc thnh phn trn Spartan-3 Starter Kit
Board
Tip cn lp trnh cho FPGA t Spartan -3

48
II. Gii thiu mi trng lp trnh ISE.
Khi kch thc v phc tp ca cc h thng s gia tng, nhiu cng
c thit k c tr gip bi my tnh CAD (Computer Aided Design) c a
vo qu trnh thit k phn cng. Phng php thit k trn giy c thay bng
cch thit k trn my tnh, t cc nh thit k c th kim tra v c cc cng c
to ra phn cng t ng t cc bn thit k . H tr mnh m nht cho cc cng
c thit k ny l cc ngn ng m t phn cng HDL (Hardware Description
Languages). Hin nay, cc nh nghin cu tm ra nhiu cch cho php HDL c
th ci tin qu trnh thit k h thng s.
Qu trnh thit k bt u t tng thit k ca ngi thit k phn cng.
Lc ny ngi thit k cn phi to ra cc nh ngha cho hnh vi ca h thng di
thit k. Sn phm ny c th l dng s khi, lu hoc ch l dng
ngn ng t nhin. Giai on ny tng thit k mi ch c u vo v u ra,
ch hon ton cha c mt chi tit no v phn cng cng nh kin trc ca h
thng.
Giai on th hai ca qu trnh thit k l vic thit k ng dn d liu h
thng. Trong giai on ny, ngi thit k ch r cc thanh ghi v cc phn t logic
cn thit cho qu trnh ci t. y chnh l giai on thit k th vin cc phn t
cho h thng. Cc thnh phn ny c th c kt ni thng qua bus 2 chiu hoc 1
chiu. Da trn chc nng hoc hnh vi ca h thng, tin trnh iu khin hot
ng ca d liu gia cc thanh ghi v cc phn t logic thng qua cc bus c
pht trin. Giai on ny khng cung cp cc c im v s hot ng ca cc b
iu khin, cch i dy, k thut m ho
Giai on th 3 l l giai on thit k logic, giai on ny lin quan n ng
dng ca cc cng v cc mch c bn cho vic ci t cc thanh ghi d liu, cc
bus h thng, cc phn t logic v phn cng iu khin chng. Kt qu ca giai
on ny chnh l mt danh sch kt ni (netlist).
Giai on thit k tip l chuyn netlist ca giai on trc thnh s hay l
danh sch cc tranzitor. Giai on ny xt n c ch ti v thi gian trong qu
Tip cn lp trnh cho FPGA t Spartan -3

49
trnh thc hin hnh vi ca h thng cng nh vic chn tranzitor hoc cc phn t
ca n. Giai on ny bao gm: tng hp logic, nh x cng ngh, flooplanning,
placement, routing. Giai on ny s dng cng c CAD l ch yu.
Giai on cui cng l np vo kid v kim tra kt qu, hon chnh sn phm.
2.1. Gii thiu gi phn mm ISE:
Phn mm ISE (Integrated Software Environment) ny l mt mi trng thit
k hon ho ca Xilinx, n tr gip cho ngi thit k hu ht cc cng c cn thit
nht c th hon thnh mt n thit k nhanh nht v hiu qu nht. ISE tch
hp cc cng ngh tin tin nht mng li tnh linh hot, giao din GUI thn thin
vi ngi s dng.
Mt s u im ca ISE l:
- Tn dng ti a tt c cc cng ngh tin tin nht ca PLD.
- Tit kim thi gian thit k, h tr tt c cc dng sn phm ca Xilinx.
- Tng hiu qu v gim gi thnh.
- H tr ti a cho vic thit k cc h thng nhng.
B sn phm ISE bao gm cc gi phn mm:
a. ISE WebPACK: y l gi sn phm dng pht trin h thng mt cch
d dng nht v n l mi trng thit k on-line (trc tuyn) trn Web v c h
tr trc tip t Xilinx. ISE WebPACK cho php ngi dng hon thnh bn thit k
nhanh chng nh s kt hp ca cc thit k u vo HDL, cc cng v tng hp
tin tin v kh nng kim tra i vi c CPLD v FPGA trc tuyn.
b. ISE BaseX: y l gi phn mm hiu qu v kinh t nht, l mi trng
thit k PLD trn my tnh c nhn linh hot v n nh. N cung cp tt c cc kh
nng nh ISE WebPACK, ngoi ra n cn c b sung nhiu cng c khc h tr
cho ngi dng.
c. ISE Alliance: gi phn mm ny c thit k ph hp vi mi trng thit
k c sn ca ngi dng. N kt hp cc cng c hay nht ca Xilinx to mi
trng thit k hon chnh vi cc tnh nng cao hn ISE BaseX.
Tip cn lp trnh cho FPGA t Spartan -3

50
d. ISE Foundation: y l gi phn mm hon chnh nht, d s dng, tnh
nng nhiu nht ng thi tch hp cc cng c phn tch, tng hp v cng ngh
kim tra sn phm vi cc gii php hu hiu.
2.2. Hng dn s dng phn mm ISE Foundation 7.1
Giao din chng trnh


Hng dn cc bc to mt n mi ( y la chn kid l Spartan 3)
Bc 1: T mnu file new project in tn vo Poject name
chn th mc lu project location chn ngn ng vit
next:


Hnh 3.4: Giao din chnh ca mi trng lp trnh ISE 7.1
Hnh 3.5: To mt n mi
Tip cn lp trnh cho FPGA t Spartan -3

51
Bc 2: La chn kid l spartan-3, loi Xc3s200, speed grade l -4,
ngn ngi son tho l VHDL, m phng dng ModenSim.



Bc 3.Sau khi l xong bc trn chng ta next, s c mt ca s ta
thm ngun mi vo n. Chn New source next chn Vhdl
module chn tn m un next:




Hnh3.6: Cc la chn c th cho mt n.
Hnh 3.7: Thm mt module vo n thit k.
Tip cn lp trnh cho FPGA t Spartan -3

52
Bc 4: Chn cc cng vo ra cho n.

Bao gm tn cng, m t vo (in), ra(out) hay vo ra (in- out). S bt vo ra
tng ng vi cc cng. Cc bc tip theo c next n khi k thc (finish). Sau
khi nh ngha v m t xong bc ny lc trnh dch s t ng to ra thc th
vi cc cng c m t bng lnh ( VHDL) nh sau:
entity chiatansodauvao is
Port ( clock : in std_logic;
1hz : out std_logic;
led : out std_logic_vector(7 downto 0));
end chiatansodauvao;
architecture Behavioral of chiatansodauvao is
begin
end Behavioral;
Nh vy ta to ra mt n. Tip theo l ta vit chng trnh ca s son tho.
Vn t ra l vi chng trnh ln c nhiu hn mt m ule ta s lm th no?
chng ny ta ch gii thiu cch thc chng ta to ra mt n mi. Cc
phn cn li bao gm kim tra cu trc lnh, kim tra mc logic, gn chn, np cu
hnh chy th s c hng dn chi tit cng vi bi tp c th.

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53
CHNG IV: NGN NG VHDL

4.1. Gii thiu chung v ngn ng VHDL
VHDL (VHSIC Hardware Description Laguage) l mt ngn ng c dng
m t cc h thng in t s. N c chng trnh quc gia v Cc mch tch
hp Tc rt cao - VHSIC (Very High Speed Integrated Circuits) do chnh ph
M khi xng vo u nhng nm 1980. Cc cng ty tham gia chng trnh
VHSIC nhn thy rng h cn phi c mt cng c no thit k cc gin
u vo cho cc IC chuyn dng c ln, v h xut vic lp ra mt ngn ng
m t phn cng dng m t cu trc v chc nng ca cc mch tch hp (cn
c gi l IC - Integrated Circuits).
K t , VHDL ra i v c pht trin, ri sau c Hip hi cc k s
in v in t - IEEE (Institude of Electrical and Electronic Engineers) chp
nhn coi nh l tiu chun ti M. Phin bn u tin l Tiu chun IEEE 1076-
1987 (cn c gi l VHDL-87). Phin bn ny c b sung sa i nm 1993
thnh IEEE 1076-1993 (cn c gi l VHDL-93).
VHDL c thit k nhm thay th cho mt s khu cn thit trong qu trnh
thit k. u tin, n cho php m t cu trc ca mt bn thit k, tc l lm th
no c th phn tch bn thit k thnh cc bn thit k con, v lm th no
kt ni cc bn thit k con li vi nhau. Th hai l n cho php m t c im
chc nng ca cc bn thit k tng t nh trong ngn ng lp trnh. Th ba l da
vo kt qu t c, n cho php mt bn thit k c th m phng c trc khi
a vo sn xut, v vy cc nh thit k c th so snh mt cch nhanh chng vic
thay th v kim tra iu chnh chnh xc m khng mt thi gian v tin bc vo
vic ch to mu th u tin.
4.1.1. M t cu trc (Describing Structure)
Mt h thng in t s c th c m t thnh cc khi - cn gi l modul
(module) vi cc u vo v/hoc u ra. Cc gi tr in 0 u ra c mi quan h
Tip cn lp trnh cho FPGA t Spartan -3

54
vi cc gi tr trn cc u vo. Hnh 4.1.a biu din mt v d nh vy. Khi F c
hai u vo A v B, v c mt u ra Y.

Hnh 4.1. (a) Khi F c hai u vo v mt u ra;
(b) Khi F gm c 3 thc th G, H v I
S dng ngn ng VHDL m t khi F, th ta gi khi F l mt thc th
(entity) thit k, v cc u vo v u ra l cc cng (port).
C mt cch m t chc nng ca khi F, l chng ta m t cc khi con
(sub-module) thnh phn ca n. Mi mt khi con c gi l mt tp hp
(instance) ca mt vi thc th, v cc cng ca cc tp hp c ni li bng
cc ng tn hiu (signal).
Hnh 4.1.b m t khi F l mt tp hp gm cc thc th G, H v I. Kiu m
t ny c gi l m t cu trc (structural). Cc thc th G, H v I cng c m
t theo cu trc tng t nh vy.
4.1.2. M t hot ng (Describing Behaviour)
Trong nhiu trng hp, vic m t cu trc khng tng ng vi vic m t
hot ng. Ngi ta thng dng cch m t hot ng theo kiu t di ln da
vo m t cu trc. V d, khi chng ta thit k h thng in t th khng cn phi
m t c th cu trc bn trong ca tng con IC m ch cn m t theo chc nng
ca cc khi ca h thng m thi. Trng hp ny c gi l m t chc nng
(fuctional) hoc m t hot ng (behavioural).
Tip cn lp trnh cho FPGA t Spartan -3

55
minh ho cho iu ny, chng ta gi s rng chc nng ca thc th F
trong hnh 4.1(a) l mt mch OR o. Khi m t hot ng ca F ta c th bin i
theo i s Boolean nh sau:
B A B A Y . . + =
i vi cc mch c chc nng hot ng phc tp hn, th khng th bin
din theo cc chc nng u vo c. Trong cc h thng c phn hi ngc, u
ra thng l cc hm chc nng theo thi gian. Ngn ng VHDL cho php gii
quyt vn ny bng cch m t hot ng theo khun dng chng trnh lp
trnh.
4.1.3. M hnh thi gian theo cc s kin ri rc
Khi chc nng hot ng v cu trc ca khi c ch nh r, th ngi ta
c th m phng khi bng cch kch hot theo m t hot ng ca n. iu ny
c th thc hin c bng cch m phng qu trnh hot ng c ri rc
thnh cc bc theo thi gian. Ti mt vi thi im m phng, khi u vo c
kch hot bng cch theo i gi tr trn cng u vo. Khi ny phn ng li bng
cch thc hin m lnh theo m t hot ng ca n c gn v to ra cc gi
tr mi a n ng tn hiu a n cc cng u ra ca n ti cc thi im
m phng tip theo sau. Vic ny c gi l k hoch giao tc (scheluding a
transaction) trn tn hiu . Nu gi tr mi khc gi tr trc c trn ng
tn hiu, th s c mt s kin (event) xy ra, v cc khi khc vi cc u vo
c kt ni vi ng tn hiu c th s c kch hot.
Qu trnh m phng bt u vi mt pha c gi l pha khi ng (initilation
phase), v sau cc qu trnh c thc hin lp li hai giai on trong mt chu
k m phng (simulation cycle). Trong pha khi ng, tt c cc tn hiu c cung
cp sn cc gi tr khi ng, thi gian m phng c a v 0, v mi mt
chng trnh hot ng ca mt khi c kch hot.
Trong giai on u tin ca chu k m phng, thi gian m phng c nng
ln thnh thi gian sm nht ti thi im m giao tc c thc hin. Tt c cc
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giao tc c a vo ti thi im ny u c kch hot, v iu ny c th gy
ra mt s s kin no .
Trong gian on th hai ca chu k m phng, tt c cc khi m phn ng li
i vi cc s kin va xy ra trong giai on mt s kch hot chng trnh hot
ng ca chng. Cc chng trnh thng l k hoch giao tc trn cc tn hiu
u ra ca chng. Khi tt c cc chng trnh kt thc hot ng, chu k m phng
c lp li. Nu khng c thm giao tc no th qu trnh m phng hon thnh.
Mc ch ca vic m phng l bit thm thng tin v s thay i trong h
thng ti tng thi im. Vic ny c th thc hin c gim st bi chng trnh
kim sot m phng (simulation monitor). Chng trnh ny nhm mc ch ghi li
qu trnh hot ng theo tng thi im ti cc im dng vo vic phn tch v
sau.

4.1.4. V d
Chng ta c mt b m hai bit COUNT nh trong hnh v 4.2, gm c 3
khi: 2 khi T_FLIPFLOP v mt khi INVERTER. B m ny c 2 u ra l q1
v q0, mt u vo l clock.

Hnh 4.2. S b m COUNT
Dng ngn ng VHDL nh ngha b m ny nh sau:
entity count2 is
generic (prop_delay : Time := 10 ns);
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port (clock : in bit; q1, q0 : out bit);
end count2;
Nhn vo on chng trnh trn chng ta thy b m COUNT c nh
ngha vi mt cng vo clock v hai cng ra q1, q0 u thit lp theo cc gi tr bit.
Hng s prop_delay c s dng iu khin hot ng ca COUNT vi thi
gian m s l 10 ns mt ln. Trn y mi ch l nh ngha b m, cn hot ng
ca b m ny s c vit theo hai cch.
Cch th nht l vit theo hot ng ca b m:
architecture behaviour of count2 is
begin
count_up: process (clock)
variable count_value : natural := 0;
begin
if clock = '1' then
count_value := (count_value + 1) mod 4;
q0 <= bit'val(count_value mod 2) after prop_delay;
q1 <= bit'val(count_value / 2) after prop_delay;
end if;
end process count_up;
end behaviour;
C th vit li hot ng da theo thnh phn cc khi trong b m v ng
tn hiu nh sau:
architecture structure of count2 is
component t_flipflop
port (ck : in bit; q : out bit);
end component;
component inverter
port (a : in bit; y : out bit);
end component;
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signal ff0, ff1, inv_ff0 : bit;
begin
bit_0 : t_flipflop port map (ck => clock, q => ff0);
inv : inverter port map (a => ff0, y => inv_ff0);
bit_1 : t_flipflop port map (ck => inv_ff0, q => ff1);
q0 <= ff0;
q1 <= ff1;
end structure;
4.2. C php v ng ngha ()
Theo nh vn cp trong mc 4.1, hot ng ca mt khi (module) c
th c m t theo dng ngn ng lp trnh. Trong mc 4.2 ny s gii thiu v c
php v ng ngha ca cc khi bo trong ngn ng BHDL.
4.2.1. Cc thnh phn t vng
4.2.1.1. Ch thch trong chng trnh
Phn ch thch trong chng trnh vit bng VHDL c phn bit bng du
gch ngang (--) v c tc dng n ht dng .
4.2.1.2. Cc kiu nh danh
Cc nh danh trong VHDL s dng bng cc t ring v do ngi lp trnh
nh ngha tn. Chng phi tun theo cc qui tc sau:
nh danh ::= ch ci {[du gch di] ch ci hoc s}
V d:
signal ff0:bit; -- ng tn hiu ff0 thuc signal
-- c nh ngha l n v l bit
Ch trng hp cc ch ci khng c trng vi k t c bit nh cc
n v, cc k t c bit, cc tn chc nng nh ns, ms, FF, read, write...
4.2.1.3. Cc kiu s
Cc s bng ch c th biu din theo h thp phn hoc h c s khc nh h
c s 2 (h nh phn), h c s 16 (h hexa). Nu cc ch bng s c du phy, n
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biu din s thc, ngc li l biu din s nguyn. S h thp phn c nh
ngha nh sau:
s thp phn bng ch::=s nguyn[.s nguyn][s m]
s nguyn::=bng s{[du gch di]bng s}
s m::=E[+]s nguyn|E-s nguyn
V d:
0 1 123_456_789 987E6 -- cc s nguyn biu din bng ch
0.0 0.5 2.718_28 12.4E-9 -- cc s thc biu din bng ch
Cc s bng ch h c s khc c nh ngha nh sau:
s h c s bng ch::=k hiu c s#s nguyn h c s[.s nguyn h c
s]#[s m]
s h s c::=s nguyn
s nguyn h c s::=s m m rng{[du gch di]bng s m rng}
s m m rng::=bng s|ch ci
Cc thnh phn c s v s m c biu din theo h thp phn. Cc ch ci
t A n F (c ch thng v in hoa) c s dng nh phn s m rng dng
biu din cc s thp phn t 10 n 15 tng ng.
V d:
2#1100_0100# 16#C4# 4#301#E1 -- c ngha l bng s nguyn 196
2#1.1111_1111_111#E+11 16#F.FF#E2 -- c ngha l bng s thc 4095.0
4.2.1.4. Kiu k t
Cc k t bng ch c khun dng tun theo chun ASCII nm du nhy n.
V d:
A * `
4.2.1.5. Kiu xu
Cc xu bng ch dng cc k t c khun dng nm trong du nhy kp.
V d:
A string
-- xu trng
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A string in a string: A string. -- xu cha du nhy kp
4.2.1.6. Kiu xu dng bit
VHDL cung cp kiu bin dng bit (0 v 1). C php nh sau:
xu bit bng ch::=k hiu h c s gi tr bng bit
k hiu h c s::=B|O|X
gi tr bng bit::=s m m rng{[du gch di]s m m rng}
K hiu h c s l B - tc l h nh phn, O - l h 8 (octal) v X l h 16
(hexa).
V d:
B 1010110 -- di l 7
O 126 -- di l 9, tng ng vi B 001_010_110
X 56 -- di l 8, tng ng vi B 0101_0110
4.2.2. Cc kiu d liu v i tng
VHDL cung cp cc kiu d liu s c bn, cc kiu d liu v hng, v cc
dng i tng tng hp gm nhiu thnh phn. Cc kiu d liu v hng gm c
cc kiu s, n v vt l, v cc s m (gm c c cc s m kiu k t), v
ngoi ra cn c cc kiu c nh ngha sn. Kiu i tng tng hp gm c
kiu bn ghi v mng. VHDL cng cung cp cch thc truy xut kiu con tr
(pointer) v kiu tp (file).
nh ngha mt kiu d liu trong chng trnh c m t nh sau:
M t tn y ca kiu d liu ::= type tn nh danh is nh ngha kiu
nh ngha kiu ::=
nh ngha kiu v hng
|nh ngha kiu tng hp
|nh ngha kiu truy xut con tr
|nh ngha kiu tp
nh ngha kiu v hng ::=
nh ngha kiu s m
| nh ngha kiu s nguyn
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|nh ngha kiu s du phy ng|
|nh ngha kiu n v vt l
nh ngha kiu tng hp ::=
nh ngha kiu mng
|nh ngha kiu bn ghi
4.2.2.1. Kiu s nguyn
Kiu s nguyn c phm vi lm vic trong cc gi tr ca s nguyn c
ch nh sn. C php ca kiu s nguyn nh sau:
nh ngha kiu s nguyn ::= phm vi cho php
phm vi cho php ::= range phm vi
phm vi ::= biu thc n iu khin biu thc n
iu khin ::= to | downto tng | gim
Biu thc ch nh trong phm vi phi c biu din bng s nguyn. Cc
kiu c km thm t kho to c gi l c phm vi tng v cng nh vy vi t
kho downto th c gi l c phm vi gim. VHDL chun cng cho php hot
ng trong phm vi cm, nhng yu cu ti a l trong phm vi t -2147483647
n + 2147483647.
V d v kiu s nguyn:
type byte_int is range 0 to 255;
-- kiu byte_int l kiu s nguyn c phm vi t 0 n 255
type signed_word_int is range 32768 to 32767;
-- kiu signed_word_int l kiu s nguyn c phm vi t -32768
-- n 32767
type bit_index is range 31 downto 0;
-- kiu bit_index l kiu s nguyn c phm vi gim t 31
-- xung 0
4.2.2.2. Kiu n v vt l
Kiu n v vt l l kiu s dng biu din mt vi n v vt l, chng
hn nh khi lng, chiu di, thi gian hoc in p. Vic biu din kiu n v
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vt l bao gm tham s ca n v c s, c th c thm mt s n v th cp,
c dn xut bng cch nhn vi n v c s.
C php ca kiu n v vt l nh sau:
nh ngha kiu vt l ::=
phm vi cho php
units
m t n v c s
{m t n v th cp}
end units
m t n v c s ::= nh danh;
m t n v th cp ::= nh danh = kiu biu din vt l bng ch
kiu biu din vt l bng ch ::= [kiu s o bng ch] tn n v
V d v kiu n v vt l:
type length is range 0 to 1E9
units
um;
mm = 1000 um;
cm = 10 mm;
m = 1000 mm;
in = 25.4 mm;
ft = 12 in;
yd = 3 ft;
rod = 198 in;
chain = 22 yd;
furlong = 10 chain;
end units;
type resistance is range 0 to 1E8
units
ohms;
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kohms = 1000 ohms;
Mohms = 1E6 ohms;
end units;
Ring kiu n v vt l thi gian (time) rt quan trng trong VHDL, v n
c s dng rt nhiu trong cc thit b m phng tr thi gian. N c nh
ngha nh sau:
type time is range implementation_defined
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
ghi gi tr ca mt kiu s vt l no c nh ngha th vit s
trc v tip theo l n v o ca n. V d: 10 mm; 10 rod; 1200 ohms; 23 ns.
4.2.2.3. Kiu s du phy ng
Kiu s du phy ng l mt tp ca kiu s thc trong mt phm vi ch nh
trc. Phm vi cho php ca kiu s du phy ng t -1E38 n +1E38. C php
ca kiu s du phy ng nh sau:
nh ngha kiu s du phy ng := phm vi cho php
V d:
Type signal_level is range 10.00 to +10.00;
Type probability is range 0.0 to 1.0;
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4.2.2.4. Cc kiu lit k
Kiu lit k l mt tp cc nh danh hoc cc k t c sp xp. Cc nh
danh v cc k t trong kiu lit k phi ring bit, r rng, tuy nhin chng c th
c s dng li trong cc kiu lit k khc nhau.
C php ca kiu lit k nh sau:
nh ngha kiu lit k ::= (kiu biu din lit k bng ch {, biu din kiu
lit k bng ch})
Kiu biu din kiu lit k bng ch ::= nh danh | kiu biu din bng k t
V d:
Type logic_level is (unknown, low, undriven, high);
Type alu_function is (disable, pass, add, subtract, multiply, divide);
Type octal_digit is (0, 1, 2, 3, 4, 5, 6, 7);
C mt s kiu lit k c nh ngha sn:
Type severity_level is (note, warning, error, failure);
Type boolean is (false, true);
Type bit is (0, 1);
Ngoi ra cn mt kiu k t c nh ngha sn l
type character is (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT,
LF, VT, FF, CR, SO, SI, DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN,
EM, SUB, ESC, FSP, GSP, RSP, USP, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-',
'.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E',
'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '[',
'\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u',
'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~', DEL);
Kiu k t ny bao gm c cc k t nh danh, s v cc ch ci.
4.2.2.5. Kiu mng
Kiu mng trong VHDL l mt tp hp c nh ch mc cc phn t c
cng kiu. Mng c th l mt chiu hoc nhiu chiu. Ngoi ra, kiu mng c th
t to - tc l phm vi ca mt ch mc c thit lp khi kiu c nh ngha.
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Hoc c th l mng t nhin - tc l phm vi ca ch mc c thit lp theo th t
tun t.
C php ca mng nh sau:
nh ngha kiu mng ::= nh ngha mng t to | nh ngha mng t nhin
nh ngha mng t to :: = array (nh ngha kiu ch mc con {, nh ngha
kiu ch mc}) of biu din ca cc phn t trong mng
nh ngha mng t nhin :: = array kiu ch mc t nhin of biu din ca
cc phn t trong mng
nh ngha kiu ch mc con ::= kiu nh du range <>
kiu ch mc t nhin ::= (phm vi ri rc {, phm vi ri rc})
phm vi ri rc ::= biu din kiu ri rc con | phm vi
nh ngha kiu ch mc con c trnh by trong mc 3.2.2.7.
V d v mng t nhin:
Type word is array (31 downto 0) of bit;
Type memory is array (address) of word;
Type transform is array (1 to 4, 1 to 4) of real;
Type register_bank is array (byte range 0 to 132) of integer;
V d v mng t to:
Type vector is array (integer range <>) of real;
K hiu <> (c gi l hp (box)) c th l kiu trng dnh s dng
trong chng trnh. Trong v d trn, khi mt i tng c th biu din theo kiu
vector c 20 phn t bng cch cung cp cho kiu vector ca n nh sau:
Vector(1 to 20);
C hai kiu mng c nh ngha sn v c hai u l l kiu t to:
Type string is array (positive range <>) of character;
Type bit_vector is array (natural range <>) of bit;
Kiu positive v natural s c trnh by trong mc 3.2.2.7.
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4.2.2.6. Kiu bn ghi
VHDL cung cp cc kiu bn ghi c bn mt cch linh hot, bao gm tp hp
tn cc phn t v kiu nh ngha ca chng.
C php ca kiu bn ghi nh sau:
nh ngha kiu bn ghi ::=
record
m t cc phn t
{m t cc phn t}
end record
m t cc phn t ::= lit k cc nh danh : nh ngha kiu phn t con;
lit k cc nh danh ::= nh danh {, nh danh}
nh ngha kiu phn t con ::= biu din kiu phn t con
V d:
Type instruction is
Record
Op_code : processor_op;
Address_mode : mode;
Operand1, operand2 : integer range 0 to 15;
End record;
4.2.2.7. Cc kiu con
Vic s dng kiu con cho php cc gi tr nhn c qua mt i tng b
hn ch v thu hp trong mt vi kiu. C php ca kiu con l:
m t kiu con ::= subtype tn nh danh is biu din kiu con;
biu din kiu con ::= [tn hm phn gii] kiu nh du [phm vi]
kiu nh du ::= tn kiu | tn kiu con
phm vi ::= di phm vi | ch s phm vi
C hai kiu con, th nht l kiu con c th c hn ch cc gi tr t mt kiu
v hng cng vi phm vi c ch nh. V d nh:
subtype pin_count is integer range 0 to 400;
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subtype digits is character range 0 to 9;
Th hai l kiu con c th c hn ch theo dng mng. V d nh:
subtype id is string(1 to 20);
subtype word is bit_vector(31 downto 0);
Ngoi ra cn c hai kiu con dng s nh ngha trc, v d nh:
subtype natural is integer range 0 to highest_integer
subtype positive is integer range 1 to highest_integer
4.2.2.8. Cc m t v i tng
Mt i tng l mt thnh phn c t tn trong mt m t VHDL m c
gi tr theo kiu c ch nh. C 3 lp i tng: hng s, bin s v tn hiu.
hai kiu u c trnh by sau y, cn kiu th ba s c trnh by trong phn
3.3.2.1. Vic m t v s dng cc hng s v bin s hon ton ging nh trong
cc ngn ng lp trnh khc.
Mt hng s l mt i tng c khi ng theo mt gi tr ch nh trc
khi n c khi to, v khng th thay i. C php ca n l:
m t hng s ::=
constant lit k tn nh danh : biu din kiu con [ := biu thc ]
Cc m t hng s thiu biu thc khi ng c gi l cc hng s hon, v
ch c th xut hin trong cc m t ng gi (xem mc 3.2.5.3). Gi tr khi ng
phi c cung cp tng ng trong thn ng gi.
V d:
constant e : real := 2.71828;
constant delay : Time := 5 ns;
constant max_size : natural;
Mt bin l mt i tng m gi tr c th thay i c sau khi khi ng.
C php ca n l:
m t bin ::=
variable lit k tn nh danh : biu din kiu con [ := biu thc ]
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Nu vng thnh phn biu thc, th mt gi tr mc nh s c gn khi bin
c khi to. Nu gi tr mc nh i vi cc kiu v hng l gi tr bn tri
nht ca kiu , th l kiu s u tin trong danh sch, v l gi tr thp nht
theo th t sp xp t di ln, hoc cao nht t trn xung. Nu bin l mt kiu
t hp, th gi tr mc nh l t hp ca cc gi tr mc nh i vi tng phn t,
da trn kiu ca phn t.
V d:
variable count : natural := 0;
variable trace : trace_array;
Da vo mt i tng c sn, n c th cung cp tn thay th cho mt phn
hoc c i tng . thc hin, ngi ta s dng kiu m t tn ph (alias). C
php nh sau:
m t tn ph ::= alias tn dnh danh : biu din kiu con is tn;
V d nh sau:
variable instr : bit_vector(31 downto 0);
alias op_code : bit_vector(7 downto 0) is instr(31 downto 24);
4.2.2.9. Cc thuc tnh
Cc kiu v cc i tng c m t trong mt m t VHDL c th c thm
thng tin ph, v c gi l cc thuc tnh, tng ng vi chng. y l mt s
thuc tnh chun nh ngha sn. Mt thuc tnh c tham chiu bng cch s
dng du `. V d:
thing`attr
u tin, i vi bt k kiu v hng hoc kiu con T no, c th s dng
cc thuc tnh sau:
Thuc tnh Kt qu tr v
T'left Left bound of T --
T'right Right bound of T
T'low Lower bound of T
T'high Upper bound of T
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i vi phm vi sp xp tng dn, T`left = T`low v T`right = T`high. i vi
phm vi sp xp gim dn, T`left = T`high v T`right = T`low.
Th hai, i vi bt k kiu vt l hoc kiu con T, kiu con X l mt phn
ca kiu con T v kiu s nguyn N, th c th s dng cc thuc tnh sau:
Thuc tnh Kt qu tr v
T'pos(X) Position number of X in T
T'val(N) Value at position N in T
T'leftof(X) Value in T which is one position left from X
T'rightof(X) Value in T which is one position right from X
T'pred(X) Value in T which is one position lower than X
T'succ(X) Value in T which is one position higher than X
i vi phm vi sp xp tng dn, T'leftof(X) = T'pred(X) v T'rightof(X) =
T'succ(X). i vi phm vi sp xp gim dn T'leftof(X) = T'succ(X) v
T'rightof(X) = T'pred(X).
Th ba, i vi bt k kiu mng hoc i tng kiu A, th c th s dng
cc thuc tnh sau:
Thuc tnh Kt qu tr v
A'left(N) Left bound of index range of dimn N of A
A'right(N) Right bound of index range of dimn N of A
A'low(N) Lower bound of index range of dimn N of A
A'high(N) Upper bound of index range of dimn N of A
A'range(N) Index range of dimn N of A
A'reverse_range(N) Reverse of index range of dimn N of A
A'length(N) Length of index range of dimn N of A
4.2.3. Cc biu thc v ton t
Cc biu thc trong VHDL hon ton tng t nh cc biu thc trong cc
ngn ng lp trnh khc. Mt biu thc l mt cng thc kt hp cc a thc vi
cc ton t. Cc a thc bao gm tn cc i s, k hiu bng ch, cc hm gi v
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cc du ngoc ca biu thc. Cc ton t c lit k trong bng 4.1 theo th t u
tin.
Bng 4.1. Cc ton t v th t u tin
u tin cao nht: **; abs; not;
*; /; mod; rem;
+ (sign); (sign)
+; ; &;
=; /=; <; <=; >; >=;
u tin thp nht: And; or; nand; nor; xor;
Cc ton t logic and, or, nand, nor, xor v not hot ng trn cc gi tr kiu
bit hoc l boolean, v trn cc mng 1 chiu ca cc kiu . i vi cc ton hng
l mng (array), s hot ng tun theo cc phn t tng ng ca tng mng,
thng th ln ca mng c cng ln vi kt qu. i vi cc ton hng bit v
boolean, cc ton t and, or, nand v nor l cc ton t ngn mch (short-circuit),
do chng ch u tin hn so vi ton hng bn phi ca chng nu ton hng bn
tri khng xc nh c kt qu. Do and v nand ch u tin hn so vi ton hng
bn phi nu ton hng bn tri l true hoc 1, cn or v nor ch u tin hn
ton hng bn phi nu ton hng bn tri l false hoc 0.
Cc ton t quan h =, /=, <, <=, > v >= phi c cc ton hng hai u cng
kiu, v thng l cho cc kt qu theo kiu boolean. Cc ton t bng (= v /=) c
th c cc ton hng theo bt k kiu no. i vi cc ton t so snh, hai gi tr
bng nhau nu tt c cc phn t tng ng ca chng bng nhau. Cc ton t cn
li phi c cc ton hng c kiu v hng hoc mng mt chiu ca cc kiu ring
bit.
Cc ton t du (+ v -), cc ton t cng (+) v tr (-) c cch s dng ca
chng trn cc ton hng dng s. Ton t mc xch (&) lm vic trn cc mng
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mt chiu thnh dng mt mng mi vi ni dung ca ton hng bn phi k tip
ton hng tri. N c th mc ni mt phn t n vo mt mng hoc hai phn t
c lp thnh mt mng mi. Ton t mc xch s dng cho hu ht cc xu.
Cc ton t nhn (*) v chia (/) lm vic vi cc s nguyn, s du phy ng
v cc kiu n v vt l. Cc ton t chia ly phn nguyn (mod- modulus) v chia
ly phn d (rem - remainder) ch lm vic vi kiu s nguyn. Ton t gi tr tuyt
i (abs) ch lm vic vi bt k kiu s no. Cui cng ton t m (**) c th lm
vic vi kiu s nguyn v ton hng tri ca kiu s du phy ng, nhng phi c
mt s nguyn ton hng phi, cn ton hng phi m m ch c php nu ton
hng tri l mt s du phy ng dng s.
4.2.4. Cc khai bo tun t
VHDL cung cp mt cong c hiu qu cho vic kim tra trng thi ca cc i
tng v iu khin lung hot ng ca cc m hnh.
4.2.4.1. Php gn bin (Variable Assignment)
Nh cc ngn ng lp trnh khc, mt bin c gn mt gi tr mi bng
cch s dng mt khai bo gn. C php l:
khai bo gn bin ::= ch := biu thc;
ch ::= tn | tp hp
Trong trng hp n gin nht, ch ca php gn l mt tn i tng, v
gi tr ca biu thc c gn theo tn i tng. i tng v gi tr phi c cng
mt kiu.
Nu ch ca php gn l mt tp hp, th cc phn t c lit k phi l cc
tn ca i tng v gi tr ca biu thc phi l mt gi tr a thc c cng kiu
nh tp hp. u tin, tt c cc tn trong tp hp c nh gi, sau biu thc
c nh gi, v cui cng l cc thnh phn ca gi tr biu thc c gn thnh
tn cc bin. Vic ny c gi l hiu ng ca php gn song song. V d, nu mt
bin r lm mt bn ghi c hai trng a v b, th chng c th trao i bng cch
vit:
(a => r.b, b => r.a) := r
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4.2.4.2. Khai bo If (nu)
Khai bo If cho php la chn cc khai bo kch hot ph thuc vo mt
hoc nhiu iu kin. C php l:
khai bo if ::=
if iu kin then
chui cc khai bo
{ elsif iu kin then
chui cc khai bo
[ else
chui cc khai bo }
end if;
Cc iu kin l cc biu thc tr v gi tr boolean. Cc iu kin c nh
gi l ng khi c mt gi tr c tr v true. Ngc li th mnh else c
thc hin, v khai bo ca n c kch hot.
4.2.4.3. Khai bo Case (cy)
Khai bo case cho php la chn cc khai bo kch hot ph thuc vo gi
tr ca mt biu thc chn. C php l:
khai bo case ::=
case biu thc is
khai bo case c th chn
{ khai bo case c th chn }
end case;
khai bo case c th chn ::=
when cc la chn =>
chui cc khai bo
cc la chn ::= la chn { | la chn}
la chn ::=
biu thc n
| phm vi n
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| tn phn t n
| others
Biu thc chn phi a n hoc l kiu ri rc hoc l mng mt chiu cc
k t. Khi mt la chn trong danh sch cha gi tr ca biu thc c chn th
khai bo ca la chn c kch hot. Cc la chn phi c lp, khng c gi
tr trng nhau. Ngoi ra, tt c cc gi tr phi c biu din trong bng danh sch
cc la chn, hoc others c bit phi nm trong khai bo cui cng. Nu khng c
la chn no cha gi tr ca biu thc, th others s c chn. Nu biu thc kt
qu l mt mng, th cc la chn c th l mt xu hoc mt xu bt.
V d th nht:
case element_colour of
when red =>
statements for red;
when green | blue =>
statements for green or blue;
when orange to turquoise =>
statements for these colours;
end case;
V d th 2:
case opcode of
when X"00" => perform_add;
when X"01" => perform_subtract;
when others => signal_illegal_opcode;
end case;
4.2.4.4. Cc khai bo vng lp
VHDL c mt khai bo vng lp c bn c th s dng cc vng lp while v
for ging nh trong cc ngn ng lp trnh khc. C php ca mt khai bo vng
lp l:
khai bo vng lp ::=
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[ nhn vng lp : ]
[ lc lp ] loop
chui cc khai bo
end loop [ nhn vng lp ];
lc lp ::=
while iu kin
| for c im tham s lp
c im tham s lp
nh danh in phm vi n
Nu lc lp b b qua, chng ta s b ri vo vng lp v tn. V d v
mt vng lp v tn:
loop
do_something;
end loop;
Lc lp while cho php kim tra mt iu kin nh gi trc mi mt
vng lp. Vng lp ch c thc hin nu vic kim tra c nh gi l ng
(true). Nu vic kim tra l sai (false), th khai bo vng lp s kt thc. V d nh
sau:
while index < length and str(index) /= loop
index := index + 1;
end loop;
Lc lp for cho php ch nh mt s c nh vng lp. c im tham s
lp c m t l mt i tng s thc hin vi gi tr ng trong phm vi cho
i vi mi vng lp. Cng vi cc khai bo ng trong vng lp, i tng c
coi nh l hng s, v do vy khng th gn c. V d nh:
for item in 1 to last_item loop
table(item) := 0;
end loop;
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C hai khai bo b sung c th s dng bn trong vng lp kim tra mu c
s ca vng lp. Khai bo next kt thc vic kch hot vng lp hin thi v bt
u vng lp con. Khai bo exit kt thc vic kch hot vng lp hin thi v kt
thc lun vng lp. C php ca cc khai bo l:
khai bo next ::= next [ nhn vng lp ] [ when iu kin ];
khai bo exit ::= exit [ nhn vng lp ] [ when iu kin ];
Nu nhn vng lp b b qua, th khai bo c p dng cho vng lp gn n
nht, ngc li n c gn cho tn ca vng lp. Nu mnh when tn ti nhng
iu kin li sai (false), th vng lp s tip tc bnh thng.
V d:
for i in 1 to max_str_len loop
a(i) := buf(i);
exit when buf(i) = NUL;
end loop;
V d:
outer_loop : loop
inner_loop : loop
do_something;
next outer_loop when temp = 0;
do_something_else;
end loop inner_loop;
end loop outer_loop;
4.2.4.5. Khai bo Null (rng)
Khai bo null khng c hiu qu. N c th c s dng biu din trng
thi r rng l khng c hnh ng no c yu cu trong trng hp . Ngi ta
thng s dng n trong cc khai bo case, trong tt c cc gi tr c th ca
biu thc la chn phi c lit k chn, nhng i vi mt vi la chn th
khng yu cu hnh ng no.
V d:
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case controller_command is
when forward => engage_motor_forward;
when reverse => engage_motor_reverse;
when idle => null;
end case;
4.2.4.6. Cc xc nhn
Mt khai bo xc nhn c s dng kim tra mt iu kin c ch
nh v lp bo co nu iu kin b vi phm. C php l:
khai bo xc nhn ::=
assert iu kin
[ report biu thc ]; -- bo co bng biu thc
[ severity biu thc ]; -- mc vi phm bng biu thc
Nu mnh report tn ti, kt qu ca biu thc phi tr v mt xu. y l
thng ip s c bo co nu iu kin l sai (false). Nu n b b qua, thng
ip mc nh l Assertion violation. Nu mnh severity tn ti, biu thc phi
tr v mc vi phm severity_level. Nu n b b qua, gi tr ngm nh l error.
4.2.5. Cc chng trnh con v cc dng ng gi
Ging nh cc ngn ng lp trnh khc, VHDL cung cp cng c thc hin
chng trnh con linh hot di dng cc th tc v cc hm. VHDL cng cung cp
mt kiu ng gi mnh i vi tp cc m t v cc i tng a vo cc n v
dng modul. Cc ng gi cng cung cp mt tiu chun v tnh tru tng d liu
v thng tin n.
4.2.5.1. Cc th tc v hm
Cc chng trnh con dng th tc v hm c m t theo c php sau:
m t chng trnh con ::= c im chng trnh con ;
c im chng trnh con ::=
procedure tn ch nh [ ( danh sch tham bin chnh ) ]
| function tn ch nh [ ( danh sch tham bin chnh ) ] return nh du
kiu tr v
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Mt chng trnh con m t theo c php trn c cc tn n gin ca chng
trnh con v ch nh tham s theo yu cu. Thn ca cc khai bo nh ngha hot
ng ca chng trnh con phi thc hin theo. i vi cc chng trnh con dng
hm (function), vic m t cng ch ra kiu ca kt qu tr v khi hm c gi.
Khun dng chng trnh con ny m t kiu thng dng c dng trong cc c
im ng gi (xem thm mc 3.2.5.3), trong thn chng trnh con c gn
trong thn ca ng gi, hoc nh ngha cho cc th tc qui.
C php i vi vic ch nh cc tham bin chnh ca chng trnh con l:
danh sch tham bin chnh ::= danh sch giao din tham s
danh sch giao din ::= phn t giao din { ; phn t giao din }
phn t giao din ::= m t giao din
m t hng s giao din
| m t tn hiu giao din
| m t bin giao din
m t hng s giao din
[constant] danh sch nh danh : [in] k hiu kiu con [ := biu thc tnh ]
m t bin giao din
[variable] danh sch nh danh : [mode] k hiu kiu con [ := biu thc tnh
]
Chng ta ch cp n cc tham s hng s v cc tham s bin, mc d cc
tham s tn hiu cng c th c s dng, tuy nhin phn ny c cp n
trong mc 3.3. u tin l v d n gin v mt th tc khng c tham s:
procedure reset;
Vic gi th tc reset trn thc hin n gin nh sau:
reset;
Tip theo l mt th tc c vi tham s:
procedure increment_reg(variable reg: inout word_32;
constant incr: in integer := 1)
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Th tc increment_reg c hai tham s l reg v incr. reg l tham bin, trong
thn chng trnh con n c s dng nh mt i tng bin v c th gn cho
n c. Cn khi th tc increment_reg c gi th tham s thc phi tng ng
vi bin reg v bn thn tham s thc cng phi l bin cng kiu. Ch ca
reg l inout, c ngha l bin ny c th c hoc gn. Nu ch c ch in - tc l
ch c, cn out - tc l ch gn. Khi ch l inout hoc out th c th b qua t
variable v c ngm nh.
Cn tham s th hai l incr, l mt tham hng (tham s hng s), c ngha l
n c gn l mt i tng hng s trong thn chng trnh con, v khng th
gn cho n c.
Vic gi mt chng trnh con bao gm mt danh sch cc tham s thc
tng ng vi tham s chnh ca chng trnh con c th c v v tr v tn gi hoc
c hai. V d:
increment_reg(index_reg, offset-2); -- b sung gi tr vo index_reg
increment_reg(prog_counter); -- b sung 1 (mc nh) vo
prog_counter
Vic gi theo tn gi tng ng theo tham s chnh nh v d sau:
increment_reg(incr => offset-2, reg => index_reg);
increment_reg(reg => prog_counter);
Trong lnh gi th hai, tham s incr khng c, nn n c gn gi tr mc
nh.
V d v m t mt hm:
function byte_to_int(byte : word_8) return integer;
Hm trn ch c mt tham s. i vi cc hm, ch tham s phi l in. Nu
lp tham s khng c ch nh th n c coi nh l constant. Gi tr tr v ca
hm trn phi l mt s nguyn (integer).
Khi thn ca chng trnh con c ch nh, c php s dng nh sau:
thn chng trnh con ::=
tham s chng trnh con is
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thnh phn m t chng trnh con
begin
thnh phn khai bo chng trnh con
end [tn ch nh];
thnh phn m t chng trnh con ::= {mc m t chng trnh con}
thnh phn khai bo chng trnh con ::= {khai bo tun t}
mc m t chng trnh con ::=
m t chng trnh con
| thn chng trnh con
| m t kiu
| m t kiu con
| m t hng s
| m t bin
| m t tn ph
Cc mc m t chng trnh con c lit k sau c im ca chng trnh
con m t tt c nhng g c s dng cc b trong thn chng trnh con. Tn
ca cc mc ny khng nhn thy c ngoi chng trnh con. Ngoi ra, cc mc
ny l bng ca tt c nhng g c cng tn c m t ngoi chng trnh
con.
Khi mt chng trnh con c gi, cc khai bo trong thn c kch hot
n khi hoc l gp du kt thc danh sch khai bo hoc khi mt khai bo quay li
(return) c kch hot. C php ca mt khai bo quay li nh sau:
khai bo quay li ::= return [biu thc];
Nu mt khai bo quay li xy ra trong thn ca mt th tc, th n phi khng
c cha mt biu thc. V cng phi c t nht mt khai bo quay li trong thn
mt hm, n phi cha mt biu thc, v hm c kt thc bng vic kch hot
mt khai bo quay li. Gi tr ca biu thc l gi tr c tr v khi gi hm.
V d :
function byte_to_int(byte : word_8) return integer is
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variable result : integer := 0;
begin
for index in 0 to 7 loop
result := result*2 + bit'pos(byte(index));
end loop;
return result;
end byte_to_int;
4.2.5.2. Overloading (trng tn)
VHDL cho php hai chng trnh con cng tn, nhng tn v kiu ca cc
tham s phi khc nhau. Tn ca chng trnh con nh vy c gi l tn
overloaded (trng tn). Khi thc hin gi mt chng trnh con s dng tn
overloaded, th s lng tham s thc, th t ca chng, kiu ca chng v cc tn
tham s chnh tng ng c s dng xc nh l chng trnh con no c
gi. Nu cuc gi l mt cuc gi hm, th kiu kt qu tr v s c s dng. V
d, chng ta c hai chng trnh con sau:
function check_limit(value:integer) return boolean;
function check_limit(value:word_32) return boolean;
Sau , khi hm no c gi th cn c vo gi tr ca kiu integer hay l
word_32 m tham s thc s dng bit. Chng hn:
test:=check_limit(4095)
s gi hm th nht, cn:
test:=check_limit(X0000_0FFF)
s gi hm th hai.
Ngi s dng c th s dng cch nh ngha tn chng trnh con theo mt
nh danh hoc mt xu biu din bi cc k hiu ton t nh lit k trong phn
2.2.3. V d nh sau:
function +(a,b:word_32) return word_32 is
begin
return int_to_word_32(word_32_to_int(a)+word_32_to_int(b));
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end +;
Ton t cng, khi thc hin php tnh ca mnh, ch thc hin vi cc ton
hng l s nguyn. Cn khi hm + ny c gi th n li thc hin biu thc vi
kiu word_32 theo hai cch nh sau:
X1000_0010 + X0000_FFD0
hoc l:
+ (X1000_0010,X0000_FFD0)
4.2.5.3. ng gi v m t thn cc ng gi
Mt ng gi l mt tp bao gm cc kiu, cc hng s, cc chng trnh con
v c th c cc thnh phn khc, thng thng n c d nh cho hot ng
ca mt vi dch v thnh phn hoc tch mt nhm cc thnh phn c lin quan
vi nhau. c bit, chi tit cc gi tr hng s v cc thn chng trnh con c th
n do ngi dng, chng ch nhn thy c giao din m thi.
Mt ng gi c th phn chia thnh hai phn: phn m t ng gi dng
nh ngha giao din ca n v phn thn ng gi dng nh ngha cc chi tit
khc. Phn thn c th b qua nu chng khng c chi tit no. C php ca phn
m t ng gi nh sau:
m t ng gi ::=
package tn nh danh is
phn m t ng gi
end [tn n ca ng gi];
phn m t ng gi ::= {thnh phn m t ng gi}
thnh phn m t ng gi ::=
m t chng trnh con
| m t kiu
| m t kiu con
| m t hng s
| m t tn ph
| mnh s dng
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Cc m t nh ngha cc thnh phn khc m nhn thy c i vi ngi
dng ng gi, v chng cng nhn thy c bn trong ca thn ng gi.
V d :
package data_types is
subtype address is bit_vector(24 downto 0);
subtype data is bit_vector(15 downto 0);
constant vector_table_loc : address;
function data_to_int(value : data) return integer;
function int_to_data(value : integer) return data;
end data_types;
Trong v d trn, gi tr ca hng s vector_table_loc v thn ca hai chng
trnh con khc nhau, do vy thn mt ng gi cng cn phi gn.
C php ca thn mt ng gi l:
thn ng gi ::=
package body tn n ca thn ng gi is
phn m t thn ng gi
end [tn n ca thn ng gi];
phn m t thn ng gi ::= {thnh phn m t thn ng gi}
thnh phn m t thn ng gi ::=
m t chng trnh con
| m t kiu
| m t kiu con
| m t hng s
| m t tn ph
| mnh s dng
Thn i vi ng gi data_types biu din trn c th vit li nh sau:
package body data_types is
constant vector_table_loc : address := X"FFFF00";
function data_to_int(value : data) return integer is
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body of data_to_int
end data_to_int;
function int_to_data(value : integer) return data is
body of int_to_data
end int_to_data;
end data_types;
Trong thn ng gi ny, gi tr i vi hng s c ch nh trc, v thn
ng gi phi c gn trc. Cc m t kiu con khng c lp li, do cc m t
ng gi l nhn thy c trong thn ng gi.
4.2.5.4. Thay th Tn v s dng ng gi
Khi mt ng gi c m t, th cc thnh phn m t km vi n c
th s dng bng cch ly tin t cc tn ca chng vi tn ng gi. Nh v d
trong mc 3.2.5.3, cc thnh phn c m t c th s dng nh sau:
variable PC : data_types.address;
int_vector_loc := data_types.vector_table_loc + 4*int_level;
offset := data_types.data_to_int(offset_reg);
Thng thng thun tin c th tham chiu n cc tn t mt ng gi
m khng cn c iu kin l mi khi s dng phi km vi tn ng gi. Vic ny
c thc hin bng mnh Use (s dng) trong mt m t cc b. C php ca
n nh sau:
mnh s dng ::= use tn c chn { , tn c chn};
tn c chn ::= tin t . hu t
Tc dng ca mnh use l cho tt c cc tn c lit k ri sau c
th s dng m khng cn tin t ca chng. Nu tt c cc tn c m t trong
mt ng gi u s dng cch ny, th ta c th dng mt hu t c bit l all, v
d nh:
use data_types.all;
4.3. M t cu trc ca VHDL
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Trong mc 4.1 tc gi gii thiu v mt s thut ng dng m t cu
trc ca mt h thng s. Trong mc ny, tc gi s cp n vic m t h thng
s bng ngn ng VHDL.
4.3.1. M t u vo
Mt h thng s thng c thit k di dng kin trc kiu cc khi
(module). Mi mt khi s c mt s cng vo/ra dng giao tip gia khi vi
cc thnh phn bn ngoi. Trong VHDL, khi nim thc th (an entity) thc ra cng
l mt khi thnh phn trong qu trnh thit k, m thng l n c thit k
mc trn cng (top level) - cn gi l thc th.
C php m t mt thc th nh sau:
m_t_thc_th ::=
entity tn_nh_danh is
header_ca_thc_th
phn_chnh_ca_thc_th
[begin
phn_khai_bo_ca_thc_th ]
end [tn_ca_thc_th];
header_ca_thc_th ::=
[mnh__nghi_thc_chung]
[mnh__nghi_thc_cng]
mnh__chung ::= generic (lit_k_c_im_chung);
lit_k_c_im_chung ::= lit_k_giao_din_chung
mnh__cng ::= port (lit_k_cng);
lit_k_cng ::= lit_k_giao_din_cng
phn_chnh_ca_thc_th ::= {cc_thnh_phn_ca_thc_th}
Phn chnh ca thc th c th c s dng m t cc thnh phn s c
dng trong qu trnh hot ng ca thc th.
Thnh phn header ca thc th l thnh phn gn nh quan trng nht trong
m t thc th. N c th cha cc thnh phn hng s chung (generic constant),
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c dng iu khin cu trc v hot ng ca thc th, cc cng (port), l cc
knh thng tin vo v ra ca thc th.
Cc hng s chung c ch nh s dng giao din lit k tng t nh vic
m t mt chng trnh con. Tt c cc thnh phn con u phi l thuc lp hng
s chung ny. Do vy, c php ch yu ca hng s giao tip (interface constant)
c m t nh sau:
m_t_hng_s_giao_tip ::=
[constant] lit_k_nh_danh : [in] biu_din_kiu_con [ := biu_din_tnh]
Gi tr thc i vi mi hng s chung c b qua khi thc th c s dng
nh mt thnh phn ca qu trnh thit k.
Cc cng (port) u vo cng c ch nh vic s dng trong giao din
c lit k, nhng cc thnh phn trong danh sch lit k phi c phn vo
lp tn hiu. C php l:
m_t_tn_hiu_giao_tip ::=
[signal] lit_k_nh_danh : [mode] biu_din_kiu_con [bus] [ :=
biu_din_tnh]
Do gia cc lp phi c tn hiu nn t signal c b qua v coi nh l c
sn. T bus c th c s dng nu cc cng c ni ti nhiu hn mt u ra.
d hiu, chng ta xem xt v d sau:
entity processor is
generic (max_clock_freq : frequency := 30 MHz);
port (clock : in bit;
address : out integer;
data : inout word_32;
control : out proc_control;
ready : in bit);
end processor;
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Trong trng hp ny, hng s chung l max_clock_freq c s dng ch
r tn s hot ng ca thc th. Vic m ho hot ng ca thc th s s dng gi
tr ny xc nh tr trong qu trnh cc gi tr tn hiu thay i.
Tip theo l v d v cc tham s chung c s dng ch nh lp ca cc
u vo vi cu trc c th thay i c.
V d:
entity ROM is
generic (width, depth : positive);
port (enable : in bit;
address : in bit_vector(depth1 downto 0);
data : out bit_vector(width1 downto 0) );
end ROM;
y hai hng s chung l width v depth c s dng ch nh s lng
cc bit d liu v cc bit a ch tng ng cho ROM. Ch rng khng c gi tr
mc nh cho trc i vi cc hng s ny.
V d cui cng l m t thc th khng c hng s chung hay cng no:
entity test_bench is
end test_bench;
Vic m t ny c biu din trong hnh 3.3. Thc th mc trn cng (top-
level) i vi vic thit k kim tra (Design under test - DUT) c s dng nh
mt thnh phn trong mch kim tra chun vi mt thc th khc (TG).

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Hnh 4.3. S mch kim tra chun
4.3.2. M t kin trc
Mi mt thc th c mt m t nh ngha ring, tuy nhin v hot ng th c
th mi thc th c nhiu chng trnh khc nhau, do vy mi thc th cn c th
c biu din dng cu trc chng trnh. Vic m t kin trc ny khc vi m
t hot ng s c trnh by trong mc 3.4.
Kin trc thn thc th c m t theo c php sau:
kin_trc_thn ::=
architecture tn_nh_danh of tn_u_vo is
phn_chnh_ca_kin_trc
begin
phn_khai_bo_ca_kin_trc
end [tn_ca_kin_trc]
phn_chnh_ca_kin_trc ::= {cc_mc_chnh_trong_khi}
phn_khai_bo_ca_kin_trc ::= {khai_bo_tng_tranh}
cc_mc_chnh_trong_khi ::=
m_t_chng_trnh_con
| thn_chng_trnh_con
| m_t_kiu
| m_t_kiu_con
| m_t_hng_s
| m_t_tn_hiu
| m_t_tn_hiu
| m_t_tn_ph_(b_danh)
| m_t_thnh_phn
| c_im_cu_hnh
| mnh__s_dng
khai_bo_tng_tranh ::=
khai_bo_khi
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| khai_bo_thuyt_minh_cc_thnh_phn
4.3.2.1. M t tn hiu
Cc tn hiu c dng ni cc khi con vi nhau trong mt thit k.
Chng c m t theo c php sau:
m_t_tn_hiu ::=
signal lit_k_tn_nh_danh : diu_din_kiu_con [loi_tn_hiu] [:=
biu_din];
loi_tn_hiu ::= register | bus
Mt im quan trng cn ch l cc cng ca mt i tng cn phi x l
ng tn hiu cho i tng .
4.3.2.2. Cc khi (Block)
Cc modul con trong kin trc khi chnh c th c biu din di dng cc
khi. Mt khi l mt n v cu trc modul, vi giao din ring, c ni n cc
khi khc hoc cc cng bng tn hiu. C php m t khi nh sau:
khai_bo_khi ::=
nhn_khi :
block [(biu_din_bt_buc)]
header_ca_khi
phn_chnh_ca_khi
begin
phn_khai_bo_ca_khi
end [nhn_khi];
header_ca_khi ::=
[ mnh__chung
[ nh_x_ca_mnh_; ]]
[ mnh__cng
[ nh_x_ca_cng; ]]
nh_x_ca_mnh_ ::= generic map
(danh_sch_tng_ng_cc_mnh_)
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nh_x_ca_cng ::= port map (danh_sch_tng_ng_cc_cng)
phn_chnh_ca_khi ::= {cc_mc_chnh_ca_khi}
phn_khai_bo_ca_khi ::= {khai_bo_tng_tranh}
Biu din header ca khi cng tng t nh header ca u vo. Danh sch
tng ng cc mnh ch nh cc gi tr i vi cc hng s chung. Danh sch
tng ng cc cng ch nh cc tn hiu thc hoc cc cng t v ca khi hoc
thn kin trc c ni n cc cng ca khi .
V d v kin trc ca mt b vi x l trong v d 3.3.1 phn 3.3.1 c m
t di dng kin trc trong v d di y.
V d v kin trc c cu trc ca mt b vi x l:
architecture block_structure of processor is
type data_path_control is ;
signal internal_control : data_path_control;
begin
control_unit : block
port (clk : in bit;
bus_control : out proc_control;
bus_ready : in bit;
control : out data_path_control);
port map (clk => clock,
bus_control => control, bus_ready => ready;
control => internal_control);
declarations for control_unit
begin
statements for control_unit
end block control_unit;
data_path : block
port (address : out integer;
data : inout word_32;
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control : in data_path_control);
port map (address => address, data => data,
control => internal_control);
declarations for data_path
begin
statements for data_path
end block data_path;
end block_structure;
4.3.2.3. M t cc thnh phn (component)
Thn kin trc cng c th s dng cc kiu m t u vo khc nhau c sn
trong th vin. Do vy, kin trc cn phi dng m t mt thnh phn no .
Sau , l t cu hnh cho vic s dng thnh phn . C php m t thnh
phn nh sau:
m t thnh phn ::=
component tn nh danh
[ mnh chung cc b ]
[ mnh cng cc b ]
end component;
V d v cng NAND 3 u vo:
component nand3
generic (Tpd : Time := 1 ns);
port (a, b, c : in logic_level;
y : out logic_level);
end component;
V d v m t thnh phn ca b ROM vi ln cc bit a ch v d liu
ph thuc vo cc hng s chung:
component read_only_memory
generic (data_bits, addr_bits : positive);
port (en : in bit;
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addr : in bit_vector(depth1 downto 0);
data : out bit_vector(width1 downto 0) );
end component;
4.3.2.4. Thuyt minh thnh phn
Sau khi m t mt thnh phn trong kin trc, chng ta c th m t thuyt
minh v n theo c php sau:
khai bo thuyt minh thnh phn ::=
tn thnh phn
[ nh x ca mnh ]
[ nh x ca cng ]
V d v thuyt minh thnh phn i vi cc m t thnh phn trong 2 v d v
cng NAND v thnh phn ca ROM phn 3.3.2.3 nh sau:
enable_gate: nand3
port map (a => en1, b => en2, c => int_req, y => interrupt);
parameter_rom: read_only_memory
generic map (data_bits => 16, addr_bits => 8);
port map (en => rom_sel, data => param, addr => a(7 downto 0);
3.4. VHDL m t hot ng
Trong mc 1.1.2, chng ta bt u cp n cc hot ng ca mt h
thng s c th m t bng ngn ng lp trnh. Trong phn ny, chng ta s m t
hot ng ca mt h thng s bao gm cc khai bo dnh cho vic thay i gi tr
tn hiu, ng thi l phn ng ca h thng cng thay i theo.
4.4.1. Ch nh tn hiu
Vic ch nh tn hiu thc hin mt hoc nhiu giao tc n tn hiu (hoc n
cng). C php ca vic ch nh tn hiu l:
khai bo ch inh tn hiu ::= ch n <= [transport] dng sng;
ch n ::= tn | tp hp
dng sng ::= dng sng phn t { , dng sng phn t }
dng sng phn t ::=
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biu din gi tr [after biu din thi gian]
| null [after biu din thi gian]
ch n phi biu din tn hiu hoc l kt hp ca nhiu tn hiu. Nu vic
biu din thi gian cho qu trnh tr b b qua, th n c mc nh l 0 fs.
Mi mt tn hiu kt hp vi mt dng sng u ra c nh x n (a
projected output waveform), l bng lit k cc giao tc cung cp cho cc gi tr sau
ny cho tn hiu. Vic ch nh tn hiu thm vo cc giao tc dng sng .
V d vic ch nh tn hiu nh sau
s <= 0 after 10 ns;
s to cho tn hiu l cho php tha nhn gi tr ng 10 ns sau khi vic ch
nh c kch hot. Chng ta c th biu din mt dng sng u ra c nh x
n bng th thng qua vic biu din cc giao tc theo trc thi gian. Nu nh
vic ch nh trong v d trn c kch hot ti thi im 5 ns, th dng sng u ra
c nh x n s c dng:



Khi m phng thi gian trong phm vi 15 ns, giao tc ny s c thc hin
v tn hiu c cp nhp.
Gi s rng sau ti thi im 16 ns, vic ch nh
s <= 0 after 10 ns, 0 after 20 ns;
c kch hot. Hai giao tc mi c thm vo dng sng u ra c nh x
n nh sau:



Ch rng khi nhiu giao tc c lit k trong mt ch nh tn hiu, th cc
thi gian tr c ch nh phi sp xp theo th t tng dn.
15 ns
0
20 ns
1
36 ns
0
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Nu mt ch nh tn hiu c kch hot, v c mt vi giao tc c ca ch
nh trc hon thnh, th cc giao tc c c th b xo. iu ny cn ph
thuc vo t kho transport c c thm vo ch nh mi khng. Nu c, ch
nh ni rng n s dng tr chuyn tip (transport delay). Trong trng hp
ny, tt c cc giao tc c xy ra sau khi giao tc mi u tin s b xo trc khi
cc giao tc mi c thm vo. Chng ta xem li v d trn, nu ch nh:
s <= transport Z after 10 ns;
c kch hot ti thi im 18 ns, th sau giao tc thc hin i vi 36 ns
s b xo, v dng sng u ra c nh x n s tr thnh:



Loi tr th hai l tr qun tnh (inertial delay), c s dng trong m hnh
cc thit b m khng phn ng vi u vo dao ng ngn hn tr u ra ca n.
Tr qun tnh c ch nh bng cch gi nh t transport t vic ch nh tn
hiu.
Khi giao tc tr qun tnh c thm vo dng sng u ra c nh x n,
th u tin l tt c cc giao tc c ang thc hin xy ra sau giao tc mi s b xo,
v giao tc mi c thm vo theo trng hp tr chuyn tip. Tip theo l tt c
cc giao tc c ang thc hin trc giao tc mi s c kim tra. Nu c bt k
gi tr no khc vi giao tc mi, th tt c cc giao tc c tng ln bng vi giao
tc cui cng theo gi tr khc u b xo. Cc giao tc cn li c cng gi tr
c y sang tri.
phn tch vic ny, chng ta xem s dng sng u ra c nh x n:



v vic ch nh:
S <= 1 after 25 ns;
20 ns
T
28 ns
Z
20 ns
T
28 ns
Z
20 ns
T
28 ns
Z
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c kch hot cng ti thi im 0 ns. Sau dng sng u ra c nh x
n mi s l:



Khi vic ch nh tn hiu vi a thnh phn dng sng c ch nh cng vi
tr qun tnh, th ch c giao tc u tin s dng tr qun tnh, cn cc giao tc cn
li s dng tr chuyn tip.
4.4.2. Khai bo X l v i
Thnh phn chnh ca m t hot ng trong VHDL l vic x l (process).
Mt x l l mt chng trnh tun t c m ho c th c kch hot khi p
ng li s thay i trng thi. Khi nhiu hn mt x l c kch hot ti cng mt
thi im, chng kch hot trng thi ng thi Mt x l c ch nh trong mt
khai bo X l, vi c php nh sau:
khai bo x l :: =
[nhn x l : ]
process [(lit k cc thnh phn nhy cm)]
phn chnh ca x l
begin
phn khai bo ca khi u vo
end process [nhn x l] ;
phn chnh ca khi u vo :: = {thnh phn ca khi u vo}
thnh phn ca khi u vo :: =
m t chng trnh con
| thn chng trnh con
| m t kiu
| m t kiu con
| m t hng s
| m t bin
20 ns
T
28 ns
Z
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| m t tn ph (b danh)
| mnh s dng
phn khai bo ca khi u vo :: = {khai bo tun t}
khai bo tun t :: =
| khai bo xc nhn
| khai bo ch nh tn hiu
| khai bo ch nh bin
| khai bo gi th tc (procedure_call)
| khai bo if (nu)
| khai bo case (cy)
| khai bo loop (vng lp)
| khai bo next (tip theo)
| khai bo exit (thot)
| khai bo return (quay li)
| khai bo null (rng)
Mt khai bo x l l mt khai bo ng thi m c th s dng trong mt
kin trc kiu cy hoc khi. Cc m t nh ngha cc thnh phn m c th c
s dng cc b trong cng mt qu trnh.
Mt qu trnh c th cha mt s khai bo ch nh tn hiu i vi tn hiu
c ch nh, m bt ngun t mt b iu khin (driver) i vi tn hiu. Thng
thng ch c th c mt b iu khin cho mt tn hiu, v do m chng trnh xc
nh mt gi tr tn hiu rng buc vo mt qu trnh.
Mt qu trnh c kch hot khi ng trong khi pha khi ng vic m
phng. N kch hot tt c cc khai bo tun t, v sau lp li, bt u li t khai
bo u tin. Mt qu trnh c th t n tm thi ngng bng cch kch hot mt
khai bo i (wait statement). Khun dng ca n nh sau:
khai bo i :: =
wait [mnh nhy] [mnh iu kin] [mnh thi gian ch]
mnh nhy :: = on danh sch nhy
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danh sch nhy :: = tn tn hiu [ , tn tn hiu]
mnh iu kin :: = until iu kin
mnh thi gian ch :: = for biu din thi gian
Danh sch nhy ca khai bo i ch nh mt tp cc tn hiu m qu trnh
l nhy cm vi chngtrong khi n ang b dng. Khi mt s kin xy ra trn bt k
tn hiu no (tc l gi tr ca tn hiu b thay i), qu trnh quay li trng thi c
v xc nh iu kin. Nu n ng hoc nu iu kin b b qua, th vic kch hot
qu trnh s theo khai bo tip theo, nu khng th qu trnh s b tm ngng tr li.
Nu mnh nhy b b qua, th qu trnh s nhy vi tt c cc tn hiu c
cp trong biu din iu kin. Biu din thi gian ch phi nh gi khong thi
gian th ng, v ch ra thi gian cc i cho qu trnh s i n. Nu n b b qua,
qu trnh c th phi i khng c thi hn (thi gian i bt nh).
Nu danh sch nhy c t trong header ca khai bo qu trnh, th sau
khi qu trnh c th nhn c mt khai bo i n ti im cui cng ca phn
khai bo ca n. Danh sch nhy ca khai bo i n ny tng t nh trong
header ca qu trnh.
V d v cc khai bo ca mt qu trnh vi danh sch nhy:
process (reset, clock)
variable state : bit := false;
begin
if reset then
state := false;
elsif clock = true then
state := not state;
end if;
q <= state after prop_delay; -- implicit wait on reset, clock
end process;
Trong qu trnh pha khi ng ca qu trnh m phng, qu trnh c kch
hot v ch nh gi tr khi ng ca trng thi ti tn hiu q. Sau n tm dng
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ti khai bo i n ch nh trong phn ch gii. Khi gi tr reset hoc clock thay i
gi tr, th qu trnh s hot ng tr li, v kch hot lp li t u.
V d tip theo m t hot ng ca mt thit b ng b c gi l Muller-C
s dng xy dng phn t logic khng ng b. u ra ca thit b bt u t gi
tr 0, ti thi im u ra thay i gi tr ln 1. u ra s dng li gi tr 1
n khi c hai u vo u la 0, ti thi im u ra thay i v 0.
V d:
muller_c_2 : process
begin
wait until a = '1' and b = '1';
q <= '1';
wait until a = '0' and b = '0';
q <= '0';
end process muller_c_2 ;
Qu trnh ny khng bao gm danh sch nhy, v vy cc khai bo i hin
c dng iu khin tm dng v kch hot mt qu trnh. Trong c hai khai
bo i, danh sch nhy l tp tn hiu a v b, c xc nh t biu din iu
kin.
4.4.3. Khai bo ch nh tn hiu tng tranh
Thng th mt qu trnh m t mt b iu khin cho mt tn hiu cha ch
mt khai bo ch nh tn hiu. VHDL cung cp mt cch biu din mt cch ngn
gn, c gi l khai bo ch nh tn hiu tng tranh, dng biu din cho qu
trnh . C php l:
khai bo ch nh tn hiu tng tranh :: =
[ nhn : ] ch nh tn hiu iu kin
| [ nhn : ] ch nh tn hiu c chn
i vi mi loi ch nh tn hiu tng tranh, c mt khai bo qu trnh
tng ng vi ngha ca n.
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4.4.3.1. Ch nh tn hiu iu kin
Mt ch nh tn hiu iu kin l mt ch nh ngn cho mt qu trnh c cha
cc ch nh tn hiu trong mt khai bo if. C php l:
ch nh tn hiu iu kin :: = ch <= cc tu chn cc dng sng iu kin;
cc tu chn :: = [ guarded ] [ transport ]
dng sng iu kin :: =
{ dng sng when iu kin else }
dng sng
Vic s dng t guarded khng c cp n trong mc ny. Nu t
transport c i km, th cc ch nh tn hiu trong qu trnh tng ng s dng
tr transport.
Gi s chng ta c mt ch nh tn hiu iu kin:
s <= dng_sng_1 when iu_kin_1 else
dng_sng_2 when iu_kin_2 else
...
dng_sng_n;
th qu trnh tng ng l:
process
if iu_kin_1 then
s <= dng_sng_1;
elsif iu_kin_2 then
s <= dng_sng_2;
elsif ...
...
else
s <= dng_sng_n;
wait [ mnh nhy ];
end process;
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Nu khng c cc biu thc gi tr dng sng hoc iu kin cha mt tham
chiu n mt tn hiu no, th khai bo i cui ca qu trnh tng ng s
khng nhn c mnh nhy. iu ny c ngha l sau khi vic ch nh c
thc hin, th qu trnh s tm dng v hn. V d, vic ch nh tn hiu:
reset <= 1, 0 after 10 ns when mt_xung_ngn_c_yu_cu else
1, 0 after 50 ns;
thc hin hai giao tc trn tn hiu reset, sau tm dng ch bo ngh ca
chng trnh m phng.
Mt khc, nu chng tham chiu n cc tn hiu trong cc biu thc gi tr
dng sng hoc iu kin, th khai bo i nhn c danh sch nhy bao gm
tt c cc tn hiu c tham chiu n. Do vic ch nh iu kin:
mux_out <= Z after Tpd when en = 0 else
in_0 after Tpd when sel = 0 else
in_1 after Tpd;
l nhy n cc tn hiu en v sel. Qu trnh c kch hot trong thi gian
pha khi ng, v sau l mi khi en hoc sel thay i gi tr.
Trng hp pht sinh li mt ch nh tn hiu iu kin, th bao gm khng
c cc thnh phn iu kin, tng ng vi mt qu trnh ch c cha mt khai
bo ch nh tn hiu. V vy:
s <= wavefom;
tng ng vi:
process
s <= waveform;
wait [ mnh nhy ];
end process;
4.4.3.2. Ch nh tn hiu c chn
Mt khai bo ch nh tn hiu c chn l mt ch nh ngn gn cho mt
qu trnh c cha cc ch nh tn hiu trong mt khai bo case. C php ca n
l:
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ch nh tn hiu c chn :: =
with biu thc select
ch <= cc tu chn cc dng sng c chn;
cc dng sng c chn :: =
{ dng sng when chn }
dng sng when chn
chn :: = chn { | chn }
Cc thnh phn tu chn tng t nh i vi mt ch nh tn hiu iu kin.
Do vy nu t transport i km, th vic ch nh tn hiu trong qu trnh tng
ng s dng tr transport.
Gi s chng ta c mt ch nh tn hiu c chn:
with biu thc select
s <= dng_sng_1 when danh_sch_chn_1,
dng_sng_2 when danh_sch_chn_2,
...
dng_sng_n when danh_sch_chn_n;
Th qu trnh tng ng l:
process
case biu thc is
when danh_sch_chn_1 =>
s <= dng_sng_1;
when danh_sch_chn_2 =>
s <= dng_sng_2;
...
when danh_sch_chn_n =>
s <= dng_sng_n;
end case;
wait [ mnh nhy ];
end process;
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Danh sch nhy i vi khai bo i c xc nh cng mt cch nh i
vi mt ch nh tn hiu iu kin. l, nu khng c cc tn hiu c tham
chiu n trong ch nh tn hiu c chn hoc khng c cc dng sng, th khai
bo i khng c mnh nhy. Ngc li mnh nhy cha tt c cc tn
hiu c tham chiu n trong biu thc v cc dng sng.
V d v mt khai bo ch nh tn hiu c chn:
with alu_function select
alu_result <= op1 + op2 when alu_add | alu_incr,
op1 op2 when alu_subtract,
op1 and op2 when alu_and,
op1 or op2 when alu_or,
op1 and not op2 when alu_mask;
Trong v d trn, gi tr ca tn hiu alu_function c s dng chn mt
ch nh tn hiu n alu_result kch hot. Vic khai bo l nhy n tn hiu
alu_function, op1 v op2, do vy mi khi c bt k s thay i gi tr no, th vic
ch nh tn hiu s c kch hot tr li.
4.5. M hnh t chc
Trong phn trc chng ta cp n vic m t hot ng VHDL mt
cch c lp. Mc ch ca phn ny l th hin cc thc lm th no kt hp tt
c cc thnh phn hot ng li thnh mt h thng s theo m t VHDL hon
chnh.
4.5.1. Cc n v v th vin thit k
Khi chng ta vit m t cc hot ng VHDL, chng ta phi ghi li dng cc
tp thit k (design file), sau dng mt trnh bin dch phn tch c php ca
chng v a chng vo thnh lp mt th vin thit k (Design Library). Mt s
cc cu trc ca VHDL c th c phn tch ring r a vo th vin thit k.
Cc cu trc c gi l cc n v th vin (Library Units). Cc n v th vin
chnh (primary) bao gm cc m t u vo, cc m t ng gi thnh phn chnh
v cc m t cu hnh (xem tip trong mc 3.5.2). Cc n v th vin ph
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(secondary) bao gm cc thn chng trnh kin trc v cc thn ca cc ng gi
thnh phn chnh. Cc n v th vin ph thuc vo c im giao din ca
chng trong cc n v th vin chnh tng ng, v n v chnh phi c phn
tch trc bt k n v ph no tng ng.
Mt tp thit k c th cha mt s n v th vin. Cu trc ca mt tp thit
k c th c ch nh nh trong c php sau:
tp thit k :: = n v thit k {n v thit k}
n v thit k :: = mnh ng cnh n v th vin
mnh ng cnh :: = {thnh phn ng cnh}
thnh phn ng cnh :: = mnh th vin | mnh s dng
mnh th vin :: = library danh sch tn logic;
danh sch tn logic :: = tn logic { , tn logic}
n v th vin :: = n v chnh | n v ph
n v chnh :: = m t u vo | m t cu hnh | m t ng gi
n v ph :: = thn kin trc | thn ng gi
Cc th vin c tham chiu s dng cc nh danh c gi l cc tn
logic (logic name). Tn ny phi c dch bi h iu hnh ch thnh mt tn lu
tr hot ng c lp. V d, cc th vin thit k c th hot ng nh cc tp c
s d liu (database file), v tn logic phi c dng c th xc nh tn tp c
s d liu. Cc n v th vin trong th vin c cung cp c th tham chiu
n thng qua hu t tn ca chng vi tn logic th vin. v d, chng ta c tn
tp l ttl_lib.ttl_10 phi tham chiu n n v ttl_10 trong th vin ttl_lib.
Mnh ng cnh c trc mi n v th vin ch nh cc th vin no
khc n s tham chiu n v cc dng ng gi no n s dng. Phm vi ca cc
tn c th nhn thy c thng qua mnh ng cnh ko di n ht n v thit
k.
C hai loi th vin c bit m hon ton c th s dng c cho tt c cc
n v thit k, v khng cn t tn trong mnh th vin. Th vin u tin c
tn l work, n tham chiu th vin thit k ang lm vic vo n v thit k hin
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ti s c t dnh cho ngi phn tch. Sau khi t vo n v thit k, cc n v
thit k c phn tch trc trong tp thit k c th tham chiu s dng tn
th vin c sn l work.
Th vin c bit th hai c gi l std, v n cha cc dng ng gi
standard v textio. Standard bao gm tt c cc kiu nh ngha sn v cc hm
chc nng. Tt c cc thnh phn con trong cc ng gi u c th s dng
c, v khng cn s dng cc mnh truy xut chng.
4.5.2. Cc cu hnh
Trong mc 4.3.2.3 v 4.3.2.4 chng ta biu din lm th no mt m t hot
ng khai bo c im ca mt thnh phn v cch to cc s kin ca thnh phn.
Chng ta cng cp rng mt thnh phn c khai bo c th c coi nh l
mt mu cho mt thc th thit k. S rng buc ca mt thc th ti mu ny t
c thng qua mt m t cu hnh. M t ny c th c s dng ch nh cc
hng s chung trong thc t cho cc thnh phn v khi. Nh vy m t cu hnh
(configuration declaration) ng vai tr chnh trong vic t chc m t thit k khi
chun b cho vic m phng hoc cc x l khc.
C php ca mt m t cu hnh l:
M t cu hnh :: =
Configuration tn nh danh of tn thc th is
cc phn m t cu hnh
cu hnh ca khi
end [tn n gin ca cu hnh];
cc phn m t cu hnh :: = {cc mc m t cu hnh}
cc mc m t cu hnh ::= mnh s dng
cu hnh ca khi :=
for c im ca khi
{mnh s dng}
{cc mc cu hnh}
end for;
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c im ca khi ::= tn kin trc | nhn khai bo ca khi
cc mc cu hnh ::= cu hnh ca khi | cu hnh ca thnh phn
cu hnh ca thnh phn ::=
for c im ca thnh phn
{use ch s rng buc}
{cu hnh ca khi}
end for;
c im ca thnh phn ::= lit k thuyt minh : tn thnh phn
lit k thuyt minh ::=
nhn thuyt minh { , nhn thuyt minh}
| others
| all
ch s rng buc ::=
v tr ca thc th
[ v tr nh x chung ]
[ v tr nh x cng ]
v tr ca thc th ::=
entity tn thc th [( tn nh danh kin trc )]
| configuration tn cu hnh
| open
v tr nh x chung ::= generic map ( lit k kt hp chung )
v tr nh x cng ::= port map ( lit k kt hp cng )
Phn miu t ca m t cu hnh cho php cu hnh s dng cc mc t th
vin v cc dng ng gi. Cu hnh ca khi ngoi cng trong m t cu hnh nh
ngha cu hnh cho mt kin trc ca thc th c t tn. V d, trong phn
4.3, chng ta c v d v mt thc th processor v kin trc ca n c cho
trong v d di y:
V d v m t mt thc th processor v thn kin trc
entity processor is
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generic (max_clock_speed : frequency := 30 MHz);
port ( port list );
end processor;
architecture block_structure of processor is
declarations
begin
control_unit : block
port ( port list );
port map ( association list );
declarations for control_unit
begin
statements for control_unit
end block control_unit;
data_path : block
port ( port list );
port map ( association list );
declarations for data_path
begin
statements for data_path
end block data_path;
end block_structure;
Ton b cu trc ca m t cu hnh i vi kin trc trn nh sau:
configuration test_config of processor is
use work.processor_types.all
for block_structure
configuration items
end for;
end test_config;
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Trong v d ny, ni dung ca ng gi c gi l processor_types trong th
vin ang lm vic hin ti l c thc, v cu hnh ca khi tham chiu n kin
trc block_structure ca thc th processor.
Cng vi cu hnh ca khi i vi kin trc, cc m-dul con ca kin trc
cng c t cu hnh. Cc m-dul con ny bao gm cc khi v cc s kin thnh
phn. V d, cc khi trong kin trc hnh 5.1 trn c th c t cu hnh nh
trong v d sau.
V d v cu hnh ca mt processor:
configuration test_config of processor is
use work.processor_types.all
for block_structure
for control_unit
configuration items
end for;
for data_path
configuration items
end for;
end for;
end test_config;
Trong mt m-dul con l mt s kin ca thnh phn, mt cu hnh thnh
phn c dng rng buc mt thc th vi s kin thnh phn. phn tch r,
gi s khi data_path trong v d trn bao gm mt s kin thnh phn l alu, c
m t nh trong v d di y.
V d v cu trc ca khi data_path trong processor:
data_path : block
port ( port list );
port map ( association list );
component alu
port (function : in alu_function;
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op1, op2 : in bit_vector_32;
result : out bit_vector_32);
end component;
other declarations for data_path
begin
data_alu : alu
port map (function => alu_fn, op1 => b1, op2 => b2, result =>
alu_r);
other statements for data_path
end block data_path;
Gi s rng mt th vin project_cells cha mt thc th c gi l alu m
c nh ngha nh sau:
entity alu_cell is
generic (width : positive);
port (function_code : in alu_function;
operand1, operand2 : in bit_vector(width-1 downto 0);
result : out bit_vector(width-1 downto 0);
flags : out alu_flags);
end alu_cell;
vi mt kin trc c gi l behaviour. Thc th ny ph hp vi thnh phn
alu mu, do ton hng ca n v cc cng result c th b bt buc ph hp vi
thnh phn trn, v cc cng flags c th khng c ni. Cu hnh ca khi i vi
data_path c th biu din trong v d di y.
V d v cu hnh ca khi s dng th vin thc th:
for data_path
for data_alu : alu
use entity project_cells.alu_cell(behaviour)
generic map (width => 32)
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108
port map (function_code => function, operand1 => op1, operand2 =>
op2,
result => result, flags => open);
end for;
other configuration items
end for;
Ngc li, nu th vin cng cung cp mt cu hnh c gi l alu_struct i
vi kin trc structure ca thc th alu_cell, th cu hnh khi c th s dng nh
trong v d di y.
V d v cu hnh ca khi s dng mt dng cu hnh khc
for data_path
for data_alu : alu
use configuration project_cells.alu_struct
generic map (width => 32)
port map (function_code => function, operand1 => op1, operand2 =>
op2,
result => result, flags => open);
end for;
other configuration items
end for;
4.5.3. Mt v d c th
phn tch ton b cu trc ca mt m t thit k, chng ta ly v d trong
phn 3.1.4., l mt b count (b m).
Ton b b m ny c m t nh trong on m VHDL di y. Tp
thit k bao gm mt s n v thit k.
n v thit k u tin l m t thc th ca count. tip theo l hai n v
ph, kin trc ca thc th count. Ch l thc th count c tham chiu n cu
hnh theo work.count, s dng trong tn th vin.
-- khi chnh: m t thc th count
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entity count is
generic (prop_delay : Time := 10 ns);
port (clock : in bit;
q1, q0 : out bit);
end count;
-- khi th 2: m t thn kin trc hot ng ca count
architecture behaviour of count is
begin
count_up: process (clock)
variable count_value : natural := 0;
begin
if clock = '1' then
count_value := (count_value + 1) mod 4;
q0 <= bit'val(count_value mod 2) after prop_delay;
q1 <= bit'val(count_value / 2) after prop_delay;
end if;
end process count_up;
end behaviour;
-- khi th 2: m t thn kin trc cu trc ca count
architecture structure of count is
component t_flipflop
port (ck : in bit; q : out bit);
end component;
component inverter
port (a : in bit; y : out bit);
end component;
signal ff0, ff1, inv_ff0 : bit;
begin
bit_0 : t_flipflop port map (ck => clock, q => ff0);
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inv : inverter port map (a => ff0, y => inv_ff0);
bit_1 : t_flipflop port map (ck => inv_ff0, q => ff1);
q0 <= ff0;
q1 <= ff1;
end structure;
-- khi chnh: m t thc th mch kim tra count: test_count
entity test_count is
end test_count;
-- khi th 2: m t thn kin trc hot ng ca test_count
architecture structure of test_count is
signal clock, q0, q1 : bit;
component count
port (clock : in bit;
q1, q0 : out bit);
end component;
begin
counter : count
port map (clock => clock, q0 => q0, q1 => q1);
clock_driver : process
begin
clock <= '0', '1' after 50 ns;
wait for 100 ns;
end process clock_driver;
end structure;
-- khi chnh: cu hnh s dng kin trc hot ng
configuration test_count_behaviour of test_count is
for structure -- of test_count
for counter : count
use entity work.count(behaviour);
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end for;
end for;
end test_count_behaviour;
-- khi chnh: cu hnh s dng kin trc cu trc
library misc;
configuration test_count_structure of test_count is
for structure -- of test_count
for counter : count
use entity work.count(structure);
for structure -- of count_2
for all : t_flipflop
use entity misc.t_flipflop(behaviour);
end for;
for all : inverter
use entity misc.inverter(behaviour);
end for;
end for;
end for;
end for;
end test_count_structure;
Cui cng l vic m t cu hnh i vi mch kim tra. N s dng hai n
v th vin t mt th vin tham chiu phn tch l misc. Cc th vin n v t th
vin ny c tham chiu n cu hnh theo misc.t_flipflop v misc.inverter.






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4.6. Ngun tham kho v VHDL
- IEEE 1029.1-1991. IEEE Standard for Waveform and Vector Exchange
(WAVES). IEEE Std 1029.1-1991. The Institute of Electrical and Electronics
Engineers, Inc., New York.
- IEEE 1076-1993. IEEE Standard VHDL Language Reference Manual
(ANSI). IEEE Std. 1076-1993. The Institute of Electrical and Electronics Engineers,
Inc., New York.
- IEEE 1076.2-1996. Standard VHDL Language Mathematical Packages.
IEEE Ref. AD129-NYF. Approved by IEEE Standards Board on 19 September
1996. [p. 404].
- ISO 8859-1. 1987 (E). Information Processing--8-bit single-byte coded
graphic character sets--Part 1: Latin Alphabet No. 1. American National Standards
Institute, Hackensack, NJ; 1987.
-Asic lp trnh c ( tp 1) v tp II ca tc gi Tng Vn On.
- Ngoi ra chng ta c th tm kim cc ti liu hng dn v VHDL trn
mng.













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Chng V: Thit k v giao tip.


Chng ny s gii thiu mt s bi ton thit k thc hin trn bo mch spartan -3
starter kid board. Cc bi tp theo hng t d n kh chng ta d dng tip cn
cch thc lp trnh VHDL, cch thc tng tc gia phn cng v phn mm, hon
chnh sn phm.Lu rng tt c cc bi ton ny u c ta kim tra k lng
trn bo mch v hot ng ng theo yu cu thit k.
I.Bi 1: Mc ch ca bi ton ny nhm gip chng ta lm quen vi vic vo ra
s liu v kim tra vic thc hin trn mch xem c p ng ng yu cu t ra
hay khng.
Bi ton nh sau: Nh gii thiu cc phn trc. Trn board
spartan 3 c tt c 8 led. Nhim v ca chng ta l to ra 4 trng thi
chuyn led khc nhau.
Phn tch bi ton : Chng ta cn to ra 4 trng thi ngha l to ra
bn trng hp khc nhau chuyn led. Nh vy ch cn 2 bt iu
khin l ( 2
2
= 4 ).
Qu trnh thc hin : u tin chng ta to ra mt i tng thit k
mi nh hng dn phn trc ( chng III). Sau khi to xong
n chng ta thc hin vit lnh. Vi bi ton nh trn chng trnh ca
chng ta nh sau:
------------------------------------------------------------------------------
Tacgia : Tran Duc Thien.
-- Create Date: 13:59:30 08/18/06
-- Module Name: chuyenled - Behavioral
-- Project Name: Chuyen led
Target Device: Spartan -3 starter kid board
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity led is
port (chuyen_led:in std_logic_vector(1 downto 0); --cng vo
led_out: out std_logic_vector(7 downto 0)); --cng ra.
end led;
architecture Behavioral of led is
signal led_in :std_logic_vector(7 downto 0);--Tn hiu dng kim tra.
begin
process(led_in,chuyen_led) danh sch nhy.
begin
led_in <= 10000000 --Bt th tm bng mt
case chuyen_led is
When "00" =>--Trang thai ra giong voi trang thai vao
led_out <= led_in;
When "01" =>--Dich trai voi '0'
led_out <= led_in(6 downto 0)& '0';
When "10" =>--Dich phai voi '0'
led_out <= '0'& led_in(7 downto 1);
When others =>--Quay phai
led_out <= led_in(0)&led_in(7 downto 1);
end case;
end process;
end Behavioral;


Bc tip theo l chng ta kim tra li v xem kt cu logic ca
mch m nhim chc nng nh chng ta va thit k. bc ny
thng thng ta gp li lm mt l kim tra kt cu logic ca mch
v trong bc ny bao gm qu trnh kim tra li.
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Kch chut vo led-behavioral ( chnh l file
chuyenled.vhdl).
Bc tip theo l kch p vo : View
RTL schematic vo xem kt cu logic
mch chc nng tng ng vi cu trc lnh
m ta va vit trn.Khi ta c s RTL
mch theo mc thit k trn nh sau:




Tip theo l thc hin gn chn linh kin. gn ng chn linh
kin ta cn phi cn c vo danh sch cc chi tit kt ni trong
phn Gui ca Spartan -3. Sau y xin gii thiu danh sch kt ni
ca 8 chuyn mch u vo nh sau :
Switch SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0
Pin K13 K14 J13 J14 H13 H14 G12 F12

bi ny ta dng SW0 v SW1 lm bin chuyn trng thi.Tng ng ta
c 8 led_out c kt ni theo bng di y:
Led LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
Pin P11 P12 N12 P13 N14 L12 P14 K12

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116
.
By gi ta tin hnh kt ni
theo ng th t cho bng
trn. Ta kch vo
Userconstrains Create Area
Constraints ( cng c th ta
chn Assign Package Pins) .

Khi trnh dch s kim tra xem c li c php hoc chnh t hay khng. Mt khc
n cng phn tch mc logic v ti u ho cch kt ni sao cho t hiu qu tt
nht.
I/O name l tn ca cc cng
vo ra m ta nh ngha
phn trn.
Loc : Cc chn FPGA ins
tng ng vi cc cng vo ra
theo bng kt ni gii thiu
trn. Lu l gn xong mt
chn th Enter chp nhn.

Bc tip theo ta tin hnh np kim tra. C hai cch np l np
trc tip vo Rom hoc cch th hai l np vo JATG kim tra.
Trc tin ta trnh by cch np theo kiu kim tra.
Kch vo Generate Programming File
Configure Device. Khi trnh dch s
chy kim tra li mt ln na bao gm c
php, tng hp logic, mc hp l, phn
tch ti u ho cch i dy, kim tra vic
gn chn c ph hp vi loi Kid m ta
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khai bo hay khng. Sau khi kim tra mi th u tho mn lc trnh dch s to
ra mt file .bit v gi ra thng bo. Lc tt nht chng ta c theo la chn mc
nh ca trnh dch. Sau khi kt thc vic xc nhn phng thc np lc trnh
dch s t ng kim tra vic kt ni gia my tnh v bo mch ca chng ta. Khi
xc nh nhn nh c vic kt ni v ng truyn thng, trnh dch gi
thng bo tm thy phn cng c kt ni v sau n s t ng kt ni
sn sng cho vic truyn d liu t my tnh sang.

tin hnh np, kch chut phi vo Xc3s200 device, chn Getdevice sau add
file led.bit vo. Xong th tc ny ta kch tip chut phi mt ln na, chn Progam

C th
chn verify
cng c
hoc b qua
cng khng
sao. Nhn
OK chp
nhn


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Sau khi nhn OK khi trn mn
hnh s hin th trng thi truyn d
liu t my tnh sang. Ton b cu
hnh cng nh cch thc x l m ta
thc hin trong phn lp trnh s
c ti sang kid.
Sau khi thc hin truyn ti thnh cng s c thng bo mu xanh programming
succeeded:

Vn tip theo l kim tra li hot ng ca kid c tho mn nhng d nh thit
k ban u hay khng. Nu nh vn cha tho mn ta phi thc hin kim tra li
phn chng trnh, kim tra li thut ton. Khi tin hnh thay i khu bt k no
ta u phi lu li. Cc bc tip theo tin hnh theo trnh t hng dn trn
n khi t c ng nh thit k.



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II. Bi s hai.
Mc ch : y l mt bi ton tng hp bao gm thc hin vic
chia tn s v lm quen vi cch thc hin th ln dn led 7 on.
Sau khi hon thnh c bi ton ny chng ta c th thc hin
c rt nhiu bi ton o c.
Ni dung bi ton : Trn c s 4 led 7 on c sn trn Spartan -3
tin hnh thit k mt ng h s hin th pht v giy.
Phn tch : Thc t ta hon ton c th thit k mt ng h hon
chnh hin th y gi pht giy. Trong khun kh bi ton ny
ta s dng ngay bn led 7 on sn c trn Sp3 th nghim.
Vi vic hin th pht v giy ta t chc nh sau. Vi 2 led cui l led 1 v led 2 s
hin th giy. Nh vy led 1 v led 3 hin th cc s t 0 n 9, led 2 v led 4 s hin
th cc s m t 0 n 5. Nh vy khi vit chng trnh ta cn t chc vic chn
led cho ph hp, vi cch thc th hin nh vy ta s chn led 1 m ti a n 9
sau v khng, khi led 1 m n 9 th tng ng led2 s m ln mt.Khi 2 led
cui m n 59 s c c reset v 0, v lc led th 3 s c tng ln mt.
Khi led th 3 tng n 9 th led s 4 c tng ln 1. V kt qu khi l 59.59 th cc
led s tr v 00.00 v thc hin m li t u.
B m ln s thc hin m sau mi giy mt. Mt giy ng h tng ng
vi tn s l 1 hz. Trn Sp3 tn s thch anh c tn s dao ng n nh l 50 Mhz,
v vy ta phi thc hin chia tn s to ra tn s 1hz. Cch thc chia tn s thc
hin nh sau:
u tin ta to ra tn s 1Mhz bng cch chia tn s 50 Mhz cho 50. Ngha
l c c 50 xung clock 50Mhz th cho ra mt xung clock 1Mhz. Tng t nh vy
ta to ra tn s 1Khz t tn s 1Mhz. Ngha l c c 1000 xung clock 1Mhz th cho
ra 1 xung 1Khz. T tn s 1Khz ta to ra tn s 1 Hz cng tng t. Nh vy, trong
chng trnh ta ch cn t chc cc b m tng ng to cc clock u ra ph
hp.
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120
Cc led c ni theo kiu Anod chung. Vic chn led no sng c thc
hin bi 4 bt AN
3
n AN
0
, chng ta c th thy vic iu khin ny thng qua 4
bt digit( 3 downto 0) phn chng trnh. C th vic chn led theo bng sau:
Digit <= 1110 --Chn led 1 ( bn phi cng)
Digit <= 1101 --Chn led 2;
Digit <= 1011 --Chn led 3;
Digit <= 0111 --Chn led 4; Do ni Anod chung nn s dng mc logic thp.
Vic hin s ln led 7 on da trn vic gii m BCD sang 7 on. C th nh sau
when "0000" => seg <= "0000001" & dp ; --s 0
when "0001" => seg <= "1001111" & dp ; --s 1
when "0010" => seg <= "0010010" & dp ; --s 2
when "0011" => seg <= "0000110" & dp ; --s 3
when "0100" => seg <= "1001100" & dp ; --s 4
when "0101" => seg <= "0100100" & dp ; --s 5
when "0110" => seg <= "0100000" & dp ; --s 6
when "0111" => seg <= "0001111" & dp ; --s 7
when "1000" => seg <= "0000000" & dp ; --s 8
when others => seg <= "0000100" & dp ; --s 9

Hnh 5.1: iu khin chn led v hin th trn Led 7 on

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T vic phn tch trn ta thc hin vic vit chng trnh nh sau:
-- File name : clock.vhd
-------------------ng h s hin th pht giy---------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity clock is port (
clk50in : in std_logic ; --u vo 50Mhz
pb_in : in std_logic_vector(3 downto 0); -- 4 Nt n.
sw_in : in std_logic_vector(7 downto 0); -- 8 chuyn mch u vo
digit_out :out std_logic_vector(3 downto 0);--Tng ng l (AN0..AN3)
led_out : out std_logic_vector(7 downto 0);-- 8 LEDs
seg_out :out std_logic_vector(7 downto 0));--Led 7 thanh v du chm
end clock ;

architecture arch_clock of clock is
--(Lu trong bi ny chng ta c s dng mt s thnh phn c sn trong
th vin ca ISE. Nhm mun chng ta n li cc lnh Component trong VHDL,
thy c vic nh x thnh cng ra sao. Nh thy trong m t pha di s
dng thnh phn Ibuf_lvcmoss33, thc t n ch l thnh phn m t cc cng vo
ra khi c xung ng b)
component ibuf_lvcmos33 port (i : in std_logic; o : out std_logic);
end component;
component ibufg_lvcmos33 port(i : in std_logic; o : out std_logic);
end component;
component obuf_lvcmos33 port(i : in std_logic; o : out std_logic);
end component;
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component bufg port(i : in std_logic; o : out std_logic);
end component;
--Khai bo cc tn hiu s dng.
signal low : std_logic ; -- logic '0'
signal high : std_logic ; -- logic '1'
signal rst : std_logic ; -- logic '1'
signal clk50int : std_logic ; --
signal clk50 : std_logic ; --
signal pb : std_logic_vector(3 downto 0) ; --
signal sw : std_logic_vector(7 downto 0) ; --
signal led : std_logic_vector(7 downto 0) ; --
signal digit : std_logic_vector(3 downto 0) ; --
signal seg : std_logic_vector(7 downto 0) ; --
signal mhertz_count : std_logic_vector(5 downto 0) ; --
signal khertz_count : std_logic_vector(9 downto 0) ; --
signal hertz_count : std_logic_vector(9 downto 0) ; --
signal mhertz_en : std_logic ; --
signal khertz_en : std_logic ; --
signal hertz_en : std_logic ; --
signal bcdint : std_logic_vector(15 downto 0) ; --
signal sthc : std_logic_vector(3 downto 0) ; --
signal cd : std_logic_vector(2 downto 0) ; --
signal point : std_logic ; --
signal dp : std_logic ; --

begin
low <= '0' ;
high <= '1' ;
rst <= pb(0) ;
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clk50in_ibuf : ibufg_lvcmos33 port map(i => clk50in, o => clk50int );
rxclka_bufg : bufg port map(i => clk50int, o => clk50 ) ;
--clk50in clk50int clk50. Vic nh x cc cng nh trn chnh l ta
thc hin vic ng nht tn hiu to ra bi b to dao ng thch anh clk50in bng
tn hiu clk50 m ta nh ngha. Khi vic x l vi xung clock clk50in s c
thay th bng vic x l vi tn hiu m ta nh ngha.
--Nh ni trn, mc ch ca vic lm ny nhm gip chng ta lm quen
vi vic nh x cu hnh thnh cng ra sao phc v cho cc bi ton ln. Chng
ta hnh dung nu nh mt bi ton bao gm rt nhiu thc th ( entity) m chng
u cn s dng mt tn hiu hay mt thnh phn ging nhau. Khi thay cho vic
m t nhiu ln, chng ta ch cn m t trong mt thc th sau nh x cc thnh
phn ca thc th dng cho tt c cc thc th khc s tit kim c rt nhiu
thi gian.
loop0 : for i in 0 to 3 generate
digit_obuf : obuf_lvcmos33 port map(i => digit(i),o=> digit_out(i));
pb_ibuf : ibuf_lvcmos33 port map(i => pb_in(i), o => pb(i));
end generate ;

loop1 : for i in 0 to 7 generate
led_obuf : obuf_lvcmos33 port map(i => led(i), o => led_out(i));
digit_obuf : obuf_lvcmos33 port map(i => seg(i),o => seg_out(i));
sw_ibuf : ibuf_lvcmos33 port map(i => sw_in(i), o => sw(i));
end generate ;
process (clk50, rst)
begin
if rst = '1' then
led <= "00000001" ; Mc nh cho led 1 lun sng.
point <= '0' ;
dp <= '0' ;
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elsif clk50'event and clk50 = '1' then
if hertz_en = '1' then
point <= not point ;
led <= led(6 downto 0) & led(7) ;--Cc led s sng quay vng ln lt
sau mi giy. Tn hiu 1hz c to ra phn di.
end if ;
if cd(1 downto 0) = "10" then
dp <= point ;
else
dp <= '1' ; --Nhm to ra du chm ngn cch pht v giy.
end if ;
end if ;
end process ;
-- tao tin hieu 1 megahec tu tin hieu chuan 50 megahec
process (clk50, rst)
begin
if rst = '1' then
mhertz_count <= (others => '0') ;
mhertz_en <= '0' ;
elsif clk50'event and clk50 = '1' then
mhertz_count <= mhertz_count + 1 ;
if mhertz_count = "110010" then chia cho 50 to 1Mhz
mhertz_en <= '1' ;
mhertz_count <= (others => '0') ;
else
mhertz_en <= '0' ;
end if ;
end if ;
end process ;
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-- tao tin hieu 1 kilohec tu tin hieu 1 megahec
process (clk50, rst)
begin
if rst = '1' then
khertz_count <= (others => '0') ;
khertz_en <= '0' ;
elsif clk50'event and clk50 = '1' then
if mhertz_en = '1' then
khertz_count <= khertz_count + 1 ;
if khertz_count = "1111101000" then Chia 1 Mhz cho 1000
khertz_en <= '1' ;
khertz_count <= (others => '0') ;
else
khertz_en <= '0' ;
end if ;
else
khertz_en <= '0' ;
end if ;
end if ;
end process ;
-- Tao tin hieu 1 hec tu tin hieu 1 kilohec
process (clk50, rst)
begin
if rst = '1' then
hertz_count <= (others => '0') ;
hertz_en <= '0' ;
elsif clk50'event and clk50 = '1' then
if khertz_en = '1' then
hertz_count <= hertz_count + 1 ;
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if hertz_count = "1111101000" then Chia 1 Khz cho 1000
hertz_en <= '1' ;
hertz_count <= (others => '0') ;
else
hertz_en <= '0' ;
end if ;
else
hertz_en <= '0' ;
end if ;
end if ;
end process ;

-- Bat dau dem
process (clk50, rst)
begin
if rst = '1' then
bcdint <= (others => '0') ;
elsif clk50'event and clk50 = '1' then
if hertz_en = '1' then
--(on m ny nhm nh ra s m ti a cho cc led 7 thanh nh phn
tch trn. Cc bcdint ( 3 downto 0), bcdint(7 downto 4) dnh cho vic hin th
giy; bcdint(11 downto 8) , bcdint (15 downto 12) dnh cho vic hin th pht. S
m ti a to ra 59:59 ).
if bcdint(3 downto 0) = "1001" then --9
if bcdint(7 downto 4) = "0101" then --5
if bcdint(11 downto 8) = "1001" then --9
if bcdint(15 downto 12) = "0101" then --5
bcdint <= "0000000000000000" ;
else
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bcdint <= (bcdint(15 downto 12) + 1) & "000000000000" ;
end if ;
else
bcdint <= bcdint(15 downto 12) & (bcdint(11 downto 8) + 1) & "00000000" ;
end if ;
else
bcdint <= bcdint(15 downto 8) & (bcdint(7 downto 4) + 1) & "0000" ;
end if ;
else
bcdint <= bcdint(15 downto 4) & (bcdint(3 downto 0) + 1) ;
end if ;
end if ;
end if ;
end process ;
--Hien thi phut , giay ln led 7 thanh
process (clk50, rst)
begin
if rst = '1' then
seg <= (others => '1') ;
digit <= (others => '1') ;
cd <= (others => '0') ;
sthc <= (others => '0') ;
elsif clk50'event and clk50 = '1' then
cd(2) <= '1' ;
if khertz_en = '1' then --To tc qut led l 1Khz.
cd(1 downto 0) <= cd(1 downto 0) + 1 ;
end if ;
case cd(1 downto 0) is
when "00" => sthc <= bcdint(3 downto 0) ; digit <= "1110" ;
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when "01" => sthc <= bcdint(7 downto 4) ; digit <= "1101" ;
when "10" => sthc <= bcdint(11 downto 8) ; digit <= "1011" ;
when others => sthc <= bcdint(15 downto 12) ; digit <= "0111" ;
end case ;
if cd(2) = '1' then
case sthc is
when "0000" => seg <= "0000001" & dp ;
when "0001" => seg <= "1001111" & dp ;
when "0010" => seg <= "0010010" & dp ;
when "0011" => seg <= "0000110" & dp ;
when "0100" => seg <= "1001100" & dp ;
when "0101" => seg <= "0100100" & dp ;
when "0110" => seg <= "0100000" & dp ;
when "0111" => seg <= "0001111" & dp ;
when "1000" => seg <= "0000000" & dp ;
when others => seg <= "0000100" & dp ;
end case ;
else
seg <= (others => '1') ;
end if ;
end if ;
end process ;
end arch_clock;

Sau khi hon thnh xong vic vit lnh, chng ta kim tra theo cc bc trnh
by v d mt. Sau khi chy xong phn RTL logic ta c s lgic v vic kt
ni cc thnh phn m ta m t trong phn vit m trn nh sau:
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Khi trnh dch a ra kt qu m t logic truyn thanh ghi (RTL) nh trn ng M@ r@ a raTj /C2_0 1 Tf 0 Tc 0 Tw 1.032 0 Td <04AB>Tj /TT0 1 Tf 0.00073Tc -0.00175Tw 0.442 0 Td (n gqu)3431trnh dv t q tr
Tip cn lp trnh cho FPGA t Spartan -3

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Hnh 5.2: Ca s cc cng tng ng vi danh sch kt ni

Cc bc tip theo l np cu hnh cho kid, chy kim tra nh lm bi tp 1.
Nh vy, thng qua bi tp ny chng ta bit cch chia tn s u vo to ra
cc tn s mong mun, bit cch hin th cc s ln dn led, bit cch iu khin tc
qut cho cc led sao cho m bo sng m vn to cm gic cc n c
thp sng lin tc.
Thng qua bi thc hnh ny, chng ta c th m rng vic thit k vi mt
vi ng dng c th nh o tn s hin th ln led by on, thit k vic m sn
phm theo quy tc xung




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II. Bi ton s 3 :Mc ch ca bi ny l gip chng ta n li cch thc
hin th d liu ln dn n led by on. Mt vn mi cp l khai
thc cng kt ni RS232 thc hin vic truyn d liu ni tip t my
tnh sang.
Ni dung bi ton nh sau: Vit chng trnh truyn thng gia
my tnh v Spartan 3 thng qua cng kt ni RS232, hin th cc k
t nhn c ln dn led by on di dng cc s hex.
Phn tch v thit k: hon thnh c bi ton giao tip v hin
th ny chng ta cn phi n li kin thc v cch thc truyn tin ni
tip thng qua Rs232. Vi bi ton ny chng ta s t chc ng
truyn 8 bt d liu, khng bt parity, 1 bt stop, 1 bt start. Nh vy
khung tin cn truyn l 10 bt.
Hot ng truyn d liu ni tip din ra nh sau: phn thit b truyn, lc bt
u lm vic n s a ra mt tn hiu txd_rdy bo l n sn sng lm vic.
phn thu cng vy, n s gi ra tn hiu rxd_rdy bo l n sn sng nhn d liu v
sau n s gi sang pha pht tn hiu enable gi sang pha bn kia kt ni
lin lc.
Vic truyn tin c gi i tng bt mt v mt khung tin l 10 bt ( bt u
bng bt start v kt thc bng bt stop). Qu trnh truyn tin khi u bi lnh bt
k c s dng thanh ghi m truyn nh mt thanh ghi ch ( l Tbuff trong
chng trnh). Tn hiu ghi vo m truyn ( tng ng TBufL = '1' ) s np gi
t 1 vo v tr bt th 9 ca thanh ghi dch truyn v bo cho khi iu khin tx v
yu cu cn truyn tin. Qu trnh truyn tin bt u bng s kch hot ca tn hiu
ng b bng mt ( LoadS = '1') dng m cng cho Txd ( t bt khi u ti
Txd), cng vi vic tn hiu ny c kch hot th d liu cng c truyn n
thanh ghi m truyn v t a n thanh ghi dch truyn n u ra TxD. Xung
nhp dch cc bt trong thanh ghi dch truyn s c xut hin ngay sau . Khi
cc bt d liu dch sang phi th cc ga tr 0 c a vo t bn tri. Khi MSB
ca byte d liu u ra ca thanh ghi dch th gi tr 1 ( ban u c np vo
Tip cn lp trnh cho FPGA t Spartan -3

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v tr th 9) s c in vo ngay bn tri ca bt MSB cn cc bt k t n sang
tri u c gi tr 0. iu kin ny s ch th khi iu khin TX thc hin ln
dch cui cng v sau a tr tn hiu TbufL v trng thi th ng, ng thi
xc lp c ngt cho TI ( gi thng bo Tx Busy= 1). Thi im ny cng ng
nht vi thi im cho php ghi vo m thu ca qu trnh thu tin. Ton b mc
phn tch ny tng ng vi vic vit lnh trong thc th Txunit.
Qu trnh nhn tin c khi u bng pht hin s chuyn trng thi t 1
n 0 ng thu ni tip RxD. pht hin chnh xc , tn hiu RxD c ly
mu tc gp 16 ln tc baud ca ng truyn. Khi mt bt c pht hin
th b m 16 c ti xc lp ngay v ga tr 1FFH c ghi vo thanh ghi dch
u vo. Vic ti thit lp b m 16 s ng nht thi im trn ca b m vi c
bin thi gian ca bt ang i ti u thu. Bng cch mi bt c chia thnh 16
phn bng nhau. Ti cc thnh phn thi gian th 7, 8, 9 ca mi bt, b pht hin
s trch mu RxD. Gi tr c chp nhn l gi tr c t nht l 2 trong 3 mu.
Phng php ny c thc hin nhm chng nhiu ng truyn. Khi cc bt d
liu i vo t pha bn phi ca thanh ghi dch, th cc gi tr 1 c dch sang bn
tri n. Khi bt khi u n v tr tri cng ca thanh ghi dch th n ch th cho
khi iu khin RX thc hin php dch chuyn cui cng ri np vo m thu ri
xc lp RI kt thc qu trnh nhn mt byte v yu cu gi byte tip theo. Ton b
qu trnh phn tch trn tng ng vi phn vit lnh trong thc th RxUnit.
Ta bit rng qu trnh nhn tin v qu trnh truyn tin khng din ra tch bit.
Vic ng b cn phi c thit lp. l thc th UART kt hp v ng b
cc thnh phn li vi nhau.
Gi s ng truyn thng. Ngha l ton b cc thnh phn thit k cho
mt ng truyn ni tip thc hin ng chc nng. By gi ta s hin th cc
d liu ln dn led 7 on. Vic hin th rt n gin, ta ch cn gn mt byte
d liu cho mt thanh ghi 8 bt sau hin th tng bn bt mt theo m hex tng
ng vi cc k t nhn c. Nh vy ch cn hai n l . Cch thc hin th ta
cng vn phi to ra mt tn hiu 1khz qut led. Vn phi t chc vic gii m.
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Cn vic hin th ra sao cc bn xem li bi tp 2 hoc c th c chng trnh
m ta vit. Ch l y tt c cc chng trnh u c np vo kid v
kim tra vic hin th kt qu ng theo yu cu thit k.
Hnh v 5.3a v 5.3b: mt m hnh trng thi n gin m t vic chuyn cc
trng thi khi thc hin truyn v nhn d liu.


Hnh 5.3a Hnh 5.3b

Di y xin trch ton b chng trnh ta thc hin chng ta tham
kho. Ch l vic c chng trnh tun theo cc bc sau : u tin l to tn
hiu ng b cho qu trnh pht. Sau vit mt chng trnh t chc vic m
dng chung cho cc thc th sau . V phi thc hin to tc baud l 9600 nn
ta chn h s chia l (50,000,000 / 9600) / 4 = 1302.
--Chng trnh to tn hiu ng b
library IEEE,STD;
use IEEE.Std_Logic_1164.all;

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entity synchroniser is
port (
C1 : in Std_Logic; -- Tn hiu d b
C : in Std_Logic; -- Clock
O : out Std_logic); -- Tn hiu ng b
end entity;

architecture Behaviour of synchroniser is
signal C1A : Std_Logic;
signal C1S : Std_Logic;
signal R : Std_Logic;
begin
RiseC1A : process(C1,R)
begin
if Rising_Edge(C1) then
C1A <= '1';
end if;
if (R = '1') then
C1A <= '0';
end if;
end process;

SyncP : process(C,R)
begin
if Rising_Edge(C) then
if (C1A = '1') then
C1S <= '1';
else C1S <= '0';
end if;
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if (C1S = '1') then
R <= '1';
else R <= '0';
end if;
end if;
if (R = '1') then
C1S <= '0';
end if;
end process;
O <= C1S;
end Behaviour;

-------------------------------------------------------------------------------
-- B m dng chung
-------------------------------------------------------------------------------
library IEEE,STD;
use IEEE.Std_Logic_1164.all;

entity Counter is
generic(Count: INTEGER range 0 to 65535);
port (
Clk : in Std_Logic; -- Clock
Reset : in Std_Logic; -- Reset input
CE : in Std_Logic; -- Chip Enable
O : out Std_Logic); -- Output
end entity;

architecture Behaviour of Counter is
begin
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counter : process(Clk,Reset)
variable Cnt : INTEGER range 0 to Count-1;
begin
if Reset = '1' then
Cnt := Count - 1;
O <= '0';
elsif Rising_Edge(Clk) then
if CE = '1' then
if Cnt = 0 then
O <= '1';
Cnt := Count - 1;
else
O <= '0';
Cnt := Cnt - 1;
end if;
else O <= '0';
end if;
end if;
end process;
end Behaviour;

-------------------------------------------------------------------------------
-Di y l m un thc hin vic truyn d liu
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity TxUnit is
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port (
Clk : in Std_Logic;
Reset : in Std_Logic;
Enable : in Std_Logic;
LoadA : in Std_Logic;
TxD : out Std_Logic;
Busy : out Std_Logic; -- Tx Busy
DataI : in Std_Logic_Vector(7 downto 0)); --Byte truyn.
end entity;

architecture Behaviour of TxUnit is
--Khai bo thnh phn ng b tn hiu cung cp cho qu trnh truyn .
component synchroniser is
port (
C1 : in Std_Logic; -- Tn hiu thiu ng b
C : in Std_Logic; -- Xung clock
O : out Std_logic);-- Tn hiu ng b
end component;

signal TBuff : Std_Logic_Vector(7 downto 0); -- m truyn
signal TReg : Std_Logic_Vector(7 downto 0); -- Thanh ghi dch truyn
signal TBufL : Std_Logic; -- Cho php ghi vo m truyn
signal LoadS : Std_Logic;-- Tn hiu ng b

begin
-- Synchronise Load on Clk
SyncLoad : Synchroniser port map (LoadA, Clk, LoadS);
Busy <= LoadS or TBufL;

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-- Tx process
TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
variable BitPos : INTEGER range 0 to 10; -- V tr ca cc bt trong khung
tin.
begin
if Reset = '1' then
TBufL <= '0';
BitPos := 0;
TxD <= '1';
elsif Rising_Edge(Clk) then
if LoadS = '1' then
TBuff <= DataI;
TBufL <= '1';
end if;
if Enable = '1' then
case BitPos is
when 0 => -- idle or stop bit
TxD <= '1';
if TBufL = '1' then Cho php ghi vo m truyn. Bt tip theo l
start bit.
TReg <= TBuff;
TBufL <= '0';
BitPos := 1;
end if;
when 1 => -- Start bit
TxD <= '0';
BitPos := 2;
when others =>
TxD <= TReg(BitPos-2); --Tng bt mt c gi ra TxD
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BitPos := BitPos + 1;
end case;
if BitPos = 10 then
BitPos := 0;
end if;
end if;
end if;
end process;
end Behaviour;
-------------------------------------------------------------------------------

--M un nhn d liu t ng truyn.

-------------------------------------------------------------------------------
-- File : Rxunit.vhd
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity RxUnit is
port (
Clk : in Std_Logic; -- Xung clock h thng
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
ReadA : in Std_logic;
RxD : in Std_Logic;
RxAv : out Std_Logic; -- Sn sng nhn d liu
DataO : out Std_Logic_Vector(7 downto 0)); -- Byte nhn
end entity;
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architecture Behaviour of RxUnit is
signal RReg : Std_Logic_Vector(7 downto 0); -- Thanh ghi dch thu
signal RRegL : Std_Logic;
begin
-- RxAv process
RxAvProc : process(RRegL,Reset,ReadA)
begin
if ReadA = '1' or Reset = '1' then
RxAv <= '0'; -- Ph nh RxAv khi ang thc hin truyn
elsif Rising_Edge(RRegL) then
RxAv <= '1';
end if;
end process;

-- Rx Process
RxProc : process(Clk,Reset,Enable,RxD,RReg)
variable BitPos : INTEGER range 0 to 10; -- V tr ca bt trong khung tin
variable SampleCnt : INTEGER range 0 to 3; -- m t 0 n 3 cho mi bt.
Nh phn tch trn, b m mu trong phn thu nhm chng nhiu ng
truyn.
begin
if Reset = '1' then -- Reset
RRegL <= '0';
BitPos := 0;
elsif Rising_Edge(Clk) then
if Enable = '1' then
case BitPos is
when 0 => --khng lm g c
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RRegL <= '0';
if RxD = '0' then -- Start Bit
SampleCnt := 0;
BitPos := 1;
end if;
when 10 => -- Stop Bit
BitPos := 0;
RRegL <= '1';
DataO <= RReg; -- Lu byte nhn c t ng truyn.
when others =>
if SampleCnt = 1 then
RReg(BitPos-2) <= RxD;
end if;
if SampleCnt = 3 then
BitPos := BitPos + 1;
end if;
end case;
if SampleCnt = 3 then
SampleCnt := 0;
else
sampleCnt := SampleCnt + 1;
end if;

end if;
end if;
end process;
end Behaviour;


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-------------------------------------------------------------------------------
-- T chc mt UART hon chnh.
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity UART is
generic(BRDIVISOR: INTEGER range 0 to 65535 := 130);
port (
WB_CLK_I : in Std_Logic; --xung dong ho
WB_RST_I : in Std_Logic; -- Dau vao reset
WB_ADR_I : in Std_Logic_Vector(1 downto 0); -- bus dia chia
WB_DAT_I : in Std_Logic_Vector(7 downto 0); -- bus du lieu vao
WB_DAT_O : out Std_Logic_Vector(7 downto 0); -- bus du lieu ra
WB_WE_I : in Std_Logic; -- Cho phep ghi
WB_STB_I : in Std_Logic; -- Bin i
WB_ACK_O : out Std_Logic;-- Bao cho biet da nhan duoc.
--Cac tin hieu xu ly
IntTx_O : out Std_Logic; -- Ngat truyen:chi ra thoi gian doi cho moi byte
truyen
IntRx_O : out Std_Logic; -- Ngat thu:///////////////////////////////////// nhan
BR_Clk_I : in Std_Logic; -- xung thoi gian cho qua trinh truyen va nhan
du lieu
TxD_PAD_O: out Std_Logic; -- Duong Tx Rs232
RxD_PAD_I: in Std_Logic); -- Duong Rx Rs232
end entity;
architecture Behaviour of UART is

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component Counter is
generic(COUNT: INTEGER range 0 to 65535);
port (
Clk : in Std_Logic; -- Clock
Reset : in Std_Logic; -- Reset input
CE : in Std_Logic; -- Chip Enable
O : out Std_Logic); -- Output
end component;
--Khai bo thnh phn RxUnit
component RxUnit is
port (
Clk : in Std_Logic;
Reset : in Std_Logic;
Enable : in Std_Logic;
ReadA : in Std_logic;
RxD : in Std_Logic;
RxAv : out Std_Logic;
DataO : out Std_Logic_Vector(7 downto 0));
end component;
--Khai bo thnh phn TxUnit
component TxUnit is
port (
Clk : in Std_Logic;
Reset : in Std_Logic;
Enable : in Std_Logic;
LoadA : in Std_Logic;
TxD : out Std_Logic;
Busy : out Std_Logic;
DataI : in Std_Logic_Vector(7 downto 0));
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end component;

signal RxData : Std_Logic_Vector(7 downto 0); -- So byte cuoi cung nhan duoc
signal TxData : Std_Logic_Vector(7 downto 0); -- So byte cuoi cung truyen di
signal SReg : Std_Logic_Vector(7 downto 0); -- Thanh ghi trang thai duong truyen
signal EnabRx : Std_Logic; -- Enable RX
signal EnabTx : Std_Logic; -- Enable TX
signal RxAv : Std_Logic; -- Du lieu nhan duoc
signal TxBusy : Std_Logic; -- Duong truyen ban
signal ReadA : Std_Logic; -- Dem truyen
signal LoadA : Std_Logic; -- Dem thu
signal Sig0 : Std_Logic; --Tin hieu muc '0'
signal Sig1 : Std_Logic; --Tin hieu muc '1'

begin
sig0 <= '0';
sig1 <= '1';
Uart_Rxrate : Counter -- Dieu chinh lai toc do Baud
generic map (COUNT => BRDIVISOR)
port map (BR_CLK_I, sig0, sig1, EnabRx);
Uart_Txrate : Counter --he so chia 4 cho Tx
generic map (COUNT => 4)
port map (BR_CLK_I, Sig0, EnabRx, EnabTx);
Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA,
TxD_PAD_O, TxBusy, TxData);
Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA,
RxD_PAD_I, RxAv, RxData);
IntTx_O <= not TxBusy;
IntRx_O <= RxAv;
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SReg(0) <= not TxBusy;
SReg(1) <= RxAv;

-- Cac thanh phan chinh trong viec trao doi du lieu.
-- Viec dong bo duoc thuc hien boi xung clock va reset
WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I,
WB_ADR_I)
variable StatM : Std_Logic_Vector(4 downto 0);
begin
if Rising_Edge(WB_CLK_I) then
if (WB_RST_I = '1') then
ReadA <= '0';
LoadA <= '0';
else
if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then
Ghi byte ra Tx
TxData <= WB_DAT_I;
LoadA <= '1'; -- Tin hieu nap
else LoadA <= '0';
end if;
if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then --
c byte t Rx
ReadA <= '1'; -- Tin hieu doc
else ReadA <= '0';
end if;
end if;
end if;
end process;
WB_ACK_O <= WB_STB_I;
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WB_DAT_O <=
RxData when WB_ADR_I = "00" else -- Doc byte tu Rx
SReg when WB_ADR_I = "01" else -- Doc trang thai thanh ghi.
X"00";
end Behaviour;

--------------------------------------------------------------------
--Hin th d liu nhn c ra led by on di dng s Hex.
--------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity rs232 is
port
( seg :out std_logic_vector(8 downto 1);
clk : in std_logic; -- Tan so 50Mhz tu Sp3
td : out std_logic; -- Duong truyen Rs232
rd : in std_logic; -- Duong nhan Rs232
reset_n : in std_logic;
barled : out std_logic_vector(8 downto 1);
ethernet_cs_n : out std_logic ; --
digit : out std_logic_vector(3 downto 0));
end rs232;

architecture arch of rs232 is
--Khai bo thnh phn UART thc hin vic nh x cng.

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component UART is
generic(BRDIVISOR : integer range 0 to 65535 := 130);
port (
WB_CLK_I : in std_logic;
WB_RST_I : in std_logic;
WB_ADR_I : in std_logic_vector(1 downto 0);
WB_DAT_I : in std_logic_vector(7 downto 0);
WB_DAT_O : out std_logic_vector(7 downto 0);
WB_WE_I : in std_logic; -- Write Enable
WB_STB_I : in std_logic; -- Strobe
WB_ACK_O : out std_logic;
IntTx_O : out std_logic;
IntRx_O : out std_logic;
BR_Clk_I : in std_logic;
TxD_PAD_O : out std_logic;
RxD_PAD_I : in std_logic);
end component;

signal reset : std_logic;
signal rcv, tx, tx_x : std_logic_vector(7 downto 0); -- cc d liu truyn
i v nhn v.
signal write, strobe, ack : std_logic;
signal td_rdy, rd_rdy : std_logic; -- C bo truyn v nhn
signal reg0 : std_logic_vector(1 downto 0); -a ch thanh ghi ca
m un UART.
type fsm_state is (read_char_state, write_char_state); --Trng thi ghi v c
signal state, state_x : fsm_state; -- Bin iu khin trng thi
signal sthc : std_logic_vector(3 downto 0);
signal bcdint:std_logic_vector(16 downto 9);
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signal cd: std_logic_vector(2 downto 0);
signal mhertz_count : std_logic_vector(5 downto 0) ; --
signal khertz_count : std_logic_vector(9 downto 0) ; --
signal dp : std_logic ; --
signal khertz_en : std_logic ;
signal mhertz_en : std_logic ; --
begin
ethernet_cs_n <= '1';
--Reset co muc tich cuc cao.
reset <= not reset_n;
reg0 <= "0" & not(rd_rdy or td_rdy);
--nh x cng
u1 : uart
generic map(
--V tn s thch anh l 50 Mhz, cn to tc baud l 9600 tng ng h
s chia l(50,000,000 / 9600) / 4 = 1302.
brdivisor => 1302
)
port map(
wb_clk_i => clk,
wb_rst_i => reset,
wb_adr_i => reg0,
wb_dat_i => tx,
wb_dat_o => rcv,
wb_we_i => write,
wb_stb_i => strobe,
wb_ack_o => ack,
inttx_o => td_rdy,
intrx_o => rd_rdy,
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br_clk_i => clk,
txd_pad_o => td,
rxd_pad_i => rd
);
barled <=tx;
bcdint(16 downto 9)<=tx;
--Hien thi cac ki tu nhan duoc ra led va led bay doan.
--Qua trinh do duoc dieu khien boi mot mo hinh may trang thai don gian.
process(rcv, td_rdy, rd_rdy, state)
begin
state_x <= state;
tx_x <= tx;
strobe <= '0';
write <= '0';
case state is
when read_char_state =>
if rd_rdy = '1' then
strobe <= '1';
tx_x <= rcv;
state_x <= write_char_state; -- Trng thi tip theo : Ghi k t nhn
c vo b m.
end if;
when write_char_state =>
if td_rdy = '1' then
strobe <= '1';
write <= '1';
state_x <= read_char_state;
end if;
when others =>
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state_x <= read_char_state;
end case;
end process;

process(clk, reset)
begin --Thuc hien chia tan tao tan so quet led bay doan
if reset = '1' then
mhertz_count <= (others => '0') ;
mhertz_en <= '0' ;
elsif clk'event and clk = '1' then
mhertz_count <= mhertz_count + 1 ;
if mhertz_count = "110010" then
mhertz_en <= '1' ;
mhertz_count <= (others => '0') ;
else
mhertz_en <= '0' ;
end if ;
end if ;
end process ;
-- tao tin hieu 1 kilohec tu tin hieu 1 megahec
process (clk, reset )
begin
if reset = '1' then
khertz_count <= (others => '0') ;
khertz_en <= '0' ;
elsif clk'event and clk = '1' then
if mhertz_en = '1' then
khertz_count <= khertz_count + 1 ;
if khertz_count = "1111101000" then
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khertz_en <= '1' ;
khertz_count <= (others => '0') ;
else
khertz_en <= '0' ;
end if ;
else
khertz_en <= '0' ;
end if ;
end if ;
end process ;
process (clk, reset )
begin
if reset = '1' then
state <= read_char_state;
seg<=(others=>'1');
cd <= (others => '0') ;
sthc <= (others => '0') ;
elsif rising_edge(clk) then
tx <= tx_x;
state <= state_x;
cd(2) <= '1' ;
if khertz_en = '1' then
cd(1 downto 0) <= cd(1 downto 0) + 1 ;
end if ;
case cd(1 downto 0) is
when "00" => sthc <= bcdint(12 downto 9) ; digit <= "1011" ;--Chon 2 led ben
trai
when others => sthc <= bcdint(16 downto 13) ; digit <= "0111" ;
end case ;
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if cd(2) = '1' then
case sthc is
when "0000" => seg <= "0000001" & dp ;--0
when "0001" => seg <= "1001111" & dp ;--1
when "0010" => seg <= "0010010" & dp ;--2
when "0011" => seg <= "0000110" & dp ;--3
when "0100" => seg <= "1001100" & dp ;--4
when "0101" => seg <= "0100100" & dp ;--5
when "0110" => seg <= "0100000" & dp ;--6
when "0111" => seg <= "0001111" & dp ;--7
when "1000" => seg <= "0000000" & dp ;--8
when "1001" => seg <= "0000100" & dp ;--9
When "1010" =>seg <= "0001000" & dp ;--Chu A
When "1011" =>seg <= "1100000" & dp ;--Chu b
When "1100" => seg <= "0110001" & dp ;--Chu C
When "1101" => seg <= "1000010" & dp; --Chu d
When "1110" => seg <= "0110000" & dp; -- Chu E
When others=> seg <= "0111000" & dp; --Chu F
end case ;
else
seg <= (others => '1') ;
end if ;
end if ;
end process ;
end arch;

Sau khi vit xong ton b chng trnh chng ta kim tra li cu trc cng nh
ng php. S logic truyn thanh ghi v netlish theo cch m t ca ta trn nh
sau
Tip cn lp trnh cho FPGA t Spartan -3

154

Hnh 5.4: S logic truyn thanh ghi ca Rs232
Vic gn chn cn c vo s kt ni sau. Ngha l TxD gn vi
R13; RxD gn vi T13.

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155
Cc thnh phn cn li bao gm vic kt ni cho cc led, led 7 on,
cc nt n, cc chuyn mch, xung clock u vo chng ta xem li
cc bi tp trn. Khi ta tin hnh to file rs232.ucf nh sau:

Hnh 5.4: kt ni cc cng s dng trong Rs232
Tin hnh np vo kid kim tra qu trnh thit k.
Hng dn kim tra vic truyn thng: Chng ta c th t vit mt
chng trnh kim tra qu trnh truyn v nhn tin qua Rs232 Tuy vy bi tp ny
tit kim thi gian ta s dng Hyper terminal l mt tin ch sn c trong
WinXP. Vo All Progams Accessories communications Hyper terminal.
Khi ca s sau s hin ra :
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Hnh 5.5: Giao din khi gi chng trnh Hyper teminal
in mt ci tn g trong phn name, v d ta t l thu nghiem. Sau nhn OK
chp nhn. Ca s sau s hin ra.

phn Country/region chn VietNam(84), Area code ta chn mt m s bt k (v
ta khng thc hin vic kt ni thc), connect using chn Com1. Nhn OK chp
nhn. Khi ca s tip theo s hin ra.
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157

Chn tc bt l 9600 tng ng vi mc thit k, s bt d liu l 8, khng bt
Parity, mt bt stop, flow control chn None. Sau apply ri OK. Tip theo ta th
nghim bng cch vit mt k t bt k gi s ta chn ch a khi led 7 on hin
th ng s 61 tng ng vi m ASCII ca k t a. Nu nh ta ng b v vit
chng trnh ng th trn mn hnh ca chng ta cng hin th ng k t a do
Spartan-3 tr v.

Hnh 5.6: Truyn tin thnh cng v ng yu cu thit k.

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Bi 4. Giao tip vi mn hnh.
Mc ch:C th ni y l mt bi ton kh kh. Tuy vy nu nh
chng ta hiu c cch thc to nh trn mn hnh v vic phi hp gia qu trnh
qut hng, qut ct v tc c d liu th chng ta c th lm ch c vic xut
tn hiu ln mn hnh. Nh vy vi bi ton ny nhm gip chng ta c th tm hiu
c cch thc to nh trn mn hnh, vic to cc im mu v c bit l vic
phi hp ng b gia cc tn hiu s dng trong k thut truyn hnh.
Ni dung: Vit chng trnh cho Spartan-3 v cc vung lin tip
nhau trn mn hnh sao cho cc vung c mu sc thay i t
, xanh, chm v vin mu en.
Phn tch v thit k: Vic hin th ln mn hnh c tin hnh
da trn cc ng qut ngang t phi qua tri v qut dc t trn xung di.Vic
hin th ln trn mn hnh di dng cc im nh ( cc picel). S Picel qut ht
mt ng ngang v s Picel qut ht mt ng dc gi l phn gii. d
dng hnh dung cch to nh trn mn hnh chng ta xt hnh v sau

Hnh v trn l mt v d minh ho cho vic hin th trn mn hnh CRT vi
phn gii l 640*480. Nh vy, to ra in p rng ca thc hin vic qut cn
Tip cn lp trnh cho FPGA t Spartan -3

159
phi cung cp mt tn hiu sao cho ng vi in p qut ngc khi s l tn hiu
xo cho mt dng qut. Di y l biu thi gian tn hiu VGA

Trong cc tham s T
PW
, T
S
,T
disp
, T
fp
, T
bp
vi cc phn gii khc nhau s khc
nhau. C hai phn gii ta thng s dng hn c l 640*480 v 800*600. Di
y l bng tham s T
PW
, T
S
,T
disp
, T
fp
, T
bp
ng vi phn gii 640*480 l phn
gii m ta hay s dng trong qu trnh thit k. Thc ra cc gi tr ny chng ta c
th thay i trong mt vi gi tr vn m bo vic ng b qut v to nh trn
mn hnh theo ng thit k vic hin th.

Nh vy to ra tn hiu qut nh trn n gin ta to ra mt b m vi s m
ti a ln n 800 s reset v khng. B m thc hin m n cc gi tr tng
ng cho trn bng trn th xut tn hiu ln mc 1. Mt iu lu l tn s ng
vi mi Picel l 25 Mhz. Chnh v vy ta phi to ra xung clock 25Mhz to s
kin m i vi mi gi tr Picel. to ra vung mu th ch cn s im nh
trn ng qut ngang bng s im nh trn ng qut dc v xut mu ti v tr
. T cc phn tch trn ta i n chng trnh c th nh sau:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGA is
port(clk50_in : in std_logic;
red_out : out std_logic;
green_out : out std_logic;
blue_out : out std_logic;
hs_out : out std_logic;
vs_out : out std_logic);
end VGA;
architecture Behavioral of VGA is
signal clk25 : std_logic;
signal horizontal_counter : std_logic_vector (9 downto 0);
signal vertical_counter : std_logic_vector (9 downto 0);
begin
--To tn hiu 25Mhz.
process (clk50_in)
begin
if clk50_in'event and clk50_in='1' then
if (clk25 = '0') then
clk25 <= '1';
else
clk25 <= '0';
end if;
end if;
end process;
process (clk25)
begin
if clk25'event and clk25 = '1' then

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if (horizontal_counter >= "0010010000" ) -- 144
and (horizontal_counter < "1100010000" ) -- 784
and (vertical_counter >= "0000100111" ) -- 39
and (vertical_counter < "1000000111" ) -- 519
then
red_out <= horizontal_counter(3)
and vertical_counter(3);
green_out <= horizontal_counter(4)
and vertical_counter(4);
blue_out <= horizontal_counter(5)
and vertical_counter(5);
else
red_out <= '0';
green_out <= '0';
blue_out <= '0';
end if;
if (horizontal_counter > "0000000000" )
and (horizontal_counter < "0001100001" ) -- 96+1
then
hs_out <= '0';
else
hs_out <= '1';
end if;
if (vertical_counter > "0000000000" )
and (vertical_counter < "0000000011" ) -- 2+1
then
vs_out <= '0';
else
vs_out <= '1';
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end if;
horizontal_counter <= horizontal_counter+"0000000001";
if (horizontal_counter="1100100000") then
vertical_counter <= vertical_counter+"0000000001";
horizontal_counter <= "0000000000";
end if;
if (vertical_counter="1000001001") then
vertical_counter <= "0000000000";
end if;
end if;
end process;
end Behavioral;
Phn tch logic truyn thanh ghi ng vi chng trnh trn nh sau:

Hnh 5.5: S logic mc truyn thanh ghi ca thc th VGA.
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By gi ta thc hin kt ni VGA vi Spartan -3. Vic kt ni cn c theo hnh v
sau:

Hnh 5.6: S kt ni VGA vi Spartan -3
Nh vy ta cn phi kt ni theo bng di y:

Cn c vo s v bng kt ni cho trn ta to ra file VGA.ucf gn cc cng
vo ra tng ng :

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Bi 5: Giao tip vi bn phm my tnh Ps2.
Mc ch: Giao tip vi bn phm thng c dng n i vi cc
thit k da trn b vi iu khin. Nhp t bn phm v xut ra led l
s la chn kinh t giao tip vi ngi s dng v thng thch
hp vi cc ng dng phc tp. Vi cc bi ton nh chng ta thng
t to mt bn phm n gin vi chc nng do ta nh ngha. Bi ton ny a ra
nhm gip chng ta lm quen vi cch thc giao tip vi bn phm PS2 bao gm
vic nhp k t s t bn phm, bin i thnh m ASCII tng ng.
Ni dung bi ton: Vit chng trnh cho Spartan-3 thc hin vic
qut bn phm Ps2, chuyn sang m AscII tng ng.
Phn tch v hng thit k: - u tin l bng m ho bn phm
PS2 do IBM cung cp c a vo Rom nhm mc ch gii m 7
bt sang m ASCII, bt a ch th 7 dnh cho phm Caplock, bits th
8 dnh cho phm Shift. Di y l bng m ho bn phm PS2 do
IBM cung cp.
x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0

x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
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Chng ta khng nht thit phi hiu qu r v sao h li m ho nh vy v
thc ra ta khng c mc ch s ch to ra bn phm kiu ny. y nhim v
chnh ca chng ta l s dng n gii quyt bi ton m chng ta t ra. Cc k
hiu gii thch bn phi cng l cc m hex tng ng vi cc k t ASCII.
Cc d liu c truyn t bn phm theo phng php truyn ni tip v vy
cng ging nh bt c cch thc thc hin truyn tin ni tip no, d liu truyn i
u phi a qua b m truyn, cng tng t nh vy, d liu nhn t bn phm
cng phi thc hin c ln lt t b m tng ng.Chnh v vy cn phi s
dng mt m hnh my trng thi iu khin thao tc chuyn i ni tip sang
song song v t song song sang ni tip. Qu trnh chuyn i t ni tip sang song
song a ra m truyn thao tc qut phm v qu trnh ngc li cho thao tc
khi phc m ASCII.
tng xng vi bng m ca IBM y chng ta c khai bo bt Parity
nhn dng cnh xung iu khin v cc lnh khc nhau t bn phm, tuy nhin do
mc ch ca chng ta khng cn qu ch trng iu v vy ta khng x l
vi bt ny. Thay vo ta dng hai bt "Extended" (0xE0) v "Released" (0xF0)
lm cng vic .
Cng ging nh qu trnh truyn thng tin ni tip khc, y chng ta cn
phi x dng cc c bo hiu, lot c chc nng bao gm xc nhn phm n, c bo
cho php chuyn i song song, ni tip, c bo li trng thi bn phm do c qu
nhiu phm b nhn, c bo nhn.u phi c khai bo s dng.
y, cng cn phi lu rng trnh tnh trng cc phm c n ng
lot, ta x l ng thi hai tn hiu Ps2_clk v Ps2_data_line thnh thong c ko
xung thp v tng ng vi cc hng in tr t trng thi tr khng cao,
ng ngha vi vic xc nhn khng c dng d liu no c php truyn i c.
Hn na trong chng trnh cng t ra vic x l chng rung cho bn phm bng
cch a ra khong thi gian hm debounce timer.
iu cn quan tm cui cng l vic ng b tc qut l xung clock 60us
c to ra bng cch chia tn s. Cng nhn mnh thm rng tn s chia y s
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166
dng tn s 12.5Mhz. Chnh v vy trong vic chia tn s to ra 60us chnh l s
dng tn s 12.5Mhz chia ch khng phi dng xung clock 50Mhz t h thng(
do vy trong chng trnh c hng s 750, l h s tn s phi chia, v
750/60us=12,5Mhz-y l iu ht sc lu khi cc bn c chng trnh. S d
chng ta lm cng vic vng vo ny v tn s chia 12.5 y chng ta s phi s
dng rt nhiu bi ton nh bi ton truyn tin ni tip, bi ton giao tip vi mn
hnh Mt tham s th hai na l xung clock 5us c s dng cho mc ch
chng rung do hin tng ny phm.
Di y l ton b chng trnh dng qut bn phm v chuyn i cc
phm ra m ASCII tng ng:
Sau y l chng trnh to xung clock 12.5Mhz:
--------------------------------------------------------------------------------
--Thuc the nay tao ra xung clock 12.5Mhz
-- Create Date: 13:56:42 11/14/06
-- Module Name: taothoigian - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity taothoigian is
port ( clkin : in std_logic;
reset : in std_logic;
clkout : out std_logic;
end taothoigian;

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architecture Behavioral of taothoigian is
signal dem: std_logic_vector(1 downto 0);
begin
process(clkin, reset)
begin
if reset='1' then
clkout<='0';
elsif clkin='1' and clkin'event then
dem <= dem +"01";
clkout<=dem(1);
end if;
end process;
end Behavioral;

Thc th di y a ra bng m ca PS2
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use unisim.all;

entity key_b4 is
Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
Tip cn lp trnh cho FPGA t Spartan -3

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rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0) );
end key_b4;

architecture rtl of key_b4 is
--Thnh phn m t cu trc Ram.
component RAMB4_S8
generic (
INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) );
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
we : in std_logic;
addr : in std_logic_vector(8 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0)
);
end component RAMB4_S8;

signal we : std_logic;
begin
ROM : RAMB4_S8
Generic map (
INIT_00 => x"00327761737a0000003171000000000000600900000000000000000000000000", -- 1F - 00
INIT_01 => x"003837756a6d00000036796768626e0000357274667620000033346564786300", -- 3F - 20
INIT_02 => x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 5F - 40
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INIT_03 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
INIT_04 => x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80
INIT_05 => x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0
INIT_06 => x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0
INIT_07 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0
INIT_08 => x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00
INIT_09 => x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20
INIT_0A => x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40
INIT_0B => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60
INIT_0C => x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80
INIT_0D => x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0
INIT_0E => x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", -- DF - C0
INIT_0F => x"0000000000000000001b000000007f0000000000000000000008000000000000" -- FF - E0
)
port map ( clk => clk,
en => cs,
we => we,
rst => rst,
addr => addr,
di => wdata,
do => rdata);

my_ram_512 : process ( rw )
begin
we <= not rw;
end process;
end architecture rtl;
--Thc th di y m t giao din chnh ca chng trnh qut phm v
chuyn sang m ASCII:
---------------------------------------------------------------------------------------

library ieee;
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use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity ps2_keyboard_interface is
port(
clk : in std_logic;
reset : in std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
rx_extended : out std_logic;
rx_released : out std_logic;
rx_shift_key_on : out std_logic;
rx_ascii : out std_logic_vector(7 downto 0);
rx_data_ready : out std_logic; -- rx_read_o
rx_read : in std_logic; -- rx_read_ack_i
tx_data : in std_logic_vector(7 downto 0);
tx_write : in std_logic;
tx_write_ack : out std_logic; -- ghi xong??
tx_error_no_keyboard_ack : out std_logic
);
end ps2_keyboard_interface;
architecture banphimPs2 of ps2_keyboard_interface is
--Thnh phn to xung clk12.5mhz
Component port
( clkin : in std_logic;
reset : in std_logic;
clkout : out std_logic);
end component;
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constant TOTAL_BITS : integer := 11;
constant EXTEND_CODE : integer := 16#E0#; -tng ng X E0(M Hex)
constant RELEASE_CODE : integer := 16#F0#;
constant LEFT_SHIFT : integer := 16#12#;
constant RIGHT_SHIFT : integer := 16#59#;
constant CTRL_CODE : integer := 16#14#;
constant CAPS_CODE : integer := 16#58#;
-- Cc hng s to clock 60us t 12.5Mhz khi thc hin chia thc th
VDU.
constant TIMER_60USEC_VALUE_PP : integer := 750; -- H s chia to 60us
constant TIMER_60USEC_BITS_PP : integer := 10; -- Tng ng s 750 th cn
10 bt.
constant TIMER_5USEC_VALUE_PP : integer := 62; --H s chia to 5us
constant TIMER_5USEC_BITS_PP : integer := 6; -- S bt tng ng
constant TRAP_SHIFT_KEYS_PP : integer := 1; -- Mc nh khng dng phm
Trap-phm lt.
--Qu trnh m ho trng thi tng ng vi nhng hng s dnh cho tnh linh
hot ca mun khi to.
type m1_type is ( m1_rx_clk_h, m1_rx_clk_l, m1_tx_wait_clk_h,
m1_tx_force_clk_l, m1_tx_clk_h, m1_tx_clk_l,
m1_tx_wait_keyboard_ack, m1_tx_done_recovery, m1_tx_error_no_keyboard_ack,
m1_tx_rising_edge_marker, m1_tx_first_wait_clk_h, m1_tx_first_wait_clk_l,
m1_tx_reset_timer, m1_rx_falling_edge_marker, m1_rx_rising_edge_marker );
signal timer_60usec_done : std_logic; --u ra clock 60us
signal timer_5usec_done : std_logic; --u ra clock 5 us
signal extended : std_logic; -- tn hiu nhn dng cnh ng vi m x 0E
signal released : std_logic; --tn hiu nhn dng cnh ng vi m x 0F
signal shift_key_on : std_logic; --cho php thc hin chuyn dch
signal ctrl_key_on : std_logic;
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signal caps_key_on : std_logic;
signal rx_output_event : std_logic;
signal rx_output_strobe : std_logic;
signal tx_parity_bit : std_logic;
signal rx_shifting_done : std_logic;
signal tx_shifting_done : std_logic;
signal shift_key_plus_code: std_logic_vector(8 downto 0);
signal q : std_logic_vector(TOTAL_BITS-1 downto 0);
signal m1_state : m1_type;
signal m1_next_state : m1_type;
signal bit_count : std_logic_vector(3 downto 0);
signal enable_timer_60usec: std_logic;
signal enable_timer_5usec : std_logic;
signal timer_60usec_count : std_logic_vector(TIMER_60USEC_BITS_PP-1
downto 0);
signal timer_5usec_count : std_logic_vector(TIMER_5USEC_BITS_PP-1
downto 0);
signal ascii : std_logic_vector(7 downto 0);
signal left_shift_key : std_logic;
signal right_shift_key : std_logic;
signal hold_extended : std_logic;
signal hold_released : std_logic;
signal ps2_clk_s : std_logic;
signal ps2_data_s : std_logic;
signal ps2_clk_hi_z : std_logic; --2 tn hiu to tr khng cao
signal ps2_data_hi_z : std_logic;
signal tx_write_ack_o : std_logic;

component key_b4
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Port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector (8 downto 0);
rdata : out std_logic_vector (7 downto 0);
wdata : in std_logic_vector (7 downto 0)
);
end component;

begin
tanso:taothoigian
Port map (
Clkint=> clk;
Reset =>reset;
Clkout=>ps2_clk);
my_key_map : key_b4
Port map (
clk => clk,
rst => reset,
cs => '1',
rw => '1',
addr => shift_key_plus_code,
rdata => ascii,
wdata => "00000000"
);
--x l vi hai tn hiu ps2_clk_hi_z, ps2_data_hi_z to ra tr khng cao
nhm khng cho truyn d liu khi c nhiu phm c n.
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ps2_direction : process( ps2_clk_hi_z, ps2_data_hi_z )
begin
if( ps2_clk_hi_z = '1' ) then
ps2_clk <= 'Z';
else
ps2_clk <= '0';
end if;
if( ps2_data_hi_z = '1' ) then
ps2_data <= 'Z';
else
ps2_data <= '0';
end if;
end process;
--Qu trnh x l tip theo nhm ng b ho cc logic u vo
--nh vy c th trnh c nhng li lin quan n vic chuyn trng thi sai.
ps2_synch : process(clk, ps2_clk, ps2_data)
begin
if clk'event and clk='0' then
ps2_clk_s <= ps2_clk;
ps2_data_s <= ps2_data;
end if;
end process;

m1_state_register : process( clk, reset, m1_state )
begin
if clk'event and clk='0' then
if (reset = '1') then
m1_state <= m1_rx_clk_h;
else
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m1_state <= m1_next_state;
end if;
end if;
end process;

m1_state_logic : process( m1_state, q,tx_shifting_done, tx_write, ps2_clk_s,
ps2_data_s, timer_60usec_done, timer_5usec_done )
begin
ps2_clk_hi_z <= '1';
ps2_data_hi_z <= '1';
tx_error_no_keyboard_ack <= '0';
enable_timer_60usec <= '0';
enable_timer_5usec <= '0';
case (m1_state) is
when m1_rx_clk_h =>
enable_timer_60usec <= '1';
if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_rx_falling_edge_marker;
else
m1_next_state <= m1_rx_clk_h;
end if;

when m1_rx_falling_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_l;
when m1_rx_clk_l =>
enable_timer_60usec <= '1';
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if (tx_write = '1') then
m1_next_state <= m1_tx_reset_timer;
elsif (ps2_clk_s = '1') then
m1_next_state <= m1_rx_rising_edge_marker;
else
m1_next_state <= m1_rx_clk_l;
end if;

when m1_rx_rising_edge_marker =>
enable_timer_60usec <= '0';
m1_next_state <= m1_rx_clk_h;

when m1_tx_reset_timer =>
enable_timer_60usec <= '0';
m1_next_state <= m1_tx_force_clk_l;

when m1_tx_force_clk_l =>
enable_timer_60usec <= '1';
ps2_clk_hi_z <= '0'; -- Force the ps2_clk line low.
if (timer_60usec_done = '1') then
m1_next_state <= m1_tx_first_wait_clk_h;
else
m1_next_state <= m1_tx_force_clk_l;
end if;

when m1_tx_first_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= '0'; -- Start bit.
if (ps2_clk_s = '0') and (timer_5usec_done = '1') then
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m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_h;
end if;
--Thi gian tr c th ln ti 10miligiy trc khi bt u mt xung clock
--Trong sut thi gian tr, chng ta khng th iu khin d liu (q[0])
when m1_tx_first_wait_clk_l =>
ps2_data_hi_z <= '0';
if (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_first_wait_clk_l;
end if;
when m1_tx_wait_clk_h =>
enable_timer_5usec <= '1';
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') and (timer_5usec_done = '1') then
m1_next_state <= m1_tx_rising_edge_marker;
else
m1_next_state <= m1_tx_wait_clk_h;
end if;

when m1_tx_rising_edge_marker =>
ps2_data_hi_z <= q(0);
m1_next_state <= m1_tx_clk_h;

when m1_tx_clk_h =>
ps2_data_hi_z <= q(0);
if (tx_shifting_done = '1') then
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m1_next_state <= m1_tx_wait_keyboard_ack;
elsif (ps2_clk_s = '0') then
m1_next_state <= m1_tx_clk_l;
else
m1_next_state <= m1_tx_clk_h;
end if;

when m1_tx_clk_l =>
ps2_data_hi_z <= q(0);
if (ps2_clk_s = '1') then
m1_next_state <= m1_tx_wait_clk_h;
else
m1_next_state <= m1_tx_clk_l;
end if;

when m1_tx_wait_keyboard_ack =>
if (ps2_clk_s = '0') and (ps2_data_s = '1') then
m1_next_state <= m1_tx_error_no_keyboard_ack;
elsif (ps2_clk_s = '0') and (ps2_data_s = '0') then
m1_next_state <= m1_tx_done_recovery;
else
m1_next_state <= m1_tx_wait_keyboard_ack;
end if;

when m1_tx_done_recovery =>
if (ps2_clk_s = '1') and (ps2_data_s = '1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_done_recovery;
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end if;

when m1_tx_error_no_keyboard_ack =>
tx_error_no_keyboard_ack <= '1';
if (ps2_clk_s = '1') and (ps2_data_s ='1') then
m1_next_state <= m1_rx_clk_h;
else
m1_next_state <= m1_tx_error_no_keyboard_ack;
end if;

when others =>
m1_next_state <= m1_rx_clk_h;
end case;
end process;
--Thc hin m n 11.
bit_counter: process(clk, reset, m1_state, bit_count )
begin
if clk'event and clk = '0' then
if ( reset = '1' ) or
( rx_shifting_done = '1' ) or
(m1_state = m1_tx_wait_keyboard_ack) then
bit_count <= "0000"; -- normal reset
elsif (timer_60usec_done = '1' ) and (m1_state = m1_rx_clk_h) and
(ps2_clk_s = '1') then
bit_count <= "0000";
elsif (m1_state = m1_rx_falling_edge_marker) or
(m1_state = m1_tx_rising_edge_marker) then
bit_count <= bit_count + 1;
end if;
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end if;
end process;
assign: process( bit_count, tx_write, tx_write_ack_o, m1_state )
begin
if (bit_count = TOTAL_BITS) then
rx_shifting_done <= '1';
else
rx_shifting_done <= '0';
end if;

if (bit_count = (TOTAL_BITS-1)) then
tx_shifting_done <= '1';
else
tx_shifting_done <= '0';
end if;
if ((tx_write = '1') and (m1_state = m1_rx_clk_h)) or
((tx_write = '1') and (m1_state = m1_rx_clk_l)) then
tx_write_ack_o <= '1';
else
tx_write_ack_o <= '0';
end if;
tx_write_ack <= tx_write_ack_o;
end process;
-- gn tx_parity_bit = ~^tx_data;
tx_parity_bit <= not( tx_data(7) xor tx_data(6) xor tx_data(5) xor tx_data(4)
xor tx_data(3) xor tx_data(2) xor tx_data(1) xor tx_data(0) );

-- Thanh ghi dch
q_shift : process(clk, tx_write_ack_o, tx_parity_bit, tx_data,
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m1_state, q, ps2_data_s, rx_shifting_done )
begin
if clk'event and clk='0' then
if (reset = '1') then
q <= "00000000000";
elsif (tx_write_ack_o = '1') then
q <= "1" & tx_parity_bit & tx_data & "0";
elsif ( (m1_state = m1_rx_falling_edge_marker) or
(m1_state = m1_tx_rising_edge_marker) ) then
q <= ps2_data_s & q((TOTAL_BITS-1) downto 1);
end if;
end if;
--To ra hai tn hiu c bit cho vic qut phm gm Caplock v Shift
if (q(8 downto 1) = EXTEND_CODE) and (rx_shifting_done = '1') then
extended <= '1';
else
extended <= '0';
end if;
if (q(8 downto 1) = RELEASE_CODE) and (rx_shifting_done = '1') then
released <= '1';
else
released <= '0';
end if;
end process;

-- To clock 60us
timer60usec: process(clk, enable_timer_60usec, timer_60usec_count)
begin
if clk'event and clk = '0' then
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if (enable_timer_60usec = '0') then
timer_60usec_count <= "0000000000";
elsif (timer_60usec_done = '0') then
timer_60usec_count <= timer_60usec_count + 1;
end if;
end if;

if (timer_60usec_count = (TIMER_60USEC_VALUE_PP - 1)) then
timer_60usec_done <= '1';
else
timer_60usec_done <= '0';
end if;
end process;

-- To tn hiu 5 us
timer5usec : process(clk, enable_timer_5usec, timer_5usec_count )
begin
if clk'event and clk = '0' then
if (enable_timer_5usec = '0') then
timer_5usec_count <= "000000";
elsif (timer_5usec_done = '0') then
timer_5usec_count <= timer_5usec_count + 1;
end if;
end if;
if( timer_5usec_count = (TIMER_5USEC_VALUE_PP - 1)) then
timer_5usec_done <= '1';
else
timer_5usec_done <= '0';
end if;
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end process;
--Qut cc phm c bit:
special_scan : process(clk, reset, rx_output_event, rx_shifting_done, extended,
released )
begin
if clk'event and clk='0' then
if (reset = '1') or (rx_output_event = '1') then
hold_extended <= '0';
hold_released <= '0';
else
if (rx_shifting_done = '1') and (extended = '1') then
hold_extended <= '1';
end if;
if (rx_shifting_done = '1') and (released = '1') then
hold_released <= '1';
end if;
end if;
end if;
end process;
--Dch tri
left_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
left_shift_key <= '0';
elsif (q(8 downto 1) = LEFT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '0') then
left_shift_key <= '1';
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elsif (q(8 downto 1) = LEFT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '1') then
left_shift_key <= '0';
end if;
end if;
end process;
--Dch phi
right_shift_proc : process(clk, reset, q, rx_shifting_done, hold_released )
begin
if clk'event and clk = '0' then
if (reset = '1') then
right_shift_key <= '0';
elsif (q(8 downto 1) = RIGHT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '0') then
right_shift_key <= '1';
elsif (q(8 downto 1) = RIGHT_SHIFT) and
(rx_shifting_done = '1') and
(hold_released = '1') then
right_shift_key <= '0';
end if;
end if;
end process;

shift_key_on <= left_shift_key or right_shift_key;
rx_shift_key_on <= shift_key_on;
--X l phm Ctr
ctrl_proc : process(clk, reset, q, rx_shifting_done, hold_released )
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begin
if clk'event and clk = '0' then
if (reset = '1') then
ctrl_key_on <= '0';
elsif (q(8 downto 1) = CTRL_CODE) and
(rx_shifting_done = '1') and
(hold_released = '0') then
ctrl_key_on <= '1';
elsif (q(8 downto 1) = CTRL_CODE) and
(rx_shifting_done = '1') and
(hold_released = '1') then
ctrl_key_on <= '0';
end if;
end if;
end process;

--
-- Phm Caplock
--
caps_proc : process(clk, reset, q, rx_shifting_done, hold_released,
caps_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
caps_key_on <= '0';
elsif (q(8 downto 1) = CAPS_CODE) and
(rx_shifting_done = '1') and
(hold_released = '0') then
caps_key_on <= not caps_key_on;
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end if;
end if;
end process;

special_scan_proc : process(clk, reset, hold_extended, hold_released, q, ascii,
ctrl_key_on )
begin
if clk'event and clk = '0' then
if (reset = '1') then
rx_extended <= '0';
rx_released <= '0';
-- rx_scan_code <= "00000000";
rx_ascii <= "00000000";
elsif (rx_output_strobe = '1') then
rx_extended <= hold_extended;
rx_released <= hold_released;
-- rx_scan_code <= q(8 downto 1);
elsif ctrl_key_on = '1' then
rx_ascii <= ascii and x"1f";
else
rx_ascii <= ascii;
end if;
end if;
end process;
rx_output_proc : process( clk, reset, rx_shifting_done, rx_output_strobe,
extended, released, q, ascii, rx_read )
begin
if (rx_shifting_done = '1') and (extended = '0') and (released = '0') then
rx_output_event <= '1';
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else
rx_output_event <= '0';
end if;

if clk'event and clk = '0' then
if reset = '1' then
rx_output_strobe <= '0';
elsif (rx_shifting_done = '1') and
(rx_output_strobe = '0') and
(extended = '0') and
(released = '0') and
(hold_released = '0' ) and
(ascii /= x"00" ) then
-- ((TRAP_SHIFT_KEYS_PP = 0) or
-- ( (q(8 downto 1) /= RIGHT_SHIFT) and
-- (q(8 downto 1) /= LEFT_SHIFT) and
-- (q(8 downto 1) /= CTRL_CODE) ) )then
rx_output_strobe <= '1';
elsif rx_read = '1' then
rx_output_strobe <= '0';
end if;
end if;
rx_data_ready <= rx_output_strobe;
end process;
--Gii m sang ASCII
shift_key_plus_code <= shift_key_on & caps_key_on & q(7 downto 1);

--shift_map : process( shift_key_plus_code )
--begin
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-- case shift_key_plus_code is
-- when x"066" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"166" => ascii <= x"08"; -- Backspace ("backspace" key)
-- when x"00d" => ascii <= x"09"; -- Horizontal Tab
-- when x"10d" => ascii <= x"09"; -- Horizontal Tab
-- when x"05a" => ascii <= x"0d"; -- Phm Enter
-- when x"15a" => ascii <= x"0d";
-- when x"076" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"176" => ascii <= x"1b"; -- Escape ("esc" key)
-- when x"029" => ascii <= x"20"; -- Space
-- when x"129" => ascii <= x"20"; -- Space
-- when x"116" => ascii <= x"21"; -- !
-- when x"152" => ascii <= x"22"; -- "
-- when x"126" => ascii <= x"23"; -- #
-- when x"125" => ascii <= x"24"; -- $
-- when x"12e" => ascii <= x"25"; --
-- when x"13d" => ascii <= x"26"; --
-- when x"052" => ascii <= x"27"; --
-- when x"146" => ascii <= x"28"; --
-- when x"145" => ascii <= x"29"; --
-- when x"13e" => ascii <= x"2a"; -- *
-- when x"155" => ascii <= x"2b"; -- +
-- when x"041" => ascii <= x"2c"; -- ,
-- when x"04e" => ascii <= x"2d"; -- -
-- when x"049" => ascii <= x"2e"; -- .
-- when x"04a" => ascii <= x"2f"; -- /
-- when x"045" => ascii <= x"30"; -- 0
-- when x"016" => ascii <= x"31"; -- 1
-- when x"01e" => ascii <= x"32"; -- 2
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-- when x"026" => ascii <= x"33"; -- 3
-- when x"025" => ascii <= x"34"; -- 4
-- when x"02e" => ascii <= x"35"; -- 5
-- when x"036" => ascii <= x"36"; -- 6
-- when x"03d" => ascii <= x"37"; -- 7
-- when x"03e" => ascii <= x"38"; -- 8
-- when x"046" => ascii <= x"39"; -- 9
-- when x"14c" => ascii <= x"3a"; -- :
-- when x"04c" => ascii <= x"3b"; -- ;
-- when x"141" => ascii <= x"3c"; -- <
-- when x"055" => ascii <= x"3d"; -- =
-- when x"149" => ascii <= x"3e"; -- >
-- when x"14a" => ascii <= x"3f"; -- ?
-- when x"11e" => ascii <= x"40"; -- @
-- when x"11c" => ascii <= x"41"; -- A
-- when x"132" => ascii <= x"42"; -- B
-- when x"121" => ascii <= x"43"; -- C
-- when x"123" => ascii <= x"44"; -- D
-- when x"124" => ascii <= x"45"; -- E
-- when x"12b" => ascii <= x"46"; -- F
-- when x"134" => ascii <= x"47"; -- G
-- when x"133" => ascii <= x"48"; -- H
-- when x"143" => ascii <= x"49"; -- I
-- when x"13b" => ascii <= x"4a"; -- J
-- when x"142" => ascii <= x"4b"; -- K
-- when x"14b" => ascii <= x"4c"; -- L
-- when x"13a" => ascii <= x"4d"; -- M
-- when x"131" => ascii <= x"4e"; -- N
-- when x"144" => ascii <= x"4f"; -- O
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-- when x"14d" => ascii <= x"50"; -- P
-- when x"115" => ascii <= x"51"; -- Q
-- when x"12d" => ascii <= x"52"; -- R
-- when x"11b" => ascii <= x"53"; -- S
-- when x"12c" => ascii <= x"54"; -- T
-- when x"13c" => ascii <= x"55"; -- U
-- when x"12a" => ascii <= x"56"; -- V
-- when x"11d" => ascii <= x"57"; -- W
-- when x"122" => ascii <= x"58"; -- X
-- when x"135" => ascii <= x"59"; -- Y
-- when x"11a" => ascii <= x"5a"; -- Z
-- when x"054" => ascii <= x"5b"; -- [
-- when x"05d" => ascii <= x"5c"; -- \
-- when x"05b" => ascii <= x"5d"; -- ]
-- when x"136" => ascii <= x"5e"; -- ^
-- when x"14e" => ascii <= x"5f"; -- _
-- when x"00e" => ascii <= x"60"; -- `
-- when x"01c" => ascii <= x"61"; -- a
-- when x"032" => ascii <= x"62"; -- b
-- when x"021" => ascii <= x"63"; -- c
-- when x"023" => ascii <= x"64"; -- d
-- when x"024" => ascii <= x"65"; -- e
-- when x"02b" => ascii <= x"66"; -- f
-- when x"034" => ascii <= x"67"; -- g
-- when x"033" => ascii <= x"68"; -- h
-- when x"043" => ascii <= x"69"; -- i
-- when x"03b" => ascii <= x"6a"; -- j
-- when x"042" => ascii <= x"6b"; -- k
-- when x"04b" => ascii <= x"6c"; -- l
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-- when x"03a" => ascii <= x"6d"; -- m
-- when x"031" => ascii <= x"6e"; -- n
-- when x"044" => ascii <= x"6f"; -- o
-- when x"04d" => ascii <= x"70"; -- p
-- when x"015" => ascii <= x"71"; -- q
-- when x"02d" => ascii <= x"72"; -- r
-- when x"01b" => ascii <= x"73"; -- s
-- when x"02c" => ascii <= x"74"; -- t
-- when x"03c" => ascii <= x"75"; -- u
-- when x"02a" => ascii <= x"76"; -- v
-- when x"01d" => ascii <= x"77"; -- w
-- when x"022" => ascii <= x"78"; -- x
-- when x"035" => ascii <= x"79"; -- y
-- when x"01a" => ascii <= x"7a"; -- z
-- when x"154" => ascii <= x"7b"; -- {
-- when x"15d" => ascii <= x"7c"; -- |
-- when x"15b" => ascii <= x"7d"; -- }
-- when x"10e" => ascii <= x"7e"; -- ~
-- when x"071" => ascii <= x"7f"; -- Delete hoc phm del
-- when x"171" => ascii <= x"7f"; -- //////////////////////////////////
-- when others => ascii <= x"ff";
-- end case;
--end process;
end my_ps2_keyboard;
--Di y l tng hp v l giao din bn phm ca chng ta:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.numeric_std.all;



entity keyboard is
port(
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
kbd_clk : inout std_logic;
kbd_data : inout std_logic
);
end keyboard;

architecture my_keyboard of keyboard is

signal kbd_stat : std_logic_vector(7 downto 0);
signal kbd_ctrl : std_logic_vector(7 downto 6);
signal kbd_ascii_code : std_logic_vector(7 downto 0);
signal kbd_tx_data : std_logic_vector(7 downto 0);
signal kbd_read : std_logic;
signal kbd_write : std_logic;
signal kbd_write_ack : std_logic;
component ps2_keyboard_interface
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port(
clk : in std_logic;
reset : in std_logic;
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
rx_extended : out std_logic;
rx_released : out std_logic;
rx_shift_key_on : out std_logic;
-- rx_scan_code : out std_logic_vector(7 downto 0);
rx_ascii : out std_logic_vector(7 downto 0);
rx_data_ready : out std_logic;
rx_read : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
tx_write : in std_logic;
tx_write_ack : out std_logic;
tx_error_no_keyboard_ack : out std_logic
);
end component;

begin
--nh x thnh phn thnh cng.
my_ps2_keyboard_interface : ps2_keyboard_interface
port map(
clk => clk,
reset => rst,
ps2_clk => kbd_clk,
ps2_data => kbd_data,
rx_extended => kbd_stat(2),
rx_released => kbd_stat(3),
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rx_shift_key_on => kbd_stat(4),
rx_ascii => kbd_ascii_code,
rx_data_ready => kbd_stat(0),
rx_read => kbd_read,
tx_data => kbd_tx_data,
tx_write => kbd_write,
tx_write_ack => kbd_write_ack,
tx_error_no_keyboard_ack => kbd_stat(5)
);

keyboard_strobe : process( clk, rst, cs, rw, kbd_stat )
begin
if( rst = '1' ) then
kbd_read <= '0';
elsif( clk'event and clk='0' ) then
if( cs='1' and rw='1' and addr='1' ) then
kbd_read <= '1';
elsif( kbd_stat(0)='1' ) then
kbd_read <= '0';
else
kbd_read <= kbd_read;
end if;
end if;
end process;

-- c t thanh ghi ca bn phm.
keyboard_read : process( addr, kbd_ascii_code, kbd_stat )
begin
if( addr = '1' ) then
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data_out <= kbd_ascii_code;
else
data_out <= kbd_stat;
end if;
end process;
-- ghi vo thanh ghi bn phm
keyboard_write : process( clk, rst, cs, rw, addr, data_in, kbd_tx_data,
kbd_write, kbd_write_ack )
begin
if(rst = '1' ) then
kbd_ctrl <= "00";
kbd_tx_data <= "00000000";
kbd_write <= '0';
elsif( clk'event and clk='0' ) then
if( cs='1' and rw='0' ) then
if( addr='1' ) then
kbd_tx_data <= data_in;
kbd_ctrl <= kbd_ctrl;
kbd_write <= '1';
else
kbd_tx_data <= kbd_tx_data;
kbd_ctrl <= data_in(7 downto 6);
kbd_write <= kbd_write;
end if;
elsif( kbd_write_ack='1' ) then
kbd_write <= '0';
else
kbd_write <= kbd_write;
end if;
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kbd_stat(1) <= not kbd_write;
end if;
end process;

keyboard_interrupt : process( kbd_ctrl, kbd_stat )
begin
kbd_stat(6) <= kbd_ctrl(6);
kbd_stat(7) <= kbd_ctrl(7) and kbd_stat(0);
irq <= kbd_stat(7);
end process;
end my_keyboard;
Di y l s logic mc truyn thanh ghi ca thc th keyboard

Hnh 5.7. S logic mc truyn thanh ghi ca keyboard(mc 1)
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Hnh 5.8.S logic mc truyn thanh ghi ca keyboard (mc 2)

Hnh 5.9. S logic mc truyn thanh ghi ca keyboard (mc 3)



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Bi ton s 6 : Bi ton tng hp.
Mc ch: Bi ton ny nhm tng hp li mt s kin thc thu nhn
c t cc bi ton ni trn. Vi cc bi ton nh l nh trn, rt nhiu
ngi cho rng lm nhng cng vic trn lm g, mc ch s dng ca
chng ra sao. By gi xin gii thiu mt ng dng nh ca vic giao tip
vi bn phm my tnh v hin th trn led by on cho bi ton m sn
phm
Gii thiu tng quan v h thng m sn phm:
Nhim v ca bi ton ny l thc hin mch m sn phm bng phng
php xung. Nh vy, mi sn phm i qua trn bng chuyn phi c mt thit b
cm nhn sn phm, thit b ny gi l cm bin. Khi mt sn phm i qua cm bin
s cm nhn v to ra mt xung in a v khi x l tng dn s m. Ti mt
thi im tc thi, xc nh c s m cn phi c b phn hin th. Tuy
nhin, mi khu vc hay mi ca sn xut li yu cu vi s m khc nhau v th
phi c s linh hot trong vic chuyn i s m. B phn chuyn i trc quan
nht l bn phm. y, ti c mt tng l s a s m vo t my tnh thng
qua ng truyn Rs232 Thc ra thao tc ny cng chng khc g thao tc a s
m vo t bn phm kt ni trc tip vi kid thng qua cng Ps2. Khi cn thay i
s m ngi s dng ch cn nhp s m ban u vo v mch s t ng m.
Khi s sn phm m c bng vi s m ban u th mch s t ng dng. T
y xc nh yu cu t ra yu cu phi c y cc ngoi vi nhn cc thao
tc iu khin bao gm :
*B phn cm bin: Gm phn pht v phn thu. Thng thng ngi ta s
dng phn pht l led hng ngoi pht ra nh sng hng ngoi mc ch
chng nhiu so vi cc loi nh sng khc, cn phn thu l Transistor quang thu
nh sng hng ngoi.
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* R le: Dng ng ngt mch iu khin dy truyn sn xut khi c xung
ngt iu khin c a ti.

Gii hn ca bi ton: Cc sn phm rt a dng vi nhiu chng loi
c, rng, kch c khc nhau. Nhng vi kh nng ca thit b lp mch ch c th
m i vi sn phm c kh nng che c nh sng v c kch thc t 10 cm
3

n 30 cm
3
. Nu chng ta c iu kin chng ta hon ton mua nhng cm bin c
cht lng cao hn nhiu, tuy vy theo bn thn ti th th nghim thit k th
ch cn mch m bo kh nng trn l .
S d trn spartan -3 ch c 4 led 7 on v vy m s sn phm trong mt thng
phm vi thay i t 2 999. Cn s thng sn phm phm vi thay i t 19999.
Vi bi ton thc t, chng ta c gng x l thm yu cu sau: Lu s sn phm, s
hp sau mi ca sn xut v cho php xem s sn phm v s hp trong cc ca sn
xut khi c yu cu. Vn ny dnh ring cho chng ta nghin cu.
S lc v b cm bin:
cm nhn mi ln sn phm i qua th cm bin phi c phn pht v phn thu.
Phn pht pht ra nh sng hng ngoi v phn thu hp th nh sng hng ngoi v
nh sng hng ngoi c c im l t b nhiu so vi nh sng thng thng. Hai
b phn thu v pht hot ng vi cng tn s. Khi c sn phm i qua, gia hai
phn pht v phn thu nh sng hng ngoi b che b phn thu hot ng khc vi
tn s pht nh th to ra mt xung tc ng n b phn x l. Vy b phn pht
v b phn thu phi c ngun to dao ng. B phn dao ng tc ng ti cng tc
ng ngt ca ngun pht v ngun thu nh sng. C nhiu linh kin pht v thu
nh sng hng ngoi nhng y dnh cho vic th nghim chng ta chn led hng
ngoi v transistor quang l linh kin pht v thu v transistor quang l linh kin rt
nhy vi nh sng hng ngoi. Hai linh kin ny rt d tm mua cc ca hng in
Tip cn lp trnh cho FPGA t Spartan -3

200
t. B phn dao ng c th dng mch Lc, hoc s dng cc IC to dao ng, tt
nht l nn s dng IC to dao ng v loi ny d lp v c bit n nh cng
kh cao. Nhng tt nht l chng ta s s dng ngay tn s dao ng to ra t bo
mch qua vic chia tn s. Cch ny s l ti u ho hn c. V tn hiu ng ra
transistor rt nh nn cn mch khuych i trc khi a n b to dao ng.





Phn tch, thit k: Thc ra bi ton ny nu nh chng ta thc hin trn
c s vi x l cng khng qu kh khn. Nhng s phi t chc cc ngoi vi kh
nhiu. Trn c s FPGA, bi ton ny s c thc hin mt cch rt n gin. Nh
trong phn gii thiu trn, bi ton ch n gin l to ra b m tng ln khi c
s kin mt xung a vo, s m c a vo t my tnh thng qua cng kt ni
Rs232. Sau khi m xong th s to ra mt xung iu khin rle thc hin ngt
dy truyn hot ng.
Vi yu cu ca bi ton nh trn chng ta s thit k nh sau: n gin
vi ton b tng thit k b m sn phm nh trn chng ta s s dng ton b
chng trnh vit bi ton s 3 bi ton giao tip vi my tnh thng qua
cng kt ni Rs232. Nh ta bit rng vic truyn v nhn d liu c thc thi c
s hin din ca tn hiu trng thi ng truyn v chng ta s dng tn hiu ny
to ra s kin lu tr cc s nhp. V sao ta phi lm thao tc ny? Chng ta hnh
dung, to ra s v d 1384, lm sao b phn x l hiu c rng y l s
mt nghn ba trm tm mi t? Nh vy nht thit phi c b phn chuyn i.
Nu nh bi ton ch n gin l nhn s trn ng truyn ri hin th trn 4 led
th chng ta khng cn phi dng n thao tc . Nh vy, b phn x l hiu
c ng s nhp chng ta cn phi tin hnh x l nh sau:
Khi
dao
ng
KHI
DAO
NG
KHUYCH
I
TRANSIST
OR THU
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201
u tin chng ta phi to ra cc s nhn c t m AscII thnh
s tng ng, v d thay v s 0 c m AscII l 30 th phi hin th
ng l s 0, s 1 c m AscII l 31 phi hin th l s 1.iu
ny rt n gin, chng ta ch vic ly d liu nhn c trn
ng truyn ri tr i 30H l c c cc s t 0..9 tng ng.
Nhng khi no th bt u nhn s m t ng truyn?
Vic nhn s m t ng truyn bt u khi nhn phm Space
(tng ng m 20H t ng truyn). Nh vy chng ta s s
dng mt tn hiu c tn gi chophepdem thc hin vic lu tr
cc s nhp.
S nhp c 4 ch s, 4 s ny ch n thun ch l 4 k t c
chng ta nh ngha l s thng qua thao tc tr i 30, bn thn b
phn x l cng s hiu l cc s ri rc. Nh vy chng ta cn
phi lm sao cho b phn x l hiu rng sau khi chophepdem th
s nhp u tin l hng nghn, tip theo l hng trm v tip
theo na l hng chc v cui cng l hng n v. Nh vy cn
phi s dng mt thanh ghi thc hin vic lu tr cc s nhn
c t ng truyn . a ch ca thanh ghi tng ln mi khi
nhn c mt s t ng truyn v s kin tng a ch
dng ngay tn hiu trng thi ng truyn ( v tn hiu ny thay
i mi thao tc truyn v nhn d liu). Mi s s c lu vo
mt nh v s c chuyn i sang cc n v tng ng ca
n.
Sau khi chuyn i xong, thao tc ny s din ra rt nhanh, ngi
dng s n phm Enter t ng truyn, lc ny s cho php dy
truyn hot ng ( ng tip im rle) v cho php b m bt
u hot ng.

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By gi, chng ta d hnh dung hn, bi ton ca chng ta s khng
s dng xung ngoi bao gm cc xung c to ra do b phn thu pht hng ngoi
tao ra va xung iu khin r le m chng ta kim tra hot ng ca mch bng cch
dng ngay nhng thnh phn trn bo mch. C th thay v xung ngoi t cm bin
a vo chng ta gi s x kin m tng ng vi s sn phm i qua dy truyn
u n l 1 giy c mt sn phm, vy ta s to ra tn hiu l mt giy thay cho
xung t b cm bin, cn vic tip im ngt c thay th bng 1 led bt k pht
sng. Nh vy, b phn x l s thc hin ng nu vi s nhp a vo, gi s
nhp vo s 0112, sau Enter th sau ng 0112 giy, th n led tng ng s
sng v chng ta kt lun b phn x l lm vic ng yu cu v t c th tin
hnh rp vi cc ngoi vi thc t.
Ton vn chng trnh m sn phm c cho chng trnh di y:
Lu : Cc thc th synchroniser.vhd, TxUnit.vhd, RxUnit.vhd,
Counter.vhd, UART.vhd y l cc thc th c gii thiu bi ton s 3 mc
ch ca l thc hin vic thc hin truyn v nhn d liu ni tip thng qua ng
truyn Rs232, phn ny ti khng trch ra y. Sau y xin gii thiu ton b
chng trnh thc hin vic x l ng vi cc phn tch v yu cu thit k trn
y nh sau:
--Muc dich thong qua duong truyen Rs232
--thuc hien truyen du lieu tu may tinh
--khi nhan phim Space(20h) thi cho phep nhap so.
--de tuong ung cac so thuc tu 0..9 thuc hien tru di 30h;
--//Do chi co 4 led 7 doan nen nhap bon so de kiem tra hien thi so nhap
--Mong muon cac so do dung vi tri hang nghin, tram, chuc, don vi
--ta su dung mot bien dem, dem cac byte nhan duoc
--bien dem duoc tang len khi co su kien da doc va ghi
--thanh cong tu duong truyen (ack='1')
--sau do se duoc luu vao thanh ghi 16 bit theo tung 4 bit 1
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--roi nhan voi 1000, 100, 10 ,1
--khi so xung vao dung bang so nhap
--Dau ra cua no se xuat 1 xung ngat ro le cua day truyen (led8='1').
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity demsanpham is
port
( seg :out std_logic_vector(8 downto 1);
clk : in std_logic; -- Tan so 50Mhz tu Sp3
td : out std_logic; -- Duong truyen Rs232
rd : in std_logic; -- Duong nhan Rs232
reset_n : in std_logic;
barled : out std_logic_vector(8 downto 1);
digit : out std_logic_vector(3 downto 0));
end demsanpham;
architecture arch of demsanpham is

component UART is
generic(BRDIVISOR : integer range 0 to 65535 := 130); -- He
so chia nham xac dinh toc do baud
port (

WB_CLK_I : in std_logic;
WB_RST_I : in std_logic;
WB_ADR_I : in std_logic_vector(1 downto 0);
WB_DAT_I : in std_logic_vector(7 downto 0); -- Bus du
lieu vao
WB_DAT_O : out std_logic_vector(7 downto 0);
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WB_WE_I : in std_logic; -- Cho phep ghi
WB_STB_I : in std_logic;
WB_ACK_O : out std_logic;
IntTx_O : out std_logic;
IntRx_O : out std_logic;
BR_Clk_I : in std_logic;
TxD_PAD_O : out std_logic;
RxD_PAD_I : in std_logic);

end component;
signal reset : std_logic;
signal rcv, tx, tx_x : std_logic_vector(7 downto 0); --Truyen va nhan du lieu
signal write, strobe, ack : std_logic; -- Cac tin hieu dieu khien
signal td_rdy, rd_rdy : std_logic; -- Cac co dung de bao hieu trang thai
duong truyen
signal reg0 : std_logic_vector(1 downto 0); --dia chi thanh ghi cua
UART
type fsm_state is (read_char_state, write_char_state); -- Mot may trang thai
don gian
signal state, state_x : fsm_state; -- Bien trang thai cu mo hinh
signal curr : std_logic_vector(3 downto 0);
signal bcdint:std_logic_vector(15 downto 0);
signal cd: std_logic_vector(2 downto 0);
signal mhertz_count : std_logic_vector(5 downto 0) ; --
signal khertz_count : std_logic_vector(9 downto 0) ; --
signal dp : std_logic ; --
signal khertz_en : std_logic ;
signal mhertz_en :std_logic ; --
signal trunggian :std_logic_vector(3 downto 0);
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signal biendem :std_logic_vector (13 downto 0);
signal doinhapso :std_logic; --Khi nhan Space thi cho phep nhap so
signal chophepdem :std_logic;--Khi nhap xong an Enter cho day truyen hoat
dong.
signal hertz_en :std_logic ;
signal hertz_count:std_logic_vector(9 downto 0) ;
signal demsonhap :std_logic_vector(2 downto 0);
signal luusonhap :std_logic_vector(15 downto 0);
signal sanphamdem :std_logic_vector ( 13 downto 0);
begin
--Cong internet khong dung;
ethernet_cs_n <= '1';
--Reset co muc tich cuc cao.
reset <= not reset_n;
--Dung thanh ghi Reg0 de lau du lieu tu duong truyen
reg0 <= "0" & not(rd_rdy or td_rdy);
--Thanh phan cua UART;
u1 : uart
generic map(
--Toc do baurd la 9600
--Chon he so chia (50,000,000 / 9600) / 4 = 1302.
brdivisor => 1302
)
port map(
wb_clk_i => clk,
wb_rst_i => reset,
wb_adr_i => reg0,
wb_dat_i => tx,
wb_dat_o => rcv,
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wb_we_i => write,
wb_stb_i => strobe,
wb_ack_o => ack,
inttx_o => td_rdy,
intrx_o => rd_rdy,
br_clk_i => clk,
txd_pad_o => td,
rxd_pad_i => rd
);
trunggian<=tx-x"30";--Tao ra so 0 ..9
--Qua trinh truyen va nhan du lieu tu duong truyen
--duoc dieu khien boi mot mo hinh may trang thai don gian.
--chi gom hai trang thai ghi va doc.
process(rcv, td_rdy, rd_rdy, state)
begin
state_x <= state;
tx_x <= tx;
strobe <= '0';
write <= '0';
--Mo mo hinh may trang thai don gian gom hai trang thai
--La trang thai ghi du lieu tu duong truyen
--Va trang thai doc du lieu tu duong truyen.
--Trang thai khi reset se la doc, khi co tin hieu
--Cho phep ghi thi trang thai tiep theo se la trang thai ghi
--Khi dang o trang thai ghi, khi td_rdy tich cuc se chuyen san
--trang thai doc.
case state is
when read_char_state =>
if rd_rdy = '1' then
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strobe <= '1';
state_x <= write_char_state;
end if;
when write_char_state =>
if td_rdy = '1' then
strobe <= '1';
write <= '1';
state_x <= read_char_state;
end if;
when others =>
state_x <= read_char_state;
end case;
if tx_x = x"20" then --Phim Space dung de cho phep nhap so
doinhapso<='1';
end if;
if tx_x= x"0d" then --Nhan phim Enter thi cho bat dau dem.
chophepdem <='1';
end if;
end process;
--********Doan chuong trinh thuc hien tao tan so quet led********
process(clk, reset)
begin --Thuc hien chia tan tao tan so quet led bay doan
if reset = '1' then
mhertz_count <= (others => '0') ;
mhertz_en <= '0' ;
elsif clk'event and clk = '1' then
mhertz_count <= mhertz_count + 1 ;
if mhertz_count = "110010" then
mhertz_en <= '1' ;
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mhertz_count <= (others => '0') ;
else
mhertz_en <= '0' ;
end if ;
end if ;
end process ;


-- tao tin hieu 1 kilohec tu tin hieu 1 megahec
process (clk, reset )
begin
if reset = '1' then
khertz_count <= (others => '0') ;
khertz_en <= '0' ;
elsif clk'event and clk = '1' then
if mhertz_en = '1' then
khertz_count <= khertz_count + 1 ;
if khertz_count = "1111101000" then
khertz_en <= '1' ;
khertz_count <= (others => '0') ;
else
khertz_en <= '0' ;
end if ;
else
khertz_en <= '0' ;
end if ;
end if ;
end process ;
-- Tao tin hieu 1 hec tu tin hieu 1 kilohec
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process (clk, reset)
begin
if reset = '1' then
hertz_count <= (others => '0') ;
hertz_en <= '0' ;
elsif clk'event and clk = '1' then
if khertz_en = '1' then
hertz_count <= hertz_count + 1 ;
if hertz_count = "1111101000" then
hertz_en <= '1' ;
hertz_count <= (others => '0') ;
else
hertz_en <= '0' ;
end if ;
else
hertz_en <= '0' ;
end if ;
end if ;
end process ;
process (clk, reset,doinhapso,chophepdem,ack)
begin
if reset = '1' then
state <= read_char_state;
seg<=(others=>'1');
cd <= (others => '0') ;
curr <= (others => '0') ;
elsif rising_edge(clk) then
tx <= tx_x;
state <= state_x;
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cd(2) <= '1' ;
--Doan nay dung de xu ly thong tin nhap
--(Chu y la o cho nay neu chuong trinh
--chua chay thi co the dao muc logic cua td_rdy len vi
--theo modun Rx_unit co dao muc cua tin hieu duong truyen ban)
if doinhapso='1' then
if ack ='1' then --co the thay bang strobe vi ack<=strobe
demsonhap <= demsonhap+1 ;
if demsonhap="100" then --Dem den 4 chinh la so nhap
demsonhap<= "000";
end if;
end if;
end if;
case demsonhap(2 downto 0) is
when "001" =>
luusonhap(15 downto 12)<= trunggian;--so hang nghin
when "010" =>
luusonhap(11 downto 8)<=trunggian; --so hang tram
when "011" =>
luusonhap(7 downto 4) <=trunggian; --so hang chuc
when others =>
luusonhap (3 downto 0)<=trunggian; --so hang don vi
end case;
--So san pham tu 0001 den 9999 de thu nghiem voi 4 led
--1000
sanphamdem <=(("1111101000" * luusonhap(15 downto 12) ) +
--100
("1100100" * luusonhap(11 downto 8)) +
--10
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("1010" * luusonhap(7 downto 4)) +
"0001" * luusonhap(11 downto 8));
--Hien thi cac so nhap ra led de kiem tra dung sai.
bcdint(15 downto 12)<= luusonhap(15 downto 12) ;
bcdint(11 downto 8 )<= luusonhap(11 downto 8);
bcdint(7 downto 4 )<= luusonhap (7 downto 4);
bcdint(3 downto 0 )<= luusonhap (3 downto 0);
--Dieu khien led thu 8 sang khi so xung dung bang so san pham nhap
if chophepdem='0' then
biendem<="00000000000000";
else
if hertz_en = '1' then --Lay mot giay de thu nghiem.
biendem<=biendem+1;
if (biendem = sanphamdem) then
barled(8 downto 1)<="10000000"; --Nhu trang thai ngat Role thuc.
biendem<="00000000000000";
else
barled(8 downto 1) <="00000000";
end if;
end if;
end if;
if khertz_en = '1' then
cd(1 downto 0) <= cd(1 downto 0) + 1 ;
end if ;
case cd(1 downto 0) is
when "00" => curr <= bcdint(3 downto 0) ; digit <= "1110" ;
when "01" => curr <= bcdint(7 downto 4) ; digit <= "1101" ;
when "10" => curr <= bcdint(11 downto 8) ; digit <= "1011" ;
when others => curr <= bcdint(15 downto 12) ; digit <= "0111" ;
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end case ;
if cd(2) = '1' then
case curr is
when "0000" => seg <= "0000001" & dp ;--0
when "0001" => seg <= "1001111" & dp ;--1
when "0010" => seg <= "0010010" & dp ;--2
when "0011" => seg <= "0000110" & dp ;--3
when "0100" => seg <= "1001100" & dp ;--4
when "0101" => seg <= "0100100" & dp ;--5
when "0110" => seg <= "0100000" & dp ;--6
when "0111" => seg <= "0001111" & dp ;--7
when "1000" => seg <= "0000000" & dp ;--8
when "1001" => seg <= "0000100" & dp ;--9
When "1010" =>seg <= "0001000" & dp ;--Chu A
When "1011" =>seg <= "1100000" & dp ;--Chu b
When "1100" => seg <= "0110001" & dp ;--Chu C
When "1101" => seg <= "1000010" & dp; --Chu d
When "1110" => seg <= "0110000" & dp; -- Chu E
When others=> seg <= "0111000" & dp; --Chu F
end case ;
else
seg <= (others => '1') ;
end if ;
end if ;
end process ;
end arch;
Sau khi b sung ton b cc thc th li chng ta tin hnh kim tra qu trnh vit
chng trnh xem c sai st g v mt c php hay khng, ng thi to ra mc
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truyn logic thanh ghi tng ng. Qu trnh ny chng ta qu quen thuc v vy
khng nhc li y:

Hnh 5.10 . S logic truyn thanh ghi ca thc th demsanpham (mc 1)

Hnh 5.11 . S logic truyn thanh ghi ca thc th demsanpham (mc 2)
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Vic gn chn tng t nh cc bi ton cp n trc y. y xin gii
thiu vi cc bn thm mt cch gn chn. S d cp ra y v cng c nhiu
ngi thc mc khi download trn mng xung mt s m ngun, thy rng xut
h cc file c lnh Net v loc trong c cc chn tng ng. Thc ra khi chng ta
thc hin gn chn bng giao din ng ngha vi vic trnh dch s vit lnh gn
chn cho chng ta v to ra mt file ring, cc lnh tng ng nh sau:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "barled<1>" LOC = "k12" ;
NET "barled<2>" LOC = "p14" ;
NET "barled<3>" LOC = "L12" ;
NET "barled<4>" LOC = "N14" ;
NET "barled<5>" LOC = "P13" ;
NET "barled<6>" LOC = "N12" ;
NET "barled<7>" LOC = "P12" ;
NET "barled<8>" LOC = "P11" ;
NET "clk" LOC = "T9" ;
NET "digit<0>" LOC = "D14" ;
NET "digit<1>" LOC = "G14" ;
NET "digit<2>" LOC = "F14" ;
NET "digit<3>" LOC = "E13" ;
NET "rd" LOC = "T13" ;
NET "reset_n" LOC = "K13" ;
NET "seg<1>" LOC = "P16" ;
NET "seg<2>" LOC = "N16" ;
NET "seg<3>" LOC = "F13" ;
NET "seg<4>" LOC = "R16" ;
NET "seg<5>" LOC = "P15" ;
NET "seg<6>" LOC = "N15" ;
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NET "seg<7>" LOC = "G13" ;
NET "seg<8>" LOC = "E14" ;
NET "td" LOC = "R13" ;
Cng ng nht vi vic gn chn bng giao din :