Ports 061006

6
e Ports
This document describes ports, an e unit member that enhances the portability and inter-operability of verication environments by making separation between an e unit and its interface possible. The following sections give an overview of how to use ports:
Introduction to e Ports on page 6-2 Creating and Using Port Bindings on page 6-11 Using Simple Ports on page 6-24 Using Buffer Ports on page 6-33 Using Event Ports on page 6-35 Using Method Ports on page 6-37
The following sections provide detailed descriptions of port-related syntax:
Dening and Referencing Ports on page 6-49 Dening and Disconnecting Port Bindings on page 6-66 Simple Port Access Operators on page 6-93 Event Port Access Operators on page 6-103 Method Port Access Operators on page 6-104 Buffer Port Access Methods on page 6-106 Simple Port MVL Access Methods on page 6-111 Simple Port Default Value Methods on page 6-131 Port Attributes on page 6-135
e Language Reference
2006 Cadence Design Systems, Inc. All rights reserved worldwide.
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e Ports
Introduction to e Ports
Global MVL Conversion Routines on page 6-171 Port-Related Commands on page 6-181
For information on the current limitations on ports, see Cadence Port and Adapter Known Limitations on page 1-32 in Specman Known Problems and Solutions/ Backwards Compatibility.
See Also Using the Specman Elite SystemC Integration on page 5-1 in the Specman Elite Integrators Guide Chapter 10 Guidelines for Migrating from HDL Tick Notation to Ports in the Specman Elite Integrators
Guide
6.1
Introduction to e Ports
A port is an e unit member that makes a connection between an e unit and its interface to another internal or external entity. There are two ways to use ports:
Internal ports (e2e ports) connect an e unit to another e unit. External ports connect an e unit to a simulated object.
External ports are a generic way to access simulated objects of various kinds. An external port is bound to a simulated object, such as Verilog registers or nets, VHDL signals, or SystemC methods. Then all access to that object is made via the port. The port can be used to access a different object simply by changing the binding; all the code that reads or writes to the port remains the same. Similarly, port semantics remain the same, regardless of what simulator is used. Note In this document, simulator means any hardware or software agent that runs in parallel with Specman, and models the behavior of any part of the design under test (DUT) or its environment.
6.1.1
Advantages of Using Ports
Although previous HDL access mechanisms are still supported, ports have the following advantages over the old access mechanisms:
Ports support modularity and encapsulation by explicitly declaring interfaces to e units. They are typed. They improve performance of accessing DUT objects with congurable names. They can pass not only single values but also other kinds of information, such as events and queues.
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Creating Port Instances
They can be accompanied in e with generic or simulator-specic attributes that let you specify
information needed for enhanced access to DUT objects.
They are suitable for use with a publicly available procedural External Simulator Interface (ESI). Some new simulator interfaces, such as SystemC, require the use of ports.
6.1.1.1
Current Limitations
For a complete list of the current limitations on ports, see Cadence Port and Adapter Known Limitations on page 1-32 in Specman Known Problems and Solutions/ Backwards Compatibility.
6.1.2
Port type is dened by three aspects:
The kind of port, either simple_port, buffer_port, event_port, or method_port: Simple ports access data directly. Buffer ports implement an abstraction of queues with blocking get and put. Event ports transfer events between e units or between an e unit and a simulator. Method ports call regular or time-consuming methods dened in other e units or written in foreign
programming languages. They also allow calling of time-consuming e methods from foreign programming languages.
Direction, either input or output (or inout for simple and event ports) Data element, the e type that can be passed through this port
You can instantiate ports only within units. Like units, port instances are generated during prerun generation and cannot be created, modied or removed during a run. When you instantiate a port, you must specify:
A unique instance name The port type (direction, port kind, and a kind-specic type specier)
The generic syntax for port declarations is as follows: port-instance-name: [direction] port-kind [of type-specier] is instance; Note Event ports do not allow a type specier.
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Examples
The following unit member creates a port instance:
data_in: in buffer_port of packet is instance;
where:
The port instance name is data_in. The port kind is a buffer port. The port direction is input. The data element the port accepts is packet.
As another example, the following line creates a list of simple ports which each pass data of type bit:
ports: list of simple_port of bit is instance;
See Also Using Simple Ports on page 6-24 Using Buffer Ports on page 6-33 Using Event Ports on page 6-35 Using Method Ports on page 6-37 Dening and Referencing Ports on page 6-49
6.1.2.1
Referencing Port Instances
Port instances may be referenced by a eld, a variable, or a method parameter of the same port type or of an abstract type:
any_simple_port any_buffer_port any_event_port any_method_port

Abstract port types reference only the port kind, not the port direction or data element. Thus, a method parameter of type any_simple_port accepts all simple ports, including, for example:
data_length: in simple_port of uint is instance; data: inout simple_port of list of bit is instance;
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Port Attributes
Note If a port reference is a eld, then it must be marked as non-generated or it must be constrained to an existing port instance. Otherwise, a generation error results.
Examples
check_bport(curr_port: any_buffer_port) is {...}; !in_int_buffer_port_ref: in buffer_port of int;
See Also Dening and Referencing Ports on page 6-49
6.1.3
Port Attributes
Ports have attributes that affect their behavior and how they can be used. You assign port attributes using the attribute() syntax in pre-generation constraints, as follows: keep [soft] port_instance.attribute() == value; You can use soft constraints if you might want to override the attribute later. Most port attributes are ignored unless the port is an external port, but it does no harm to specify attributes for ports that are not external ports. Attributes intended for external ports may or may not be supported for a particular simulator. A particular adapter can also dene additional port attributes that are required to enhance access to simulated objects.
Example
The following lines of code create a port named data and bind it to an external simulator-related object whose HDL pathname is data.
data: inout simple_port of list of bit is instance; keep bind(data, external); keep data.hdl_path() == "data";
See Also Port Attributes on page 6-135
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Accessing Ports and Port Values
6.1.4
Ports are containers, and the values they hold are separate entities from the port itself. The name of the port refers to the port itself, not to the port value. Thus, the following print command prints information about the port mvl_data:
cmd-prompt> print sys.mvl_data mvl_data = inout simple_port of list of mvl e_path: sys.mvl_data agent: NULL_SIM current value: (empty) next value (propagated at end of tick): 0. MVL_Z 1. MVL_U 2. MVL_L 3. MVL_Z 4. MVL_L 5. MVL_H 6. MVL_0 7. MVL_U 8. MVL_X 9. MVL_N 10. MVL_L 11. MVL_Z 12. MVL_W
For more information about the ports in the verication environment, you can use the following commands:
show ports describes the characteristics of each port trace ports displays the activity on a port during a run Sample Output of show ports -full
Ports = 0. sys.ver.dut_inp - out simple_port of int (bits: 2) e_path: sys.ver.dut_inp agent: osci hdl_path: sn_xor->/inp 1. sys.ver.dut_out - in simple_port of uint e_path: sys.ver.dut_out agent: osci hdl_path: sn_xor->/out 2. sys.ver.clk - in event_port e_path: sys.ver.clk agent: osci
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hdl_path: sn_xor->/clk
See Also Port-Related Commands on page 6-181
6.1.4.1
Accessing Port Values
The way to read or write port values depends on the port kind:
To access the port value on a simple port or an event port, append the $ access operator to the port
name. For example:
print sys.mvl_data$ sys.mvl_data$ = data_list
Note To read and write multi-value logic (MVL) data to simple ports whose data type is not mvl or list of mvl, you must use the simple port MVL methods. For example, if data is a numeric simple port:
data.put_mvl_list({MVL_H; MVL_0; MVL_L; MVL_0});
To access the port value on a buffer port, use the predened methods get() and put(). For example:
current_cell = cell_in.get()
To access a method port, append the $(param-list) access operator to the port name. For example:
var u: uint; u = convert_string$("32");
The $() access operator calls the method associated with the method port, convert_string in this example. The parameter list you specify must match the declared parameter list for the method.
See Also Accessing Simple Ports and Their Values on page 6-25 Accessing Event Ports on page 6-36 Invoking Method Ports on page 6-46 Buffer Port Access Methods on page 6-106 Simple Port MVL Access Methods on page 6-111 Global MVL Conversion Routines on page 6-171
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Using Port Values and Attributes in Constraints
6.1.5
Using Port Values and Attributes in Constraints
Like units, port instances can be created only during pre-run generation. They cannot be created with new, nor generated at runtime. Consequently, a port value cannot be initialized or sampled in pre-run generation constraints. Port values can be used in on-the-y generation constraints in accordance with the basic constraint principles, such as the bidirectional nature of constraints. See Example 1 on page 6-8. Another methodological requirement is that you must explicitly specify attribute values in hard constraints if the attributes are used anywhere in bidirectional constraints, including implication constraints. See Example 2 on page 6-8.
Example 1
This example shows the correct way to initialize an out port.
<' extend sys { inport: in simple_port of int is instance; keep bind(inport, external); outport: inout simple_port of int is instance; keep bind(outport, external); !startval: int; run() is also { gen startval; outport$ = startval; }; }; '>
// Use port$ to set a value
Trying to constrain the generation of startval to equal the value of the out port does not work because outport$ in this context samples the port value, but does not affect it:
gen startval keeping { outport$ == startval}; // does not work
Example 2
This example shows how using port attribute values in bidirectional constraints can have undesired effects.
<' extend sys { pclk: out buffer_port of packet is instance; keep synthesized() == FALSE => pclk.pass_by_pointer() == TRUE; }; '>
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Ports Example
The implication constraint above requires the following constraint to be set in every specic non-synthesized test, instead of relying on the default value of FALSE:
extend sys { keep synthesized() == FALSE; };
Adding a constraint such as

keep pclk.pass_by_pointer()==FALSE;
silently sets synthesized() to TRUE.
6.1.6
Ports Example
The e code in this section shows examples of instantiating and using internal buffer ports. An output buffer port and an input buffer port are created, the ports are connected together, and data elements of type cell are generated and transmitted from the output buffer port to the input buffer port.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 struct cell { header[2] : list of byte; data[50] : list of byte; }; unit trans { data_out: out buffer_port of cell is instance; !cells : int; keep cells == 100; drive_all() @sys.any is { var stimuli: cell; var counter: int=0; while counter < cells { wait [1]*cycle; gen stimuli; data_out.put(stimuli); counter+=1; }; }; }; unit rec { data_in: in buffer_port of cell is instance; keep data_in.buffer_size() == 20; get_all() @sys.any is { while TRUE { print data_in.get(); };
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Ports Example
29 30 31 32 33 34 35 36 37 38 39 40
}; }; extend sys{ transmitter: trans is instance; receiver: rec is instance; keep bind(transmitter.data_out, receiver.data_in); run() is also { start transmitter.drive_all(); start receiver.get_all(); }; };
Lines 1-4 dene cell, the data element that is passed by the output buffer port. Line 7 creates a port instance named data_out, whose type is out buffer_port of cell. Lines 10-19 dene a TCM that generates a variable named stimuli of type cell every cycle until 100 have been generated. This variable is written to the output buffer port by a predened buffer port TCM, put(), in Line 16. Line 23 creates a port instance named data_in of type in buffer_port of cell. This port complements
the data_out port created in the trans unit, and is used to receive cell data written to the data_out port.
Line 24 constrains the maximum number of cells that can be held in the port queue to 20. Lines 25-29 dene a TCM that retrieves and prints, one by one, the cells that have been placed on the
port queue by the drive_all() TCM. Another predened buffer port method, get(), is used to do this.
Lines 33-35 create instances of the rec and trans units and connect the data_out port with the data_in
port.
See Also Using Simple Ports on page 6-24 Using Buffer Ports on page 6-33 Using Event Ports on page 6-35 Using Method Ports on page 6-37
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Creating and Using Port Bindings
6.2
Creating and Using Port Bindings
You can bind (connect) ports to other e ports or to external simulated objects such as Verilog registers, VHDL signals, or SystemC methods. For all port kinds except buffer ports, you can connect a single port to many ports or objects (one to many). You can also connect multiple ports to a single port or object (many to one). The bound set of a port is the set of all ports and external connections bound to that port. Ports can also be dened as disconnected using empty or undened. You can subsequently over-ride empty and undened bindings. You dene port bindings either declaratively or procedurally. Regardless of how you bind ports, you use them the same way and they behave the same way. Procedural binding is recommended for complex, highly congurable environments. You can display a trace of the port binding process and query the state of port bindings procedurally during the binding process or interactively during the run. These features are described in more detail in the following sections:
Declarative and Procedural Port Bindings on page 6-11 Multiple Bindings on page 6-13 Implicit External Binding on page 6-17 Disconnected Ports and Dangling Ports on page 6-18 Bundled Binding on page 6-19 Port Binding and Rule Checking During Generation on page 6-20 Querying the State of Port Bindings on page 6-22
The methods and routines that you use to dene, disconnect, and query port bindings are described in:
Dening and Disconnecting Port Bindings on page 6-66
6.2.1
Declarative and Procedural Port Bindings
You can bind ports either declaratively or procedurally.
6.2.1.1
1.
Declarative Bindings
You can create declarative bindings by: (Optional) Dening unit references by using a pre-run generation constraint. For example:
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Declarative and Procedural Port Bindings
keep bfm.sigmap == read_only(sigmap); keep agent.id == read_only(id);
See Propagating Data when Generating the VE on page 5-4 for more information on how to do this. 2. Dening port bindings by using a pre-run generation constraint on the bind() routine. For example:
keep bind(port1, port2); keep bind(port3, external);
6.2.1.2
Procedural Bindings
Procedural binding is recommended for:
Complex, highly congurable environments, where declarative bindings overly constrain generation
and make it difcult for Specman to generate the unit tree.
Multiple port bindings (one-to-many or many-to-one). Bundled port binding (binding a units ports all at once using a shorthand notation).
Note Procedural binding is strongly recommended to enable acceleration. You can create procedural bindings by: 1. (Optional) Dening unit references by extending the connect_pointers() predened method of sys or of a unit. For example:
connect_pointers() is also { bfm.driver = driver; driver.bfm = bfm; };
See Propagating Data when Generating the VE on page 5-4 for more information on how to do this. 2. Dening port bindings, by extending the connect_ports() predened method of sys or of a unit.
connect_ports() is also { do bind(port1, port2); do_bind(port2, external); do_bind_unit(agent.monitor_i, monitor); --binds ports with same name };
You can also extend connect_ports() to
Set nal values that depend on unit references, either by assignment or by a gen action. Disconnect ports, using disconnect() or disconnect_bound_set()
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Multiple Bindings
3.
(Optional) Performing sanity checks, by extending the check_generation() predened method of sys or of any unit. For example, you might want to:
Check unit references Check port bindings, using is_connected() or get_bound_set() Check port attributes
Note You can perform procedural binding only during the elaboration sub-phase of generation.
See Also Port Binding and Rule Checking During Generation on page 6-20
6.2.2
Multiple Bindings
You can bind together any number of ports. The ports must be of the same kind (simple_port, event_port, or method_port) and must have the same element type. Note Buffer ports cannot be bound to multiple objects. The set of all ports and external connections bound to a port (its bound set) can contain multiple internal ports and multiple external connections. The external connections use the attributes on the port associated with them. You can, for example, bind p1 and p2, bind each of them to external, and then set:
keep p1.hdl_path() == "clk1"; keep p1.agent() == "verilog"; keep p2.hdl_path() == "clk2"; keep p2.agent() == "vhdl"; keep p2.vhdl_drive() == TRUE;
External attributes on ports not connected to external are ignored. (Keep in mind that any port for which the hdl_path() attribute is dened and that has no other binding is implicitly bound to external, as described in Implicit External Binding on page 6-17.) The topology of a multiple binding is a star topology, with all ports connected via a common channel. Thus, assuming the following:
a: b: c: d: in simple_port of int is instance; in simple_port of int is instance; out simple_port of int is instance; out simple_port of int is instance;
Then:
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Multiple Bindings
do_bind(a, b); do_bind(a, c); do_bind(a, d);
is exactly the same as:

do_bind(a, b); do_bind(b, c); do_bind(c, d);
or any other combination. In all cases, if you type:

c$ = 5; wait cycle; print a$; print b$;
the value assigned to c is visible in a and b, because it sits in the common channel, as shown below:
a b c d <--|-------| <--|common | -->|channel| -->|-------|
This section contains the following:
Multiple Bindings for Simple Ports on page 6-14 Multiple Bindings for Event Ports on page 6-15 Multiple Bindings for Method Ports on page 6-16 Hierarchical Binding on page 6-17
6.2.2.1
Multiple Bindings for Simple Ports
There is no value resolution for simple ports. The last value applied prevails, as is the case for multiple assignments to one port. You can set default values for a simple port or a bound set of simple ports using the set_default_value() or set_default_mvl_value() methods. By default, all simple ports are delayed. The value assigned to an out port only appears on an in port connected to it in the next Specman tick. You can override this default behavior by typing:
keep p.delayed() == FALSE;
In the case of a bound set with multiple ports, if even one of the ports is not delayed, then the whole set becomes not delayed. Thus, even if you declare p2 in the following example delayed, connections among those ports is not delayed, and no error message is issued:
connect_ports() is also {
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Multiple Bindings
do_bind(p1, p2); }; keep p2.delayed() == FALSE;
Multiple Bindings with External Simple Ports

A simple port bound set can comprise one of the following legal combinations:
Any number of external out ports and any internal ports One external inout port and any internal ports One external in port and any number of internal in ports
There is a limitation if the bound set contains multiple external output ports that are bound to HDL entities with different release effects, for example, if one external port is connected to verilog wire and one to verilog register. In this case, if a tick has a force action followed by a release action, then ambiguity exists in the way Specman should handle the rst force action, and an error is issued.
Example
o1 : out simple_port of bit is instance; keep bind(o1,external); keep o1.hdl_path() == "~/top.some_register"; o2 : out simple_port of bit is instance; keep bind(o2,external); keep o2.hdl_path() == "~/top.some_wire"; keep o2.verilog_wire() == TRUE; keep o2.verilog_forcible() == TRUE; my_tcm()@sys.any is { force o1$ = 0; release o1; // runtime error. };
6.2.2.2
Multiple Bindings for Event Ports
Multiple in event ports are all triggered whenever any of the corresponding out event ports are emitted. The order of execution of the corresponding on methods is undened. If multiple out event ports emit in the same cycle, the effect is as if one of them emitted multiple times in the same cycle. Broadcast event ports are typically used for distributing clocks.
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Multiple Bindings
6.2.2.3
Multiple Bindings for Method Ports
There are three common uses of multiple bindings for method ports:
Broadcast method ports one caller (out method_port) and multiple servers (in method_port).
For example, a monitors might want to broadcast an event occurrence to any number of scoreboards.
Multiple callers served by a single server. Multiple callers and multiple servers.
Notes
You can have multiple concurrent calls to the same method port or to all out method ports in a bound
set, unless the method port is an external SystemC method port.
If there are multiple servers (in method_port) in a bound set, then the method cannot be a TCM,
cannot return a value, and cannot have by-reference parameters. This rule is checked during elaboration. The intention is to protect the user. Because the order in which multiple servers are called is undened, it is unclear which result will be returned. With side effects, users can still cause undened behavior. Methodologically, such broadcast method ports should contain no such side effects. However, some side effects may be considered perfectly reasonable by users. For example, if you want each of the servers to tell you whether it could handle your request, you might want to have a parameter that is a list, into which each server adds, some success/failure code. Even though the list is not passed by reference, called routines can still add to it, and thus after all calls are done the caller can look at the list and nd out what happened. In the following example, the do_report in method port has a parameter that is a list. Even though the list is not passed by reference, it can still be updated and monitored.
unit tester { get_report : out method_port of report_type is instance; collect_reports() is { var l : list of report; get_report$(l); // process l }; };
unit my_unit { my_id : int; do_report : in method_port of report_type is instance; do_report(l : list of report) is {
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Implicit External Binding
var r : report = new; r.id = my_id; r.res = TRUE; l.add(r); }; };
6.2.2.4
Hierarchical Binding
While Specman allows ports to be connected without any respect to unit nesting and hierarchy, sometimes code is more readable if ports are connected hierarchically. For example, rather than binding directly:
do_bind(monitor.p, agent.p);
you can do the following:

do_bind(monitor.p, outer_monitor.p); do_bind(outer_agent.p, agent.p);
and nally use:

do_bind(outer_monitor.p, outer_agent.p);
Notes
Like all multiple bindings, the created topology is a star. Thus, the four ports are connected to a
common channel, with no real concept of hierarchy.
For method ports, all intermediate ports should be out (client) ports. Otherwise, there is an automatic
binding of the port to a method with the same name as the port, which is called automatically.
6.2.3
Implicit External Binding
When a port has no bind() constraint, but does have an hdl_path() attribute dened, the port is implicitly bound to external. The implicit external binding occurs at the beginning of the procedural binding, before any call to the connect_ports() method. A port that is implicitly bound to external must be explicitly disconnected before binding using procedural binding (unless it rst bound to external in the procedural binding). To explicitly disconnect the port, use the disconnect() or disconnect_bound_set() pseudomethod. This feature is intended for use for ports that are not procedurally bound: it saves you the effort of explicitly binding external ports to external.
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Disconnected Ports and Dangling Ports
Example
In the following example, the port sys.u1.p1 is implicitly bound to external, even though there is no bind constraint on this port:
unit u { p1 : out simple_port of int is instance; keep p1.hdl_path() == "~/top.foo"; }; extend sys { u1 : u is instance; };
Disabling Implicit Binding

The notication ID NOTIFY_IMPLICIT_BIND_TO_EXTERNAL identies ports that are implicitly bound to external. By default, the severity level for this notication is IGNORE, which means that the message associated with it is never displayed. If you want to avoid implicit binding, set this notication ID to ERROR. Example:
set notify -severity=ERROR NOTIFY_IMPLICT_BIND_TO_EXTERNAL
When you do so, Specman Elite issues an error message whenever it encounters implicit binding, giving you the opportunity to edit the code to add explicit external binding.
See Also disconnect() on page 6-82 disconnect_bound_set() on page 6-83
6.2.4
Disconnected Ports and Dangling Ports
A disconnected port is one of the following:
A port that is bound using the empty or undened keyword A dangling port a port that has been declared but not bound or a port that has been disconnected
with disconnect() or disconnect_bound_set() Note Dangling ports cause errors at during elaboration. Empty bindings and undened bindings let you dene a port that is connected to nothing. You can subsequently over-ride an empty or undened binding either declaratively or procedurally.
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Bundled Binding
The difference between empty and undened bindings is that runtime accessing of a port with an undened binding causes an error. Runtime accessing of an empty-bound port is allowed. Its effect depends on the operation and type of the port:
Reading from an empty-bound simple port returns the last written value or the default value, if no
value has been written so far. You can set a default value using the set_default_value() or set_default_mvl_value() methods. Otherwise, the default value of the port is the default value of the port element type.
Writing to an empty-bound out or inout simple port stores the new value internally. Reading from an empty-bound buffer port causes the thread to halt. Writing to an empty-bound buffer port causes the thread to halt if the buffer is full. Waiting for an empty-bound event port causes the thread to halt. If the port direction is inout then
emitting the port resumes the thread.
An empty-bound event port can be emitted.
6.2.5
Bundled Binding
The do_bind_unit() routine makes it easier to bind all of a units ports at once. You can create user interfaces using bundled binding. For example, if an agent needs three services from a monitor, you could dene a monitor interface unit with three ports, rather than creating ports in the agent called monitor_a, monitor_b and monitor_c.
unit a: b: c: }; monitor_interface in simple_port of in simple_port of in simple_port of { uint is instance; byte is instance; bit is instance;
extend agent { monitor_int: monitor_interface is instance; }; extend env { monitor: monitor; agent: agent; connect_ports() is also { do_bind_unit(agent.monitor_int, monitor); -- Bind all ports in monitor_i by name instead of -- do_bind(agent.monitor_int.a, monitor.a); -- do_bind(agent.monitor_int.b, monitor.b);
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Port Binding and Rule Checking During Generation
-- do_bind(agent.monitor_int.c, monitor.c); }; };
Then, for example, you can do

print monitor_int.a$
instead of
print agent.monitor_a$
See Also do_bind_unit() on page 6-77
6.2.6
Port bindings are created and checked during the generation test phase. As you can see in Figure 22-1 on page 22-4 in the e Language Reference, the following is the order of processes inside the generation phase (for example, when you type gen): 1. 2. 3. 4. 5. The full tree under sys is generated, including all calls to post_generate(). All declarative bindings are processed during this step in depth-rst eld order. All ports with an hdl_path() attribute dened, but with no binding dened are implicitly bound to external. (See Implicit External Binding on page 6-17.) The connect_pointers() method is called for all units, starting at sys. The connect_ports() methods is called for all units, starting at sys. The check_generation() method is called for all units, starting at sys.
Specman performs elaboration and rule checking, and then passes the list of bound port instances to the simulator adapter, which creates the data structures required to hold adapter-specic information about each port instance.
Port Binding Rules Only ports of the same kind may be bound together. For example, a simple port cannot be bound to
a buffer port. Binding ports of different kinds causes a load-time error.
Only ports with the same element type may be bound together. For example, a simple port of uint
cannot be bound to a simple port of uint(bits: 64). Binding ports of different element types causes a load-time error.
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At elaboration, there can be no dangling (disconnected) ports. Each port must be bound to empty or
undened or be a member of a bound set. Note The same port cannot be bound to both empty and undened. Attempting to apply such contradicting constraints to one port causes an elaboration-time error.
At elaboration, each bound set must have at least: One in port and one out port, or One inout port and one other port, or One external port For simulator adapters provided by Cadence: You cannot bind a port to a part select of a VHDL signal. It must be bound to the entire signal.
The declared_range() must also match the actual range of the signal. However, assignments to a part select of a simple external port are allowed, for example:
outp$[31:16] = data;
You can bind a simple or event port to a part select of a Verilog signal, for example:
<' unit u { myport: in simple_port of int is instance; keep bind(myport, external); keep myport.hdl_path == "~/top/data_vector[31:16]"; }; '>
However, you cannot bind an inout or out simple port to a part select of a Verilog wire. Ports that are bound to a part select of a Verilog wire are only available for reading, not for writing. Thus, combining a part select hdl_path() with port attributes such as verilog_wire(), driver(), and driver_delay() is not supported. A possible workaround is to bind to a part select of a register that is attached to the wire, rather than to the wire itself. In addition, you cannot force or release a port that is bound to a part select. If you add, remove, or change the hdl_path() of a port that is bound to a part select, you must regenerate the Verilog stub le.
If you add or change the bind attribute for an external port, you must rewrite the stubs le. See Also Mapping e Ports and Units to SystemC Objects on page 5-29 in the Specman Elite Integrators Guide
6-21
e Ports
Querying the State of Port Bindings
6.2.7
You can query the state of port bindings interactively at the cmd-prompt > prompt or procedurally using the following:
bind() get_bound_set() is_connected() print port show ports -full trace bind
Using bind() in Queries on page 6-22 Using get_bound_set() in Queries on page 6-23 Using is_connected() in Queries on page 6-23 Using Commands to Query Port Bindings on page 6-23
6.2.7.1
Using bind() in Queries
The bind() routine can be called in procedural code or interactively from the vrst-tool > prompt with the print command. It returns TRUE if the two ports are bound directly or if they are part of the same bound set. For example:
connect_ports() is also { if (!bind(p, q)) then { do_bind(p, q); }; };
You can also call bind() with empty, undened and external. For external, bind() returns TRUE only if the specied port is bound to external, not if it is in a bound set that also has external connections. For example:
connect_ports() is also { do_bind(p, q); do_bind(q, external); print bind(p, external); --prints FALSE print bind(q, external); --prints TRUE };
6-22
e Ports
See Also bind() on page 6-66 connect_ports() on page 6-72 do_bind() on page 6-75
6.2.7.2
Using get_bound_set() in Queries
You can use get_bound_set() to return a list of all ports bound directly or indirectly to a specied port. If the port is disconnected, get_bound_set() returns only the port itself. For example:
cmd-prompt> print p.get_bound_set()
See Also get_bound_set() on page 6-84
6.2.7.3
Using is_connected() in Queries
You can use is_connected() to determine whether a port is connected or not.

cmd-prompt> print p.is_connected()
See Also is_connected() on page 6-85
6.2.7.4
Using Commands to Query Port Bindings
The show ports command displays the ports bound to a port

cmd-prompt> show ports -full rx.trans
The trace bind command prints the state of the binding after declarative binding is complete and then prints out the steps in the procedural binding process.
cmd-prompt> trace bind
See Also show ports on page 6-181

6-23
e Ports
Using Simple Ports
trace bind on page 6-185
6.3
Using Simple Ports
You can use simple ports to transfer one data element at a time to or from either an external simulated object, such as a Verilog register, a VHDL signal or a SystemC method, or an internal object (another e unit). A simple ports direction can be either input, output or inout. Internal simple ports can transfer data elements of any type. External ports can transfer scalar types and lists of scalar types, including MVL data elements. Currently there is no support for passing structs or lists of struct through external simple ports. You can also use simple ports in @sim expressions, as an alternative to using event ports. You can read or write port values using the $ port access operator. To access multi-value logic (MVL) on simple ports, you can either declare a ports data element to be mvl or list of mvl, or you can use the MVL methods. You can set default values for a simple port or a bound set of simple ports using the set_default_value() or set_default_mvl_value() methods. For both internal and external ports, you can use the delayed() attribute to control whether new values are propagated immediately or at the next Specman tick. An external simple port must have an hdl_path() attribute to specify the name of the object that it is connected to. In addition, an external simple port can have several additional attributes that enable continuous driving of external signals. See Port Attributes on page 6-135 for more information on attributes for simple ports.
See Also Accessing Simple Ports and Their Values on page 6-25 Multi-Value Logic (MVL) on Simple Ports on page 6-27 @sim Temporal Expressions with External Simple Ports on page 6-29 An Internal Simple Ports Example on page 6-30 An External Simple Ports Example on page 6-31 simple_port on page 6-49 any_simple_port on page 6-51 Simple Port Default Value Methods on page 6-131
6-24
e Ports
Accessing Simple Ports and Their Values
Accessing SystemC Objects with e Simple Ports on page 5-33 in the Specman Elite Integrators
Guide
6.3.1
Ports are containers, and the values they hold are separate entities from the port itself. The $ access operator distinguishes port value expressions from port reference expressions. The $ access operator, for example p$, is used to access or update the value held in a simple port p. When used on the right-hand side, p$ refers to the ports value. On the left-hand side of an assignment, p$ refers to the values location, so an assignment to p$ changes the value held in the port. Without the $ operator an expression of any type port refers to the port itself, not to its value. In particular, an expression without the $ operator can be used for operations involving port references. Note You cannot apply the $ access operator to an item of abstract type, such as any_simple_port. This type does not have any access methods. The expression port_arg$ == 0 in the following code causes a syntax error.
foo_tcm ( port_arg : any_simple_port )@clk is { if ( port_arg$ == 0) then { -- syntax error out (sys.time, " Testing port logic comparison."); }; };
Examples of Accessing Port Values

print p$;
Prints the value of a simple port, p. Note Compare with print p, which prints information about port p.
p$ = 0;
Assigns the value 0 to a simple port, p. Note Compare with pref = NULL, which modies a port reference so that it does not point to any port instance.
force p$ = 0; print q$[1:0]; print q$[2:2]; print sys.pp$;
Forces a simple external port to 0. Prints the two least-signicant bits of the value of q. Prints the third least-signicant bit of the value of q. Prints the value of port sys.pp.
6-25
e Ports
print sys.plist[0]$; Prints the value of port plist[0] from a list of ports, plist. print blist$[0..1];
Prints the rst two elements of a list value. blist is dened as:
blist: in simple_port of list of bit is instance;
print listbl[0]$[1]; Prints the second bit in a list value of the rst element in a list of ports.
Could be written (listbl[0])$[1]. listbl is dened as:

listbl: list of in simple_port of list of bit is instance;
Note The list slicing operator [..], the list indexing operator [], and the eld access operator are not supported for ports in LHS expressions. In other words, p$[l..h], p$[i], and my_unit.p$ are not supported on the LHS of an assignment operator.
Examples of Accessing a Port

print p;
Prints the information about port p. Port p is dened as:

p: simple_port of int (bits:8) is instance;
// p = 5; keep q == p;
An error, as it is an attempt to assign incompatible types. q refers to the port instance p. Port reference q is dened as:
!q: simple_port of int (bits:8);
r = q;
Port reference r refers to the port instance p too. It is dened as:

var r: any_simple_port;
keep plist.size() == 3;
plist is dened as:

plist: list of in simple_port of int (bits:8) is instance;
keep plist[0] == p; keep plist[1] == p2;
plist[0] refers to the port instance p. plist[1] refers to the port instance p2. p2 is dened as:
p2: simple_port of int (bits:8) is instance;
keep plist[2] == q;
plist[2] refers to the port instance p (because of q).
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27
6-26
e Ports
Multi-Value Logic (MVL) on Simple Ports
Simple Port Access Operators on page 6-93
6.3.2
There are two ways to read and write multi-value logic on simple ports:
Dene numeric ports (uint, int, and so on) and use the predened MVL methods described in Simple
Port MVL Access Methods on page 6-111 to read and write values to the port.
Dene ports of type mvl or list of mvl and use the $ access operator, use the predened MVL methods,
or use a combination of both to read and write values to the port. Ports of type mvl or list of mvl (MVL ports) allow easy transformation between exact e values and multi-value logic, which is useful for communicating with objects that sometimes model bit values other than 0 or 1 during a test. Otherwise, using numeric ports is preferable, since numeric ports allow keeping the port values in a bit-by-bit representation, while MVL ports require having an e list for a multi-value logic vector. The enumerated type mvl is dened as: type mvl: [MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, MVL_N] An MVL literal, which is a literal of type list of mvl, provides a more convenient syntax for assigning MVL values. The syntax of an MVL literal is as follows:
<width-number>'(b|o|h)<value-number>
The width number is an unsigned decimal integer specifying the size of the list. The value number is any sequence of digits that are legal for the base, plus x, z, u, l, h, w, n. Notes
You will get a syntax error if you use the Verilog comparison operators (=== or !==) with either
numeric ports or MVL ports. These operators can be used only with the tick access syntax.
Not all supported simulators need all the potential MVL values. All nine values are supported only
for VHDL simulations. For Verilog simulations, only four values (MVL_Z, MVL_X, MVL_0, MVL_1) are supported.
Example 1
Numeric Port
This example shows how tick access notation translates to MVL methods, assuming the following numeric port declaration:
ready: out simple_port of byte is instance; keep bind (ready, external); data: inout simple_port of int is instance;
6-27
e Ports
keep bind (data, external); keep data.hdl_path() == "data"; d: int;
d = 'data'; 'ready' = 8'bz; 'data' = 32'bz;
d = data$; ready.put_mvl_list({MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z;}); data.put_mvl_list(32'bz);
check that 'data@x' == check that data.get_mvl_list().has(it == MVL_X) == 0; FALSE; check that data.has_x() == FALSE; d = 'data[31:10]@z'; d = mvl_to_int(data.get_mvl_list(), {MVL_Z})[31:0];
Example 2
MVL Port
This example shows how tick access notation translates to use of an MVL port, assuming the following MVL port declaration:
data: inout simple_port of list of mvl is instance; keep bind (data, external); keep data.hdl_path() == "data";
check that 'data@x' == 0; check that data$.has(it == MVL_X} == FALSE; check that data.has_x() == FALSE; 'data' = 32'bz; data$ = 32'bz;
Example 3
Checking Numeric Ports for MVL Values
If you have several ports that pass numeric data elements of different sizes, you might want to create a generic method that checks these ports for MVL values such as MVL_X or MVL_Z. For example, you can create a generic method for the following ports:
byte_port: in simple_port of byte is instance; uint_port: in simple_port of uint is instance;
The correct way to create a generic method is to pass the port value, not the port itself, to the method. You must convert the port value to the desired type before passing it. For example:
x_chk(m: list of mvl) is inline { check that m.has(it == MVL_X) == FALSE else dut_error("Bus has value of X!");
6-28
e Ports
@sim Temporal Expressions with External Simple Ports
}; run() is also { x_chk(byte_port.get_mvl_list()); x_chk(uint_port.get_mvl_list()); };
See Also Simple Port MVL Access Methods on page 6-111 Global MVL Conversion Routines on page 6-171
6.3.3
@sim Temporal Expressions with External Simple Ports
When you specify an event port, you cause Specman to be sensitive to the corresponding HDL signal during the entire simulation session. This might result in some unnecessary runtime performance cost if you need Specman to be sensitive only in certain scenarios. In such cases you can use an external simple port in temporal expressions with @sim, using the following syntax: [change|rise|fall](simple-port$)@sim; Note Trying to apply the @sim operator to a bound internal port causes an error when the corresponding temporal expression is evaluated, which occurs at runtime.
Examples
You can use this syntax in wait actions. For example:
transaction_complete: in simple_port of bit is instance; keep bind(transaction_complete, external); write_transaction(data: list of byte) @clk$ is { ... data_port$ = data; wait rise(transaction_complete$)@sim; };
This syntax might be also useful if you are interested in accessing a value of a signal, in addition to knowing if it changed. For example:
counter: in simple_port of uint is instance; keep bind(counter, external); event counter_change is change(counter$)@sim; on counter_change {
6-29
e Ports
An Internal Simple Ports Example
if (counter$ >= 255) {out("Counter is full")}; };
Here is a complete example.

unit collector { pclk1: in simple_port of bit is instance; dataport: in simple_port of byte is instance; read_packet(pclk: in simple_port of bit) @sys.any is { var p: packet = new; var len := dataport$; for j from 0 to len - 1 { wait fall(pclk$)@sim; p.data.add(dataport$); }; sys.packets.add(p); }; run() is also { start read_packet(pclk1); }; };
See Also simple_port on page 6-49
6.3.4
An Internal Simple Ports Example
This example shows two units communicating through simple ports, with no external ports.
unit u1 { p1: in simple_port of int(bits:64) is instance; // Define a simple port doit()@sys.any is { for i from 1 to 10 do { wait cycle; print p1$; // Do a get from the port wait cycle; }; stop_run(); }; run() is also { start doit(); }; };
6-30
e Ports
An External Simple Ports Example
unit u2 { p2: out simple_port of int(bits:64) is instance; // Define another simple port doit()@sys.any is { var v: int(bits:64); while TRUE { gen v; p2$ = v; wait cycle; wait cycle; }; }; run() is also { start doit(); }; }; extend sys { u1: u1 is instance; u2: u2 is instance; keep bind(u1.p1, u2.p2); // Bind the two ports };
6.3.5
The following e code describes a testbench component that drives data into an encoder and checks the output of the encoder for errors. In this example the clk, data_length, data, address and rq ports are external ports associated with various Verilog signals. The name of the simulator is established by the pre-run generation constraint on Line 67 (keep e.agent() == verilog). You can re-direct the access to another simulator (and possibly, to another modeling language) by changing this constraint. Verilog objects associated with the external ports are registers (clk, temp_address, data_width) and nets (data). On the Specman side, each ports behavior corresponds to its specied typeevent port, simple port, or buffer port. The event port clk, in Line 3, is used to synchronize Specman with the simulator. Port rq, in Line 21, illustrates the declaration of a buffer port. The other ports read and write the specied Verilog objects directly. The postx $ access operator, for example clk$ or data$ in Line 29 and Line 32, is used to access the event associated with an event port or to read or write to a simple port. Access to a buffer port, on the other hand, is performed using the predened methods for buffer ports, get() and put(), as shown in Line 42.
1 2 3 unit encoder { clk: in event_port is instance;
6-31
e Ports
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
keep bind(clk, external); keep clk.hdl_path() == "clk"; data_length: in simple_port of uint is instance; keep bind(data_length, external); keep data_length.hdl_path() == "data_width"; data: inout simple_port of list of bit is instance; keep bind(data, external); keep data.hdl_path() == "data"; keep data.verilog_wire() == TRUE; -- simple port attribute keep data.declared_range() == "[31:0]"; -- simple port attribute address: in simple_port of uint is instance; keep bind(address, external); keep address.hdl_path() == "PRIO/temp_address"; rq: in keep keep keep buffer_port of bool is instance; bind(rq, external); rq.buffer_size() == 8; -- buffer port attribute rq.hdl_path() == "rq";
data_list: list of bit; keep data_list.size() < 32; inject()@clk$ is { for j from 0 to 15 { gen data_list; data$ = data_list; wait cycle; }; stop_run(); }; checker() @clk$ is { while TRUE { wait cycle; if not rq.get() { check that address$ == 0; check that data$.has(it != 0)== FALSE; } else { check that address$ != 0; var mask: uint = 0x10000000; for {var i: byte = data_length$ - 1; i>0; i -= 1} { if (data$[31:0] & mask) != 0 { check that address$ == i;
6-32
e Ports
Using Buffer Ports
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
break; }; mask >>= 1; }; }; }; }; run() is also { start inject(); start checker(); }; }; extend sys { e: encoder is instance; keep e.hdl_path() == "~/priority_encoder"; keep e.agent() == "verilog"; };
6.4
Using Buffer Ports
You can use buffer ports to insert data elements into a queue or extract elements from a queue. Data is inserted and extracted from the queue in FIFO order. When the queue is full, write access to the port is blocked. When the queue is empty, read access to the port is blocked. The queue size is xed during generation by the buffer_size() attribute and cannot be changed at runtime. The queue size may be set to 0 for rendezvous ports. A buffer ports direction can be either input or output. Inout is not supported. Internal buffer ports can transfer data elements of any type. Currently the Cadence adapters do not support external buffer ports. You can read or write port values using the buffer ports predened get() and put() methods. These methods are time-consuming methods (TCMs). Use of the $ port access operator with buffer ports is not supported. For buffer ports, you can use the delayed() attribute to control whether new values are propagated immediately or at the next Specman tick. The pass_by_pointer() attribute controls how data elements of composite type are passed. See Port Attributes on page 6-135 for more information on these attributes.
See Also Rendezvous-Zero Size Buffer Queue on page 6-34 An Internal Buffer Ports Example on page 6-34
6-33
e Ports
Rendezvous-Zero Size Buffer Queue
buffer_port on page 6-53 any_buffer_port on page 6-55 Buffer Port Access Methods on page 6-106
6.4.1
Rendezvous-Zero Size Buffer Queue
In rendezvous-style handshaking protocol, access to a port is blocked after each put() until a subsequent get() is performed, and access is blocked after each get() until a subsequent put() is performed. This style of communication is easily achieved by using buffer ports with a data queue size of 0. The following example shows how this is done.
Example
unit consumer { in_p: in buffer_port of atm_cell is instance; }; unit producer { out_p: out buffer_port of atm_cell is instance; }; extend sys { consumer: consumer is instance; producer: producer is instance; keep bind(producer.out_p, consumer.in_p); keep producer.out_p.buffer_size() == 0; };
See Also buffer_port on page 6-53
6.4.2
An Internal Buffer Ports Example
This example shows two units communicating through buffer ports, with no external ports.
unit producer { p: out buffer_port of atm_cell is instance; producer()@sys.any is { var cell: atm_cell; for i from 1 to 100 do { gen cell;
6-34
e Ports
Using Event Ports
p.put(cell) }; stop_run();
// Waits if the buffer is full
}; }; unit consumer { p: in buffer_port of atm_cell is instance; consumer()@sys.any is { while (TRUE) do { var cell: atm_cell; cell = p.get(); // Waits if the buffer is empty // Inject the cell into the DUT }; }; }; extend sys { consumer: consumer is instance; producer: producer is instance; keep bind(producer.p, consumer.p); keep producer.p.buffer_size() == 10; };
6.5
Using Event Ports
You can use event ports to transfer events between two e units or between an e unit and an external object. An internal event ports direction can be either input, output or inout. Note Currently external out and inout event ports are supported only by the Cadence SystemC adapter. You can read or write port values using the $ port access operator. An external event port must have an hdl_path() attribute to specify the name of the object that it is connected to. The edge() attribute for an external input event port species the edge on which an event is generated.
unit u { ext_ep: in event_port is instance; keep bind(ext_ep,external); keep ext_ep.hdl_path() == "transaction_done"; keep ext_ep.edge() == MVL_0_to_1; }; extend sys { u: u is instance; keep u.hdl_path() == "top_s"; };
6-35
e Ports
Accessing Event Ports
See Also Accessing Event Ports on page 6-36 event_port on page 6-57 any_event_port on page 6-60 edge() on page 6-149 hdl_path() Port Attribute on page 6-154 Synchronizing Specman Elite and SystemC with e Event Ports on page 5-39 in the Specman Elite
Integrators Guide
6.5.1
Accessing Event Ports
The $ access operator is used to access the event associated with an event port. An expression of type event_port without the $ operator refers to the port itself and not to its event.
Example 1
emit me.ep$; monitor()@ep$ is { ... }; wait @lep[0]$; event ep1 is @ep$; wait cycle @ep$; expect @a => { ... }@ep$;
Example 2
This example shows how to connect event ports, using declarative bind, and how to use the $ operator to access event ports in event contexts.
unit u1 { in_ep: in event_port is instance; tcm1()@in_ep$ is { // ... }; }; unit u2 { out_ep: out event_port is instance; event clk is @sys.any; counter: uint; on clk { counter = counter + 1;
6-36
e Ports
Using Method Ports
if counter %10 == 0 { emit out_ep$ }; }; }; extend sys { u1: u1 is instance; u2: u2 is instance; keep bind(u1.in_ep,u2.out_ep); };
See Also Event Port Access Operators on page 6-103
6.6
Using Method Ports
Method ports let you call regular or time-consuming methods dened in other e units or written in foreign programming languages. The advantages of method ports are:
You can implement a transaction-level interface between Specman and a high-level model described
in a foreign language.
You can postpone the decision about which method to call (an e method or a foreign function, for
example) from compile time to pre-run generation. Note Currently, method ports can only be used with internal (e2e) ports or with SystemC. They cannot be used with HDL simulators.
Figure 6-1 shows an e Bus Functional Model (BFM) that calls a write method in the e client, passing to
that method some generated input data. The client manipulates the data and then passes back the modied data by calling a check method in the BFM. Figure 6-1 Internal Method Port Interface
e BFM e Client
write$(burst)
check$(burst)
6-37
e Ports
Using Method Ports
Figure 6-2 shows an e BFM that calls a write function in a foreign agent, passing to that method some
generated input data. The foreign agent manipulates the data and then passes back the modied data by calling a read method in the BFM. Figure 6-2 External Transaction Level Interface
e BFM write$(burst) Foreign Agent
read$(burst)
Figure 6-3 shows a variation of the above example, where the foreign agent emits an event, in this case
an event port called notify. This causes the e BFM to call a read function in the foreign agent, which returns the manipulated data. Figure 6-3 External Transaction Level Interface Using an Event Port
e BFM write$(burst) emit notify$ read$():burst Foreign Agent
Using Method Ports Overview on page 6-39 Method Ports Examples on page 6-42 Method Types on page 6-44 Input Method Ports on page 6-45 Output Method Ports on page 6-46 Invoking Method Ports on page 6-46 Method Port Bindings on page 6-48
6-38
e Ports
Using Method Ports Overview
See Also Accessing Functions and Methods with e Method Ports on page 5-42 in the Specman Elite
Integrators Guide
6.6.1
1.
To implement an internal method port interface: Dene a method type that matches the prototype of the associated method. The method type species the semantics of the method port, for example:
method_type burst_method_t (b: burst)@sys.any;
2.
Specify an output method port instance in the e unit that makes the call, for example:
write: out method_port of burst_method_t is instance;
e BFM write: out method_port of burst_method_t is instance;
write$(burst)
e Client
3.
Specify an input method port instance in the enclosing unit of the method to be called, for example:
write_scoreboard: in method_port of burst_method_t is instance;
Because the input port instance is associated with the actual method by name, the names must match exactly.
6-39
e Ports
e BFM write: out method_port of burst_method_t is instance; write$(burst)
e Client write_scoreboard: in method_port of burst_method_t is instance; write_scoreboard(data:burst) @clk is {};
4.
Bind the method ports, for example:

keep bind(e_bfm.write, e_client.write_scoreboard);
5.
Invoke the method by applying the $() operator to the output method port, for example;
write$(b);
Notes
You can call only the output port, not the input port. You can bind internal ports only if they are the same method type.
To call a function in a foreign agent from e: 1. Dene a method type that matches the foreign function prototype. The method type species the semantics of the method port, for example:
2.
Create an output method port instance in the e unit that makes the call, for example:
write: out method_port of burst_method_t is instance;
e BFM write: out method_port of burst_method_t is instance;
write$(burst)
Foreign Agent
6-40
e Ports
3.
Bind the method port, for example:

keep bind(e_bfm.write, external);
4.
Specify the corresponding path in the foreign model (hdl_path()) and other language-specic attributes such as hdl_convertor(). See Generic Port Attributes on page 6-137 for more information.
5.
Invoke the method by applying the $() operator to the output method port, for example;
write$(b);
To call an e method from a foreign agent: 1. Dene a method type that matches the e method prototype. The method type species the semantics of the method port, for example:
2.
Specify an input method port instance in the e unit that contains the method to be called, for example:
read: in method_port of burst_method_t is instance;
Because the input port instance is associated with the actual method by name, the names must match exactly.
e BFM read: in method_port of burst_method_t is instance; read(data:burst)@clk is {}; read$(burst)
Foreign Agent
3.
Bind the method ports, for example:

keep bind(e_bfm.read, external);
4.
Specify the corresponding path in the foreign model (hdl_path()) and other language-specic attributes such as hdl_convertor() and sync_mode(). See Generic Port Attributes on page 6-137 for more information.
6-41
e Ports
Method Ports Examples
6.6.2
The examples in this section show how to connect a monitor to a scoreboard using method ports. The rst example shows how to connect one monitor and one scoreboard. The second example shows how to connect the monitor to several scoreboards (broadcasting), using multiple binding. These examples are described in the following sections:
Connecting a Monitor and One Scoreboard on page 6-42 Connecting a Monitor to Multiple Scoreboards (Broadcasting) on page 6-43 See Also Method Port Examples on page 5-43 in the Specman Elite Integrators Guide for examples of using
method ports with SystemC.
Creating and Using Port Bindings on page 6-11
6.6.2.1
Connecting a Monitor and One Scoreboard
<' method_type hookup_method_t (data: uint); unit monitor { send: out method_port of hookup_method_t is instance; run() is also { start ver(); }; ver()@sys.any is { for i from 1 to 3 { // generates and sends data var data : uint; gen data; send$(data); wait cycle; }; wait[1]; stop_run(); }; };
unit scoreboard { add_scoreboard: in method_port of hookup_method_t is instance; add_scoreboard(data :uint) is { out("[scoreboard ",e_path(),"] ",sys.time," : ",data); };
6-42
e Ports
}; extend sys { my_monitor: monitor is instance; sb : scoreboard is instance; keep bind(my_monitor.send,sb.add_scoreboard); }; '>
Output:
[scoreboard sys.sb] 0 : 1025553357 [scoreboard sys.sb] 1 : 1779848724 [scoreboard sys.sb] 2 : 1089920023
6.6.2.2
Connecting a Monitor to Multiple Scoreboards (Broadcasting)
The following example uses multiple binding to extend the example in Connecting a Monitor and One Scoreboard on page 6-42. The extension show below connects the out method port of the monitor to all the input method ports to create broadcasting. The do_bind() method used here is described in do_bind() on page 6-75.
extend sys { my_monitor: monitor is instance; sb_list[3] : list of scoreboard is instance; // instead of one scoreboard, // connect the single monitor to three socreboards // using multiple binding connect_ports() is { for each in sb_list { do_bind(my_monitor.send , it.add_scoreboard); }; }; };
Output:
[scoreboard [scoreboard [scoreboard [scoreboard [scoreboard [scoreboard [scoreboard [scoreboard [scoreboard sys.sb_list[0]] sys.sb_list[1]] sys.sb_list[2]] sys.sb_list[0]] sys.sb_list[1]] sys.sb_list[2]] sys.sb_list[0]] sys.sb_list[1]] sys.sb_list[2]] 0 0 0 1 1 1 2 2 2 : : : : : : : : : 1025553357 1025553357 1025553357 1779848724 1779848724 1779848724 1089920023 1089920023 1089920023
6-43
e Ports
Method Types
6.6.3
Method Types
A method port must be parameterized by a type of a special kinda method type. The method type species the prototype (signature) of the method. For example, the following declares a method type for a method that accepts two integer arguments and returns an integer:
method_type adder_method_t (arg1: int, arg2: int): int;
A method type that is associated with a TCM must be dened with the @sys.any sampling event, for example:
method_type send_packet_method_t (p : packet)@sys.any;
Method types must be dened with a unique name, and this name must be explicitly specied in the instance declaration of the method port. For example, the following associates the add method port with the adder_method_t method type:
add: out method_port of adder_method_t is instance;
Parameter mapping in e is positional, so the names of the formal parameters do not have to match the actual parameter list. However, it is recommended to use meaningful formal parameter names to improve the readability of the code. Note The method type has semantic implications for the port beyond the simple matching of parameters and result types. The method type is also used to clarify runtime messages related to a particular method port. Thus, you cannot bind two method ports just because they have the same signature; they must also be associated with the same method type.
Example
method_type adder_method_t (arg1: int, arg2: int): int; method_type subtractor_method_t (arg1: int, arg2: int): int; unit calculator { add(arg1: int, arg2: int): int is { result = arg1 + arg2; }; add: in method_port of adder_method_t is instance; }; extend sys { calculator1: calculator is instance; calculator2: calculator is instance; op1: out method_port of adder_method_t is instance; op2: out method_port of subtractor_method_t is instance; keep bind(op1, calculator1.add); -- OK keep bind(op2, calculator2.add); -- ERROR: method types are different };
6-44
e Ports
Input Method Ports
The method port op2, which is associated with the subtractor_method_t method type, cannot be bound to port calculator.add, even though both methods receive two integer parameters and return an integer result. This similarity is not enough to make them compatible; they must have the same method type.
See Also method_type method-type-name on page 6-63
6.6.4
Input Method Ports
An input method port declares an e method as callable from another e unit or from a foreign agent. The method port instance:
Must reside in the same unit as its associated method Must have an instance name that matches the name of the associated method Must have a method type that matches the prototype of the associated method
The method prototype and the method type match if:
They have the same number of parameters. Parameter types, if any, are literally equivalent. Return value, if any, is of the same type. For TCMs, the method type declaration must include the @sys.any sampling event.
Notes
Inline methods cannot be associated with method ports. Input method ports can be externally bound. The only adapters that support external input method
ports currently are the SystemC adapters (OSCI and NC SystemC).
Example
method_type write_transaction_method_t (t: xyz_transaction): bool; method_type report_transaction_method_t (t: xyz_transaction); unit xyz_server { scoreboard(t: xyz_transaction) is { ... }; }; ... extend xyz_server {
6-45
e Ports
Output Method Ports
scoreboard: in method_port of report_transaction_method_t is instance; };
See Also method_port on page 6-62 Using Input Method Ports on page 5-45 in the Specman Elite Integrators Guide for information
related to SystemC
6.6.5
Output Method Ports
Output method ports let you call regular or time-consuming methods dened in other e units or written in foreign programming languages.
Example
unit xyz_client { write: out method_port of write_transaction_method_t is instance; keep bind(write, external); -- external binding keep write.hdl_path() == "transactor"; keep write.hdl_convertor() == "(transaction: TRCONV)"; mark: out method_port of report_transaction_method_t is instance; }; extend sys { client: xyz_client is instance; keep client.hdl_path() == "~/ip"; keep client.agent() == "systemc"; server: xyz_server is instance; keep bind(client.mark, server.scoreboard); -- internal binding };
See Also method_port on page 6-62 Using Output Method Ports on page 5-43 in the Specman Elite Integrators Guide for information
related to SystemC
6.6.6
Invoking Method Ports
You must use the $(param-list) access operator in order to call the method port.
6-46
e Ports
Invoking Method Ports
The rules for parameter type checking, time-consuming method call requirements, and so on are the same as those for invoking an e method directly. In particular, TCM method ports can only be called from inside a TCM scope. For input TCM method ports, you cannot activate the same instance of a port multiple times in parallel. The same restriction applies for output TCM method ports. A runtime error is issued if your code attempts to invoke an input TCM method port before the previous call has completed. (If the input TCM method port is an external port, then the error message is issued by the simulator adapter.) The parameter passing semantics are the same as in direct calls to e methods. Scalar parameters are passed by value, while composite parameters (struct or list types) are passed by pointer. Notes
Do not rely on the ability to modify separate elds or list elements of the incoming parameter in the
actual method. In particular, this ability cannot be supported for external method ports. The return value (or explicit passing of parameters by reference) must be used instead.
All ports are elaborated after the end of post_generate(). Thus, you cannot invoke method ports either
before generation or from constraints.
Calling an empty-bound method port is equivalent to calling an empty e method. Example

extend xyz_client { clock: in event_port is instance; keep bind(clock, external); keep clock.hdl_path() == "clock"; tr_list[17]: list of xyz_transaction; verify() @clock$ is { for each in tr_list { if write$(it) == TRUE { mark$(it); }; }; }; };
See Also method_port$() on page 6-104
6-47
e Ports
Method Port Bindings
6.6.7
Method Port Bindings
In general, when you bind two output ports and three input ports, all ports are connected, no matter how the binding pairs were specied, and a change on either output port affects both inputs. This makes sense for simple ports, which are used to emulate wires. However, for method ports this behavior can have unintended side effects. For example, if there are two output method ports, Ao and Bo, and three input method ports, Ai, Bi, and ABi and the binding looks like:
bind(Ao,Ai); bind(Bo,Bi); bind(Ao,ABi); bind(Bo,ABi);
the intention probably is that a call to Ao causes a call of Ai and ABi, while a call to Bo causes a call of Bi and ABi. This intention is implemented; however, a call to Ao also causes a call of Bi, and a call to Bo also causes a call of Ai. To bind multiple output ports to a common input, you can dene the common input as a list of in method ports. When a list of input method ports is dened, each of the input method ports is associated with the method with the list name.
type src_t : [ A, B ]; method_type p_t (s: src_t); extend sys { Ao : out method_port of p_t is instance; Bo : out method_port of p_t is instance; ABi : list of in method_port of p_t is instance; keep ABi.size() == 2; ABi(src: src_t) is { out("AB(", src, ")") };
And the binding is:

// each output also invokes the common input keep bind(Ao, ABi[0]); keep bind(Bo, ABi[1]); run() is also { Ao$(A); Bo$(B); }; };
6-48
e Ports
Dening and Referencing Ports
6.7
Defining and Referencing Ports
This section covers the following topics:
simple_port on page 6-49 any_simple_port on page 6-51 buffer_port on page 6-53 any_buffer_port on page 6-55 event_port on page 6-57 any_event_port on page 6-60 method_port on page 6-62 method_type method-type-name on page 6-63 any_method_port on page 6-64
6.7.1
Purpose
simple_port
Access other port instances or external simulated objects directly
Category
Unit member
Syntax
port-instance-name: [list of] [direction] simple_port of element-type is instance; Syntax Example
data: in simple_port of byte is instance;
Parameters
port-instance-name A unique identier you can use to refer to the port or access its value.
6-49
e Ports
simple_port
direction
One of in, out, or inout. The default is inout, which means that you can read values from and write values to this port. For an in port, you can only read values from the port, and for an out port you can only write values to the port. Any predened or user-dened e type except a port type or a unit type.
element-type
Description
You can use simple ports to transfer one data element at a time to or from either an external simulated object or an internal object (another e unit). Internal simple ports can transfer data elements of any type. External ports can transfer scalar types and lists of scalar types, including MVL data elements. Currently there is no support for passing structs or lists of struct through external simple ports. The port can be congured to access a different signal simply by changing the binding; all the code that reads or writes to the port remains the same. Similarly, port semantics remain the same, regardless of what simulator is used. Binding is xed during generation. A simple ports direction can be either input, output, or inout. The direction specier in a simple port is not a when subtype determinant. This means, for example, that the following type:
data: simple_port of byte is instance;
is not the base type of:

data: out simple_port of byte is instance;
Furthermore, the following types are fully equivalent:

data: simple_port of byte is instance; data: inout simple_port of byte is instance;
Thus, the following constraint is an error because the two types are not equivalent:
data: out simple_port of byte is instance; !data_ref: simple_port of byte; // means inout simple_port of byte keep data_ref == data; // error
Notes
Simple ports whose element type is dened as int(bits: *)that is, simple ports of type innite
integerare not supported by any simulator adapter provided by Cadence.
Passing structs of lists of structs through external simple ports is not supported by any simulator
adapter provided by Cadence.
6-50
e Ports
any_simple_port
Example
<' unit encoder { data: out simple_port of int(bits:64) is instance; keep bind(data, external); keep data.hdl_path() == "data"; drive()@sys.any is { var v: int(bits:64); while TRUE { gen v; data$ = v; wait cycle; wait cycle; }; }; run() is also { start drive(); }; }; '>
See Also Using Simple Ports on page 6-24 any_simple_port on page 6-51 Simple Port MVL Access Methods on page 6-111 Global MVL Conversion Routines on page 6-171
6.7.2
Purpose
any_simple_port
Reference a simple port instance
Category
Unit eld, variable or method parameter
6-51
e Ports
any_simple_port
Syntax
[! | var] port-reference-name: [direction] simple_port of element-type [! | var] port-reference-name: any_simple_port Syntax Example
!last_printed_port: any_simple_port; !in_int_simple_port_ref: in simple_port of int;
Parameters
port-reference-name direction element-type A unique identier. One of in, out, or inout The data element that can be passed through this port.
Description
Simple port instances may be referenced by a eld, a variable, or a method parameter of the same port type or of the abstract type any_simple_port. Abstract port types reference only the port kind, not the port direction or data element. Thus, a method parameter of type any_simple_port accepts all simple ports, including, for example:
data_length: in simple_port of uint is instance; data: inout simple_port of list of bit is instance;
If a port reference is a eld, then it must be marked as non-generated or it must be constrained to an existing port instance. Otherwise, a generation error results. Port binding is allowed only for port instance elds, not for port reference elds.
Notes You cannot apply the $ access operator to an item of type any_simple_port. Abstract types do not
have any access methods. For example, the expression port_arg$ == 0 in the following code causes a syntax error.
check_sig ( port_ref : any_simple_port )@clk is { if ( port_ref$ == MVL_U) then { -- syntax error out (sys.time, " Undefined sig"); }; };
6-52
e Ports
buffer_port
You cannot use the any_simple_port abstract type in a port instance. Example
To access the value of referenced port that is dened with an abstract type, you can rst cast the referenced port to a specic type, as shown below.
check_sig ( port_ref : any_simple_port ) is { if ( port_ref.as_a(in'direction simple_port of mvl)$ == MVL_U) then { out (sys.time, " Undefined sig"); }; };
See Also Using Simple Ports on page 6-24 simple_port on page 6-49
6.7.3
Purpose
buffer_port
Implement an abstraction of queues with blocking get and put
Category
Unit member
Syntax
port-instance-name: [list of] direction buffer_port of element-type is instance; Syntax Example
rq: in buffer_port of bool is instance;
Parameters
port-instance-name A unique identier you can use to refer to the port or access its value.
6-53
e Ports
buffer_port
direction
One of in or out. There is no default. For an in port, you can only read values from the port, and for an out port you can only write values to the port. See Buffer Port Access Methods on page 6-106 for information on how to read and write buffer ports. Any predened or user-dened e type except a unit or a port type.
element-type
Description
You can use buffer ports to insert data elements into a queue or extract elements from a queue. Data is inserted and extracted from the queue in FIFO order. When the queue is full, write access to the port is blocked. When the queue is empty, read access to the port is blocked. The queue size is xed during generation by the buffer_size() attribute and cannot be changed at runtime. The queue size may be set to 0 for rendezvous ports. You can read or write port values using the buffer ports predened get() and put() methods. These methods are time-consuming methods (TCMs). Use of the $ port access operator with buffer ports is not supported. A typical usage of a buffer port is in a producer and consumer protocol, where one object puts data on an output port at possibly irregular intervals, and another object with the corresponding input port reads the data at its own rate. Notes
External buffer ports are not supported by any simulator adapter provided by Cadence. Example
unit encoder { rq: in buffer_port of bool is instance; keep rq.buffer_size() == 8; -- buffer port attribute };
See Also Using Buffer Ports on page 6-33 Buffer Port Access Methods on page 6-106 any_buffer_port on page 6-55
6-54
e Ports
any_buffer_port
6.7.4
Purpose
any_buffer_port
Reference a buffer port instance
Category
Syntax
[! | var] port-reference-name: direction buffer_port of element-type [! | var] port-reference-name: any_buffer_port Syntax Example
!last_printed_port: any_buffer_port; !in_int_buffer_port_ref: in buffer_port of int;
Parameters
port-reference-name direction element-type A unique identier. One of in or out The data element that can be passed through this port.
Description
Buffer port instances may be referenced by a eld, a variable, or a method parameter of the same port type or of any_buffer_port. Abstract port types reference only the port kind, not the port direction or data element. Thus, a method parameter of type any_buffer_port accepts all buffer ports, including, for example:
data_length: in buffer_port of uint is instance; data: out buffer_port of list of bit is instance;
6-55
e Ports
any_buffer_port
Notes You cannot call the get() or put() methods of an item of type any_buffer_port. Abstract types do
not have any access methods. For example, the expression port_ref.get() in the following code causes a syntax error.
check_queues ( port_ref : any_buffer_port )@clk is { if ( port_ref.get() == 0) then { -- syntax error out (sys.time, "Problem with queues"); }; };
You cannot use an abstract type in a port instance. Example

The print_port() method in the following example can be called with any buffer port. The iterate() method shows an alternative way to print a list of ports.
unit u { plist: list of in buffer_port of int is instance; !last_printed_port: any_buffer_port; // A field, so must be // non-generated print_port(p: any_buffer_port) is { // A method parameter print p; // Prints the port's e path, agent name, and so on last_printed_port = p; }; iterate() is { for each in plist { var buffer_port_ref: any_buffer_port; buffer_port_ref = it; print_port(buffer_port_ref); }; }; };
See Also Using Buffer Ports on page 6-33 buffer_port on page 6-53
6-56
e Ports
event_port
6.7.5
Purpose
event_port
Transfer events between units or between simulators and units
Category
Unit member
Syntax
event-port-eld-name: [list of] [direction] event_port is instance; Syntax Example
clk: in event_port is instance;
Parameters
event-port-eld-name direction A unique identier you can use to refer to the port or access its value. One of in, out, or inout. The default is inout, which means that events can be both emitted and sampled on the port. For a port with direction in, events can only be sampled. For a port with direction out, events can only be emitted.
Description
You can use event ports to transfer events between two e units or between an e unit and an external object. The attribute hdl_path() must be specied for external event ports. The edge() attribute for an external input event port species the edge on which an event is generated. You can read or write port values using the $ port access operator. See Accessing Event Ports on page
6-36 for more information.
An internal event ports direction specier can be either input, output or inout. The direction specier is not a when subtype determinant. This means, for example, that the following type
clk: event_port is instance;
is not the base type of
6-57
e Ports
event_port
clk: out event_port is instance;
Furthermore, the following types are fully equivalent:

clk: event_port is instance; clk: inout event_port is instance;
Notes Currently, external out and inout event ports are not supported. The on struct member for event ports is not supported. Coverage on event ports is currently not supported. The echo event command is not supported for event ports. It is impossible to specify a temporal formula (like event_port is ) for denition of an out event
port. In order to use any of the above unsupported capabilities (except the rst in the list) it is possible to dene an additional event and connect it to the event port as follows:
ep: in event_port is instance; keep bind(ep,external); event e is @ep$;
Example 1
References to event ports are supported. In the following example, current_clk is an event port reference.
unit u { clks: list of in event_port is instance; events: list of out event_port is instance; }; extend u { !current_clk: in event_port; keep current_clk == clks[0]; };
Example 2
You can pass an event port as a parameter to a TCM. In this example, each event in a list of events is passed as a parameter to the drive() method.
6-58
e Ports
event_port
extend u { drive(ep: out event_port) @current_clk$ is { emit ep$; }; run() is also { for each in events do { start drive(it); }; }; };
Example 3
In the following example, an event is transferred to ext_ep when ~/top_s/transaction_done transitions from 0 to 1.
unit u { ext_ep: in event_port is instance; keep bind(ext_ep,external); keep ext_ep.hdl_path() == "transaction_done"; keep ext_ep.edge() == MVL_0_to_1; }; extend sys { u: u is instance; keep u.hdl_path() == "top_s"; };
Example 4
This example shows how to congure an event port to emit based either on an HDL signal change or on sys.any (if no simulator is attached).
<' extend sys { e_clock_port : out event_port is instance; on any { emit e_clock_port$; }; my_event_port: in event_port is instance; keep my_event_port.hdl_path() == "~/top/clk"; dut_connected: bool; keep dut_connected == FALSE => bind(my_event_port,e_clock_port);
6-59
e Ports
any_event_port
keep dut_connected == TRUE => bind(my_event_port,external); }; '>
See Also Using Event Ports on page 6-35 Event Port Access Operators on page 6-103 hdl_path() Port Attribute on page 6-154 edge() on page 6-149
6.7.6
Purpose
any_event_port
Reference an event port instance
Category
Syntax
[! | var] port-reference-name: [direction] event_port [! | var] port-reference-name: any_event_port Syntax Example
!curr_clk: any_event_port; !event_port_ref: out event_port;
Parameters
port-reference-name direction A unique identier. One of in, out, or inout
6-60
e Ports
any_event_port
Description
Event port instances may be referenced by a eld, a variable, or a method parameter of the same port type or of the abstract type any_event_port. Abstract port types reference only the port kind, not the port direction. Thus, a method parameter of type any_event_port accepts all event ports, including, for example:
hdl_clk: in event_port is instance; e_event: out event_port is instance;
Notes You cannot apply the $ access operator to an item of type any_event_port. Abstract types do not
have any access methods. For example, the expression port_ref$ == 0 in the following code causes a syntax error.
check_clks ( port_ref : any_event_port ) is { if ( port_ref$ == 0) then { -- syntax error out (sys.time, " Testing port logic comparison."); }; };
You cannot use an abstract type in a port instance Example

unit u { clks: list of in event_port is instance; events: list of out event_port is instance; }; extend u { !current_clk: in event_port; keep current_clk == clks[0]; };
See Also Using Event Ports on page 6-35 event_port on page 6-57
6-61
e Ports
method_port
6.7.7
Purpose
method_port
Enable invocation of abstract functions
Category
Unit member
Syntax
port-instance-name: [list of] direction method_port of method-type is instance; Syntax example:
convert_string: out method_port of str2uint_method_t is instance;
Parameters
port-instance-name A unique identier you can use to refer to the port or to invoke the actual method. Note For input method ports, this name must match the actual name of the associated method. direction One of in or out. There is no default.
For an output port, you can invoke the method. For an input port you can only specify the actual method to be activated.
method-type A method_type that species the port semantics.
Description
Implements an abstraction of calling methods (time-consuming or not) in other units or in external agents, while delaying the binding from compile time to pre-run generation time.
See Also Using Method Ports Overview on page 6-39
6-62
e Ports
method_type method-type-name
6.7.8
Purpose
method_type method-type-name
Dene method port semantics and enable notication
Category
Statement
Syntax
method_type method-type-name ([param-list]) [:return-type] [@sys.any]; Syntax example:
method_type str2uint_method_t (s: string):uint;
Parameters
method-type-name param-list return-type @sys.any A legal e name. The name must be different from any other predened type name or user type name. The parameter list must match the parameter list of the e method or external function. The type of the returned value must match the return type of the e method or external function. If the method type declaration includes the @sys.any sampling event, this type can only be used for method ports associated with a TCM.
Description
A method port must be parameterized by a method type, which species the prototype (signature) of the method. The method type name may also be included in runtime messages related to a specic method port. If you are using incremental compilation and a C le requires a method type that is neither declared or used in the e le you are compiling with sn_compile.sh, it may be necessary to explicitly export the method type using a C export statement.
6-63
e Ports
any_method_port
See Also Using Method Ports Overview on page 6-39 C export on page 11-54 in the Usage and Concepts Guide for e Testbenches
6.7.9
Purpose
any_method_port
Reference a method port instance
Category
Syntax
[! | var] port-reference-name: direction method_port of method-type [! | var] port-reference-name: any_method_port Syntax Example
!in_method_port_ref: in method_port of burst_method_t; !last_called_port: any_method_port;
Parameters
port-reference-name direction method-type A unique identier. One of in or out A method_type that species the port semantics.
Description
Method port instances may be referenced by a eld, a variable, or a method parameter of the same port type or of the abstract type any_method_port. Abstract port types reference only the port kind, not the port direction or method type. Thus, a method parameter of type any_method_port accepts all simple ports, including, for example:
inbox : out method_port of deliver_method_t is instance;
6-64
e Ports
any_method_port
inbox_int : in
method_port of subscribe_method_t is instance;
Notes You cannot apply the $()access operator to an item of type any_method_port. Abstract types do not
have any access methods. For example, the expression port_ref()$ == 0 in the following code causes a syntax error.
call_any_mports( port_ref : any_method_port )@clk is { if ( port_ref$() == 0) then { -- syntax error out (sys.time, " Method returns 0"); }; };
You cannot use an abstract type in a port instance. Example

In the following example, port references are used as parameter in the method publish().
method_type deliver_method_t (msg_id : string); unit publisher { deliver1 : out method_port of deliver_method_t is instance; deliver2 : out method_port of deliver_method_t is instance; verify()@sys.any is { publish(deliver1,first message); publish(deliver2,second message); }; publish(p:out method_port of deliver_method_t,msg : string) is { p$(msg); }; };
See Also Using Method Ports on page 6-37 Method Port Access Operators on page 6-104
6-65
e Ports
Dening and Disconnecting Port Bindings
6.8
Defining and Disconnecting Port Bindings
You can use the following methods and routines to dene, disconnect, and query port bindings and to set a default value for a bound set:
bind() on page 6-66 connect_pointers() on page 6-70 connect_ports() on page 6-72 check_generation() on page 6-74 do_bind() on page 6-75 do_bind_unit() on page 6-77 remap_hdl_path() on page 6-80 disconnect() on page 6-82 disconnect_bound_set() on page 6-83 get_bound_set() on page 6-84 is_connected() on page 6-85 The connect_pointers() Method of sys on page 6-86 The connect_ports() Method of sys on page 6-90 The check_generation() Method of sys on page 6-91
6.8.1
Purpose
bind()
Connect ports
Category
Predened routine
Syntax
keep bind(port-exp1, port-exp2) [== TRUE];
6-66
e Ports
bind()
keep bind(port-exp1, external) [== TRUE]; keep bind(port-exp1, empty | undened) [== TRUE]; Syntax Example
keep bind(bfm.data_in, driver.data_out);
Parameters
port-exp1, port-exp2 external empty undened One or two expressions of port type. If two expressions are given and the port types are compatible, the two port instances are connected. Denes a port as connected to a simulated object, such as a Verilog register, a VHDL signal, or a SystemC object, such as a method. Denes a disconnected port. Runtime accessing of a port with an empty binding is allowed. Denes a disconnected port. Runtime accessing of a port with an undened binding causes an error.
Description
You can use the bind() routine in a keep constraint to create a declarative binding that connects a port to another e port or to an external simulated object such as a Verilog register, a VHDL signal, or a SystemC method. Ports can also be dened explicitly as disconnected with empty or undened. You can also call the bind() routine procedurally to determine if two ports are connected or if a port is connected to an external object. For external, bind() returns TRUE only if the specied port is bound to external, not if it is in a bound set that also has external connections. See Declarative and Procedural Port Bindings on page 6-11 to determine whether declarative or procedural bindings are best for your environment.
Notes It is an error to declare a port disconnected in more than one way. For example:
-- the following is an error keep bind(p1, empty); keep bind(p1, undefined);
For bindings with the syntax keep bind(port-exp1, port-exp2), the order of the port expressions does
not matter.
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bind()
If a port is declared both connected and disconnected, the port connection declaration always
over-rides the explicit port disconnection.
The keyword soft is deprecated because it has no effect. For example, any combination of soft or
hard on either of the following constraints results in the same binding. The p1 port is bound to the p2 port because an explicit port connection always over-rides an explicit port disconnection:
keep soft bind(p1, p2); keep bind(p1, empty);
Example 1
Valid Binding for Buffer Ports
<' unit driver_u { data_out: out buffer_port of int(bits:16) is instance; keep data_out.buffer_size() == 20; }; unit bfm_u { data_in: in buffer_port of int(bits:16) is instance; }; extend sys { driver: driver_u is instance; bfm: bfm_u is instance; keep bind(bfm.data_in, empty); // data_in is explicitly disconnected }; '> <' extend sys { keep bind(bfm.data_in, driver.data_out);// data_in is bound to // data_out, over-riding // previous empty binding }; '>
Example 2
Valid Binding for Simple External Ports
unit monitor_u { data_in: in simple_port of int is instance; }; extend sys { monitor: monitor_u is instance; keep bind(monitor.data_in, external); // data_in is bound keep monitor.data_in.hdl_path() == "data"; // to external signal "data" };
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bind()
Example 3
Valid Multiple Binding Examples for Simple Ports
unit bfm_u { data_out: out simple_port of int is instance; }; unit scoreboard_u { stim_in: in simple_port of int is instance; }; extend sys { bfm: bfm_u is instance; scoreboard: scoreboard_u is instance; keep bind(bfm.data_out, external); // data_out is bound keep bfm.data_out.hdl_path() == "data"; // to external signal "data" keep bind (bfm.data_out, scoreboard.stim_in); // data_out is also bound // to scoreboard.stim_in };
Example 4
Valid Binding Example for Method Ports
method_type write_transaction_method_t (t: xyz_transaction): bool; method_type report_transaction_method_t (t: xyz_transaction); unit xyz_client { write: out method_port of write_transaction_method_t is instance; keep bind(write, external); // external binding keep write.hdl_path() == "transactor"; keep write.hdl_convertor() == "(transaction: TRCONV)"; mark: out method_port of report_transaction_method_t is instance; }; extend sys { client: xyz_client is instance; keep client.hdl_path() == "~/ip"; keep client.agent() == "systemc"; server: xyz_server is instance; keep bind(client.mark, server.scoreboard); // internal binding };
Example 5
Invalid Bindings
buf_in2: in buffer_port of int(bits:32) is instance; buf_out2: out buffer_port of int(bits:16) is instance; keep bind(buf_in2, buf_out2); // Invalid; different bit size buf_in3: in buffer_port of packet is instance; buf_out3: out buffer_port of small packet is instance; keep bind(buf_in3, buf_out3); // Invalid; different subtypes
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connect_pointers()
Example 6
Example of Procedural Call to bind()
The bind() routine can also be called in procedural code. It returns TRUE if the two ports are bound directly or if they are part of the same bound set. For example:
connect_ports() is also { if (!bind(p, q)) then { do_bind(p, q); }; };
Example 7
Example of Procedural Call to bind()
You can also call bind() with empty, undened and external. For external, bind() returns TRUE only if the specied port is bound to external, not if it is in a bound set that also has external connections. For example:
connect_ports() is also { do_bind(p, q); do_bind(q, external); print bind(p, external); --prints FALSE print bind(q, external); --prints TRUE };
See Also Declarative and Procedural Port Bindings on page 6-11 Creating and Using Port Bindings on page 6-11 do_bind() on page 6-75
6.8.2
Purpose
connect_pointers()
Connect unit references (pointers)
Category
Predened method for any unit
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connect_pointers()
Syntax
connect_pointers() is also {} Syntax Example
Description
When you issue a test, start, or generate command from the Specman command line, after the unit tree is generated and calls to post_generate() are complete, the sys.connect_pointers() method is called. Then, every unit under sys is processed in depth-rst eld order and its connect_pointers() method called before proceeding to the next unit instance. See Figure 22-1 on page 22-4 for more information on test phases. See The connect_pointers() Method of sys on page 6-86 for an explanation of depth-rst eld order. This method is initially empty. You can extend this method to set unit references.
Notes You must mark all unit pointers that are set procedurally with a !. Failing to do so while failing to
constrain them results in a generation-time error message:
Cannot generate xxx - not an instance
Because connect_pointers() is called after the unit tree for the VE is generated and after
post_generate() is called, any reference assigned in connect_pointers() must not be used in constraints or in post_generate(). In general, connect_pointers() is recommended only to create cross references between sibling units. See Propagating Data when Generating the VE on page 5-4 in the Generation Guide for more information.
Example
Note The dependent elds, bfm.driver and driver.bfm in this example, must be marked as do-not-generate.
extend agent { bfm: ex_atm_bfm is instance; driver: ex_atm_sequence_driver is instance; connect_pointers() is also { bfm.driver = driver;
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connect_ports()
driver.bfm = bfm; }; };
See Also The connect_pointers() Method of sys on page 6-86 Declarative and Procedural Port Bindings on page 6-11 Creating and Using Port Bindings on page 6-11
6.8.3
Purpose
connect_ports()
Connect ports procedurally
Category
Syntax
connect_ports() is also {} Syntax Example
connect_ports() is also { do_bind(driver.bfm.data_in, bfm.driver.data_out); };
Description
When you issue a test, start, or generate command from the Specman command line, after the unit tree is generated and calls to connect_pointers() are complete, the sys.connect_ports() method is called. Then, every unit under sys is processed in depth-rst eld order and its connect_ports() method called before proceeding to the next unit instance. See The connect_pointers() Method of sys on page 6-86 for more information on depth-rst order. See Figure 22-1 on page 22-4 for more information on test phases.
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connect_ports()
This method is initially empty. You can extend this method to connect ports procedurally using the do_bind() routine to connect ports. You can also call other routines to disconnect or query bindings, such as do_bind_unit(), disconnect(), disconnect_bound_set(), get_bound_set() and is_connected(). See Declarative and Procedural Port Bindings on page 6-11 in the e Language Reference for more information. Sometimes you need to set nal values that depend on unit references, either by assignment or by a gen action. You can do this in connect_ports(). Note You cannot use the port values from within connect_ports(). Ports only become operational at after the generation phase completes.
Example 1
Simple Example of connect_ports()
unit my_sequence_driver_u { !bfm: my_bfm_u; data_out: out buffer_port of uint is instance; keep data_out.buffer_size() == 20; }; unit my_bfm_u { !driver: my_sequence_driver_u; data_in: in buffer_port of uint is instance; }; extend sys { driver: my_sequence_driver_u is instance; bfm: my_bfm_u is instance; connect_pointers() is also { bfm.driver = driver; driver.bfm = bfm; }; connect_ports() is also { do_bind(driver.bfm.data_in, bfm.driver.data_out); }; };
Example 2
Setting Final Values
This example shows how to set nal values when unit references have been created procedurally. You cannot use post_generate() to set nal values in this case, since calls to post_generate() complete before the unit references are created.
extend my_module_evc { -- The following two fields are set by connect_ports() !serial_kind: serial_kind_t; !initial_length: int; connect_ports() is also {
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check_generation()
-- Assumes that the pointer to the corresponding serial interface -- eVC (a field called serial_interface) has already been set by -- connect_pointers() -- Procedural assignment using a unit reference serial_kind = serial_interface.kind; -- Random generation using a cross pointer gen initial_length keeping {it < serial_interface.max_length}; }; };
See Also The connect_ports() Method of sys on page 6-90 Declarative and Procedural Port Bindings on page 6-11 Creating and Using Port Bindings on page 6-11
6.8.4
Purpose
check_generation()
Implement user-dened checks, including connection checks
Category
Syntax
check_generation() is also {} Syntax Example
check_generation() is also { check that bind(driver.data_out, bfm.data_in); };
Description
When you issue a test, start, or generate command from the Specman command line, after the unit tree is generated and calls to connect_ports() are complete, the sys.check_generation() method is called.
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do_bind()
Then, every unit under sys is processed in depth-rst eld order and its check_generation() method called before proceeding to the next unit instance. See The connect_pointers() Method of sys on page 6-86 for more information on depth-rst order. See Figure 22-1 on page 22-4 for more information on test phases. This method is initially empty. You can extend this method to implement user-dened checks, such as port binding or nal value checks. See Creating and Using Port Bindings on page 6-11 for more information.
Example
unit external_interface { // external_clk is intended to be bound to some external clock external_clk : in simple_port of bool is instance; check_generation() is also { check that bind(external_clk, external); }; };
See Also Declarative and Procedural Port Bindings on page 6-11 Creating and Using Port Bindings on page 6-11 The check_generation() Method of sys on page 6-91
6.8.5
Purpose
do_bind()
Connect ports
Category
Predened routine
Syntax
do_bind(port-exp1, port-exp2[,]); do_bind(port-exp1, external);
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do_bind()
do_bind(port-exp1, empty | undened); Syntax Example

do_bind(driver.bfm.data_in, bfm.driver.data_out);
Parameters
port-exp1, port-exp2[,] external empty undened One or more expressions of port type. If two expressions are given and the port types are compatible, the two port instances are connected. Denes a port as connected to a simulated object, such as a Verilog register, a VHDL signal, or a SystemC object, such as a method. Denes a disconnected port. Runtime accessing of a port with an empty binding is allowed. Denes a disconnected port. Runtime accessing of a port with an undened binding causes an error
Description
By calling the do_bind() routine, you procedurally connect a port to one or more e ports or to one or more external simulated object such as a Verilog register, a VHDL signal, or a SystemC method. Ports can also be left explicitly disconnected with empty or undened.
Notes The do_bind() method can only be called during the connect_ports() sub-phase. Calling it at any
other time results in an error message.
It is an error to declare a port disconnected in more than one way. For example:
-- the following is an error do_bind(p1, empty); do_bind(p1, undefined);
Example
In the following example, connect_ports() calls do_bind(). The parameters of the do_bind() routine are pointers set during the connect_pointers sub-phase of generation. This is a typical use of do_bind().
unit my_sequence_driver_u { !bfm: my_bfm_u; data_out: out buffer_port of uint is instance; keep data_out.buffer_size() == 20;
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do_bind_unit()
}; unit my_bfm_u { !driver: my_sequence_driver_u; data_in: in buffer_port of uint is instance; }; extend sys { driver: my_sequence_driver_u is instance; bfm: my_bfm_u is instance; connect_pointers() is also { bfm.driver = driver; driver.bfm = bfm; }; connect_ports() is also { do_bind(driver.bfm.data_in, bfm.driver.data_out); }; };
See Also Declarative and Procedural Port Bindings on page 6-11 bind() on page 6-66 connect_ports() on page 6-72
6.8.6
Purpose
do_bind_unit()
Bind all of the ports of a unit at once
Category
Predened routine
Syntax
do_bind_unit(unit-exp1, unit-exp2[, explicit-mappings]); do_bind_unit(unit-exp1, external); do_bind_unit(unit-exp1, empty | undened);
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do_bind_unit()
Syntax Example
do_bind_unit(agent.monitor_int, monitor);
Parameters
unit-exp1, unit-exp2 One or more expressions of unit instance type. If two expressions are given and no explicit mappings are given, each port instance in the rst unit instance is bound to the port instance of the same name in the second unit. Note If there is no port in the second unit of the same name as in the rst unit, an error is issued. explicit-mappings A comma-separated list of pairs of elds to be bound explicitly, not by name. The second item in the pair can be one of the keywords external, empty, undened, or none. none indicates that the current binding of the port should not be modied. If none is specied for a port, you cannot subsequently repeat the port in the explicit mappings list with a different mapping. Note The elds should match the static type of the unit, otherwise a load-time error is issued. external empty undened Binds all port instances in the unit to external objects, such as Verilog registers, VHDL signals, or SystemC methods. Denes all port instances in the unit as disconnected. Runtime accessing of a port with an empty binding is allowed. Denes all port instances in the unit as disconnected. Runtime accessing of a port with an undened binding causes an error
Description
Denes all port instances in a unit in one of the following ways:
As bound by name to the port instances in a second unit As bound by explicit mapping to the port instances in a second unit As bound to external objects As disconnected
Implicit mappings, including type matching checks, are performed during elaboration. Explicit mapping is checked at load time, using the static types of the units.
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do_bind_unit()
Port connections made with do_bind_unit() are identical to those created with keep bind() or do_bind(). You disconnect them and query them with the same routines, and you can create additional multiple bindings, following the general rules for multiple bindings.
Notes The do_bind_unit() method can only be called during the connect_ports() sub-phase. Calling it at
any other time results in an error message.
Only ports instances are considered by this pseudo-routine. Port references are not mapped. do_bind_unit() is not symmetrical. do_bind_unit(X, Y) is not the same as do_bind_unit(Y, X).
do_bind_unit() considers all port instances of unit1, but unit2 may have ports that are not considered.
Currently, the pseudo-routine do_bind_unit() cannot receive as its rst argument a unit that has an
instance eld of the type list of port.
Example 1
Assume unit X has ports p1 and p2, while unit Y has ports p1, p2, and p3. In that case:
do_bind_unit(X, Y);
is the same as:

do_bind(X.p1, Y.p1); do_bind(X.p2, Y.p2);
No port binding of Y.p3 is created by this call to do_bind_unit().
Example 2
Assume unit X has ports p1 and p2, while unit Y has ports p1, p2, and p3. In that case:
do_bind_unit(X, Y, p1, p3);
is the same as:

do_bind(X.p1, Y.p3); do_bind(X.p2, Y.p2);
The port binding of Y.p1, if any, remains unchanged. No port binding of Y.p1 is created by this call to do_bind_unit().
Example 3
You can also specify undened, empty, external or none in list of port instances to be bound. For example, the list p1, p3, p2, external makes the following bindings:
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remap_hdl_path()
unit-exp1.p1<=>unit-exp2.p3 unit-exp1.p2=>external All other remaining pairs of port instances with the same names, for example: unit-exp1.p5<=>unit-exp2.p5 unit-exp1.p6<=>unit-exp2.p6
As another example, if X and Y each has the ports p1, p2, p3 then
do_bind_unit(X, Y, p1, none)
binds X.p2 to Y.p2 and X.p3 to Y.p3 but does nothing with X.p1 or Y.p1.
See Also Bundled Binding on page 6-19 do_bind() on page 6-75
6.8.7
Purpose
remap_hdl_path()
Change the external object to which a port instance is bound
Category
Port pseudo-method
Syntax
port-exp.remap_hdl_path(new-hdl-path); Syntax Examples
p1.remap_hdl_path("~/top.a1.r1"); p2.remap_hdl_path("r1");
Parameters
port-exp An expression of a port type.
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remap_hdl_path()
new-hdl-path
The path to the new external object, enclosed in double quotes.
Description
To access an external, simulated object, you must provide a path to the object with the hdl_path() attribute. The remap_hdl_path() pseudo-method lets you change the value of the HDL path. Note The remap_hdl_path() pseudo-method can be called only during the connect_ports phase.
Dening the HDL Path

If you start the HDL path with ~/, the path is treated as the absolute HDL path of the port. If you do not start the HDL path with ~/, then the path is a concatenation of the partial paths you provide for the port itself and for its enclosing units. The partial paths can contain any separator that is supported by the adapter for the simulator you are using.
Example
unit A { p1 : out simple_port of int is instance; keep p1.hdl_path() == "r"; }; extend sys { A : a is instance; keep a.hdl_path() == "~/top.u1"; }; extend A { connect_ports() is also { print p1.full_hdl_path(); // will print "top.u1.r"; p1.remap_hdl_path("m1.r"); print p1.full_hdl_path(); // will print "top.u1.m1.r" }; };
See Also hdl_path() Port Attribute on page 6-154 Canonical Naming Conventions on page 9-9 in the Specman Elite Integrators Guide
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disconnect()
6.8.8
Purpose
disconnect()
Disconnect a port from its bound set
Category
Pseudo-method
Syntax
port-exp.disconnect(); Syntax Example
data_out.disconnect();
Description
Calling this pseudo-method of a port disconnects this port from the bound set it belongs to, and returns it to its initial, dangling state. The rest of the bound set remains intact.
Notes The disconnect() method can only be called during the connect_ports() sub-phase. Calling it at any
other time results in an error message.
Since dangling ports result in an error at elaboration time, you should explicitly bind the port to
empty or undened after disconnecting it with disconnect(), or bind it to another object.
If any port in the bound set is bound only to the port you disconnect, then you have effectively returned
that port to its initial dangling state also. For example, if p1 is bound only to p2 and you disconnect p2 as follows:
p2.disconnect();
you effectively make p1 a dangling port.
Specman deals only with bound sets and ignores the order of connection. Hence, if you write:
do_bind(p1, p2); do_bind(p2, p3); p2.disconnnect();
p1 and p3 are still connected. After the second do_bind(), the bound set contained p1, p2 and p3. p2.disconnect() just removed p2 from the bound set.
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disconnect_bound_set()
Example
unit bfm_u { data_in: in simple_port of uint is instance; }; extend sys { bfm: bfm_u is instance; data_out: out simple_port of uint is instance; connect_ports() is { data_out.disconnect(); do_bind(data_out, bfm.data_in); }; };
See Also disconnect_bound_set() on page 6-83
6.8.9
Purpose
disconnect_bound_set()
Disconnect all ports in the bound set of a port
Category
Pseudo-method
Syntax
port-exp.disconnect_bound_set(); Syntax Example
data_out.disconnect_bound_set();
Description
Calling this pseudo-routine of a port disconnects all the ports in the bound set of this port, and sets the status of all of them to be dangling. This is logically implemented in Specman as follows:
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get_bound_set()
var ports: list of any_port = port.get_bound_set(); for each (p) in ports do { p.disconnect(); };
Note The disconnect_bound_set() method can only be called during the connect_ports() sub-phase.
Calling it at any other time results in an error message.
Example
connect_ports() is { data_out.disconnect_bound_set(); do_bind(data_out, bfm.data_in); };
See Also disconnect() on page 6-82 get_bound_set() on page 6-84
6.8.10
Purpose
get_bound_set()
Returns the bound set of a port
Category
Pseudo-method
Syntax
port-exp.get_bound_set(): list of any_port Syntax Example
var ports: list of any_port = data_out.get_bound_set();
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is_connected()
Description
Returns the set of ports connected to that port, including itself. Calling get_bound_set() on a disconnected port returns only the port itself.
Note The get_bound_set() method can be called at any time, not just during the connect_ports()
sub-phase.
Example
connect_ports() is { var ports: list of any_port = data_out.get_bound_set(); if (!ports.has(it == bfm.data_in)) then { do_bind(data_out, bfm.data_in); }; };
Example 4
cmd-prompt> print p2.get_bound_set()
See Also is_connected() on page 6-85 bind() on page 6-66
6.8.11
Purpose
is_connected()
Returns TRUE if a port is a member of a bound set
Category
Pseudo-method
Syntax
port-exp.is_connected();
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The connect_pointers() Method of sys
Syntax Example
if (!data_out.is_connected()) then { do_bind(data_out, bfm.data_in); };
Description
Returns TRUE if the port is connected to another port or to external.
Note is_connected() can be called at any time, not just during the connect_ports() sub-phase. Example 1
connect_ports() is also { if (!data_out.is_connected()) then { do_bind(data_out, bfm.data_in); }; };
Example 2
cmd-prompt> print p2.is_connected()
See Also get_bound_set() on page 6-84 bind() on page 6-66
6.8.12
Purpose
Connect unit references (pointers)
Category
Predened method for sys
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Syntax
[sys.]connect_pointers() Syntax Example
Description
When you issue a test, start, or generate command from the Specman command line, after the unit tree is generated and calls to post_generate() are complete, the sys.connect_pointers() method is called. Then, every unit under sys is processed in depth-rst eld order and its connect_pointers() method called before proceeding to the next unit instance. As shown in the example below, this means that the child of a node is visited before the sibling of that node. As a result, code in lower-level units can depend on pointers dened in higher-level units.
Example
This example shows that the connect_pointers() method of the top-level unit, u_instance, is called rst. Then the connect_pointers() methods of the u1_instance and its child, u3_instance, are called, because u1_instance is instantiated in u_instance before u2_instance. Finally, the connect_pointers() methods of the u2_instance and its child, u4_instance, are called.
<' unit u3 { connect_pointers() is { out("===>in connect_pointers of u3"); }; }; unit u4 { connect_pointers() is { out("===>in connect_pointers of u4"); }; }; unit u1 { u3_instance: u3 is instance; connect_pointers() is { out("===>in connect_pointers of u1"); };
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}; unit u2 { u4_instance: u4 is instance; connect_pointers() is { out("===>in connect_pointers of u2"); }; }; unit u { u1_instance: u1 is instance; u2_instance: u2 is instance; connect_pointers() is { out("===>in connect_pointers of u"); }; }; extend sys { u_instance: u is instance; }; '> vrst-tool > test Doing setup ... Generating the test using seed 1... ===>in connect_pointers of u ===>in connect_pointers of u1 ===>in connect_pointers of u3 ===>in connect_pointers of u2 ===>in connect_pointers of u4 Starting the test ... Running the test ... No actual running requested. Checking the test ... Checking is complete - 0 DUT errors, 0 DUT warnings.
(See Figure 22-1 on page 22-4 for more information on test phases.)
Suggested Use
You can extend this method to set unit references procedurally. You must mark all unit pointers that are set procedurally with a !. Failing to do so (and not constraining them either) results in a generation-time error message:
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Cannot generate xxx - not an instance
Notes Because connect_pointers() is called after the unit tree for the VE is generated and after
post_generate() is called, any reference assigned in connect_pointers() must not be used in constraints or in post_generate(). In general, connect_pointers() is recommended only to create cross references between sibling units. See Propagating Data when Generating the VE on page 5-4 in the Generation Guide for more information.
It is not recommended to modify unit pointers after the generation phase. To set values that depend on unit pointers, use sys.connect_ports() method or the connect_ports()
method of any unit. See Unit Hierarchical References on page 5-5 in the e Language Reference for more information.
Example
unit my_sequence_driver_u { !bfm: my_bfm_u; }; unit my_bfm_u { !driver: my_sequence_driver_u; }; extend sys { driver: my_sequence_driver_u is instance; bfm: my_bfm_u is instance; connect_pointers() is also { bfm.driver = driver; driver.bfm = bfm; }; };
See Also The connect_pointers() Method of sys on page 6-86 The connect_ports() Method of sys on page 6-90 The connect_ports() Method of sys on page 6-90
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The connect_ports() Method of sys
6.8.13
Purpose
The connect_ports() Method of sys
Connect ports procedurally and set nal values that depend on unit pointers
Category
Syntax
[sys.]connect_ports() Syntax Example
connect_ports() is also { do_bind(driver.data_out, bfm.data_in); };
Description
When you issue a test, start, or generate command from the Specman command line, after the unit tree is generated and calls to connect_pointers() are complete, the sys.connect_ports() method is called. Then, every unit under sys is processed in depth-rst eld order and its connect_ports() method called before proceeding to the next unit instance. See The connect_pointers() Method of sys on page 6-86 for more information on depth-rst order. See Figure 22-1 on page 22-4 in the e Language Reference for more information on test phases.
Suggested Use
You can extend this method to connect ports procedurally and to set nal values that depend on unit pointers.
Example
In the following example, connect_ports() calls do_bind(). The parameters of the do_bind() routine are pointers set during the connect_pointers sub-phase of generation. This is a typical use of do_bind().
unit my_sequence_driver_u { !bfm: my_bfm_u; data_out: out buffer_port of uint is instance;
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e Ports
The check_generation() Method of sys
keep data_out.buffer_size() == 20; }; unit my_bfm_u { !driver: my_sequence_driver_u; data_in: in buffer_port of uint is instance; }; extend sys { driver: my_sequence_driver_u is instance; bfm: my_bfm_u is instance; connect_pointers() is also { bfm.driver = driver; driver.bfm = bfm; }; connect_ports() is also { do_bind(driver.bfm.data_in, bfm.driver.data_out); }; };
See Also connect_ports() on page 6-72 do_bind() on page 6-75
6.8.14
Purpose
Implement user-dened checks, including connection checks
Category
Syntax
[sys.]check_generation() Syntax Example
check_generation() is also { check that bind(external_clk,external); };
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e Ports
Description
When you issue a test, start, or generate command from the Specman command line, after the unit tree is generated and calls to connect_ports() are complete, the sys.check_generation() method is called. Then, every unit under sys is processed in depth-rst eld order and its check_generation() method called before proceeding to the next unit instance. See The connect_pointers() Method of sys on page 6-86 for more information on depth-rst order. See Figure 22-1 on page 22-4 in the e Language Reference for more information on test phases.
Suggested Use
You can extend this method to implement user-dened checks, such as port binding or nal value checks.
Example
unit my_sequence_driver_u { !bfm: my_bfm_u; data_out: out buffer_port of uint is instance; keep data_out.buffer_size() == 20; }; unit my_bfm_u { !driver: my_sequence_driver_u; data_in: in buffer_port of uint is instance; }; extend sys { driver: my_sequence_driver_u is instance; bfm: my_bfm_u is instance; connect_pointers() is also { bfm.driver = driver; driver.bfm = bfm; }; connect_ports() is also { do_bind(driver.bfm.data_in, bfm.driver.data_out); }; check_generation() is also { check that bind(driver.bfm.data_in, bfm.driver.data_out); }; };
See Also check_generation() on page 6-74
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e Ports
Simple Port Access Operators
6.9
Simple Port Access Operators
To read values from a simple port or to write values to it, you can use one of the following access operators:
simple_port$ on page 6-93 simple_port$[ : ] on page 6-94 force port$ on page 6-99 release port on page 6-102 force port$[ : ] on page 6-100
To read or write MVL data from a port whose data element is not mvl or list of mvl, use the simple port MVL methods.
See Also Simple Port MVL Access Methods on page 6-111
6.9.1
Purpose
simple_port$
Read or write a value to a simple port
Category
Operator
Syntax
port-exp$ Syntax Example
np$ = 0; mp$ = 32'bz; // Assigns the value 0 to the simple numeric port 'np' // Assigns an mvl literal to the simple mvl port 'mp'
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e Ports
simple_port$[ : ]
Parameters
port-exp An expression that returns a simple port.
Description
The $ access operator is used to access or update the value held in a simple port. When used on the right-hand side, p$ refers to the ports value. On the left-hand side of an assignment, p$ refers to the values location, so an assignment to p$ changes the value held in the port. Without the $ operator an expression of any type port refers to the port itself, not to its value. In particular, an expression without the $ operator can be used for operations involving port references. Note You cannot apply the $ access operator to an item of type any_simple_port. Abstract types do not have any access methods.
Example
<' unit u { init_port(np: inout simple_port of uint) is { np$ = 0; // Assigns the value 0 to the simple numeric port 'np' }; free_port(mp: inout simple_port of list of mvl) is { mvlp$ = 32'bz; // Assigns an mvl literal to the port 'mvlp' }; }; '>
See Also Accessing Simple Ports and Their Values on page 6-25 Multi-Value Logic (MVL) on Simple Ports on page 6-27 Simple Port MVL Access Methods on page 6-111
6.9.2
Purpose
simple_port$[ : ]
Read or write a value to a bit or a bit slice of a simple port
6-94
e Ports
simple_port$[ : ]
Category
Operator
Syntax
simple-port-exp$[[high-exp]:[low-exp][: slice]] = rhs-exp lhs-exp = simple-port-exp$[[high-exp]:[low-exp][: slice]] Syntax Example
p$[10:3] = 123; p$[:] = 0x17;
Parameters
simple-port-exp high-exp An expression that returns a simple port instance. The element type has to be scalar, list of bit or list of byte. A non-negative numeric expression, greater than or equal to the low expression. To extract a single bit, use the same expression for both the high and the low expression. A non-negative numeric expression, less than or equal to the high expression. Default is zero. One of bit, byte, int, or uint. The default is bit. A numeric expression. A expression that returns an e variable or eld.
low-exp slice rhs-exp lhs-exp
Description
The bit slicing operator can be used in a left-hand side (LHS) or right-hand side (RHS) port access expression. The syntax of the bit slicing expression is described in [ : ] on page 2-70. When the expression appears on the left-hand side of an assignment, the specied bits in the location that the port refers to are set to the value of the RHS expression. The RHS value is chopped or zero/sign extended, if necessary. When the expression appears on the right-hand side of an assignment, the specied bits in the location that the port refers to are written to the LHS expression.
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e Ports
simple_port$[ : ]
Access to non-existing bits Any access to non-existing bits of e2e ports causes an error, unless the port is of type unbounded integer. This is the same behavior of the bit slicing operator. For external ports, if the element type is list of bit or list of byte, then the list is resized by adding enough zero bits to make the high expression index valid. On all other port types, any access to non-existing bits causes an error. Note External ports of type innite integer are not supported. For external ports, in all cases, the result of the assignment is passed to the adapter, which may modify the value according to the actual entity accessed on the simulator side. This modication is adapter dependent. For Cadence adapters, if the passed value is longer than the value holder on the simulator side, a warning is issued about the loss of information. Omitting the high expression index When the high expression index is not given, if the port is of a bound type (in other words, it is not a port of type innite integer or list), then the high expression is taken to be the size of the port expression - 1. If the port is of unbound type, then
For e2e ports, the size of the port expression is the size of the last assigned value. For external ports, if there was any assignment during the current tick, it determines the size of the
assigned value. Otherwise, the size of the port expression is the size of the value that the port referred to, as returned by the adapter. The effect of an assignment All the assignments in one Specman tick are executed in the end of the tick. Assignments to different bits are accumulated. If several assignments were done to the same bit, then the last assignment wins. That means that if a value is assigned to an input port, then any output port that connected to this port returns this value only on the next tick. For example:
<' unit u { p1 : out simple_port of int is instance; p2 : in simple_port of int is instance; keep bind(p1,p2); //... rw()@sys.any is { p1$ = 0xffffffff; wait[1]; p1$[7:0] = 0; print p2$ using hex; -- will print 0xffffffff
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e Ports
simple_port$[ : ]
wait[1]; print p2$ using hex; -- will print 0xffffff00 //... }; }; '>
In cases where the non_delayed attribute of the port is set to TRUE, then the effect of the assignment is immediate. Note The list slicing operator [..] and the list indexing operator [] are not supported for ports in LHS expressions. In other words, p$[l..h] and p$[i] are not supported on the LHS of an assignment operator.
Example
top.e
<' unit verifier { p : inout simple_port of int is instance; keep bind(p,external); keep p.hdl_path() == "sig"; clk : in simple_port of bit is instance; keep bind(clk,external); keep clk.hdl_path() == "clk"; event clk_rise is rise(clk$)@sim; run() is also { start do_the_test(); }; do_the_test()@clk_rise is { p$ = 0xffffffff; wait [1]; p.put_mvl_list(32'hxxxxzzzz); wait [1]; p$[15:12] = 0xa; p.put_mvl_to_bit_slice(11,8,4'hx); p$[7:4] = 0xb; p.put_mvl_to_bit_slice(3,0,4'hx); check that p.get_mvl_list() == 32'hxxxxzzzz; -- assignments are -- reflected only in the -- next tick wait[1]; force p$ = 0x123;
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e Ports
simple_port$[ : ]
check that p$ == 0x123; -- value is reflected immediately wait[1]; p$ = 100; -- is ignored check that p$ == 0x123; p.put_mvl_list(32'hzzzzzzzz); -- is ignored check that p$ == 0x123; wait[1]; p.force_mvl_to_bit_slice(31,24,8'hzx); -- force the most significant -- byte wait[1]; release p; wait[1]; p$ = 0xabcd; wait[1]; stop_run(); }; }; extend sys { v : verifier is instance; keep v.hdl_path() == "~/top"; }; '>
top.v
module top(); reg reg[31:0] clk; sig;
initial clk <= 0; always #50 clk <= ~clk; always @(sig) $display($time, " : sig = %x",sig); endmodule
See Also force port$[ : ] on page 6-100 put_mvl_to_bit_slice() on page 6-124 force_mvl_to_bit_slice() on page 6-126
6-98
e Ports
force port$
6.9.3
Purpose
force port$
Force a value to a simple port
Category
Action
Syntax
force simple-port-exp$= rhs-exp Syntax Example
force p1$ = 123;
Parameters
simple-port-exp rhs-exp An expression that returns a simple port instance. An expression of the same type as the ports type.
Description
Forces a value to the simple port. For both e2e and external ports, updates the value held inside the port. Until the port is released, any other non-force assignment to the port will be ignored. Any subsequent force assignment overrides the last one. In addition, for external ports, the result of the force assignment is passed to the adapter. Effect of force assignment Force assignments are not delayed. Any forced value is immediately seen by any port that is bound to the assigned port.
Example
<' unit u p1 : p2 : keep { out simple_port of int is instance; in simple_port of int is instance; bind(p1,p2);
6-99
e Ports
force port$[ : ]
//... rw()@sys.any is { p1$ = 0xffffffff; wait[1]; force p1$ = 0xabc; print p2$ using hex; -- will print 0xabc //... }; }; '>
See Also simple_port$[ : ] on page 6-94 put_mvl_to_bit_slice() on page 6-124 force_mvl_to_bit_slice() on page 6-126
6.9.4
Purpose
force port$[ : ]
Force a value to a bit or a bit slice of a simple port
Category
Action
Syntax
force simple-port-exp$[[high-exp]:[low-exp][: slice]] = rhs-exp Syntax Example
force p1$[10:3] = 123; force p2$[:] = 0x17;
Parameters
simple-port-exp An expression that returns a simple port instance. The element type has to be scalar, list of bit or list of byte.
6-100
e Ports
force port$[ : ]
high-exp
A non-negative numeric expression, greater than or equal to the low expression. To extract a single bit, use the same expression for both the high and the low expression. A non-negative numeric expression, less than or equal to the high expression. Default is zero. One of bit, byte, int, or uint. The default is bit. A numeric expression.
low-exp slice rhs
Description
For e2e ports, forcing a slice of a port is the same as forcing the entire port, except that values are written only to the specied slice. That is, until the next release action, any subsequent non-force assignment is ignored. Any subsequent force assignment overrides the last one. For external ports, in addition to the behavior specied for e2e ports, the result of the force assignment is passed to the adapter. Effect of force assignment Force assignments are not delayed. Any forced value is immediately seen by any port that is bound to the assigned port.
Example
<' unit u { p1 : out simple_port of int is instance; p2 : in simple_port of int is instance; keep bind(p1,p2); //... rw()@sys.any is { p1$ = 0xffffffff; wait[1]; force p1$[7:0] = 0; print p2$ using hex; -- will print 0xfffff00 //... }; }; '>
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e Ports
release port
See Also simple_port$[ : ] on page 6-94 put_mvl_to_bit_slice() on page 6-124 force_mvl_to_bit_slice() on page 6-126
6.9.5
Purpose
release port
Remove a force action from a port
Category
Action
Syntax
release simple-port-exp Syntax Example
release p1;
Parameters
simple-port-exp An expression that returns a simple port instance.
Description
Releases a simple port that you previously forced. For e2e ports, the value held in the port is that last forced value. For external ports, a release request is passed to the adaptor.
See Also simple_port$[ : ] on page 6-94 force port$ on page 6-99 force port$[ : ] on page 6-100 put_mvl_to_bit_slice() on page 6-124
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e Ports
Event Port Access Operators
force_mvl_to_bit_slice() on page 6-126
6.10 Event Port Access Operators

To emit an event associated with an out event port or to be sensitive to an event associated with an in event port, use the $ access operator.
6.10.1
Purpose
event_port$
Emit or be sensitive to an event associated with an event port
Category
Operator
Syntax
port-exp$ Syntax Example
... inject()@clk$ is { };
Parameters
port-exp An expression that returns an event port.
Description
The $ access operator is used to refer to the event associated with an event port. Without the $ operator an expression of event_port type refers to the port itself, not to its event. Note You cannot apply the $ access operator to an item of type any_event_port. Abstract types do not have any access methods.
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Method Port Access Operators
Example
In the following example, the use of the expression @clk$ causes the inject method to trigger when the external signal clk changes.
unit encoder { data: inout simple_port of list of bit is instance; keep bind(data, external); keep data.hdl_path() == "data"; clk: in event_port is instance; keep bind(clk, external); keep clk.hdl_path() == "clk"; keep clk.edge() == any_change; data_list: list of bit; keep data_list.size() < 32; inject()@clk$ is { for j from 0 to 15 { gen data_list; data$ = data_list; wait cycle; }; }; };
See Also Accessing Event Ports on page 6-36 Using Event Ports on page 6-35
6.11 Method Port Access Operators

To call a method associated with an out method port, use the $() access operator.
6.11.1
Purpose
method_port$()
Call an out method port
6-104
e Ports
Method Port Access Operators
Category
Operator
Syntax
port-exp$(out-method-port-param-list) Syntax Example
u = convert_string$("32"); //calls the convert_string out method port
Parameters
port-exp out-method-port-param-list An expression that returns an output method port instance. A list of actual parameters to the output method port. The number and type of the parameters, if any, must match the method_type.
Description
The $ access operator is used to call an output method port. If you attempt to call the method via the port without the $ operator a syntax error is issued. Without the $ operator an expression of any type port refers to the port itself, not to its value. In particular, an expression without the $ operator can be used for operations involving port references. Note You cannot apply the $ access operator to an item of type any_method_port. Abstract types do not have any access methods.
Example
method_type str2uint_method_t (s:string):uint; unit encoder { convert_string: out method_port of str2uint_method_t is instance; m() is { var u: uint; u = convert_string$("32"); //calls the convert_string out method port }; };
See Also Using Method Ports Overview on page 6-39

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e Ports
Buffer Port Access Methods
Invoking Method Ports on page 6-46 Accessing Functions and Methods with e Method Ports on page 5-42 in the Specman Elite
Integrators Guide
6.12 Buffer Port Access Methods

The methods in this section are used to read from or write to buffer ports and to check whether a buffer port queue is empty or full. The methods are:
get() on page 6-106 put() on page 6-107 is_empty() on page 6-109 is_full() on page 6-110 See Also Using Buffer Ports on page 6-33
6.12.1
Purpose
get()
Read and remove data from an input buffer port queue
Category
Predened TCM for buffer ports
Syntax
in-port-instance-name.get(): port element type Syntax Example
rec_cell = in_port.get();
Description
Reads a data item from the buffer port queue and removes the item from the queue.
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e Ports
put()
Since buffer ports use a FIFO queue, get() returns the rst item that was written to the port. The thread blocks upon get() when there are no more items in the queue. If the queue is empty, or if it has a buffer size of 0 and no put() has been done on the port since the last get(), then the get() is blocked until a put() is done on the port. The number of consecutive get() actions that is possible is limited to the number of items inserted by put().
Example
unit consumer { cell_in: in buffer_port of atm_cell is instance; current_cell: atm_cell; update_cell() @clk$ is { current_cell = cell_in.get(); }; };
See Also Using Buffer Ports on page 6-33 put() on page 6-107 is_empty() on page 6-109 is_full() on page 6-110
6.12.2
Purpose
put()
Write data to an output buffer port queue
Category
Predened TCM for buffer ports
Syntax
out-port-instance-name.put(data: port-element-type)
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put()
Syntax Example
out_port.put(trans_cell);
Parameters
data A data item of the port element type.
Description
Writes a data item to the output buffer port queue. The sampling event of this TCM is sys.any. The new data item is placed in a FIFO queue in the output buffer port. If the queue is full, or if it has a buffer size of 0 and no get() has been done on the port since the last put(), then the put() is blocked until a get() is done on the port. The number of consecutive put() actions that is possible is limited to the buffer size. The thread blocks upon put() when there is no more room in the queue, that is, when the number of consequent put() operations exceeds the buffer_size() of the port instance.
Example
unit producer { clk: in event_port is instance; cell_out: out buffer_port of atm_cell is instance; write_cell_list(atm_cells: list of atm_cell) @clk$ is { for each in atm_cells do { cell_out.put(it); }; }; };
See Also Using Buffer Ports on page 6-33 get() on page 6-106 is_empty() on page 6-109 is_full() on page 6-110
6-108
e Ports
is_empty()
6.12.3
Purpose
is_empty()
Check if an input buffer port queue is empty
Category
Pseudo-method for buffer ports
Syntax
in-port-instance-name.is_empty(): bool Syntax Example
var readable: bool; readable = not cell_in.is_empty();
Description
Returns TRUE if the input port queue is empty. Returns FALSE if the input port queue is not empty.
Example
unit consumer { cell_in: in buffer_port of atm_cell is instance; clk: in event_port is instance; check_and_read(atm_cell): atm_cell @clk$ is { if cell_in.is_empty() { // No data is available - avoid blocking: dut_error("No atm cell is available"); } else { // Read data from the port: return cell_in.get(); }; }; };
6-109
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is_full()
See Also Using Buffer Ports on page 6-33 get() on page 6-106 put() on page 6-107 is_full() on page 6-110
6.12.4
Purpose
is_full()
Check if an output buffer port queue is full
Category
Pseudo-method for buffer ports
Syntax
out-port-instance-name.is_full(): bool Syntax Example
var overflow: bool; overflow = cell_out.is_full();
Description
Returns TRUE if the output port queue is full. Returns FALSE if the output port queue is not full.
Example
unit producer { cell_out: out buffer_port of atm_cell is instance; clk: in event_port is instance; check_and_write(cell: atm_cell)@clk$ is { if cell_out.is_full() { // Cannot write to the port without being blocked dut_error("Overflow in atm cells queue"); }
6-110
e Ports
Simple Port MVL Access Methods
else { // Write data to the port cell_out.put(cell); }; }; };
See Also Using Buffer Ports on page 6-33 get() on page 6-106 put() on page 6-107 is_empty() on page 6-109
6.13 Simple Port MVL Access Methods

To read and write multi-value logic (MVL) data to simple ports whose data type is not mvl or list of mvl, you must use the simple port MVL methods. For ports of type mvl or list of mvl, you can use the simple port access operator (simple_port$), or you can use the MVL methods, or a mixture of both. The type mvl is dened as follows: type mvl: [MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, MVL_N] The enumeration literals are the same as those of VHDL, except for MVL_N, which corresponds to the VHDL - (dont care) literal. The MVL methods are applicable in accordance to the port direction. Methods that write a value to a port are accessible for out and inout simple ports, while methods that read a value from a port are accessible for in and inout simple ports. The predened methods for simple ports are:
put_mvl() on page 6-112 get_mvl() on page 6-113 put_mvl_list() on page 6-115 get_mvl_list() on page 6-116 put_mvl_string() on page 6-118 get_mvl_string() on page 6-119 get_mvl4() on page 6-120
6-111
e Ports
put_mvl()
get_mvl4_list() on page 6-122 get_mvl4_string() on page 6-123 put_mvl_to_bit_slice() on page 6-124 force_mvl_to_bit_slice() on page 6-126 has_x() on page 6-128 has_z() on page 6-129 has_unknown() on page 6-130 See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27
6.13.1
Purpose
put_mvl()
Put an mvl data on a port of a non-mvl type
Category
Predened method for simple ports
Syntax
exp.put_mvl(value: mvl) Syntax Example
p.put_mvl(MVL_Z)
Parameters
exp value An expression that returns a simple port instance. A multi-value logic value.
6-112
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get_mvl()
Description
Place an mvl value on an output or inout simple port, to initialize an object to a disconnected value, for example. Placing an mvl value on a port whose element type is list places the value in the LSB of the list.
Example
unit uo { pbo: out simple_port of bit is instance; keep bind(pbo, external); disconnect_pbo() is { pbo.put_mvl(MVL_Z); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 get_mvl() on page 6-113 put_mvl_list() on page 6-115 put_mvl_string() on page 6-118 string_to_mvl() on page 6-171 int_to_mvl() on page 6-175 bits_to_mvl() on page 6-177 mvl_to_mvl4() on page 6-178
6.13.2
Purpose
get_mvl()
Read mvl data from a port of a non-mvl type
Category
6-113
e Ports
get_mvl()
Syntax
exp.get_mvl(): mvl Syntax Example
check that pbi.get_mvl() != MVL_X else dut_error("Bad value");
Parameters
exp An expression that returns a simple port instance.
Description
Reads an mvl value from an input or inout simple port, to check that there are no undened x bits, for example. Getting an mvl value from a port whose element type is list reads the LSB of the list.
Example
unit ui { pbi: in simple_port of bit is instance; keep bind(pbi, external); chk_pbi() is { check that pbi.get_mvl() != MVL_X else dut_error("Bad value"); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl_list() on page 6-116 get_mvl_string() on page 6-119 get_mvl4() on page 6-120 mvl_to_string() on page 6-172 mvl_to_int() on page 6-174 mvl_to_bits() on page 6-176
6-114
e Ports
put_mvl_list()
mvl_to_mvl4() on page 6-178
6.13.3
Purpose
put_mvl_list()
Put a list of mvl values on a port of a non-mvl type
Category
Syntax
exp.put_mvl_list(values: list of mvl) Syntax Example
pbo.put_mvl_list({MVL_H; MVL_0; MVL_L; MVL_0}); pbo.put_mvl_list({4'bz});
Parameters
exp values An expression that returns a simple port instance. A list of mvl values
Description
Writes a list of mvl values to an output or inout simple port. You can write the value as a list, for example:
{MVL_X;MVL_X;MVL_X;MVL_X}
Alternatively, you can write the value as an MVL literal. An MVL literal, which is a literal of type list of mvl, provides a more convenient syntax for assigning MVL values. The syntax of an MVL literal is as follows:
<width-number>'(b|o|h)<value-number>
The width number is an unsigned decimal integer specifying the size of the list. The value number is any sequence of digits that are legal for the base, plus x, z, u, l, h, w, n. Putting a list of mvl values on a port whose element type is a single bit writes only the LSB of the list.
6-115
e Ports
get_mvl_list()
Example
unit ui { pbi: in simple_port of uint(bits:4) is instance; }; unit uo { uin: ui is instance; pbo: out simple_port of uint(bits:4) is instance; keep bind(pbo, uin.pbi); wr_pbo() is { pbo.put_mvl_list({MVL_H; MVL_0; MVL_L; MVL_0}); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl() on page 6-113 get_mvl_list() on page 6-116
6.13.4
Purpose
get_mvl_list()
Get a list of mvl values from a port of a non-mvl type
Category
Syntax
exp.get_mvl_list(): list of mvl Syntax Example
check that pbil.get_mvl_list().has(it == MVL_U) == FALSE else dut_error("Bad list");
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e Ports
get_mvl_list()
Parameters
Description
Reads a list of mvl values from an input or inout simple port.
Note
For external ports of a xed scalar type, the get_mvl_list() method currently gets a list that is the same size as the HDL signal to which the port is bound. As of Specman 5.0.1, this behavioralthough it continues to be the default behavioris under deprecation. The new behavior is to get a list that is the same size as the scalar element type of the port. You can turn on the new behavior by setting cong simulation -resize_mvl_list to TRUE. With the new behavior:
If the size of the MVL list from the HDL signal is larger than the size of the element type of the port,
The MVL list is shortened to the size of the element type of the port.
If the size of the MVL list from the HDL signal is smaller than the size of the element type of the
port, The MVL list is enlarged to the size of the element type of the port, and the new positions are lled with the ll value MVL_U. Note that the new behavior applies only for external simple ports of a xed scalar type. For external simple ports of other types, for example type list of int, get_mvl_list() will continue to get a list that is the same size as the HDL signal, under both the old behavior and the new behavior.
Example
unit uo { pbol: out simple_port of list of bit is instance; }; unit ui { uout: uo is instance; pbil: in simple_port of list of bit is instance; keep bind(uout.pbol, pbil); chk_pbil() is { check that pbil.get_mvl_list().has(it == MVL_U) == FALSE else dut_error("Bad list"); }; };
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e Ports
put_mvl_string()
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl() on page 6-113 put_mvl_list() on page 6-115 get_mvl4_list() on page 6-122 congure simulation on page 6-60 in the Specman Command Reference
6.13.5
Purpose
put_mvl_string()
Put an mvl value on a port of a non-mvl type when a value is represented as a string
Category
Syntax
exp.put_mvl_string(value: string) Syntax Example
pbol.put_mvl_string("32'hxxxxllll");
Parameters
exp value An expression that returns a simple port instance. An mvl value in the form of a base and one or more characters, entered as a string. The mvl values in the string must be lowercase. Use 1 for MVL_1, 0 for MVL_0, z for MVL_Z, and so on.
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get_mvl_string()
Description
Writes a string representing a list of mvl values to a simple output or inout port. The mvl value consists of any legal Specman base, for example, 32'b, followed by one or more characters, for example xxxxzzzz. The string representation follows the same rules as Verilog literals. The difference is that Verilog literals support only 4-value logic digits (1,0,x and z) while Specman allows also the characters u, l, h, w and n.
Example
unit uo { pbol: out simple_port of uint(bits:4) is instance; keep bind(pbol, external); wr_pbol() is { pbol.put_mvl_string("32'hxxxxllll"); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl() on page 6-113 get_mvl_string() on page 6-119
6.13.6
Purpose
get_mvl_string()
Get a value in form of a string from a port of a non-mvl type
Category
Syntax
exp.get_mvl_string(radix: radix): string
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get_mvl4()
Syntax Example
print pbis.get_mvl_string(BIN);
Parameters
exp radix An expression that returns a simple port instance. One of BIN, OCT, or HEX.
Description
Returns a string in which each character represents an mvl value. The characters are lowercase. HDL value 1 is represented by the character 1, Z by z, - by character n. The returned string always includes all the bits, with no implicit extensions. For example, a port of type uint returns a string of 32 characters, since an int is a 32-bit data type.
Example
unit ui { pbis: in simple_port of uint(bits:4) is instance; keep bind(pbis,external); chk_pbis() is { print pbis.get_mvl_string(BIN); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl() on page 6-113 put_mvl_string() on page 6-118 get_mvl4_string() on page 6-123
6.13.7
Purpose
get_mvl4()
Get an mvl value from a port, converting 9-value logic to 4-value logic
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get_mvl4()
Category
Syntax
exp.get_mvl4(): mvl Syntax Example
check that pbi.get_mvl4() != MVL_Z else dut_error("Bad value");
Parameters
Description
Reads a 9-value mvl value from an input simple port and converts it to 4-value subset mvl. The predened mapping from 9-value logic to 4-value logic is:
MVL_U, MVL_W, MVL_X, MVL_N -> MVL_X MVL_L, MVL_0 -> 0 MVL_H, MVL_1 -> 1 MVL_Z -> MVL_Z
Example
unit ui { pbi: in simple_port of bit is instance; keep bind(pbi, external); chk_pbi() is { check that pbi.get_mvl4() != MVL_X else dut_error("Bad value"); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl() on page 6-113
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get_mvl4_list()
get_mvl4_list() on page 6-122 get_mvl4_string() on page 6-123 mvl_to_mvl4() on page 6-178
6.13.8
Purpose
get_mvl4_list()
Get a list of mvl values from a port, converting from 9-value logic to 4-value logic
Category
Syntax
exp.get_mvl4_list(): list of mvl Syntax Example
check that pbi4l.get_mvl4_list().has(it == MVL_X) == FALSE else dut_error("Bad list");
Parameters
Description
Reads a list of 9-value mvl values from an input simple port and converts them to 4-value MVL. The predened mapping from 9-value logic to 4-value logic is:
MVL_U, MVL_W, MVL_X, MVL_N -> MVL_X MVL_L, MVL_0 -> 0 MVL_H, MVL_1 -> 1 MVL_Z -> MVL_Z
Example
unit ui {
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get_mvl4_string()
pbi4l: in simple_port of list of bit is instance; keep bind(pbi4l, external); chk_pbi4l() is { check that pbi4l.get_mvl4_list().has(it == MVL_X) == FALSE else dut_error("Bad list"); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl() on page 6-113 get_mvl4() on page 6-120 mvl_list_to_mvl4_list() on page 6-179
6.13.9
Purpose
get_mvl4_string()
Get a 4-state value in form of a string from a port of a non-mvl type
Category
Syntax
exp.get_mvl4_string(radix): string Syntax Example
print pbi4s.get_mvl4_string(BIN);
Parameters
exp radix An expression that returns a simple port instance. One of BIN, OCT, or HEX.
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put_mvl_to_bit_slice()
Description
Reads a string in which each character represents a 4-value logic digit from a subset of mvl, converted from 9-value logic. The characters are lowercase. The predened mapping from 9-value logic to 4-value logic is the same as it is commonly used when converting from VHDL std_logic to Verilog:
U, W, X, N -> x L, 0 -> 0 H, 1 -> 1 Z -> z
The returned string always includes all the bits, with no implicit extensions. For example, a port of type int returns a string of 32 characters, since an int is a 32-bit data type.
Example
unit ui { pbi4s: in simple_port of list of int(bits:4) is instance; keep bind(pbi4s,external); chk_pbi4s() is { print pbi4s.get_mvl4_string(HEX); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 put_mvl() on page 6-112 get_mvl() on page 6-113 get_mvl4() on page 6-120 string_to_mvl4() on page 6-180
6.13.10 put_mvl_to_bit_slice()
Purpose
Write mvl data to a bit slice of a port
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put_mvl_to_bit_slice()
Category
Predened method for simple out and inout ports
Syntax
exp.put_mvl_to_bit_slice(high: int, low: int, value: list of mvl) Syntax Example
p1.put_mvl_to_bit_slice(7, 4, 4'hx); p2.put_mvl_to_bit_slice(12, 7, {MVL_X;MVL_X;MVL_H;MVL_H;MVL_U});
Parameters
exp high low value An expression that returns a simple out or inout port instance. The supported element types are scalar, list of bit or list of byte. An integer that species the high index of the bit slice. An integer that species the low index of the bit slice. A list of mvl.
Description
Writes an mvl list to a specied slice of bit. Like the LHS bit slice operator, you can call this method port of type scalar, list of bit or list of byte. If the size of the value is smaller than the slice size (1 + high - low), the value is padded with MVL_Us. If the size of the value is larger than the slice size, then the MSBs of value are truncated. Access to non-existing bits For e2e ports, any access to non-existing bits causes an error, unless the port is of type unbounded integer. For external ports, if the port type is list of bit or list of byte, then the port's mvl list is resized by adding enough MVL_U-s, to make the high index valid. On all other port types, the behavior is as on e2e ports. Note External ports of type innite integer are not supported. In all cases, the result of the assignment is passed to the adapter, which may modify it according to the entity on the simulator side. This modication is adapter dependent. For Cadence adapters, if the passed value is longer than the value holder on the simulator side, a warning is issued regarding the loss of information.
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force_mvl_to_bit_slice()
Effect of the function call Like the bit slice operator, the effect of the assignment is delayed to the next tick. Thus, if the function put_mvl_to_bit_slice() is called for a port, the consequence of this call is not seen until the next tick by any other port that is bound to it. For example:
unit u{ p1: out simple_port of int is instance; p2: in simple_port of int is instance; keep bind(p1,p2); rw() @sys.any is { p1.put_mvl_list(32'hzzzzzzzz); wait[1]; p1.put_mvl_to_bit_slice(7,0,8'hxx); print p2.get_mvl_string(HEX); --will print "32'hzzzzzzzz" wait[1]; print p2.get_mvl_string(HEX); --will print "32'hzzzzzzxx" }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 simple_port$[ : ] on page 6-94 force port$[ : ] on page 6-100 force_mvl_to_bit_slice() on page 6-126
6.13.11 force_mvl_to_bit_slice()
Purpose
Force mvl data to a bit slice of a port
Category
Predened method for simple out and inout ports
6-126
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force_mvl_to_bit_slice()
Syntax
exp.force_mvl_to_bit_slice(high: int, low: int, value: list of mvl,) Syntax Example
p1.force_mvl_to_bit_slice(7, 4, 4'hx); p2.force_mvl_to_bit_slice(12, 7, {MVL_X;MVL_X;MVL_H;MVL_H;MVL_U});
Parameters
exp high low value An expression that returns a simple out or inout port instance. The supported element types are scalar, list of bit or list of byte. An integer that species the high index of the bit slice. An integer that species the low index of the bit slice. A list of mvl.
Description
For e2e ports, forcing a slice of a port is the same as forcing the entire port, except that values are written only to the specied slice. That is, until the next release action, any subsequent non-force assignment is ignored. Any subsequent force assignment overrides the last one. For external ports, in addition to the behavior specied for e2e ports, the result of the force assignment is passed to the adapter. Effect of the function call Force assignments are not delayed. The effect of the function call is immediately seen by any port that is bound to the assigned port.
Example
unit u { p1 : out simple_port of int is instance; p2 : in simple_port of int is instance; keep bind(p1,p2); //... rw()@sys.any is { p1.put_mvl_list(32'hzzzzzzzz); wait[1]; p1.force_mvl_to_bit_slice(7,0,8'xx); print p2.get_mvl_string(HEX); --will print "32'hzzzzzzxx" };
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has_x()
};
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 simple_port$[ : ] on page 6-94 force port$[ : ] on page 6-100 put_mvl_to_bit_slice() on page 6-124
6.13.12 has_x()
Purpose
Determine if port has X
Category
Syntax
exp.has_x(): bool Syntax Example
print pbi4s.has_x();
Parameters
exp An expression of a simple port type.
Description
Returns TRUE if at least one bit of the port is MVL_X.
Example
unit ui { pbi4s: in simple_port of uint(bits:4) is instance; keep bind(pbi4s,external);
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has_z()
chk_pbi4s() is { print pbi4s.has_x(); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 has_z() on page 6-129 has_unknown() on page 6-130
6.13.13 has_z()
Purpose
Determine if port has Z
Category
Syntax
exp.has_z(): bool Syntax Example
print pbi4s.has_z();
Parameters
Description
Returns TRUE if at least one bit of the port is MVL_Z.
Example
unit ui {
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has_unknown()
pbi4s: in simple_port of uint(bits:4) is instance; keep bind(pbi4s,external); chk_pbi4s() is { print pbi4s.has_z(); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 has_x() on page 6-128 has_unknown() on page 6-130
6.13.14 has_unknown()
Purpose
Determine if port has U
Category
Syntax
exp.has_unknown(): bool Syntax Example
print pbi4s.has_unknown();
Parameters
Description
Returns TRUE if at least one bit of the port is one of the following:
MVL_U MVL_X
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Simple Port Default Value Methods
MVL_Z MVL_W MVL_N Example

unit ui { pbi4s: in simple_port of uint(bits:4) is instance; keep bind(pbi4s,external); chk_pbi4s() is { print pbi4s.has_unknown(); }; };
See Also Multi-Value Logic (MVL) on Simple Ports on page 6-27 has_x() on page 6-128 has_z() on page 6-129
6.14 Simple Port Default Value Methods

You can use the following methods to set the default value for a simple port or a bound set of simple ports:
set_default_value() on page 6-131 set_default_mvl_value() on page 6-133
6.14.1
Purpose
set_default_value()
Set the default value for a simple port or a bound set of simple ports
Category
Pseudo-method
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e Ports
set_default_value()
Syntax
port-exp.set_default_value(value: port-element-type); Syntax Example
p1.set_default_value(15);
Parameters
port-exp value An expression of a simple port type. An expression of the same type as the port element.
Description
Sets the default value of a simple port or a bound set of simple ports. The default value is stored as the value of the port or ports during the connect_ports() phase before simulation begins. If this value is not specied, then the default value is the same as the default value of the element type (usually 0 or NULL). The default value applies if an input port is read before it is written. The typical use of these methods is to set the value read from a port with an empty binding. As with port assignments, the default value can be either a non-MVL or an MVL value. To set a non-MVL value, use set_default_value(). To set an MVL value, use set_default_mvl_value(). A port holds only one default value, so these functions override each other. When set_default_value() is applied to a port in a bound set, the default value is applied to the entire bound set. If set_default_value() is applied to a bound set several times, then each new operation overrides the previous ones. When two ports that belong to different bound sets are bound to form a new bound set:
If both ports have default values dened and those values are different, the default value of the new
bound set is considered invalid. The default value must be set again or an elaboration time error occurs
If both ports have the same default value, it becomes the default value of the newly bound set.
Note In the above two cases, if one default value was set using set_default_mvl_value(), and another one was set using set_default_value(), the default values are always considered different. The default value has to be set again after the binding to avoid elaboration time error.
If only one port has a default value, then this becomes the default value of the new bound set.
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set_default_mvl_value()
If no port has a default value, then the new bound set has no default value. Notes set_default_value() can be called only during the connect_ports() sub-phase. If a bound set contains an input port with an external binding, the value is always read from the
simulator and the default value never applies.
Example
unit my_unit { p1 : in simple_port of int is instance; keep bind(p1,empty); connect_ports() is also { p1.set_default_value(15); }; verify()@sys.any is { print p1$; // prints 15; check that p1.get_mvl_list() == 32h0000000F }; };
See Also set_default_mvl_value() on page 6-133
6.14.2
Purpose
Set the default value for a simple port or a bound set of simple ports
Category
Pseudo-method
Syntax
port-exp.set_default_mvl_value(mvl-list: list of mvl);
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Syntax Example
p1.set_default_mvl_value(32'huuuuxxzz);
Parameters
port-exp mvl-list An expression of a simple port type. An expression of type list of mvl.
Description
Sets the default value of a simple port or a bound set of simple ports. The default value is stored as the value of the port or ports during the connect_ports() phase before simulation begins. If this value is not specied, then the default value is the same as the default value of the element type (usually 0 or NULL). The default value applies if an input port is read before it is written. The typical use of these methods is to set the value read from a port with an empty binding. As with port assignments, the default value can be either a non-MVL or an MVL value. To set a non-MVL value, use set_default_value(). To set an MVL value, use set_default_mvl_value(). A port holds only one default value, so these functions override each other. When set_default_mvl_value() is applied to a port in a bound set, the default value is applied to the entire bound set. If set_default_mvl_value() is applied to a bound set several times, then each new operation overrides the previous ones. When two ports that belong to different bound sets are bound to form a new bound set:
If both ports have default values dened and those values are different, the default value of the new
bound set is considered invalid. The default value must be set again or an elaboration time error occurs
If both ports have the same default value, it becomes the default value of the newly bound set.
Note In the above two cases, if one default value was set using set_default_mvl_value(), and another one was set using set_default_value(), the default values are always considered different. The default value has to be set again after the binding to avoid elaboration time error.
If only one port has a default value, then this becomes the default value of the new bound set. If no port has a default value, then the new bound set has no default value.
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Port Attributes
Note set_default_mvl_value() can be called only during the connect_ports() sub-phase. If a bound set contains an input port with an external binding, the value is always read from the
simulator and the default value never applies.
Example 1
unit my_unit { p1 : in simple_port of int is instance; keep bind(p1,empty); connect_ports() is also { p1.set_default_mvl_value(32'huuuuxxzz); }; verify()@sys.any is { print p1$; // will print 255 check that p1.get_mvl_list() == 32'huuuuxxzz; }; };
See Also set_default_value() on page 6-131
6.15 Port Attributes

Ports have attributes that affect their behavior and how they can be used. You assign port attributes using the attribute() syntax in pre-generation constraints, as follows: keep [soft] port_instance.attribute() == value; You can use soft constraints for attributes that you might want to override later. Most port attributes are ignored unless the port is an external port, but it does no harm to specify attributes for ports that are not external ports. Attributes intended for external ports may or may not be supported for a particular simulator. A particular adapter can also dene additional port attributes that are required to enhance access to simulated objects. This section contains the following:
Generic Port Attributes on page 6-137 Port Attributes for HDL Simulators on page 6-139 Port Attributes for SystemC Integration on page 6-142
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Port Attributes
agent() Port Attribute on page 6-142 buffer_size() on page 6-142 declared_range() on page 6-144 delayed() on page 6-145 driver() on page 6-146 driver_delay() on page 6-148 driver_initial_value() on page 6-149 edge() on page 6-149 external_type() on page 6-151 hdl_convertor() on page 6-152 hdl_path() Port Attribute on page 6-154 pack_options() on page 6-156 pass_by_pointer() on page 6-156 sc_variable() on page 6-157 sensitive() on page 6-159 static_sensitivity() on page 6-160 sync_mode() on page 6-162 verilog_delta_delay() on page 6-163 verilog_drive() on page 6-165 verilog_drive_hold() on page 6-166 verilog_forcible() on page 6-166 verilog_strobe() on page 6-167 verilog_wire() on page 6-168 vhdl_delay_mode() on page 6-169 vhdl_disconnect_value() on page 6-170 See Also Predened Attributes and Methods for Any Unit on page 5-18
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Generic Port Attributes
6.15.1
Port attributes that are potentially valid for all simulators are described in Table 6-1. However, a particular simulator adapter might not implement some of these attributes. If you are using an adapter that is not provided by Cadence, refer to the documentation for that adapter for the list of supported attributes. Note Depending on the simulator adapter you are using, port attributes might cause additional code to be written to the stubs le. In that case, if you add or change an attribute, you must rewrite the stubs le. Table 6-1 Attribute agent() Generic Port Attributes Description Identies the simulator used to simulate the corresponding DUT component. Type: string Default: See also agent() Port Attribute on page 6-142. buffer_size() Species the maximum number of elements for a buffer port queue. Type: uint Default: none See also buffer_size() on page 6-142. declared_range() Species the bit width of an external multi-bit object. Type: string Default: See also declared_range() on page 6-144. External output simple ports that are bound to some kinds of multi-bit objects Buffer ports Applies to External ports
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Table 6-1 Attribute delayed()
Generic Port Attributes (continued) Description Species whether propagation of a new port value assignment occurs immediately or is delayed to the Specman tick boundary. Type: bool Default: TRUE See also delayed() on page 6-145. Applies to Internal and external simple ports
driver()
When TRUE, an additional resolved HDL driver is created for the corresponding simulator item, and that driver is written to instead of the port. Type: bool Default: FALSE See also driver() on page 6-146.
External output simple ports
driver_delay()
Species the delay time for all assignments from Specman to the port. Type: time Default: 0 See also driver_delay() on page 6-148.
edge()
Species the edge on which an event is generated. Type: event_port_edge Default: change See also edge() on page 6-149.
External input event ports
hdl_path()
Species a relative path of the corresponding simulated item as a string. Type: string Default: See also hdl_path() Port Attribute on page 6-154.
External ports
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Port Attributes for HDL Simulators
Table 6-1 Attribute
Generic Port Attributes (continued) Description Species how the ports data element is implicitly packed and unpacked. Type: pack_options Default: global.packing.adapter See also pack_options() on page 6-156. Applies to External simple ports whose data element is a composite type (lists and structs)
pack_options()
pass_by_pointer()
When TRUE, composite data (structs or lists) are transferred by reference. Type: bool Default: FALSE (pass by value) See also pass_by_pointer() on page 6-156.
Internal simple or buffer ports whose data element is a composite type (lists and structs)
6.15.2
Port attributes that are potentially valid for all HDL simulators are described in Table 6-2. However, a particular simulator adapter might not implement some of these attributes. If you are using an adapter that is not provided by Cadence, refer to the documentation for that adapter for the list of supported attributes. For Cadence adapters, the port attributes in Table 6-2 enable extended functionality. They cause additional information to be written into the HDL stubs le to enhance user control over the driving of HDL signals. For this reason, if you add or change any attribute shown in Table 6-2, you must rewrite the stubs le. Some of these attributes are similar to Verilog or VHDL unit members, such as verilog variable or vhdl driver.
Example
The following verilog variable declaration
verilog variable 'sig[7:0]' using strobe="#1", drive="#5" ;
is equivalent to the following port attributes:

data : inout simple_port of uint(bits: 8) is instance; keep bind(data, external);
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keep keep keep keep
data.hdl_path()=="sig"; data.declared_range() == "[7:0]"; data.verilog_strobe() == "#1"; data.verilog_drive() == "#5";
Table 6-2 Attribute
Port Attributes for HDL Simulators Description Applies an initial mvl value to the port. Type: list of mvl Default: {} (empty list) See also driver_initial_value() on page 6-149. Applies to External output simple ports
driver_initial_value()
verilog_delta_delay
Requires Specman to sample the old value of the appropriate Verilog signal, as it was one simulator schedulers iteration before the change. Type: bool Default: FALSE See also verilog_delta_delay() on page 6-163.
External input simple ports
verilog_drive()
Species the event on which the data is driven to the Verilog object. Type: string Default: none See also verilog_drive() on page 6-165.
verilog_drive_hold()
Species an event after which the port data is set to Z. Type: string Default: none See also verilog_drive_hold() on page 6-166.
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Table 6-2 Attribute
Port Attributes for HDL Simulators (continued) Description Allows forcing of Verilog wires. Type: bool Default: FALSE See also verilog_forcible() on page 6-166. Applies to External output simple ports
verilog_forcible()
verilog_strobe()
Species the sampling event for the Verilog signal that is bound to the port. Type: string Default: none See also verilog_strobe() on page 6-167.
External input simple ports
verilog_wire()
Binds an external out port to a Verilog wire. Type: bool Default: FALSE See also verilog_wire() on page 6-168.
vhdl_delay_mode()
Species whether pulses whose period is shorter than the delay are propagated through the driver. Type: sn_vhdl_delay_mode Default: TRANSPORT (all pulses, regardless of length, are propagated) See also vhdl_delay_mode() on page 6-169.
vhdl_disconnect_value()
Applies an mvl value to the port when you restore Specman after issuing a test command but do not restart the simulator. Type: list of mvl Default: {} (empty list) See also vhdl_disconnect_value() on page 6-170.
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Port Attributes for SystemC Integration
Table 6-2 Attribute
Port Attributes for HDL Simulators (continued) Description This is an alias for the driver() attribute. Type: bool Default: FALSE See also driver() on page 6-146. Applies to External output simple ports
vhdl_driver()
See Also Predened Attributes and Methods for Any Unit on page 5-18
6.15.3
Port Attributes for SystemC Integration
Port attributes (generic and SystemC-specic) that can be used while coding for SystemC are described in SystemC-Related Port and Unit Attributes on page 5-71 in the Specman Elite Integrators Guide.
6.15.4
agent() Port Attribute
Note The agent() attribute for ports uses the same syntax and follows the same rules as the agent() attribute for units. For more information about this attribute, see agent() Unit Attribute on page 5-22.
6.15.5
Purpose
buffer_size()
Specify the size of a buffer port queue
Category
Buffer port attribute
Syntax
port-exp.buffer_size() == num
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buffer_size()
Syntax Example
keep producer.out_p.buffer_size() == 500;
Parameters
port-exp num An expression of a buffer_port type. An integer specifying the maximum number of elements for the queue.
Description
This attribute determines the number of put() actions that can be performed before a get(). A get() action is required to remove data and make more room in the queue. Specifying a buffer size of 0 means rendezvous-style synchronization. No default buffer size is provided. If a buffer size is not specied in a constraint, an error occurs. It is only necessary to specify a buffer size for one of the two ports in a pair of connected ports. That size applies to both ports. If the two ports have different buffer sizes specied, then both of them get the larger of the two sizes.
Example
Like all port attributes, the buffer size can also be used as an expression.
unit consumer { in_p: in buffer_port of atm_cell is instance; }; unit producer { out_p: out buffer_port of atm_cell is instance; }; extend sys { consumer: consumer is instance; producer: producer is instance; keep bind(producer.out_p, consumer.in_p); keep producer.out_p.buffer_size() == 500; run() is also { // Print the size of the queue outf("Size of the queue is set to %u\n", consumer.in_p.buffer_size()); }; };
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declared_range()
See Also buffer_port on page 6-53
6.15.6
Purpose
declared_range()
Specify the bit width of a multi-bit external object
Category
External port attribute
Syntax
port-exp.declared_range() == string Syntax Example
keep u.p.declared_range() == "[31:0]";
Parameters
port-exp string An expression of a simple port type. An expression in the form:
"[msb:lsb]"
Description
This string attribute is meaningful for external simple ports that are bound to multi-bit objects. Because it is legal to bind a port to an HDL object with a different size, Specman does not extract the range information from the port declaration. In order to implement access to multi-bit signals correctly in the stubs le, this attribute is required by Cadence adapters when using the verilog_wire(), verilog_drive(), verilog_strobe() or driver() attributes. The interpretation of the string is adapter-specic. For Cadence adapters, the declared range must match the actual range of the signal; it cannot be a part select.
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delayed()
Example
unit u { p: simple_port of int is instance; }; extend sys { u: u is instance; keep u.hdl_path() == "top"; keep u.agent() == "Verilog"; keep bind(u.p, external); keep u.p.hdl_path() == "shr"; keep u.p.verilog_wire() == TRUE; keep u.p.declared_range() == "[31:0]"; };
6.15.7
Purpose
delayed()
Specify immediate or delayed propagation of new values
Category
Simple port attribute
Syntax
port-exp.delayed() == bool Syntax Example
keep u.p.delayed() == FALSE;
Parameters
port-exp bool An expression of a simple port type. Either TRUE or FALSE. The default is TRUE.
Description
This Boolean attribute species whether propagation of a new port value assignment occurs immediately or is delayed.
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driver()
When the delayed() attribute is TRUE (the default), propagation of external ports is delayed until the next Specman tick. Propagation of internal ports is delayed until the next Specman tick at which the sys.time value changes. This behavior is consistent with the denition of delayed assignments in e and matches temporal e semantics with regard to the multiple Specman ticks occurring at the same simulator time. To make assigned values on ports visible immediately, constrain this attribute to be FALSE, for example:
keep u.p.delayed() == FALSE;
6.15.8
Purpose
driver()
Create a resolved driver for an external object
Category
External out simple port attribute
Syntax
port-exp.driver() == bool Syntax Example
keep u.p.driver() == TRUE;
Parameters
port-exp bool An expression of a simple port type. Either TRUE or FALSE. The default is FALSE.
Description
This Boolean attribute is meaningful only for external out or inout ports. When this attribute is set to TRUE, an additional resolved HDL or SystemC driver is created for the corresponding simulator item. Every port instance associated with the same simulator can create a separate driver, thus allowing HDL resolution to be applied for multiple Specman unit instances.
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driver()
General Notes For Cadence adapters, if you add or change this attribute, you must rewrite the stubs le. Cadence adapters require that you also use declared_range() if the object that is driven is multi-bit. HDL Notes Cadence Verilog adapters make use of this attribute only if it is applied to an external signal that can
be driven continuously and allows multiple drivers, such as Verilog wires (not registers or memories).
Cadence VHDL adapters make use of this attribute only if the VHDL signals are of a resolved type
(not VHDL variables or signals of unresolved type).
Currently, the continuous driving of VHDL signals is supported only inside a Specman tick that is
synchronized with a VHDL event. This means that you cannot apply the VHDL driver in a mixed Verilog/VHDL design in a Specman tick triggered by a Verilog clock.
SystemC Notes SystemC adapters make use of this attribute only for SystemC sc_in ports that are driven from
Specman. The driver() attribute is required for all such SystemC ports. Note You cannot use the driver() attribute with sc_clock ports.
In addition to driver(), the external_type() attribute must be specied for SystemC sc_in ports that
are driven from Specman.
You can avoid the need for driver() and external_type() by changing the sc_in port to an sc_inout
port.)
Example
In SystemC:
SC_MODULE(mxor) { sc_in<sc_int<50> > inp; }
In Specman:
inp: inout simple_port of int (bits:50) is instance; keep bind(inp, external); keep inp.hdl_path() == "inp"; keep inp.driver() == TRUE; keep inp.external_type() == "sc_int<50>";
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driver_delay()
See Also external_type() on page 6-151 Driving sc_in Ports on page 5-37 in the Specman Elite Integrators Guide
6.15.9
Purpose
driver_delay()
Specify the delay for assignments to a port
Category
External out simple port attribute
Syntax
port-exp.driver_delay() == time Syntax Example
keep u.p.driver_delay() == 10;
Parameters
port-exp time An expression of a simple port type. A value of type time (64 bits). The default is 0.
Description
This attribute of type time is meaningful only for external out ports. It species the delay time for all assignments from Specman to the port. This attribute is silently ignored unless the driver() attribute or the vhdl_driver() attribute is set to TRUE. Note For Cadence adapters, if you add or change this attribute, you must rewrite the stubs le.
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driver_initial_value()
6.15.10 driver_initial_value()
Purpose
Specify an initial value for an HDL object
Category
HDL port attribute
Syntax
port-exp.driver_initial_value() == mvl-list Syntax Example
keep u.p.driver_initial_value() == {MVL_X;MVL_X;MVL_1;MVL_1};
Parameters
port-exp mvl-list An expression that returns a port instance. A lists of mvl values. Possible values are MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, MVL_N. The default is {} (an empty list).
Description
This mvl list type attribute applies an initial mvl value to an external Verilog or VHDL object. This attribute is silently ignored unless the driver() attribute or the vhdl_driver() attribute is set to TRUE. When Specman is driving a std_logic signal that is also driven from VHDL, unless an initial value is specied, the adapter creates a VHDL driver that is initialized by MVL_X.
6.15.11 edge()
Purpose
Specify the edge on which an event is generated
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edge()
Category
Event port attribute
Syntax
port-exp.edge() == edge-option Syntax Example
keep e.edge() == any_change;
Parameters
port-exp edge-option An expression of an event port type. Possible values are of type event_port_edge:
change, rise, fall equivalent to the behavior of @sim temporal expressions.

This means that transitions between x and 0, z and 1 are not detected, x to 1 is considered a rise, z to 0 a fall, and so on. any_change any change within the supported MVL values is detected, including transitions from x to 0 and 1 to z. MVL_0_to_1 transitions from 0 to 1 only. MVL_1_to_0 transitions from 1 to 0 only. MVL_X_to_0 transitions from X to 0 only. MVL_0_to_X transitions from 0 to X only. MVL_Z_to_1 transitions from Z to 1 only. MVL_1_to_Z transitions from 1 to Z only.
The default is change.
Description
This attribute of type event_port_edge for an external event port species the edge on which an event is generated. Note Currently all Cadence adapters support edge attribute only for event ports that are bound to a single-bit DUT signal.
Example
e: in event_port is instance; keep bind(e,external);
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external_type()
keep e.hdl_path() == "clk"; keep e.edge() == any_change;
6.15.12 external_type()
Purpose
Identies the type for an external simulator object that is being driven by Specman
Category
Port attribute
Syntax
[port-exp.]external_type() == string Syntax Example
keep inp.external_type() == "sc_int<50>";
Parameters
port-exp string An expression of a port type. The type for the external simulator object in question, enclosed in double quotes.
Description
Required for all e ports that have the driver() attribute, in order for the signal created by the driver() attribute to be added to the stubs le. The external_type() attribute species the exact type of the corresponding external simulator object, for example, a SystemC sc_in port. Note For Cadence SystemC adapters, if you add or change this attribute, you must rewrite the stubs le.
Example
In SystemC:
SC_MODULE(mxor) { sc_in<sc_int<50> > inp;
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hdl_convertor()
In Specman:
inp: inout simple_port of int (bits:50) is instance; keep bind(inp, external); keep inp.hdl_path() == "inp"; keep inp.driver() == TRUE; keep inp.external_type() == "sc_int<50>";
See Also driver() on page 6-146
6.15.13 hdl_convertor()
Purpose
Species user-dened convertors for external output method ports
Category
Output method port attribute
Syntax
[port-exp.]hdl_convertor() == string Syntax Example
keep mport.hdl_convertor() == "(p : conv_packet) : conv_packet ";
Parameters
port-exp An expression of a port type.
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hdl_convertor()
string
Species user-dened convertors for a method port. The string has the following syntax: (argument-name: convertor-name [, argument-name: convertor-name...]) [: result-convertor] Note The parentheses inside the string are required. You must specify argument-name : convertor-name for each method-port argument that requires a user-dened convertor:
The argument-name is the name as it appears in the method type. The convertor-name is the name of the external convertor. The result-convertor is the name of the external convertor for the result returned by the
method.
Description
hdl_convertor() species type or size casting operations for method parameters. This attribute is required to specify user dened convertors to convert arguments of method ports between Specman and SystemC. Note For Cadence SystemC adapters, if you add or change this attribute, you must rewrite the stubs le.
Example
In SystemC:
SC_MODULE(module) { Packet packet_func( Packet& packet1, int number ) { ... } }
In Specman:
method_type packet_mt( p : packet, i : int ) : packet; unit foo { mport : out method_port of packet_mt is instance; keep bind( mport, external ); keep mport.hdl_path() == "packet_func"; keep mport.hdl_convertor() == "(p : conv_packet) : conv_packet "; };
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e Ports
hdl_path() Port Attribute
See Also method_type method-type-name on page 6-63 Using Method Ports Overview on page 6-39 Method Types on page 6-44 Creating Type Convertors for Method Port Arguments on page 5-56 in the Specman Elite Integrators
Guide
6.15.14 hdl_path() Port Attribute

Purpose
Map port instance to an external object
Category
Port attribute
Syntax
port-exp.hdl_path() == string Syntax Example
clk: in event_port is instance; keep clk.hdl_path() == "clk";
Parameters
port-exp string An expression of a port type. The path to the external object, enclosed in double quotes. The default is an empty string.
Description
To access an external, simulated object, you must provide a path to the object with the hdl_path() attribute. This path is a concatenation of the partial paths you provide for the port itself and for its enclosing units. The partial paths can contain any separator that is supported by the adapter for the simulator you are using.
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hdl_path() Port Attribute
To allow portability between simulators, you can use es canonical path notation. (See the documentation for the adapter for a description of supported separators.) Note For Cadence adapters, if you add or change this attribute, you must rewrite the stubs le.
Example
In this example, all ports inherit the Verilog simulator specied as the agent for the encoder instance. The clk, data_width, data and rq ports access Verilog signals of the same name in the top-level module priority_encoder. The address port accesses a signal with the path priority_encoder.PRIO.temp_address.
unit encoder { clk: in event_port is instance; keep bind(clk, external); keep clk.hdl_path() == "clk"; data_length: in simple_port of uint is instance; keep bind(data_length, external); keep data_length.hdl_path() == "data_width"; data: inout simple_port of list of bit is instance; keep bind(data, external); keep data.hdl_path() == "data"; keep data.verilog_wire() == TRUE; -- simple port attribute keep data.declared_range() == "[31:0]"; -- simple port attribute address: in simple_port of uint is instance; keep bind(address, external); keep address.hdl_path() == "PRIO/temp_address"; rq: in keep keep keep buffer_port of bool is instance; bind(rq, external); rq.buffer_size() == 8; -- buffer port attribute rq.hdl_path() == "rq";
extend sys { e: encoder is instance; keep e.hdl_path() == "~/priority_encoder"; };
See Also hdl_path() Unit Attribute on page 5-19

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e Ports
pack_options()
HDL Object Names on page 9-6 in the Specman Elite Integrators Guide
6.15.15 pack_options()
Purpose
Specify how an external ports data element is implicitly packed and unpacked
Category
External simple port attribute
Syntax
port-exp.pack_options() == pack-option Syntax Example
keep u.p.pack_options() == packing.low_big_endian;
Parameters
port-exp pack-option An expression of a simple or buffer port type. A predened or user-dened pack option. The default is global.packing.adapter.
Description
This attribute of type pack_options is meaningful only for external ports whose data element is a composite type (lists and structs). It affects the way a ports data element is implicitly packed and unpacked. This attribute exists both for units and ports and may be propagated downwards from an enclosing unit instance to its ports and other unit instances. Note None of the existing simulator adapters supports external simple port of structs.
6.15.16 pass_by_pointer()
Purpose
Specify how composite data is transferred by internal ports
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sc_variable()
Category
Internal port attribute
Syntax
port-exp.pass_by_pointer() == bool Syntax Example
keep u.p.pass_by_pointer() == TRUE;
Parameters
port-exp bool An expression of a simple or buffer port type. Either TRUE or FALSE. The default is FALSE.
Description
This Boolean attribute species how composite data (structs or lists) are transferred by internal simple ports or buffer ports. By default, this attribute is FALSE and complex objects are deep-copied upon an internal port access operation. To pass data by reference and speed up the test, you can set this attribute to TRUE. If you do so, you must write your code such that it does not result in test correctness violations. If one port in a bound set has pass_by_pointer() set to TRUE, this attribute is set to TRUE for all other ports in a bound set. There is also a global cong misc option, ports_data_pass_by_pointer. Setting this option inuences all internal ports.
6.15.17 sc_variable()
Purpose
Identies SystemC class elds and global variables to Specman
Category
SystemC simple port attribute
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e Ports
sc_variable()
Syntax
port-exp.sc_variable() == bool Syntax Example
keep mxor_field.sc_variable() == TRUE;
Parameters
port-exp bool An expression of a simple port type for accessing a SystemC class eld or global variable. Either TRUE or FALSE. The default is FALSE.
Description
The sc_variable() attribute is necessary to identify SystemC class elds and global variables to Specman. The SystemC object can be of any supported type (see SystemC Types That Are Automatically Converted on page 5-53 in the Specman Elite Integrators Guide).
Example
In SystemC:
SC_MODULE(mxor) { sc_bv<80> > field; }
In Specman:
mxor_field: inout simple_port of uint (bits: 80) is instance; keep bind(mxor_field, external); keep mxor_field.hdl_path() == "field"; keep mxor_field.sc_variable() == TRUE; // required
See Also Accessing SystemC Class Fields or Global Variables on page 5-38 in the Specman Elite Integrators
Guide
SystemC Types That Are Automatically Converted on page 5-53 in the Specman Elite Integrators
Guide
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e Ports
sensitive()
6.15.18 sensitive()
Purpose
Specify that an @sim event can be dened for this simple e port
Category
Simple port attribute
Syntax
port-exp.sensitive() == bool Syntax Example
keep clk.sensitive() == TRUE;
Parameters
Description
A boolean attribute named sensitive() species that an @sim event can be dened for this e port. @sim is a special annotation used to detect changes in external signals. When the sensitive() attribute is set to TRUE, additional code is generated in the Specman stubs le to enable change notication. Trying to dene an @sim event for a simple e port without the sensitive() attribute set to TRUE results in a run time error.
Example
In SystemC:
sc_clock clk;
In Specman:
clk: in simple_port of bool is instance; keep bind(clk, external); keep clk.hdl_path() == "clk";
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static_sensitivity()
keep clk.sensitive() == TRUE; event clk is fall(clk$) @sim;
6.15.19 static_sensitivity()
Purpose
Use an external out method port to call a time-consuming external function from e code
Category
Method port attribute
Syntax
port-exp.static_sensitivity() == string Syntax Example
keep func.static_sensitivity() == append(full_hdl_path(), "ev");
Parameters
port-exp string An expression of an external out method port type. The full path to the external static sensitivity event, enclosed in double quotes. In SystemC: the full path to a SystemC static sensitivity event, dened in SC_MODULE.
Description
The attribute static_sensitivity() lets you use an external out method port to call a time-consuming external function from e code. SystemC Notes The SystemC function must contain:
A static sensitivity event, dened in the SC_MODULE constructor. A wait statement with no arguments.
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static_sensitivity()
The e code must contain an external out method port whose static_sensitivity() attribute species the global path to the event in SystemC. The SystemC thread waits on the static event specied for the external out method port.
Example
In the following SystemC code example, ev is the static sensitivity event for func. Any wait action with no arguments inside the time-consuming function waits on this static event.
SC_MODULE(my_module) { void func() { cout << "Beginning of func" << endl; for ( int i = 0 ; i < 4 ; ++i ) { wait(); -- wait on static event 'ev' }; }; sc_event ev; SC_CTOR(module) { SC_THREAD(func); sensitive << ev; }; }; extern my_module* my_top;
To call my_top->func() via an external out method port, you specify my_top->ev as the static event, using the port attribute static_sensitivity().
method_type ft(); extend sys { v : verifier is instance; keep v.hdl_path() == "sn_top->"; keep v.agent() == "SYSTEMC"; }; unit verifier { func : out method_port of ft is instance; keep bind(func,external); keep func.hdl_path() == "func"; keep func.static_sensitivity() == append(full_hdl_path(), "ev"); };
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e Ports
sync_mode()
6.15.20 sync_mode()
Purpose
Synchronize an e input method port call from an external simulator object
Category
Method port attribute
Syntax
port-exp.sync_mode() == sync-options Syntax Example
keep func.sync_mode() == async_tick_call;
Parameters
port-exp sync-options An expression of an input method port type. One of the following:
sync_call (default value) The call is executed at the beginning of the next
Specman tick.
async_callThe e method is invoked immediately, regardless of the status of the

simulation cycle.
async_tick_callA Specman tick is created immediately, regardless of the status

of the simulation cycle, and the e method is invoked in this Specman tick. See the description below for more details.
Description
When an e input method port is called from the external simulator object, the synchronization of this call depends on the sync_mode() value for the port. This attribute has three possible values:
sync_call (default value): The call is executed at the beginning of the next Specman tick. In this case,
the caller is blocked even if the input method port is a non-time-consuming method port. Thus, for example, input method ports dened with sync_call must be called from a SystemC thread and not from a SystemC method.
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e Ports
verilog_delta_delay()
async_callThe e method is invoked immediately, regardless of the status of the simulation cycle: Specifying async_call for a time-consuming method port is illegal. From the run-time performance point of view, this kind of method call is the fastest.
Warning if there is an error in Specman when async_call is in effect, the error is not handled correctly. Thus, using this value can be unsafe. To avoid problems use async_call only when the e method is short and does not activate any complex activities on the Specman side, such as generation.
async_tick_callA Specman tick is created immediately, regardless of the status of the simulation
cycle, and the e method is invoked in this Specman tick. A call for a non-time-consuming e method is not blocked in this case. async_tick_call makes the method call safe, but slows the runtime performance. Warning It is strongly recommended not to drive any DUT signals from the e method when async_tick_call is in effect, because it may cause race conditions in the entire environment.
6.15.21 verilog_delta_delay()
Purpose
Require sampling of old value
Category
Verilog port attribute for input simple ports
Syntax
port-exp.verilog_delta_delay() == bool Syntax Example
keep u.p.verilog_delta_delay() == TRUE;
Parameters
port-exp bool An expression of an input simple port type. Either TRUE or FALSE. The default is FALSE.
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verilog_delta_delay()
Description
This attribute requires Specman to sample the old value of the appropriate Verilog signal, as it was one simulator schedulers iteration before the change. This attribute is functionally equivalent to a verilog variable using delta_delay declaration. For example, if you need to sample the value of a signal that is assigned with a blocking assignment on the clock edge before the new value is propagated, you should set this attribute to TRUE.
Example
This example requires Specman to sample the value of top.data before the rising edge of top.clk. Verilog code
module top; reg clk; reg data; initial clk = 0; initial data = 0; always @(posedge clk) data = clk; endmodule
e code
<' extend sys { event clock is rise('top.clk')@sim; data: in simple_port of bit is instance; keep data.hdl_path() == "top.data"; keep data.verilog_delta_delay() == TRUE; on clock { out ("data = ", 'top.data', " ", data$); }; }; '>
Note For Cadence adapters, if you add or change this attribute, you must rewrite the stubs le.
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verilog_drive()
6.15.22 verilog_drive()
Purpose
Specify timing control for data driven to the Verilog object
Category
Verilog port attribute
Syntax
port-exp.verilog_drive() == timing-control Syntax Example
keep u.p.verilog_drive() == "@posedge clk2";
Parameters
port-exp timing-control An expression of a simple port type. A string specifying any legal Verilog timing control (event or delay).
Description
This string attribute tells an external output port to drive its data to the Verilog signal when the specied timing occurs. It can be either a Verilog temporal expression such as @(posedge top.clk) or a simple delay of kind #1. This attribute is functionally equivalent to a verilog variable using drive declaration.
Notes For Cadence adapters, if you add or change this attribute, you must rewrite the stubs le. Cadence adapters require that you also use declared_range() if the object that is driven is multi-bit.
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verilog_drive_hold()
6.15.23 verilog_drive_hold()
Purpose
Specify when to set the port to Z
Category
Syntax
port-exp.verilog_drive_hold() == event Syntax Example
keep u.p.verilog_drive() == "@posedge clk2"; keep u.p.verilog_drive_hold() == "@negedge clk2";
Parameters
port-exp event An expression of a simple port type. A string specifying any legal Verilog timing control.
Description
On the rst occurrence of the specied event after Specman drive the port data, the value of the corresponding Verilog signal is set to Z. The event is a string specifying any legal Verilog timing control. This attribute requires that you also specify the verilog_drive() attribute.
6.15.24 verilog_forcible()
Purpose
Species that a Verilog object can be forced
Category
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verilog_strobe()
Syntax
port-exp.verilog_forcible() == bool Syntax Example
keep u.p.verilog_wire() == TRUE; keep u.p.verilog_forcible() == TRUE;
Parameters
Description
This Boolean attribute allows forcing of Verilog wires. By default Verilog wires are not forcible. This attribute requires that you also specify the verilog_wire() attribute.
6.15.25 verilog_strobe()
Purpose
Specify the sampling event for a Verilog object
Category
Syntax
port-exp.verilog_strobe() == event Syntax Example
keep u.p.verilog_strobe() == "@posedge clk1";
Parameters
port-exp An expression of a simple port type.
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verilog_wire()
event
A string specifying any legal Verilog timing control.
Description
This string attribute species the sampling event for the Verilog signal that is bound to an external input port. This attribute is equivalent to the verilog variableusing strobe declaration.
6.15.26 verilog_wire()
Purpose
Create a single driver for a port (or multiple ports)
Category
Syntax
port-exp.verilog_wire() == bool Syntax Example
keep u.p.verilog_wire() == TRUE;
Parameters
Description
This Boolean attribute allows an external out port to be bound to a Verilog wire, in a manner similar to a verilog variable using wire declaration.
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e Ports
vhdl_delay_mode()
The main difference between this attribute and the driver() attribute is that, being backward compatible, the verilog_wire() attribute merges all of the ports that have this attribute into a single Verilog driver, while the driver() attribute creates a separate driver for each port.
6.15.27 vhdl_delay_mode()
Purpose
Specify whether short pulses are propagated through driver
Category
HDL port attribute
Syntax
port-exp.vhdl_delay_mode() == mode-option Syntax Example
keep u.p.vhdl_driver() == TRUE; keep u.p.driver_delay() == 10; keep u.p.vhdl_delay_mode() == INERTIAL;
Parameters
port-exp mode-option An expression of a simple port type. Either TRANSPORT (the default) or INERTIAL.
Description
This sn_vhdl_delay_mode type attribute applies a VHDL delay mode value to an external out port. This attribute species whether pulses whose period is shorter than the delay specied by the driver_delay() attribute are propagated through the driver. INERTIAL species that such pulses are not propagated. TRANSPORT species that all pulses, regardless of length, are propagated.
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e Ports
vhdl_disconnect_value()
This attribute also inuences what happens if another driver (either VHDL or another unit) schedules a signal change and before that change occurs, this driver schedules a different change. With INERTIAL, the rst change never occurs. This attribute is silently ignored unless the driver_delay() attribute is also specied.
6.15.28 vhdl_disconnect_value()
Purpose
Specify value to apply on Specman restore
Category
HDL port attribute
Syntax
port-exp.vhdl_disconnect_value() == mvl-value-list Syntax Example
keep u.p.vhdl_disconnect_value() == {32'bz};
Parameters
port-exp mvl-value-list An expression that returns a port instance. A list of one or more of the following: MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, MVL_N.
Description
This mvl type attribute applies an mvl value to an external output port when you restore Specman after issuing a test command but do not restart the simulator. This value should be set to a value that does not affect the overall value of the resolved signal. In the ModelSim VHDL adapter the default value for std_logic signals is MVL_Z. This attribute is silently ignored unless the driver() attribute or the vhdl_driver() attribute is set to TRUE.
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e Ports
Global MVL Conversion Routines
6.16 Global MVL Conversion Routines

The global routines for manipulating MVL values are:
string_to_mvl() on page 6-171 mvl_to_string() on page 6-172 mvl_to_int() on page 6-174 int_to_mvl() on page 6-175 mvl_to_bits() on page 6-176 bits_to_mvl() on page 6-177 mvl_to_mvl4() on page 6-178 mvl_list_to_mvl4_list() on page 6-179 string_to_mvl4() on page 6-180
6.16.1
Purpose
string_to_mvl()
Convert a string to a list of mvl values
Category
Predened routine
Syntax
string_to_mvl(value-string: string): list of mvl Syntax Example
mlist = string_to_mvl("8'bxz1");
Parameters
value-string A string representing mvl values, consisting of a width and base followed by a series of characters corresponding to mvl values. Format of the input string is the same as in Verilog literals, except there are additional 9-value logic digits: u, l, h, w and n.
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e Ports
mvl_to_string()
Description
Converts each character in the input string to an mvl value.
Example
var mlist: list of mvl; mlist = string_to_mvl("8'bz"); // returns {MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z}; mlist = string_to_mvl("8'bxz1"); // returns {MVL_1; MVL_Z; MVL_X; MVL_X; MVL_X; MVL_X; MVL_X; MVL_X};
See Also mvl_to_string() on page 6-172
6.16.2
Purpose
mvl_to_string()
Convert a list of mvl values to a string
Category
Predened routine
Syntax
mvl_to_string(mvl-list: list of mvl, radix: radix): string Syntax Example
mstring = mvl_to_string({MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_X; MVL_X; MVL_X; MVL_X}, BIN);
Parameters
mvl-list radix A list of mvl values. One of BIN, OCT, or HEX.
6-172
e Ports
mvl_to_string()
Description
Converts a list of mvl values to a string. The mapping is done in the following way:
MVL_U MVL_X MVL_0 MVL_1 MVL_Z MVL_W MVL_L MVL_H MVL_N is converted to character "u" (lowercase) - "x" - "0" - "1" - "z" - "w"; - "l" - "h" - "n"
Note This routine always returns a sized number as a string.
Example 1
var mstring: string; mstring = mvl_to_string({MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_X; MVL_X; MVL_X; MVL_X}, BIN); // returns "8b'zzzzxxxx"
Example 2
var l: list of mvl = {MVL_1;MVL_0}; print mvl_to_string(l, BIN); --prints 2'b10 print mvl_to_string(l, HEX); --prints 2'h2
See Also string_to_mvl() on page 6-171 mvl_to_int() on page 6-174 mvl_to_bits() on page 6-176 mvl_to_mvl4() on page 6-178 mvl_list_to_mvl4_list() on page 6-179
6-173
e Ports
mvl_to_int()
6.16.3
Purpose
mvl_to_int()
Convert an mvl value to an integer
Category
Predened routine
Syntax
mvl_to_int(mvl-list: list of mvl, mask: list of mvl): uint Syntax Example
var ma: uint = mvl_to_int(l, {MVL_X});
Parameters
mvl-list mask A list of mvl values to convert to an integer value. A list of mvl values that are to be converted to 1.
Description
Converts each value in a list of mvl values into a binary integer (1 or 0), using a list of mvl mask values to determine which mvl values are converted to 1. When the list is less than 32 bits, it is padded with 0. When it is greater than 32 bits, it is truncated, leaving the 32 least signicant bits.
Example
var l: list of mvl = {MVL_X; MVL_X; MVL_0; MVL_1}; var ma: uint = mvl_to_int(l,{MVL_X}); // returns 12 (0b1100) var mb: uint = mvl_to_int(l, {MVL_Z}) // returns 0
See Also int_to_mvl() on page 6-175

6-174
e Ports
int_to_mvl()
mvl_to_bits() on page 6-176 mvl_to_mvl4() on page 6-178 mvl_list_to_mvl4_list() on page 6-179
6.16.4
Purpose
int_to_mvl()
Convert an integer value to a list of mvl values
Category
Predened routine
Syntax
int_to_mvl(value: uint, mask: mvl): list of mvl Syntax Example
var mlist: list of mvl = int_to_mvl(12, MVL_X)
Parameters
value mask An integer value to convert to a list of mvl values. An mvl value that replaces each bit in the integer that has the value 1.
Description
Maps each bit that has the value 1 to the mask mvl value, retains the 0 bits as MVL_0, and returns a list of 32 mvl values. The returned list always has a size of 32.
Example
var mlist: list of mvl = int_to_mvl(12, MVL_X) // returns MVL_0;..........MVL_X;MVL_X;MVL_0;MVL_0
6-175
e Ports
mvl_to_bits()
See Also mvl_to_int() on page 6-174
6.16.5
Purpose
mvl_to_bits()
Convert a list of mvl values to a list of bits
Category
Predened routine
Syntax
mvl_to_bits(mvl-list: list of mvl, mask: list of mvl): list of bit Syntax Example
var bl: list of bit = mvl_to_bits({MVL_Z; MVL_Z; MVL_X; MVL_L}, {MVL_Z; MVL_X})
Parameters
mvl-list mask A list of mvl values to convert to bits. A list of mvl values that species which mvl values are to be converted to 1.
Description
Converts a list of mvl values to a list of bits, using a mask of mvl values to indicate which mvl values are converted to 1 in the list of bits.
Example
var bl: list of bit = mvl_to_bits({MVL_Z; MVL_Z; MVL_X; MVL_L}, {MVL_Z; MVL_X}) // returns {1; 1; 1; 0}
6-176
e Ports
bits_to_mvl()
See Also mvl_to_string() on page 6-172 mvl_to_int() on page 6-174 mvl_to_mvl4() on page 6-178
6.16.6
Purpose
bits_to_mvl()
Convert a list of bits to a list of mvl values
Category
Predened routine
Syntax
bits_to_mvl(bit-list: list of bit, mask: mvl): list of mvl Syntax Example
var ml: list of mvl = bits_to_mvl({1; 0; 1; 0}, MVL_Z)
Parameters
bit-list mask A list of bits to convert to mvl values. An mvl value that replaces each bit in the list that has the value 1.
Description
Maps each bit with the value 1 to the mask mvl value, retains the 0 bits as MVL_0, and returns an mvl list that is bit-list size.
Example
var ml: list of mvl = bits_to_mvl({1; 0; 1; 0}, MVL_Z) // returns {MVL_Z;MVL_0;MVL_Z;MVL_0}
6-177
e Ports
mvl_to_mvl4()
See Also mvl_to_bits() on page 6-176
6.16.7
Purpose
mvl_to_mvl4()
Convert an mvl value to a 4-value logic value
Category
Predened routine
Syntax
mvl_to_mvl4(value: mvl): mvl Syntax Example
var m4: mvl = mvl_to_mvl4(MVL_U)
Parameters
value An mvl value to convert to a 4-value logic value
Description
Converts an mvl value to the appropriate 4-value logic subset value. The predened mapping from 9-value logic to 4-value logic is:
MVL_U, MVL_W, MVL_X, MVL_N -> MVL_X MVL_L ,MVL_0 -> 0 MVL_H, MVL_1 -> 1 MVL_Z -> MVL_Z
Example
var m4: mvl = mvl_to_mvl4(MVL_U) // returns MVL_X
6-178
e Ports
mvl_list_to_mvl4_list()
See Also mvl_to_string() on page 6-172 mvl_to_int() on page 6-174 mvl_to_bits() on page 6-176 mvl_list_to_mvl4_list() on page 6-179
6.16.8
Purpose
mvl_list_to_mvl4_list()
Convert a list of mvl values to a list of 4-value logic subset values
Category
Predened routine
Syntax
mvl_list_to_mvl4_list(mvl-list: list of mvl): list of mvl Syntax Example
var m4l: list of mvl = mvl_list_to_mvl4_list({MVL_N; MVL_L; MVL_H; MVL_1})
Parameters
mvl-list A list of mvl values to convert to a list of 4-value logic subset values
Description
Converts each value in a list of mvl values to the corresponding 4-value logic value. The predened mapping from 9-value logic to 4-value logic is:
MVL_U, MVL_W, MVL_X, MVL_N -> MVL_X MVL_L, MVL_0 -> MVL_0 MVL_H, MVL_1 -> MVL_1 MVL_Z -> MVL_Z
6-179
e Ports
string_to_mvl4()
Example
var m4l: list of mvl = mvl_list_to_mvl4_list({MVL_N; MVL_L; MVL_H; MVL_1}) // returns {MVL_X; MVL_0; MVL_1; MVL_1;}
See Also mvl_to_string() on page 6-172 mvl_to_int() on page 6-174 mvl_to_bits() on page 6-176 mvl_to_mvl4() on page 6-178
6.16.9
Purpose
string_to_mvl4()
Convert a string to a list of 4-value logic mvl subset values
Category
Predened routine
Syntax
string_to_mvl4(value-string: string): list of mvl Syntax Example
mlist = string_to_mvl("8'bxz");
Parameters
value-string A string representing MVL values, consisting of a width and base followed by a series of characters corresponding to 9-value logic values.
Description
Converts each character in the string to the corresponding 4-value logic value. If the string contains characters other than 0, 1, x, z, h, l, u, w or n a runtime error is issued.
6-180
e Ports
Port-Related Commands
Example
var mlist: list of mvl; mlist = string_to_mvl4("8'bz"); // returns {MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z; MVL_Z}; mlist = string_to_mvl("8'bxz"); // returns {MVL_Z; MVL_X; MVL_X; MVL_X; MVL_X; MVL_X; MVL_X; MVL_X};
See Also string_to_mvl() on page 6-171 mvl_to_string() on page 6-172 mvl_to_mvl4() on page 6-178 mvl_list_to_mvl4_list() on page 6-179
6.17 Port-Related Commands

Specman commands related to ports are described in this section. The commands are:
show ports on page 6-181 trace ports on page 6-183 trace bind on page 6-185
6.17.1
Purpose
show ports
Lists ports with basic information
Category
Command
Syntax
show ports [-full] [wildcard-pattern] Syntax Example
show ports -full rx.trans;
6-181
e Ports
show ports
Parameters
full wildcard-pattern Show additional information about the listed ports, such as connectivity and agent. The pattern is unit-name.port-name, with the default of *.*
Description
Unless a specic expression is given, this command lists all ports. Without the -full option, only the e path and the port declaration are displayed. With the -full option, the following information is also displayed:
The agent attached to the port The hdl_path() attribute of the port (if set) The ports bound to that port (if any) Example 1
show ports
Results
Ports = 0. sys.ver.dut_inp - OSCI out simple_port of int (bits: 2) 1. sys.ver.dut_out - OSCI in simple_port of uint
Example 2
show ports -full
Results
Ports = 0. sys.ver.dut_inp - out simple_port of int (bits: 2) e_path: sys.ver.dut_inp agent: osci hdl_path: sn_xor->/inp 1. sys.ver.dut_out - in simple_port of uint e_path: sys.ver.dut_out agent: osci hdl_path: sn_xor->/out 2. sys.ver.clk - in event_port e_path: sys.ver.clk
6-182
e Ports
trace ports
agent: osci hdl_path: sn_xor->/clk
See Also trace ports on page 6-183
6.17.2
Purpose
trace ports
Trace activity on ports
Category
Command
Syntax
tra[ce] non_external_port-activity [off] [unit-wildcard.port-wildcard] tra[ce] external_port-activity [off] [[agent-wildcard.]unit-wildcard.port-wildcard]
Parameters
non_external_ The type of non-external activity to be traced for the specied ports. This may be one of port-activity the following: ports simple_ports event_ports buffer_ports write_simple_port, read_simple_port emit_event_port, occur_event_port Trace all ports and all activities Trace all activities of simple ports Trace all activities of event ports Trace all activities of buffer ports Trace write or read activities of simple ports Trace event emitting and event occurrence of an event port
6-183
e Ports
trace ports
write_buffer_port, read_buffer_port external_ port-activity
Trace write or read activities of buffer ports
Trace only the external activities of the specied port kind. This may be one of the following: external_simple_port, external_buffer_port, external_event_port, external_method_port Note You can precede the unit-wildcard.port-wildcard with an agent name, for example trace external_simple_ports verilog.*.*, or agent wildcard. (See the denition of agent_wildcard below.)
off unit-wildcard port-wildcard
If port tracing has previously been turned on, then turn it off. The name of the unit type in which the port is dened. Wildcards are allowed. The name of a eld of type port or of type list of port. Wild cards are allowed. If the eld is of type list of port, all the port instances in the list are traced.
agent-wildcard The name of the external agent type for which the port is dened. See agent() Unit Attribute on page 5-22 for the list of predened agent names. Wildcards are allowed.
Description
This command enables tracing of activity on a port or all ports that match the specied expression. Note Tracing port references is not supported. You can only trace port instances or lists of port instances.
Example 1
The following example command turns on tracing of all port activities for all u1 ports, where u1 is the unit type name.
cmd-prompt> trace ports u1.*
Example 2
The following example command turns on tracing of all external simple port activities for all existing ports
cmd-prompt> trace external_simple_port *.*.*
See Also show ports on page 6-181

6-184
e Ports
trace bind
6.17.3
Purpose
trace bind
Turn on or off the tracing of the port binding process
Category
Command
Syntax
tra[ce] bind [on | off]
Description
This command prints the status of all port bindings that result from declarative binding and displays step-by-step the procedural binding process. The source reference for any method related to procedural binding is printed, followed by information on the result of the binding.
Example
The following example command turns on tracing of port binding
cmd-prompt> trace bind
6-185
e Ports
trace bind
6-186

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6

Advantages of Using Ports

Creating Port Instances

Port type is dened by three aspects:

Referencing Port Instances

any_simple_port any_buffer_port any_event_port any_method_port

See Also Dening and Referencing Ports on page 6-49

See Also Port Attributes on page 6-135

Accessing Ports and Port Values

See Also Port-Related Commands on page 6-181

Accessing Port Values

Using Port Values and Attributes in Constraints

// Use port$ to set a value

Adding a constraint such as

silently sets synthesized() to TRUE.

Creating and Using Port Bindings

Dening and Disconnecting Port Bindings on page 6-66

Declarative and Procedural Port Bindings

You can bind ports either declaratively or procedurally.

keep bfm.sigmap == read_only(sigmap); keep agent.id == read_only(id);

Procedural binding is recommended for:

You can also extend connect_ports() to

do_bind(a, b); do_bind(a, c); do_bind(a, d);

is exactly the same as:

or any other combination. In all cases, if you type:

This section contains the following:

Multiple Bindings for Simple Ports

do_bind(p1, p2); }; keep p2.delayed() == FALSE;

Multiple Bindings with External Simple Ports

Multiple Bindings for Event Ports

Multiple Bindings for Method Ports

var r : report = new; r.id = my_id; r.res = TRUE; l.add(r); }; };

you can do the following:

and nally use:

Implicit External Binding

Disabling Implicit Binding

See Also disconnect() on page 6-82 disconnect_bound_set() on page 6-83

Disconnected Ports and Dangling Ports

A disconnected port is one of the following:

An empty-bound event port can be emitted.

Then, for example, you can do

See Also do_bind_unit() on page 6-77

Port Binding and Rule Checking During Generation

Querying the State of Port Bindings

Using bind() in Queries

Using get_bound_set() in Queries

See Also get_bound_set() on page 6-84

Using is_connected() in Queries

You can use is_connected() to determine whether a port is connected or not.

See Also is_connected() on page 6-85

Using Commands to Query Port Bindings

The show ports command displays the ports bound to a port

See Also show ports on page 6-181

trace bind on page 6-185

Using Simple Ports

Accessing Simple Ports and Their Values

Examples of Accessing Port Values

force p$ = 0; print q$[1:0]; print q$[2:2]; print sys.pp$;

Could be written (listbl[0])$[1]. listbl is dened as:

Examples of Accessing a Port

Prints the information about port p. Port p is dened as:

Port reference r refers to the port instance p too. It is dened as: