Crosstalk & Power Reduction in on Chip-VLSI Interconnect by using Bus Encoding Technique

A synopsis submitted in partial fulfillment of the requirements for the award of the degree of Bachelor of Technology. (Electronics and Communication Engineering) To Gautam Buddh Technical University, Lucknow

Prashant Kesarwani (0806831052) Rohit Singh (0806831062) Shivam Bansal (0806831073) Shubham Singhal (0806831075)

Under the guidance of Shri H.P Singh Sr. Lecturer Department of Electronics & Communication Engineering Meerut Institute of Engineering & Technology

Broad area of the project

The feature size of integrated circuits has been aggressively reduced in the pursuit of improved speed, power, silicon area and cost characteristics. Semiconductor technologies with feature sizes of several tens of nanometers are currently in development. As per, International Technology Roadmap for Semiconductors (ITRS), the future nanometer scale circuits will contain more than a billion transistors and operate at clock speeds well over 10GHz. Distributing robust and reliable power and ground lines; clock; data and address; and other control signals through interconnects in such a high-speed, high-complexity environment, is a challenging task. The function of interconnects or wiring systems is to distribute clock and other signals and to provide power/ground to and among the various circuits/systems functions on the chip. The performance i.e. time delay and power dissipation of a high speed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. In current DSM (Deep Submicron) technology, coupling capacitance plays an important role for deciding the behavior of on-chip interconnects. Due to the coupling capacitance, crosstalk, delay and power consumption problems will arise. The above problems are very much dependent on the frequency of signal used, length of interconnects etc. The components that affect the behavior of the on-chip bus are internal parasitic capacitances of the transistors, interconnect capacitances and input capacitances of the fan out gates. The most common methods to reduce crosstalk, propagation delay and power are:

Insert repeater Insert shielding between adjacent wires Introduction of intentional delay among coupled signal transmission. Bus encoding methods. The use of tight geometry in most systems can reduce crosstalk significantly. Use maximum allowable spacing between signal lines Minimize spacing between signal and ground lines etc.

Proposed title of the project

The proposed title for the project as per the consultation of the project guide and the group members is

Crosstalk & Power Reduction in on Chip-VLSI interconnect by using Bus encoding technique

Brief of the proposed work

Bus Encoding is widely used technique to reduce dynamic switching power and the effects of crosstalk (signal
noise, delay) during data transmission on buses. Low power encoding techniques aims to transform the data being transmitted on buses in such a manner, so that the self and coupling switching activity on buses reduced. Crosstalk aware encoding techniques also modify the switching patterns of a group of wires to reduce crosstalk coupling effect. These techniques are extremely valuable for reducing power consumption, improving transmission reliability, and increasing system performance. For any encoding scheme, the encoder and decoder functions are the inverse of one another. Bus encoding schemes can be classified according to several criteria, such as the Type of code used (algebraic, permutation, or probability based), the degree of encoding adaptability (static or dynamically adaptable encoding), the targeted capacitance for switching reduction (self, coupling, or both), the amount of extra information needed for coding (redundant or irredundant coding), and the method of encoding implementation (hardware, software, or a combination of the two). Encoding techniques are often aimed at power reduction, signal transmission delay reduction and reliability improvement, or a combination of these due to the reduction in the transition. Certain optimizations such as crosstalk reduction can have multiple benefits associated with them, such as power reduction, signal delay reduction, and noise reduction.

120 100 80 60 40 20 0 Type2 Type3 Type4 Achieved Reduction Projected Reduction

Fig: Reduction of crosstalk (typewise)

Estimation of power and crosstalk in RC bus model

The total power consumption in the VLSI chip comprises of dynamic power, short circuit power, static power and leakage power. It can be simply described as summation of all these components i.e; P
Dissipation

=P +P
Static

Dynamic

+L

eakage

+P

Shortckt

The capacitance of interconnect can be classified as coupling capacitance and self capacitance. The coupling Capacitance is the capacitance between the adjacent wires while the self capacitance refers to the capacitance between the substrate and the wire itself. The dynamic power in VLSI chip decides the behavior of chip and it highly dependent on the load capacitance and coupling capacitance i.e. bus line signal transitions. The coupling between the groups of the three wires is classified into five Types depending upon the nature of transitions of signals in the wire that are Type-0, Type-1, Type-2, Type-3 and Type-4. The Type-0 coupling occurs when all of the 3-bit wires are in the same state transition. A transition from 000 to 111, causes a Type-0 coupling. For Type-0, coupling capacitance is zero. Type-1 coupling occurs when there is a transition in one or the two wires (including the centre wire) and the third wire remains quite. There are eight possibilities by which Type-1 condition occur. The coupling capacitance in this case is CC. A Type-2 coupling occurs when the centre wire is in the opposite state transition with one of its adjacent wires while the other wires undergo the same state transition as the centre wire i.e.100 to 011. Ten different conditions are possible for Type-2 coupling. The coupling capacitance is 2*CC in this case. A Type-3 coupling occurs when the centre wire undergoes the opposite state transition with one of the two wires while the other wires are quiet i.e. 010 to 001. Coupling capacitance in the case of Type-3 coupling is 3*CC and there are four possibilities that causes Type-3 coupling.

For a Type-4 coupling, all three wire transitions in the opposite states with respect to each other. Two conditions causes Type-4 coupling with a coupling capacitance effect of 4*CC. All the five Types of couplings are shown in Table-1. Table-1: Crosstalk Types for a 3-bit bus Type-0
___

Type-1 __
_ __ _ __ _ __ _

Type-2
__ _ _ __ _ _

Type-3
_ _ _ _

Type-4

: Switch from 0 to 1, : Switch from 1 to 0, _: No transition

Basic Terminologies Used Interconnects

The wires linking transistors together are called interconnects and play a major role in the performance of the modern systems.

Crosstalk
In the early days of VLSI, transistors were relatively slow. Wires were thick and thus had low resistance. Under those circumstances wires could be treated as ideal equipotential nodes with the lumped capacitance. In modern VLSI processes transistors switch much faster. Meanwhile wires have become narrower, driving up their resistance to the point that in many paths the wire RC delay exceeds gate delay. Moreover the wires are packed very closely together and thus a large fraction of their capacitance is to their neighbors. When one wire switches it tends to affect its neighbor through capacitive coupling; this effect is called Crosstalk. On-chip interconnects inductance had been negligible but is now becoming a factor for systems with fast edge rates and closely packed buses. As viewed in the figure wires have capacitances to their adjacent neighbors as well as to ground. When wire A switches, it tends to bring its neighbors B along with it on account of capacitive coupling, also called Crosstalk. If B supposed to switch simultaneously, this may increase or decrease the switching delay. If B is not supposed to switch, crosstalk cause noise on B. We will see that the impact of crosstalk depends on the ratio of Cadj to the total capacitance. Note that load capacitance is included in the total, so for short wires and large loads, the load capacitance dominates and crosstalk is unimportant. Conversly long wires crosstalk is very unimportant.

Work Completed in this semester

From the beginning, we have been consistently collecting data and looking out for new methods to develop algorithm for reducing crosstalk. Afterwards we had simulated the two algorithms one formed as an algebraic expression and the other consisting of a Fibonacci series. Both have been producing efficient result but below our desired levels. We are comparing our results with present state of art result. We are below the desired level of result but we are aiming to convert it into desired results soon

100 90 80 70 60 50 40 30 20 10 0 Alg ebric alg orithm F ibonacci S eries Alg orithm Partial B Encoding us Alg orithm

Type 2

Type 3

Type 4

Work to be done in the next semester

In the next semester we are planning to design and simulate the encoder and decoder circuit using the HSPICE software and hence we are also gathering the information regarding the HSPICE commands. We would simulate and compare our results with the previous work and find out the gain in efficiency if possible.

REFERENCES

CMOS VLSI Design- A circuits and system perspective by Neil.H.E.Weste, David Harris, Ayan Banerjee.
1.

2.
3.

Exploiting Crosstalk to speed up on chip buses by Chunjie Duan and Sunil.P.khatri Digital Integrated Circuits. A Design Perspective by Jan M. Rabaey CMOS Digital Integrated Circuits Design by Sung Mo Kang

4.

Under the Guidance of:

Sh. H.P Singh (Sr. Lecturer) Electronics & Communication Department