1. Vit chng trnh Verilog HDL m t mch m ln-xung c c im sau: - u vo Clear: nu =1. b m s xa v reset v 0.

- u vo U/D: o =1, m ln o = 0, m xung - B m s m ti sn m ca xung clock. - B m s m ln hoc xung trong khong t 0 n N, N l s 4 bit.
module counterup(a,clk,N); input clk; input[3:0]N; output[3:0]a; reg[3:0]a; initial a=4'b0000; always@(negedge clk) a=(a==N)?4'b0000:a+1'b1; endmodule module tst_counterup;//TEST_BENCH reg clk; reg[3:0]N; wire[3:0]a; counterup c1(a,clk,N); initial begin clk = 0; N = 4'b1011; end always #2 clk=~clk; initial $monitor($time,"a=%b,clk=%b,N=%b",a,clk,N); endmodule //==================================================== module counterdn(a,clk,N); input clk; input[3:0]N; output[3:0]a; reg[3:0]a; initial a =4'b0000; always@(negedge clk) a=(a==4'b0000)?N:a-1'b1; endmodule module tst_counterdn();//TEST_BENCH reg clk; reg[3:0]N; wire[3:0]a; counterdn cc(a,clk,N); initial begin N = 4'b1010; Clk = 0; end always #2 clk=~clk; initial $monitor($time,"a=%b,clk=%b,N=%b",a,clk,N); initial #55 $stop; endmodule //===================================================== module updcounter(a,clk,N,u_d); input clk,u_d; input[3:0]N;

output[3:0]a; reg[3:0]a; initial a =4'b0000; always@(negedge clk) a=(u_d)?((a==N)?4'b0000:a+1'b1):((a==4'b0000)?N:a- 1'b1); endmodule module tst_updcounter();//TEST_BENCH reg clk,u_d; reg[3:0]N; wire[3:0]a; updcounter c2(a,clk,N,u_d); initial begin N = 4'b0111; u_d = 1'b0; clk = 0; end always #2 clk=~clk; always #34u_d=~u_d; initial $monitor ($time,"clk=%b,N=%b,u_d=%b,a=%b",clk,N,u_d,a); initial #64 $stop; endmodule

2. Vit chng trnh Verilog HDL m t thanh ghi dch 8 bit v vit test band m phng . Thanh ghi s dch 1 bit sang phi nu r_l= 1 v dch tri nu r_l=0. Cu lnh : always@(negedge clk) a=(r_l)?(a>>1'b1):(a<<1'b1);
module shifrlter(a,clk,r_l); input clk,r_l; output [7:0]a; reg[7:0]a; initial a= 8'h01; always@(negedge clk) begin a=(r_l)?(a>>1'b1):(a<<1'b1); end endmodule module tst_shifrlter;//test-bench reg clk,r_l; wire [7:0]a; shifrlter shrr(a,clk,r_l); initial begin clk =1'b1; r_l = 0; end always #2 clk =~clk; initial #16 r_l =~r_l; initial $monitor($time,"clk=%b,r_l = %b,a =%b ",clk,r_l,a); initial #30 $stop; endmodule

Bi 3. Memory Block: Have a 1 kb size memory with a 10-bit Memory Address Register. Use clock beta for memory read and memory write. Use Wr and Rd as two separate control input lines. The operations to be realized are: - Wr=1: Write into the location specified by the MAR. - RD=1: Read from location specified by MAR. - Wr=0 & Rd=0: Condition to be satisfied to write into the MAR. Data input and data output are to be through an 8-bit-wide bus ba. Bi 4: M t thit k b m ln mod n v test band. Sau mi xung ng h b m tng ln 1. khi b m t gi tr n, b m s reset v 0. Gi tr ban u ca n c xc nh trong module v c th thay i c. .
//counter using if else if; module countif(a,clk); output[7:0]a; input clk; reg[7:0]a,n; initial begin n=8'h0a; a=8'b00000000; #45 n=8'h23; end always@(posedge clk) begin $write ("time=%0d ",$time); if(a==n) a=8'h00; else a=a+1'b1; end endmodule module tst_countif();//test-bench reg clk; wire[7:0]a; countif c1(a,clk); initial clk =1'b0; always #2 clk=~clk; initial $monitor(" n=%h, a=%h",c1.n,a); initial #200 $stop; endmodule 3.