ChandraSekhar PermanantAddress: Plot No:90,Road:5J,Krishnanagar Colony, Nr A.P.H.

B Colony,Moula-Ali,Hyderabad ,India- 500040 CurrentAddress: Plot No:79,Road:5,Kundalahalli C olony, ITPLMain Road,Bangalore,India- 560037 Ph: +91 40 27 143093[H] +91 40 27123708 [H] +91 8 105805149[M] Email: chanmalladi@gmail.com; ________________________________________________________________________________ ____________ Date of Birth:25th April, 1980 OBJECTIVE Looking for a challenging position as an integrated circuit (VLSI)-ASIC/ hardwar e design engineer interested In testing/verification,layouts,coding. EDUCATION M.Tech, |Micro Electronics&VLSI Design, IIT-Madras,India. CGPA:7.65 (2004)

BTech, Electronics & Communications Engineering, National Institute of Technolog y (Regional Engineering College (REC)), Warangal, AP, India GPA: First Divi sion (2001) SUMMARY * Experience with programming in C, C++ . * Background in semiconductor physics, device operation and processing theory. * communication and people skills developed through active participation in tea ching instruction, team projects, and extracurricular activities. EXPERIENCE SrResearch EnggMirafraTechnologies,Bangalore (June'10-Till Dt) Working on Hakuya WGModem Netlist * Register issue in Hamsa Tests * ID issue in CoreSight Tests * TimeOut Issue in EmodemTests RTL * Emulation Model Issue in Hamsa Interrupt Init Routine * Porting of Raker Master Access Test * Searcher Ram Memory Mapping Issue Worked on Unicorn M2M MSM * Debugging and Fixing issues in module level test suites of AHB2AXI bridge,mss_ intctlr * Integration of JTAG Vera QVFC VIP Library with platformenv(Chip Level) ,TestPl annng,,running some tests * Sanity Bringup of VFE(Video Front End Engine) at chip level * Integration of Camera Serial Interface (CSI) Vera VIP at chip level Worked on Dalton BOFDMReceiver

* AHB Path verification from BOFDM Receiver to the rest of the chip in Vera * Frequency Plan Regressions for different blocks in the chip

SrASICEngg with IncubeSolutions, Hyderabad Worked on Graphics Verification of Arceibo GPU (Dec'09- May'10) * Specifications of cp,tx,xf,su,ras0,ras1,ras2,tev blocks of tako gfx * OpenGL Programming Guide - Official Guide to Learning OpenGl,The Red Book * Architecure Presentations for all of the Graphics Blocks * Block and System(chip) Level Rtl-Verification Environment Integration and veri fication * Debugging and Fixing the Issues in the following test suites: * Memory Driver Issue in Reg Suite * Tap Controller issue in Plgx Tests * Envmnt Flow related Issues in SX Suite for environment upgradation * Driver,Synchronisation,Test Case Environment Synchronisation Issues in TaTcTd Suite * PLI Driver Issues,Golden FileMismatch issues in SH Suite * Golden File Mismatch issues in VGT,TCC suites Worked on Verification of Video Codecs (Nov'08-Nov'09) * Background Study: * Multi Dimensional Signal,Image , Video Processing and Coding - J.H.Woods * Insight into Wavelets from Theory to Practice * Fractal and Wavelet Image Compression Techniques -Stephen Welstead * Projects: * JPEG Codec Verification: * Study of T.81 Digitl Compression and Coding of Continuous Tone Still Images Requirements And Guidelines from ITU-T * JPEG Decoder Verification. * The Organisation and The Architecture of codec Verification Environment, Code Part of Decoder Library,Application Programs * Testing of the Decoder. && * Writing the SystemVerilog Model for the input side of the decoder with VMM * TestBench for Huffman Decoder : Generator,Driver,Receiver,ScoreBoard,Env Deve lopment * Classes used:vmm_data,vmm_xactor,vmm_atomic_gen,vmm_channel,vmm_callback,cover age,vmm_env. H.264: Study of * H.264 standard from ITU-T * The H.264 Advanced Video Coding Standard -IAN E.RichardSon * VLSI Digital Signal Processing Systems Design and Implementation-Keshab.K.Parh i * VLSI Design for Video Coding:H.264/AVC Encoding from Standard Specification to Chip SeniorDesign Engineer,Ordyn Technologies,Bangalore. (Apr'07 - Aug'08) * Implementation of L2VPN(Layer2 Virtual Private Network ) * Study: study of 2 technologies Viz.,MPLS and IEEE802.1Q in Q (ad and Q) for Layer2VPNs.

* MPLS:: RFC4665 Service Requirements for layer2 ProviderProvisioned NetWo rks, * RFC3916 Requirements for pseudo-wire-Emulation_Edge_to_Edge(PWE3) * RFC4448 draft_IETF_PWE3_Ethernet_encap_11 * RFC3031 MPLS Architecture,RFC3036 LDP Specification from IETF * ITU-T G8110/Y.1370 MPLS Layer Network Archtecture * IEEE802.1QinQ: IEEE802.1Q std for Virtual BridgedLans ( that support MSTP and other Protocols like GVRP etc) IEEE802.1ad:Service Provider Network * Design: Ascertaining the behaviourof 802.1ad system and Designing IEEE802.1ad (Q in Q) Service Provider Network Base * MADM Project: * study of SDH Specification ITU-T G7071/Y1322,Knowing the MicroArchitecture of STM-1,4,16. * worked on Design Changes in STM-4 from 1-Port to 4-Port. * Design Engineer,Conexant Systems,Hyderabad. (Mar'06 -Mar'07) * Worked on Sunburst Cable Modem Chip. * Verification and Understanding the design of EMAC,adding features to the enet model. * Gate Level Simulations of EMAC. * Verification , bug fixing in the design of DMAController which supports 8 c hannles and has got Circular Pointer Buffer,Linear LinkedList,Two Variants of L inked List using Tables. * The Circular Ptr ,Linked lists has got feaures to go to the start of the curr ent Packet when ever is aborted inbetween a transaction.Linked List has also got Dynamic Address Loding Feature into it. * Knowing some of the back end issues while designing, and of DMAC . * Verification of Transport Stream Mux.(Knowing the design) * Understanding the designs of PCI,USB2.0,Tranport streamDeMux. * Arm940T SlaveMode Testing :Bug Fix in the Wrapper. * Worked on Solo SetTop Box Chip. * AudioBlock Tempest (MPEG1,MPEG4). * Bigeye Display Processor: * NoiseReduction Block:: * MAT Lab Coding of Image Segmantation,Block Boundary Detection,Noise Estimation ,Noise Calculation,Block Artifact Rediction Blocks(Luminance,Chrominance),Spatia lNoise Correction(Luminance, Chrominance),TemporalNoiseCorrection Blocks. * Overlay Block Verification(This Block Combines images from Main,PIP,OSD source s). * Knowledge in MAVP Processor(Motion Adaptive Video Processor). * This processor converts interlaced fields to progressive frames. * Overview of the behaviour of its submodules from the specification. * The submodules are:Mavp Controller,Video Input Buffer,Memory Write Agent ,Memo ry Read Agent,Motion Detector Block,VT Filter,Chroma Filter,AAP(Anti Aliasing Pr ocessor),Output Blending. * Sunburst * Bug fix in EMAC design and in the Netlist and LEC check * CDP(Cable Down Stream processor) VHDL code environment setup and integrate with Verilog Sunburst. Member Technical Staff in DGB Micro Systems,Madras. (May'04 - Feb'06) * Worked on Apache Network Routing Chip.

* Verification of UART Block by developing UART Model. * Verification of I2C, * Verification of Watch Dog timer Using Arm Assembly Language * PCI: * Verification of PCI Block by Developing PCI Model. * Study of PCI (2.3) -SIG Specification Worked on Mobile Chip * Study of Verification environment. * EMAC,SPI * Verification of I2S,SPI,Ethernet Blocks,Implementing AMBA-AHB InterFace(Tx ,Rx) between Enet and Memory. * Writing enet software_model,study of enet_HardWare_Bfm * SYSTEM Level Verification * Tuning the memory controller for Soc_Data_path_tests of the mobile chip in volving all the modules. * USB2.0 * Verification of USB 2.0 Block. * Study of USB 2.0 Specification

COMPUTER SKILLS CAD Tools PSpice, Hardware 8086 assembly/interfacing, Languages Programming VHDL, Verilog,C,C++, C interface Verilog PLI( VPI,acc ,tf routines) HVLs Specman,Vera(LRM:TestBench,OVA;RVM) HDVL System-Verilog(LRM;SVA,VMM;OVM) ArchitectureModelling SystemC Scripting Perl ,Make,Bash Shell Signal Processing MATLAB,Digital Image Processing using MATLAB Graphics OpenGL FrontEndTools NCSim,AtHdl,VCS,Xilinx,Quartus Equipment Oscilloscopes, Function Generators, Multimeters Software Packages MS Word, Excel, Power Point Platforms Linux, , Windows 98/2001/XP HONORS AND ACHIEVEMENTS * Achieved 78th in EAMCET in Engg entrance Exam in AndhraPradesh. * Was a Merit Scholar at NIT (REC), Warangal during the year 1998-1999. * Achieved GATE score of 99.65 with AIR -64.