Está en la página 1de 110

# Chapter 10

Combinational Circuits

Figure 10.1

Microcode level Logic gate level Electronic device level Physics level

Combinational circuit
The output depends only on the input

Figure 10.2

In a b c

Out x y

## Methods to describe a combinational circuit

Truth table Boolean algebraic expression Logic diagram

Truth table
Lists the output for every combination of
the input

Figure 10.3

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

x 0 1 0 1 0 0 0 0

y 0 0 0 1 1 0 0 0

Figure 10.4

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

x 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1

y 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0

Boolean algebra
Three basic operations
Binary OR + Binary AND Unary Complement

## Ten properties of boolean algebra

Commutative Associative Distributive Identity Complement

## Commutative C OMPUTER S YSTEMS C HAPTER 10

x+y =y+x xy =yx

(x + y) + z = x + (y + z) x + (y z) = (x + y) (x + z) (x y) z = x (y z)

## Associative x+y =y+x

(x + y) + z = x + (y + z) x + (y z) = (x + y) (x + z) x (y + z) = (x y) + (x z) x+0=x (x y) z = x (y z) xy =yx

x + (x ) = 1

## (x + y) + z = x + (y + z) x + Identity + y) (x + z) (y z) = (x x (y + z) = (x y) + (x z) x+0=x x1=x (x y) z = x (y z)

x + (x ) = 1 x (x ) = 0

x + (y z) = (x + y) (x + z)

Complement x+0=x
x + (x ) = 1 x (x ) = 0 x1=x

x (y + z) = (x y) + (x z)

x (y + z) = x y + x z

x + y z = (x + y) (x + z)

Figure 10.5

## Operator Complement AND OR

x + (x ) = 1

x1=x

Distributive x (x ) = 0

x (y + z) = x y + x z x+x =1 xx =0

x + y z = (x + y) (x + z)

x (x ) = 0

Complementy) (x + z) x + y z = (x +
x (y + z) = x y + x z x+x =1 xx =0 (x + y) + z x+y+z

x (y + z) = x y + x z x+x =1

Associativity xx =0
(x + y) + z x+y+z x+x=x xx=x

Duality
To obtain the dual expression
Exchange + and Exchange 1 and 0

## (x + y) + z Idempotentz property x+y+ x+x=x xx=x x+1=1 x0=0

x+xy =x

x+y+z

Zero+ x = x theorem x
x+1=1 x0=0 xx=x

## xy+x z+yz =xy+x z

x (x + y) = x

x+xy =x

Absorption 1property x+ =1
x (x + y) = x x+xy =x x0=0

x+x=x xx=x

(x + y) (x + z) (y + z) = (x + y) (x + z)

## Consensus ytheorem x+x =x

(x + y) (x + z) (y + z) = (x + y) (x + z) (a b ) = a + b xy+x z+yz =xy+x z x (x + y) = x

x+1=1 x0=0

(a + b) = a b

De Morgans + y) (x law x + y) (x + z) (y + z) = (x
(a + b) = a b (x ) = x 1 =0 0 =1 (a b) = a + b

## xy+x z+yz =xy+x z

x (x + y) = x

+ z)

Complement theorems
(a + b) = a b (x ) = x 1 =0 0 =1
1

(a b ) = a + b

Logic diagrams
An interconnection of logic gates Closely resembles the hardware
Gate symbol represents a group of transistors and other electronic components Lines connecting gate symbols represent wires

Figure 10.6

a x b

a x b

x= a . b a 0 0 1 1 b 0 1 0 1
(a) AND gate.

x =a+ b x 0 0 0 1 a 0 0 1 1 b 0 1 0 1
(b) OR gate.

x 0 1 1 1

x =a a 0 1 x 1 0

(c) Inverter.

Figure 10.7

a x b

a x b

a x b

x = (a . b) a 0 0 1 1 b 0 1 0 1
(a) NAND gate.

x = (a + b) x 1 1 1 0 a 0 0 1 1 b 0 1 0 1
(b) NOR gate.

x=a x 1 0 0 0 a 0 0 1 1

b b 0 1 0 1
(c) XOR gate.

x 0 1 1 0

Figure 10.8

a x b

a x b

## (a) AND inverter.

(b) NAND.

Figure 10.9

Precedence Highest

## Operator Complement AND XOR OR

Lowest

Figure 10.10

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

x 0 0 0 0 0 0 0 1

a b c x=a b c

## Set theory representation

OR gate is set union AND gate is set intersection Inverter is set complement

Figure 10.11

x (a) x

x (b) x y

x (c) x + x y

Figure 10.12

Truth table

One-to-one correspondence

## Boolean expressions and logic diagrams

AND gate corresponds to AND operation OR gate corresponds to OR operation Inverter corresponds to complement
operation

Figure 10.13

a b c b bc a+b.c

Figure 10.14

a b b

ab

a (ab + bc ) a ab + bc ((ab + bc ) a)

bc c c

## Abbreviated logic diagrams

Any signal can be duplicated by a junction of
two wires

## The complement of any variable can be

produced by an inverter

Figure 10.15

a b b c

Figure 10.16

(a bc c + a + d)
a b c c a d

## Truth tables and boolean expressions

Given a truth table, write a boolean
truth table expression without parentheses as an OR of several AND terms

## Each AND term corresponds to a 1 in the

Figure 10.17

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

x 1 1 1 0 1 1 0 1

Figure 10.18

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

x 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0

Two-level circuits
The gate delay is the time is the time it takes
for the output of a gate to respond to a change in its input

## Any combinational circuit can be

transformed into an AND-OR circuit or an OR-AND circuit with at most two gate delays (not counting the gate delay of any inverters)

Figure + (a bc c10.19 a +

a bd + a c d
a b d

(a + b + c )(a

a c d

a bd + a c d

Figure 10.20

(a + b + c )(a + b + c)
a b c a b c

## AND-OR versus OR-AND

To transform any expression x to an
equivalent OR-AND expression Transform the complement of x to an AND-OR expression without parentheses using boolean algebra theorems Use x = (x) and De Morgans law

## (a + b + c )(a + b + c) (abc) = a + b + c abc + def = [(abc) (def ) ]

a b c a b c

(abc) = a + b + c (a + b + c) = a b c

Figure 10.21

a b c a b c

a b c a b c

Figure 10.22

a b c

d e f

d e f

d e f

a b c

(c) as

d e f

## (a + + (abc) b= ac)+= a bcc b + abc b def = a b c (a ++ + c) = [(abc) (def ) ]

a (a a) = a abc + def = [(abc) (def ) ]

Figure 10.23

## (a a) ) a (a + a = = a (a + b = a (a + a) + c) = [(a +ab + c)(d + e + f )] (a + b + c) = [(a + b + c)(d + e + f )]

a

(a + a) = a

Figure 10.24

(a + b + c)(d + e + f ) = [(a + b + c) + (d + e + f ) ]
a b c a b c a b c

d e f

(c) T circu

## d e f (c) The same NOR-NOR circuit as in part (b).

quivalent R circuit.

Canonical expressions
A minterm is a term in an AND-OR
expression in which all input variables occur exactly once in which no two identical minterms appear

## A canonical expression is an OR of minterms A canonical expression is directly related to

a truth table because each minterm in the expression represents a 1 in the truth table

(a + a) = a

Figure 10.25

(a + b + c)(d + e + f ) =
Row (dec) 0 1 2 3 4 5 6 7 a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 x 0 0 0 1 0 0 1 1

x(a, b, c) = (3, 6, 7)

(a + b + c)(d + e + f ) = [(
Figure 10.25

x(a, b, c) = (3, 6, 7)
Row (dec) 0 1 2 3 4 5 6 7 a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 x 0 0 0 1 0 0 1 1

x(a, b, c) = (0, 1, 2, 4, 5)

Karnaugh maps
The distance between two minterms is the
number of places in which they differ between them is one

Two minterms are adjacent if the distance A Karnaugh map is a truth table arranged so

Figure 10.26

bc 11 10

Figure 10.26

## x(a, b, c) = (0, 1, 2, 4, 5) x(a, b, c) = a bc + a bc x(a, b, c) = a b

bc 00 0 a 1 0 0 0 0 0 01 0 11 1 10 1 a 1 0

x(a, b, c) = a bc + a x(a, b, c) = a b

Figure 10.27

bc 00 01 11 1 10 1

## (b) The minimization.

Figure 10.27

x(a, b, c) = a b
bc 00 0 a 1 1 1 a 01 11 10

Figure 10.28

30)

x(a, b, c) = ab c + abc = ac
(b) Region a. c (c) Region c .

31)

## Figure 10.28 1 a c (c) Region c .

p.

(b) Region a.

x(a, b, c) = (0, 1, 2, 4, 5)
bc x(a, b, c) = a bc + a bc 00 01 11 10

Figure 10.29

b 1

x(a, b, c) = a b 0 1
a 1 1 1 a

(30)
b 1 1 1

x(a, b, c) = ab c + abc c
(a) a bc + abc = bc (b) abc + abc =ab = ac

(c) x =

1 1 1

## x(a, b, c) = a bc + abc + abc

Figure 10.29

= bc + ab

c c = ab

(c) x = bc + ab

Figure 10.30

bc 00 0 a 1 4 5 7 6 0 01 1 11 3 10 2

Figure 10.30

x(a, b, c) = a b
bc b

Figure 10.31

(30) (31)0 a
11

00 1

01 1 1

11

10

x(a, b, c) = ab c + abc
1 1 1

= ac
1

(32)
(a) (33) A bad strategy. b

## x(a, b, c) = a bc + abc + abc c

(b) The result ofbc + ab = the bad strategy.

## (c) The cor

(34) (35)

1 1 1

x(a, b, c) = (0, 1, 5, 7) = a b + ac
Figure 10.31

## x(a, b, c) = (0, 1, 5, 7) (36) (37) = a b + ac x(a, (38) = (0, 2, 4, 6, 7) b, c) (39) = b c + bc + ab

cd x(a, b, c) = (0, 2, 4, 6, 7) 00 0 a 1 1 1 1 a 1

Figure 10.32

= c + ab

01

11

10 1 1 1 c 1

b 1 1

Figure 10.33

## (b) The regions where the variables are 1.

Figure 10.34

x(a, b, c) = c d + b d x(a, b, c, d) = a c d + b c + b d cd
00 00 01 ab 11 10 1 1 1 1 1 01 1 1 11 10 1

x(a, b, c) = c d + b d x(a, b, c, d) = a c d + b c + b d
cd 00 00 01 ab 11 10 1 1 1 1 01 1 1 11 10 1

Figure 10.35

x(a, b, c) = c d + b d

x(a, b, c, d) = a c d Figure 10.36+ b d +bc x(a, b, c, d) = a c d + b c + b d x(a, b, c, d) = c d + bcd + abc x(a, b, c, d) = c d + bcd + abc x(a, b, c, d) = c d + bcd + abd x(a, b, c, d) = c d + bcd + abd
cd 00 00 01 ab 11 10 1 1 1 1 a 1 d (a) One possible minimization. (b) A different minimization. 1 1 1 1 1 1 01 11 10 1 1 1 b c

## x(a, b, c, d) = c d + bcd + abc x(a, b, c, d) = c d + bcd + abd ac + a c + c d + a b + bcd ac + a d + a bcd+ bcd

00 1 01 1 1 1 1 1 1 11 1 1 00 01 ab 11 10 1 a 10 1 1

x(a, b, c, d) = c d + bcd +
Figure 10.37

ac + a c + c d + a b + b ac + a d + a b + bcd
c 1 1 1 1 1 1 1 d 1 1 1 1 b 1

## (b) A correct minimization.

ac + a d + a b + bcd a c + b c + c d + abd
cd 00 00 01 ab 11 10 1 1 1 1 1 1 01 1 1 11 1 1 10 1 1

Figure 10.38

## Dual Karnaugh maps

To minimize a function in an OR-AND Use x = (x) and De Morgans law
expression minimize the complement of the function in the AND-OR expression

## x(a, b, c, d) = c d + bcd + abc

ac + a c + c d + a b + bcd ac + a d + a b + bcd a c + b c + c d + abd
1

## x(a, b, c, d) = c d + bcd + abd

Figure 10.29(c), 10.39

## x(a, b, c, d) = c d + bcd + abd ac + a c + c d + a b + bcd ac + a d + a b + bcd

x = bc1 + ab 1
0 a 1 1 1 bc 00 1 01 1 11 10 1

a c + b c + c d + abd
(c) x = bc + ab

## (40) (43) (41)

x = b(a + c) =b +ac x = (x )

Dont-care conditions
If an input combination is never expected to
be present, you can choose to make it 0 or 1, whichever will better minimize the circuit Karnaugh map

(45) = b(a + c)

= (b + a c )

b 1 a 1 c 1

= bc + ac
bc

0 a 1 1 1

=c

## (b) Minimizing the same function with dont-care conditions.

Enable lines
An enable line to a combinational device
turns the device on or off If enable = 0 the output is 0 regardless of any other inputs If enable = 1 the device performs its function with the output depending on the other inputs

Figure 10.41

Enable =
a x

a 0 1

Enable

## (b) Truth table with the d turned on.

Enable = 1 a 0 1 x 0 1 a 0 1

Enable = 0 x 0 0

Figure 10.42

Invert
a x

a 0 1

Invert

## (b) Truth table with th turned on.

Invert = 1 a 0 1 x 1 0 a 0 1

Invert = 0 x 0 1

## (c) Truth table with the inverter turned off.

Multiplexer
A multiplexer selects one of several data
input to be passed through inputs to be routed to a single data output

## Control lines determine the particular data

Figure 10.43

S2
D0 D1 D2 D3 D4 D5 D6 D7

S1 0 0 1 1 0 0 1 1

S0 S2 00 10 00 10 01 11 01 11

S1 F S0 0 0 1 1 0 0 1 1 D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 1 0 1 0 1

D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 0 1 1 1 1

D D D D D D D D

S2 S1 S0

S2 S1 S0

## (b)!!Truth table. (b)!!Truth table.

Figure 10.44

D0 S1 S0 D1 S1 S0 F D2 S1 S0 D3 S1 S0

Binary decoder
A decoder takes a binary number as input
and sets one of the data output lines to 1 and the rest to 0 value of the binary number that is input

## The data line that is set to 1 depends on the

Figure 10.45

S1 S0 S1 D0 D1D0D2D1D3D2 D3 S0 0 0 1 1 0 1 0 1 0 0 1 1 10 01 00 01 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1

S1 S0

S1 S0

D0 D1 D2 D3

D0 D1 D2 D3

Figure 10.46

## S 1' D0 S 0' S 1' D1 S0 S1 D2 S 0' S1 D3 S0

Figure 10.47

S1 S0

D0 D1 D2 D3

Enable

Demultiplexer
A demultiplexer routes a single input value
to one of several output lines

## Control lines determine the data output line

to which the input gets routed

Figure 10.48

S1 S0
D D0 D1 D2 D3

D0 D1 D2 D3 D 0 0 0 0 D 0 0 0 0 D 0 0 0 0 D

0 0 1 1

0 1 0 1

S1 S0

## (a) Block diagram.

(b)!Truth table.

The half adder adds the right-most two bits
of a binary number

Inputs: The two bits Outputs: The sum bit and the carry bit

Figure 10.49

A A B

A 0 0 1 1

B 0 1 0 1

Sum 0 1 1 0

Carry 0 0 0 1

Carry

Carry

Sum (a) Block diagram. (b) Truth table. Sum (c) Implementation.

Figure 10.49

The full adder adds one column of a binary
number

## Inputs: The two bits for that column and the

carry bit from the previous column the next column

## Outputs: The sum bit and the carry bit for

Figure 10.50

A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

Sum 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

Cout

Cin

Sum

Figure 10.51

A A C S

B B

## Cin A Cout C S Sum B

The ripple-carry adder adds two n-bit binary

Inputs: The two n-bit binary numbers to be Outputs: The n-bit sum, the C bit for the
carry out, and the V bit for signed integer overow

Figure 10.52
A3 A2 A1 A0 B3 B2 B1 B0

Cout V

## A3 B3 A Cout V Cout S B Cin

A2 B2 A Cout S B Cin

A1 B1 A Cout S B Cin C

A0 B0 A B

S3

S2 (b) Implementation.

S1

S0

## Computing the V bit

You can only get an overow in one of two
cases A and B are both positive, and the result is negative A and B are both negative, and the result is positive

Based on the relation
NEG x = 1 + NOT x

## XOR gates act as selective inverters A B = A + (B)

Figure 10.53
A3 A2 A1 A0 B3 B2 B1 B0

Cout V

Sub

A Cout V Cout S

B Cin

A Cout S

B Cin

A Cout S

B Cin

Cout Cin S

S3

S2

S1

S0

## Arithmetic Logic Unit (ALU)

Performs 16 different functions Inputs: Two n-bit binary numbers, four
control lines that determine which function will be executed, and one carry input line

Figure 10.54

4 ALU

## ALU Cin Cout V Zout N

Result

Figure 10.55

ALU control (dec) (bin) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Result A A plus B A plus B plus Cin A minus B 1 plus B plus A plus B plus Cin A B A B A+B A+B A B A ASL A ROL A ASR A ROR A 0

N N N N N N N N N N N N N N N N A<4>

## Status bits Zout Zone V Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z A<5> 0 V V V V 0 0 0 0 0 0 V 0 0 0 A<6>

Cout Cont

0 C C C C 0 0 0 0 0 0 C C C C A<7>

Figure 10.56

Cin 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

Computation Unit

Result

VC

ALU

0 0 0 0 0 0 0 0

Result

## The multiplexer of Figure 10.56

If line 15 is 1, Result and NZVC from the left
are routed to the output

## If line 15 is 0, Result and NZVC from the

right are routed to the output

A 8

B 8

Figure 10.57

14

E 0 0

V Result

Figure 10.58

## Figure 10.59 Arithmetic Unit

A7

B7

A6

B6

A0

B0 Sub Cin d e f g

## C A Cout S B Cin A Cout S B Cin A B

Cout Cin S

V Result

A<high> B<high> A<low> B<low>

## A plus B plus Cin

Cin

Cout

A plus B

S<high>

S<low>

16-bit subtract
A<high> B<high> A<low> B<low>

## A plus B plus Cin

Cin

Cout

A plus B plus 1

D<high>

D<low>

Figure 10.60

Function A plus B A plus B plus Cin A plus B plus 1 minus B A plus B plus Cin

d 1 0 0 0

e 0 1 0 0

f 0 0 1 0

g 0 0 0 1

Sub 0 0 1 1

C 0 Cin 1 Cin

Figure 10.60

Figure 10.61

a b

a b

(a) a b c

(b)

(c)

Figure 10.62

(a)

(b)

(c)

(d)

Figure 10.62

Figure 10.63

s=0 a b s x y a b

s=1 x y s

Figure 10.64

s1 s0 = 00 a b s1 s0 x y a b

s1 s0 = 01 x y s1 s0 a b

s1 s0 = 10 x y s1 s0 a b

s1 s0 = 11 x y s1 s0