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Khoa in t-Vin thng, i hc Bch khoa H ni

BI 6: TRNG THI MY HU HN FSM

1. Mc tiu ca bi th nghim Trin khai mt mch logic nhn bit hai chui ca cc tn hiu u vo xc nh dng FSM, c th l bn ln lin tc mc 1 hoc bn ln lin tc mc 0. C mt u vo w v mt u ra z. Bt k khi no w = 1 hoc w = 0 trong bn xung nhp ng h lin tip th u ra z c gi tr 1; ngc li, z = 0. Cho php hin tng chng cc chui, v th nu w = 1 trong nm xung nhp ng h lin tip u ra z s bng 1 sau xung nhp th bn v th nm. Hnh 1 minh ha quan h yu cu gia w v z.

Hnh 1. Yu cu v mt thi gian cho u ra z

2. Cc kin thc cn trang b trc khi thc hin bi th nghim - Hiu bit v FSM, cc cch m ha trng thi my thng dng - K nng c bn v ngn ng VHDL - K nng c bn vi b cng c phn mm Quartus II - Nm r cch s dng kit DE1 3. Cc kin thc v k nng s c c sau khi hon thnh bi th nghim - C k nng v cch xy dng cc FSM trong cc mch logic - Thnh tho hn v cu trc VHDL dng trin khai vit m cho FSM 4. Ni dung bi th nghim Phn 1: Trin khai FSM dng m one-hot Phn ny yu cu thc hin mch FSM gn trng thi bng tay bao gm cc biu thc logic np mi trng thi cho cc flip-flop trng thi. trin khai FSM dng chn flip-flop trng thi gi l y8y7y6y5y4y3y2y1y0 v php gn trng thi kiu one-hot a ra trong bng 1.

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni

Bng 1. M one-hot dnh cho FSM

Hnh 2. S trng thi my cho FSM Bc 1: To mt d n Quartus II mi cho mch FSM. Chn loi chip Cyclone II EP2C20F484C7N. Buc 2: Vit v a vo d n tp VHDL c ni dung nh sau. Trong m VHDL ny ch dng chn flipflop trong mch v nh ngha cc biu thc logic iu khin cc cng vo flip-flop. Ch dng cc lnh gn n gin trong m VHDL xc nh gi tr logic np cho cc flip-flop.

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni


library IEEE; use IEEE.STD_LOGIC_1164.all; entity part1 is port( clk, rst, w: in std_logic; z: out std_logic; led: out std_logic_vector(8 downto 0)); end entity; architecture Behavioral of part1 is signal states: std_logic_vector(8 downto 0); begin process(clk) begin if(rising_edge(clk)) then if(rst='0') then states<=(0=>'1',others=>'0'); else states(1)<=(states(0) or states(5) or states(6) or states(7) or states(8)) and (not w); states(2)<=states(1) and (not w); states(3)<=states(2) and (not w); states(4)<= (states(3) or states(4)) and (not w); states(5)<=(states(0) or states(1) or states(2) or states(3) or states(4)) and w; states(6)<=states(5) and w; states(7)<=states(6) and w; states(8)<= (states(7) or states(8)) and w; states(0)<=not(states(1) or states(2) or states(3) or states(4) or states(5) or states(6) or states(7) or states(8)); end if; end if; end process; z <= '1' when states(4)='1' or states(8)='1' else '0'; led <= states; end Behavioral;

Bc 3: Gn chuyn mch SW0 lm u vo reset mc thp cho FSM, gn SW1 lm u vo w, v gn nt bm KEY0 lm u vo xung nhp ng h. Gn LEDG0 lm u ra z, v gn cc u ra flip-flop trng thi vi cc LED t LEDR8 ti LEDR0. Bc 4: Bin dch d n. Bc 5: M phng chc nng ca mch. Bc 6: Khi chc chn mch lm vic ng da theo kt qu m phng, np mch bin dch xung FPGA. Kim tra chc nng ca thit k bng cch a chui u vo qua SW v quan st u ra trn cc LED. Bc 7: Trin khai li FSM trn dng m one-hot c biu din nh trong bng 2. Gi : Cn to ra vi thay i cho cc biu thc logic trong mch trin khai cc m one-hot thay i. Bin dch li d n v kim tra bng c m phng v np FPGA.

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni

Bng 2. Cc m one-hot thay i cho FSM.

Phn 2: Trin khai FSM dng cc Process


Phn ny yu cu vit mt kiu khc ca m VHDL cho FSM. Trong cch vit m ny, khng cn ly cc biu thc logic cn thit cho mi trng thi flip-flop bng tay. Cc trng thi hin ti v trng thi k tip cho FSM c nh ngha dng lit k vi cc gi tr c th c bi cc k hiu t A n I. Trnh bin dch VHDL t ng nhn ra c bao nhiu trng thi flip-flop dng cho mch, v t ng la chn php gn trng thi.

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni

Hnh 3. Khung m VHDL dng cho FSM

Bc 1: To d n mi cho FSM. Chn chip Cyclone II EP2C20F484C7N. Bc 2: Vit v a vo d n tp VHDL c ni dung nh sau:

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni


library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity part2 is Port(clk,rst,w: in std_logic; z: out std_logic; led: out std_logic_vector(8 downto 0)); end part2; architecture Behavioral of part2 is type state_type is (A,B,C,D,E,F,G,H,I); signal current_state,next_state: state_type; begin process(w,current_state) begin z<='0'; case current_state is when A=> if w='1' then next_state<=F; else next_state<=B; end if; when B=> if w='1' then next_state<=F; else next_state<=C; end if; when C=> if w='1' then next_state<=F; else next_state<=D; end if; when D=> if w='1' then next_state<=F; else next_state<=E; end if; when E=> z<='1'; if w='1' then next_state<=F; else next_state<=E; end if; when F=> if w='1' then next_state<=G; else next_state<=B; end if; when G=> if w='1' then next_state<=H;

else next_state<=B; endif; whenH=> ifw='1'then next_state<=I; else next_state<=B; endif; whenI=> z<='1'; ifw='1'then next_state<=I; else next_state<=B; endif; endcase; endprocess; process(clk) begin ifrising_edge(clk)then

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni

if w='1' then next_state<=H; else next_state<=B; end if; when H=> if w='1' then next_state<=I; else next_state<=B; end if; when I=> z<='1'; if w='1' then next_state<=I; else next_state<=B; end if;

end case; end process; process(clk) begin if rising_edge(clk) then if rst='0' then current_state<=A; else current_state<=next_state; end if; end if; end process; with current_state select led<="000000001" when A, "000000010" when B, "000000100" when C, "000001000" when D, "000010000" when E, "000100000" when F, "001000000" when G, "010000000" when H, "100000000" when I, "000000000" when others; end Behavioral;

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni Bc 3: Gn SW0 lm u vo reset mc thp cho FSM, gn SW1 lm u vo w, v gn nt bm KEY0 lm u vo xung nhp ng h a vo bng tay. Gn LEDG0 lm u ra z, v gn chn LED t LEDR8 n LEDR0 xc nh trng thi ca FSM. Bc 4: Chn Assignments > Settings trong Quartus II, nhp vo Analysis and Aynthesis bn tri ca s, v nhp vo nt More Settings. i thng s State Machine Processing thnh Minimal Bits.

Hnh 4. Xc nh phng php gn trng thi trong Quartus II.

Bc 5: kim tra mch to bi Quartus II, m cng c Tool > RTL Viewer. Nhp i vo hp hin th trn mch th hin FSM, v xc nh xem s trng thi my hin th c tng ng vi s trng thi trong hnh 2 hay khng. Bc 6: M Compilation Report, chn phn Analysis and Synthesis ca bo co, v nhp vo State Machines. Quan st m trng thi dng trong FSM va trin khai. Bc 7: M phng chc nng ca mch. Bc 8: Khi chc chn mch lm vic ng da theo m phng, np mch bin dch xung FPGA. Kim tra chc nng ca thit k bng cch a chui u vo qua SW v quan st u ra trn LED. Bc 9: Chn Assignments > Settings trong Quartus II, nhp vo Analysis and Aynthesis bn tri ca s, v nhp vo nt More Settings. Thay i thit lp cho State Machine Processing t Minimal Bits thnh One-Hot. Bin dch li mch v sau m tp bo co, chn phn Analysis and Synthesis ca bo co, v nhp vo State Machines. So snh cc m trng thi vi cc m trng thi trong bng 2, v phn tch bt k s khc bit no thy c.

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng

Khoa in t-Vin thng, i hc Bch khoa H ni 5. Cc gi m rng Hy m rng trin khai FSM b pht hin chui dng cc thanh ghi dch, thay v dng cc cch nh trn. To m VHDL dng hai thanh ghi dch 4 bit; mt thanh ghi dng nhn ra chui 0, v thanh ghi cn li dng nhn ra chui 1. Gp cc biu thc logic ph hp vo trong thit k ca bn to ra kt u ra z. Dng cc chuyn mch v cc LED trn bo mch tng t nh lm trong cc phn 1 v phn 2, v quan st hnh vi ca cc thanh ghi cng u ra z. Tr li cu hi sau: C th dng 1 thanh ghi 4 bit thay v dng hai thanh ghi 4 bit hay khng? Gii thch cu tr li. 6. Ti liu tham kho - Douglas L. Perry, VHDL Programming by Example, McGraw-Hill, 2002 - Daniel D. Gajski, Principles of Digital Design, Prentice-Hall, 1996 - Altera. (2006). DE1 Development and Education Board User Manual [Online]. Available: http://www.altera.com 7. Cc cu hi nh gi hiu bit

Ngi bin son: KS. Nguyn Minh Tin v TS. Hong Mnh Thng