CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

October 1987 Revised January 1999

CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

General Description
The CD4094BC consists of an 8-bit shift register and a 3STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QS output is transferred to a second output, QS, on the following negative clock edge. The output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH.

Features
s Wide supply voltage range: s High noise immunity: s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s 3-STATE outputs 3.0V to 18V 0.45 VDD (typ.)

Ordering Code:
Order Number CD4094BCWM CD4094BCN Package Number M16B N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram
Pin Assignments for DIP and SOIC

Top View

Truth Table
Clock Output Enable 0 0 1 1 1 1 X X 0 1 1 1 X X X 0 1 1 Strobe Data Parallel Outputs Q1 Hi-Z Hi-Z 0 1 QN Hi-Z Hi-Z QN1 QN1 Serial Outputs QS (Note 1) Q7 No Change Q7 Q7 Q7 Q No Change Q7 No Change No Change No Change Q7

 

X = Don't Care = HIGH-to-LOW = LOW-to-HIGH

     

No Change No Change

No Change No Change No Change

Note 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.

1999 Fairchild Semiconductor Corporation

DS005983.prf

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CD4094BC

Block Diagram

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CD4094BC

Absolute Maximum Ratings(Note 2)

(Note 3) Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW 0.5 to +18 VDC 0.5 to VDD +0.5 VDC 65C to +150C

Recommended Operating Conditions (Note 3)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) +3.0 to +15 VDC 0 to VDD VDC 40C to +85C

Note 2: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of Recommended Operating Conditions and Electrical Characteristics provide conditions for actual device operation. Note 3: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

Symbol IDD Quiescent Device Current VOL LOW Level Output Voltage VOH HIGH Level Output Voltage VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN IOZ Input Current 3-STATE Output Leakage Current
Note 4: IOH and IOL are tested one output at a time.

Parameter

Conditions VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5.0V, VO = 0.5V or 4.5V VDD = 10V, VO = 1.0V or 9.0V VDD = 15V, VO = 1.5V or 13.5V VDD = 5.0V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5.0V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V VDD = 15V, VIN = 0V or 15V |IO| 1 A |IO| 1.0 A

40C Min Max 20 40 80 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 0.52 1.3 3.6 0.3 0.3 1 3.5 7.0 11.0 0.44 1.1 3.0 0.44 1.1 3.0 4.95 9.95 14.95 Min

+25C Typ Max 20 40 80 0 0 0 5.0 10.0 15.0 1.5 3.0 4.0 0.05 0.05 0.05

+85C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0

Units A A A V V V V V V V V V V V V mA mA mA mA mA mA

0.88 2.25 8.8 0.88 2.25 8.8 0.3 0.3 1

0.36 0.9 2.4 0.36 0.9 2.4 1.0 1.0 10

A A A

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AC Electrical Characteristics
TA = 25C, CL = 50 pF Symbol tPHL, tPLH Parameter Propagation Delay Clock to QS tPHL, tPLH Propagation Delay Clock to Q tPHL, tPLH Propagation Delay Clock to Parallel Out tPHL, tPLH Propagation Delay Strobe to Parallel Out tPHZ Propagation Delay HIGH Level to HIGH Impedance tPLZ Propagation Delay LOW Level to HIGH Impedance tPZH Propagation Delay HIGH Impedance to HIGH Level tPZL Propagation Delay HIGH Impedance to LOW Level tTHL, tTLH Transition Time

(Note 5)
Conditions Min Typ 300 125 95 230 110 75 420 195 135 290 145 100 140 75 55 140 75 55 140 75 55 140 75 55 100 50 40 80 40 20 1 1 1 200 100 83 200 80 70 1.5 3.0 4.0 100 50 40 100 40 35 3.0 6.0 8.0 5.0 7.5 40 20 10 Max 600 250 190 460 220 150 840 390 270 580 290 200 280 150 110 280 150 110 280 150 110 280 150 110 200 100 80 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ns ns ns ns ns ns MHz MHz MHz pF

VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V

tSU

Set-Up Time Data to Clock

VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V VDD = 5.0V VDD = 10V VDD = 15V

tr , tf

Maximum Clock Rise and Fall Time

tPC

Minimum Clock Pulse Width

tPS

Minimum Strobe Pulse Width

fmax

Maximum Clock Frequency

CIN

Input Capacitance

Any Input

Note 5: AC Parameters are guaranteed by DC correlated testing.

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Timing Diagram

Test Circuits and Timing Diagrams for 3-STATE

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CD4094BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M16B

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CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

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