Report | Computer Hardware | Software Engineering

California State University, Sacramento

College of Engineering and Computer Science

CSC 242 –COMPUTER AIDED SYSTEM DESIGN AND VERIFICATION ASSIGNMENT 2

Submitted by Venkata Subba Reddy Yelampalli

Instructor: Prof. Behnam Arad

On 11th October 2011.

1

The number of occurrences is provided through an 8-bit output called INTERVAL. i. INTERVAL is cleared (0) whenever RESET is low. This is an active low signal. any 8-bit data in which the upper nibble (the upper half) is 4'b1000..CSC 242 Assignment 2 100 points The objective of this assignment is to design an interval counter in SystemVerilog that works by monitoring an 8-bit incoming data called DATA and counts the number of clock cycles between occurrences of “8X”. Assume the count does not exceed the 8-bit INTERVAL.e. Finite State Machine 2 . The unit has an asynchronous reset input called RESET.

} monitor_t.pkg): `ifndef `define package typedef DEFS_DONE DEFS_DONE package2. end else begin state <= next. interval1 <= 0. endpackage import package2::*.sv): `include "p2. logic [7:0]interval. we are assigning comb output(interval) to ff output end 3 . typedef struct { logic [7:0]data. enum {check_8x. input wire resetN.// interval1 is ff output.next.//local interval state_t state. interval1 <= interval. always_ff @(posedge clk. byte interval. inside_con} state_t. output byte interval1).pkg" module dut(input byte data1. negedge resetN) if(!resetN) begin state <=check_8x. `endif Dut (dut. input wire clk.Source code: Package (p2. con_8x.

resetN.data_interval. forever #5 clk=~clk.interva l).resetN.always_comb begin case (state) check_8x: begin interval=0. next=con_8x. if ( data1[7:4] == 4'h8) next = con_8x. monitor_t data_interval.data_interval.sv" module testbench. initial begin clk=1'b1.interval). end inside_con: begin interval=interval1+1. dut dut_instance(data_interval. reg clk.data. end 4 .data_interval. else next=inside_con. if (data1[7:4] == 4'h8) else next = inside_con. end endcase end endmodule TestBench TestBench (tb2. else next =check_8x.clk. resetN. if (data1[7:4] == 4'h8) next=con_8x.sv): `include "dut. initial $monitor("resetN=%b data=%h interval=%d".data. end con_8x: begin interval=1.

300 seconds.12.data_interval. Runtime version D-2009. data_interval.12.sv". #10 data_interval. Data structure size: 0.data=8'h99. #5 resetN=1. $finish at simulation time 110 V C S S i m u l a t i o n R e p o r t Time: 110 CPU Time: 0.data=8'h8b.data=8'h71.data=8'h87. #10 data_interval. line 35.data=8'h70. #10 data_interval. #10 data_interval. #5 resetN=0. #10 data_interval.data=8'h86. #10 data_interval.data=8'h81.data=8'haa. #10 resetN=1. Compiler version D-2009.0Mb Tue Oct 11 11:50:45 2011 5 .initial begin resetN=0. Oct 11 11:50 2011 resetN=0 data=xx interval= 0 resetN=1 data=70 interval= 0 resetN=1 data=71 interval= 0 resetN=1 data=80 interval= 0 resetN=1 data=90 interval= 1 resetN=1 data=99 interval= 2 resetN=1 data=86 interval= 3 resetN=1 data=87 interval= 1 resetN=0 data=87 interval= 0 resetN=1 data=aa interval= 0 resetN=1 data=8a interval= 0 resetN=1 data=8b interval= 1 $finish called from file "tb2. #10 data_interval. #10 data_interval. end endmodule Simulation Results: Chronologic VCS simulator copyright 1991-2009 Contains Synopsys proprietary information.data=8'h90.data=8'h80. #10 data_interval.data=8'h8a. $finish.

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