# California State University, Sacramento

College of Engineering and Computer Science

CSC 242 –COMPUTER AIDED SYSTEM DESIGN AND VERIFICATION ASSIGNMENT 2

Submitted by Venkata Subba Reddy Yelampalli

On 11th October 2011.

1

The unit has an asynchronous reset input called RESET. INTERVAL is cleared (0) whenever RESET is low. This is an active low signal.CSC 242 Assignment 2 100 points The objective of this assignment is to design an interval counter in SystemVerilog that works by monitoring an 8-bit incoming data called DATA and counts the number of clock cycles between occurrences of “8X”. any 8-bit data in which the upper nibble (the upper half) is 4'b1000. Assume the count does not exceed the 8-bit INTERVAL.e.. i. The number of occurrences is provided through an 8-bit output called INTERVAL. Finite State Machine 2 .

//local interval state_t state. we are assigning comb output(interval) to ff output end 3 . } monitor_t. input wire resetN. `endif Dut (dut. enum {check_8x. negedge resetN) if(!resetN) begin state <=check_8x. typedef struct { logic [7:0]data. byte interval.sv): `include "p2. input wire clk. output byte interval1). end else begin state <= next.next. logic [7:0]interval.Source code: Package (p2. interval1 <= 0.pkg): `ifndef `define package typedef DEFS_DONE DEFS_DONE package2. interval1 <= interval. con_8x. endpackage import package2::*. always_ff @(posedge clk.pkg" module dut(input byte data1. inside_con} state_t.// interval1 is ff output.

data_interval.data_interval.data. reg clk. forever #5 clk=~clk. if (data1[7:4] == 4'h8) next=con_8x.sv): `include "dut. resetN. if ( data1[7:4] == 4'h8) next = con_8x. initial begin clk=1'b1. next=con_8x.data_interval.sv" module testbench.interva l).clk.interval). monitor_t data_interval. end 4 . end endcase end endmodule TestBench TestBench (tb2.resetN. end inside_con: begin interval=interval1+1. else next=inside_con. end con_8x: begin interval=1.always_comb begin case (state) check_8x: begin interval=0. else next =check_8x. initial \$monitor("resetN=%b data=%h interval=%d". if (data1[7:4] == 4'h8) else next = inside_con.resetN. dut dut_instance(data_interval.data.

data=8'h71. data_interval. #10 data_interval.data=8'h90.0Mb Tue Oct 11 11:50:45 2011 5 . Data structure size: 0. #10 data_interval.data=8'h86. Oct 11 11:50 2011 resetN=0 data=xx interval= 0 resetN=1 data=70 interval= 0 resetN=1 data=71 interval= 0 resetN=1 data=80 interval= 0 resetN=1 data=90 interval= 1 resetN=1 data=99 interval= 2 resetN=1 data=86 interval= 3 resetN=1 data=87 interval= 1 resetN=0 data=87 interval= 0 resetN=1 data=aa interval= 0 resetN=1 data=8a interval= 0 resetN=1 data=8b interval= 1 \$finish called from file "tb2.data=8'h81. #10 data_interval.sv".data=8'h80.data=8'h8b. #10 data_interval.300 seconds.data_interval. #10 data_interval.data=8'h87.data=8'h8a. end endmodule Simulation Results: Chronologic VCS simulator copyright 1991-2009 Contains Synopsys proprietary information. #5 resetN=0. #10 resetN=1. #5 resetN=1. #10 data_interval. #10 data_interval.12.data=8'haa. #10 data_interval.initial begin resetN=0. line 35.data=8'h99. \$finish. Compiler version D-2009.12. #10 data_interval.data=8'h70. Runtime version D-2009. \$finish at simulation time 110 V C S S i m u l a t i o n R e p o r t Time: 110 CPU Time: 0.

6 .