California State University, Sacramento

College of Engineering and Computer Science

CSC 242 –COMPUTER AIDED SYSTEM DESIGN AND VERIFICATION ASSIGNMENT 2

Submitted by Venkata Subba Reddy Yelampalli

Instructor: Prof. Behnam Arad

On 11th October 2011.

1

CSC 242 Assignment 2 100 points The objective of this assignment is to design an interval counter in SystemVerilog that works by monitoring an 8-bit incoming data called DATA and counts the number of clock cycles between occurrences of “8X”. INTERVAL is cleared (0) whenever RESET is low. The number of occurrences is provided through an 8-bit output called INTERVAL. Finite State Machine 2 . Assume the count does not exceed the 8-bit INTERVAL. This is an active low signal. any 8-bit data in which the upper nibble (the upper half) is 4'b1000..e. The unit has an asynchronous reset input called RESET. i.

pkg): `ifndef `define package typedef DEFS_DONE DEFS_DONE package2.// interval1 is ff output. } monitor_t. end else begin state <= next. byte interval. interval1 <= 0. typedef struct { logic [7:0]data.sv): `include "p2. always_ff @(posedge clk. input wire clk.next. enum {check_8x. con_8x. output byte interval1). inside_con} state_t. we are assigning comb output(interval) to ff output end 3 . input wire resetN. negedge resetN) if(!resetN) begin state <=check_8x. logic [7:0]interval.pkg" module dut(input byte data1.Source code: Package (p2.//local interval state_t state. `endif Dut (dut. endpackage import package2::*. interval1 <= interval.

end endcase end endmodule TestBench TestBench (tb2.sv): `include "dut. else next =check_8x.always_comb begin case (state) check_8x: begin interval=0. initial $monitor("resetN=%b data=%h interval=%d".resetN. if (data1[7:4] == 4'h8) else next = inside_con. resetN. forever #5 clk=~clk. dut dut_instance(data_interval.interva l).data. if (data1[7:4] == 4'h8) next=con_8x. if ( data1[7:4] == 4'h8) next = con_8x. initial begin clk=1'b1.interval).clk.resetN. reg clk.data. end inside_con: begin interval=interval1+1.data_interval. monitor_t data_interval. end 4 .data_interval. next=con_8x.data_interval.sv" module testbench. else next=inside_con. end con_8x: begin interval=1.

data=8'h99. #10 data_interval.data=8'h90.data=8'h81. $finish. end endmodule Simulation Results: Chronologic VCS simulator copyright 1991-2009 Contains Synopsys proprietary information.data=8'haa. Compiler version D-2009.300 seconds. #5 resetN=0.0Mb Tue Oct 11 11:50:45 2011 5 .data=8'h86. #10 data_interval. #10 data_interval. Data structure size: 0.data=8'h8a. $finish at simulation time 110 V C S S i m u l a t i o n R e p o r t Time: 110 CPU Time: 0. data_interval.sv". #10 data_interval. #10 data_interval. line 35. #10 data_interval.data=8'h80. #10 data_interval. Oct 11 11:50 2011 resetN=0 data=xx interval= 0 resetN=1 data=70 interval= 0 resetN=1 data=71 interval= 0 resetN=1 data=80 interval= 0 resetN=1 data=90 interval= 1 resetN=1 data=99 interval= 2 resetN=1 data=86 interval= 3 resetN=1 data=87 interval= 1 resetN=0 data=87 interval= 0 resetN=1 data=aa interval= 0 resetN=1 data=8a interval= 0 resetN=1 data=8b interval= 1 $finish called from file "tb2.data_interval.initial begin resetN=0.data=8'h70. #10 data_interval. #10 data_interval.data=8'h8b.12.12. #5 resetN=1.data=8'h71.data=8'h87. #10 resetN=1. Runtime version D-2009.

6 .

Sign up to vote on this title
UsefulNot useful