California State University, Sacramento

College of Engineering and Computer Science

CSC 242 –COMPUTER AIDED SYSTEM DESIGN AND VERIFICATION ASSIGNMENT 2

Submitted by Venkata Subba Reddy Yelampalli

Instructor: Prof. Behnam Arad

On 11th October 2011.

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The number of occurrences is provided through an 8-bit output called INTERVAL.CSC 242 Assignment 2 100 points The objective of this assignment is to design an interval counter in SystemVerilog that works by monitoring an 8-bit incoming data called DATA and counts the number of clock cycles between occurrences of “8X”. Assume the count does not exceed the 8-bit INTERVAL. any 8-bit data in which the upper nibble (the upper half) is 4'b1000. The unit has an asynchronous reset input called RESET. i..e. This is an active low signal. Finite State Machine 2 . INTERVAL is cleared (0) whenever RESET is low.

byte interval.sv): `include "p2. input wire resetN. logic [7:0]interval. enum {check_8x. interval1 <= interval. always_ff @(posedge clk.next.// interval1 is ff output.pkg): `ifndef `define package typedef DEFS_DONE DEFS_DONE package2. input wire clk. typedef struct { logic [7:0]data. `endif Dut (dut. } monitor_t. interval1 <= 0.//local interval state_t state.pkg" module dut(input byte data1. end else begin state <= next. con_8x. endpackage import package2::*.Source code: Package (p2. inside_con} state_t. output byte interval1). negedge resetN) if(!resetN) begin state <=check_8x. we are assigning comb output(interval) to ff output end 3 .

if (data1[7:4] == 4'h8) else next = inside_con. if ( data1[7:4] == 4'h8) next = con_8x. reg clk. resetN. dut dut_instance(data_interval.sv" module testbench.data_interval.always_comb begin case (state) check_8x: begin interval=0. next=con_8x. monitor_t data_interval.data. initial $monitor("resetN=%b data=%h interval=%d". else next=inside_con. end endcase end endmodule TestBench TestBench (tb2.resetN.clk.data. else next =check_8x.interval).data_interval.resetN. forever #5 clk=~clk. end con_8x: begin interval=1. if (data1[7:4] == 4'h8) next=con_8x.interva l). initial begin clk=1'b1. end 4 .data_interval. end inside_con: begin interval=interval1+1.sv): `include "dut.

$finish. Oct 11 11:50 2011 resetN=0 data=xx interval= 0 resetN=1 data=70 interval= 0 resetN=1 data=71 interval= 0 resetN=1 data=80 interval= 0 resetN=1 data=90 interval= 1 resetN=1 data=99 interval= 2 resetN=1 data=86 interval= 3 resetN=1 data=87 interval= 1 resetN=0 data=87 interval= 0 resetN=1 data=aa interval= 0 resetN=1 data=8a interval= 0 resetN=1 data=8b interval= 1 $finish called from file "tb2. end endmodule Simulation Results: Chronologic VCS simulator copyright 1991-2009 Contains Synopsys proprietary information. Compiler version D-2009. #5 resetN=1. #10 resetN=1. line 35. #10 data_interval.data=8'h90.data=8'h71.initial begin resetN=0. #10 data_interval.data_interval. #5 resetN=0.sv". Data structure size: 0. #10 data_interval.300 seconds.data=8'haa.data=8'h99. Runtime version D-2009. #10 data_interval. #10 data_interval.data=8'h8a. #10 data_interval. $finish at simulation time 110 V C S S i m u l a t i o n R e p o r t Time: 110 CPU Time: 0.data=8'h80.12. #10 data_interval.0Mb Tue Oct 11 11:50:45 2011 5 .data=8'h70.data=8'h87.data=8'h86.12.data=8'h8b. #10 data_interval. #10 data_interval.data=8'h81. data_interval.

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