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TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

. DEPARTMENT OF ECE PAGE NO.-4

Figure 2.-5 . The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers.1. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. As shown at the bottom of Figure 1. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. the real-number system comprises the continuum of real numbers from minus infinity (. only a subset of the real-number continuum can be used in real-number calculations. As shown in Figure 1.) to plus infinity (+ ). DEPARTMENT OF ECE PAGE NO.1: Binary Real Number System Because the size and number of registers that any computer can have is limited. . The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations.

With unsigned fraction notation. low-cost development tools. For instance. DSPs enable designers to build innovative features and differentiating value into their products.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. the signed fraction format allows . Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data. Digital Signal Processing can be divided into two categories. In unsigned integer. 2. the number is an integer). some specific assumption is made about where the radix point is located in the string. These refer to the format used to store and manipulate numbers within the devices.-6 .2. Among the key factors to consider are the computational capabilities required for the application. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. from -32. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. Balancing these factors together. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there.536 possible bit patterns can represent a number. the stored number can take on any integer value from 0 to 65. In fixed-point systems. designers can identify the DSP that is best suited for an application. and ease of development. There are four common ways that these 216 ' 65. fixed point and floating point. signed integer uses two's complement to make the range include negative numbers. Motorola manufactures a family of fixed point DSPs that use 24 bits. Software programmable for maximum flexibility and supported by easy-touse.768 to 32. Lastly. In common mathematical notation. performance attributes. Similarly. Fixed point DSPs usually represent each number with a minimum of 16 bits.536 levels are spread uniformly between 0 and 1.767. the 65. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. the digit string can be of any length. but decimal fixed point is common in commercial applications. DEPARTMENT OF ECE PAGE NO. processor and system costs. although a different length can be used.535. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. Fixed-point Vs floating-point in digital signal processing Fig 2. while floating-point DSPs support either integer or real arithmetic.

this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). DEPARTMENT OF ECE PAGE NO. which is capable of representing real and decimal numbers.754-1985). it can be placed anywhere relative to the significant digits of the number. a necessity to implement counters. This is important because it places large gaps between large numbers. The represented values are unequally spaced between these two extremes. or sometimes the mantissa (see below) or coefficient.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. it depends on the internal architecture. 2. The floating-point operations are incorporated into the design as functions. For instance. The speed of floating-point operations is an important measure of performance for computers in many application domains.3. equally spaced between -1 and 1. This is known as the significand. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. that is.4 ×1038 and ±1. The radix point is not explicitly included." rather than just "Floating Point. respectively. This position is indicated separately in the internal representation. The term” floating point” refers to the fact that the radix point can "float". It is measured in” FLOPS”. but small gaps between small numbers." 2. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . In the most common format (ANSI/IEEE Std. and executes them with equal efficiency. The logic for these is different from the ordinary arithmetic functions.2 ×1038. the largest and smallest numbers are ±3.In comparison. For this reason.However. 2324. Floating point A floating-point number is the one. the SHARC devices are often referred to as "32-bit DSPs.-7 . All floating point DSPs can also handle fixed point numbers.296 to be exact. the SHARC DSPs are optimized for both floating point and fixed point operations. and signals coming from the ADC and going to the DAC.4. and floating-point representation can thus be thought of as a computer realization of scientific notation.967. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. loops. This results in many more bit patterns than for fixed point. floating point DSPs typically use a minimum of 32 bits to store each value. A key feature of floating point notation is that the represented numbers are not uniformly spaced.294.

2. floating-point numbers achieve their greater range at the expense of precision. The floating-point format needs slightly more storage (to encode the position of the radix point). b is the base.32-BIT FLOATING POINT PROCESSOR TEC significant digit. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. DEPARTMENT OF ECE PAGE NO. 1 for negative values. this final value is where s is the value of the significand (after taking into account the implied radix point). Prior to the IEEE-754 standard. The length of the significand determines the precision to which numbers can be represented. A signed integer exponent.-8 . the format of the representations. Significand is a real number.5. so when stored in the same space. These differing systems implemented different parts of the arithmetic in hardware and software. These differed in the word sizes. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. also referred to as the characteristic or scale. or to the right of the rightmost digit. composed as integer. and the rounding behaviour of operations.Fraction. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. 10 or 16. with an average error of about 3%. which modifies the magnitude of the number. Symbolically. (This is because the exponent field is in . computers used many different forms of floating-point. and e is the exponent. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. The significand is multiplied by the base raised to the power of the exponent.

A float is represented using 32 bits. 1 denotes a negative number. The Mantissa: The mantissa. and the mantissa. or 1023 plus the true exponent for double precision. The first bit of the mantissa is typically assumed to be 1. Flipping the value of this bit flips the sign of the number.-9 . the exponent. It is composed of an implicit leading bit and the fraction bits. to sum up: 1. also known as the significand. and each possible combination of bits represents one real number. represents the precision bits of the number. To do this. This means that at most 232 possible real numbers can be exactly represented. 0 denotes a positive number. There are many formats that are used for representation of floating point number. 1 for negative.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. The exponent field contains 127 plus the true exponent for single-precision. 4. The Sign Bit: The sign bit is as simple as it gets. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. such as volume ramping in digital sound processing. So. 3.) This can be exploited in some applications. 2. even though there are infinitely many real numbers (even between 0 and 1). where f is the field of fraction bits. The Exponent: The exponent field needs to represent both positive and negative exponents. DEPARTMENT OF ECE . The sign bit is 0 for positive. a bias is added to the actual exponent in order to get the stored exponent.f. The exponent's base is two.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. IEEE-754 specifies binary representations for floating point numbers: Table 2.

2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. S. then V=NaN ("Not a number") If E=255 and F is zero and S is 1.1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values.5. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010). IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude.5.-10 .1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2. 'E'.5. then V=-Infinity If E=255 and F is zero and S is 0. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero. left to right. DEPARTMENT OF ECE PAGE NO. then V=Infinity . exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). Table 2. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. the next eight bits are the exponent bits. which may be represented as numbered from 0 to 31.

then V=-0 If E=0 and F is zero and S is 0.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0. If E=0 and F is zero and S is 1.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1. DEPARTMENT OF ECE PAGE NO.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.0 The biased exponent is .101 = 6. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.101 = -6.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.F) where "1.F) These are "unnormalized" values.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0. then V=0 In particular.-11 . then V=(-1)**S * 2 ** (-126) * (0. If E=0 and F is nonzero.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.3125 The biased exponent is -2+127=125= (01111101 • 1.

5 × 2 = 0.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0.40625 0.203125 0.5 The based exponent: 127+5= (10000100 .203125 × 2 = 0.1015625 × 2 = 0.8125 × 2 = 1.5 × 2 = 1. . DEPARTMENT OF ECE PAGE NO.312510 = 10100100001. 10 + 127 = 137 = 100010012.0 0 1 0 1 1313. So -1313. = 1.-12 .25 × 2 = 0.625 0.8125 .3125 131310 = 101001000012 0.32-BIT FLOATING POINT PROCESSOR TEC • 37.625 × 2 = 1.25 The biased exponent: 127+6=133=(10000101 • -1313. • -78.1015625 0.01012. sign bit is 1.3125 0.010010000101012 × 210.25 0.40625 × 2 = 0.3125 is • 0.

0 1 0.25 1 × 2 = 0. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001).5 0 × 2 = 1.3.00011012 = 1. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0).5. DEPARTMENT OF ECE . S.5 × 2 = 1.101562510 = 0. 'E'. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.625 0.1015625 is 0 00111101 110100000000000000000000 TEC 2.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.-13 . left to right. The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero. the next eleven bits are the exponent bits. The first bit is the sign bit.25 0. which may be represented as numbered from 0 to 63. then V=NaN ("Not a number") PAGE NO.32-BIT FLOATING POINT PROCESSOR 0.5.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.

If E=0 and F is zero and S is 1. .F) These are "unnormalized" values. Table 2.-14 . 15 exponent bits and 112 significand bits. then V=-Infinity If E=2047 and F is zero and S is 0.53 ~ 10308. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. while maintaining good precision. then V=(-1)**S * 2 ** (-1022) * (0.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. If E=0 and F is nonzero. floating-point notation allows calculations over a wide range of magnitudes. using a fixed number of digits.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit .4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038.6.5.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1. then V=-0 If E=0 and F is zero and S is 0.F) where "1.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). DEPARTMENT OF ECE PAGE NO.

32-BIT FLOATING POINT PROCESSOR TEC Table 2. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2. Negative numbers greater than -2-149 (negative underflow) 3.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. P is the precision of the system to P numbers. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand. DEPARTMENT OF ECE PAGE NO.-15 . Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent.53 ~10-323.6. Positive numbers less than 2-149 (positive underflow) . There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. L is the smallest exponent represent able in the system. Zero 4. P.2: Effective Range of IEEE Floating Point Number with Denormalized.3 to ~10308. and the smallest possible value for the exponent. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1). L. the range for negative numbers is given by the negation of the above values. There is a smallest positive normalized floating-point number.85 to ~1038. There is a largest floating point number. Normalized And Approximate Decimal Values. The number of normalized floating point numbers in a system F(B. U) (where B is the base of the system. Approximate Decimal 2127 21023 ~10-44.

Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. 2. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. DEPARTMENT OF ECE PAGE NO. the largest value which is defined in bias-127 exponent representation. However the CPU will have to perform extra arithmetic to read the number when stored in this format.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. When this occurs.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . the exponent is set to -127 (E = 0).infinity. 2. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or .-16 .32-BIT FLOATING POINT PROCESSOR 5. the number is exactly zero. Recently. Underflow occurs when the sum of the exponents is more negative than -126. If M = 0. the most negative value which is defined in bias-127 exponent representation. When this occurs. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex.

Add the numbers with decimal points aligned. both the numbers are added. Floating point addition is analogous to addition using scientific notation. as the smaller number here is a=2. But by using floating point addition this can be avoided to a little extent. Normalize the result. i. Hence the value of number ‘a’ becomes 0.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points. Division 2. . Multiplication 4.. DEPARTMENT OF ECE PAGE NO.-17 . Now as both the exponent values are same..32-BIT FLOATING POINT PROCESSOR TEC Fig 2.25x and b= 1. They are: 1. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. For example.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. Addition 2. let us consider two numbers a= 2. Subtraction 3.8.0225x .e.1.

Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value. b= 9. then bit 1 is represented for sign.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. But the normalised result may sometimes carry the required result.. The mantissa of both numbers A and B are added. 2. ExpB as exponent of number B and ManB as mantissa of number B.1.1.234567x and b= 9.876543x after shifting becomes b= 0. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: . DEPARTMENT OF ECE PAGE NO..e. 2.2345670 x in which the remaining part (9876543) which is discarded also carries the result. then sign of greater number is considered. i.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.234567x b= 0.8.8. ManA as mantissa of number A.-18 . Thus this case can said to be having rounding errors.1. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.8.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . then the following result may occur: 1.e.1.2. Now both the numbers are added. a =1. signB as sign of number B. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i.876543x and if the addition has to be performed. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.00000009876543 x c= 1. If the numbers are represented with both positive and negative sign. Consider a example in which a =1.00000009876543 x 2. ExpA as exponent of number A .

the bias value must be subtracted from the sum 3. the significand is rounded to the appropriate number of bits required and again normalization is checked. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.8. 1. If there is an underflow or overflow. Thus. 4. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. the numbers are represented in IEEE floating point format.2: Flow Chart for Floating Point Adder.1. If the exponents are stored in biased form. 5. . Addition of significands is done. 2. the exponent sum would have doubled the bias. Firstly. DEPARTMENT OF ECE PAGE NO. exception is made.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. 6. If not.-19 .

-20 . the result is converted back to signmagnitude form.8. DEPARTMENT OF ECE PAGE NO. Subtraction .340625x .25x and 1. If the sum overflows the position of the hidden bit. Normalization in this case may require shifting by the total number of bits in the mantissa. then the mantissa must be shifted one bit to the right and the exponent incremented. The mantissa is always less than 2.32-BIT FLOATING POINT PROCESSOR TEC 7.25 in IEEE Floating Point Standard is: The number 134. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form.0625 in IEEE Floating Point Standard is: To align the binary points. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. When adding numbers of opposite sign. 2. The number 2. so the hidden bits can sum to no more than 3 (11).25 becomes: The mantissas are added using integer addition: The result is already in normal form. resulting in a sum which is arbitrarily small. After the addition is performed. Negative mantissas are handled by first converting to 2's complement and then performing the addition. Thus. or even zero if the numbers are equal in magnitude. cancellation may occur. 2. resulting in a large loss of accuracy.2. Consider addition of the numbers 2.

Subtract the numbers with decimal points aligned. as the smaller number here is a=2. Normalize the result. i.-21 .2. then sign is represented according to the number i.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .8. The mantissa of both numbers A and B are subtracted.. ExpA as exponent of number A .1. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if .32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2.e.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. both the numbers are added. ExpB as exponent of number B and ManB as mantissa of number B. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. Now as both the exponent values are same.e.8.. DEPARTMENT OF ECE PAGE NO..340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal. Hence the value of number ‘a’ becomes 0. 2. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.0225x .25x and b= 1.1. The normalised result may contain the required number of digits discarding the unwanted part.2. signB as sign of number B. ManA as mantissa of number A.

If the exponents are stored in biased form. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. 4. If there is an underflow or overflow. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. 2.0625 in IEEE Floating Point Standard is: To align the binary points. the significand is rounded to the appropriate number of bits required and again normalization is checked.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign. Subtraction of significands is done. exception is made.25x and 1. DEPARTMENT OF ECE PAGE NO. The number 2. 2. 6. The numbers are represented in IEEE floating point format. the exponent sum would have doubled the bias.2.25 become: The mantissas are subtracted using integer subtraction: .8. 2.340625x . the bias value must be subtracted from the sum 3. 5.-22 . If not. Thus. Consider subtraction of the numbers 2.25 in IEEE Floating Point Standard is: The number 134. Thus.2. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.

If the sum overflows the position of the hidden bit. then the following steps can be followed: Exponents of both the numbers are checked. If the significand is zero then it is returned if not significand overflow is checked. DEPARTMENT OF ECE PAGE NO.2.. If overflow occurred then overflow is reported and returned. then number Y is checked. If it is ‘0’ then the resultant solution Z would be Y i. In the first step.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction.3.2.e. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent . If it is ‘0’. If overflow occurs. consider two numbers X and Y and the resultant be Z. If both the numbers X and Y are non zeros. then the result would be Z=X. Z=Y. If the exponents are same. If not then the result is normalized. At this point. then the mantissa must be shifted one bit to the right and the exponent incremented. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked.8. Flow chart for floating point subtraction: Subtract significand si Fig 2.8. If number X is not ‘0’. then the significands of numbers X and Y are subtracted. number X is checked.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form.-23 . 2.

5 in IEEE FPS format is: .-24 . Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.8.8 x 9. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly. 2.5x : Perform unsigned integer multiplication of the mantissas.3. The number 18. If underflow occurred then it is reported if not the normalized result is given out.8. if the significand is not zero then subtraction and further process is carried out.0 in IEEE FPS format is: The number 9. to multiply 1.8x times 9.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result. If the exponents are not same. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z. 1.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked.3. 2.5 ----17. For example. DEPARTMENT OF ECE PAGE NO.1.

The sign of the result is the xor of the sign bits of the two numbers. DEPARTMENT OF ECE PAGE NO. Block diagram of floating point multiplication: . the mantissa is: The biased-127 exponents are added. If the position of the hidden bit overflows.2.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in (). the mantissa must be shifted right and the exponent incremented. When the fields are assembled in IEEE FPS format.3. the result is: 2.-25 . Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form.8.

expB as exponent of number B and manB as mantissa of number B.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. the exponent sum would have doubled the bias.3. The exponents of both the numbers are added and subtracted from the bias 127. manA as mantissa of number A. At the first step.3.8. Sign of the result is given by performing xor operation of signA and signB. Thus. Resultant mantissa is truncated and normalized to fit for the IEEE format. The mantissa of both numbers A and B are multiplied. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported.3. expA as exponent of number A . .2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. then the exponents are added and a bias of 127 is subtracted from the result. DEPARTMENT OF ECE PAGE NO. If the exponents are stored in biased form. If both the numbers X and Y are not zero.8.-26 . Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. XOR operation for sign bit can be given as follows: Table 2.3. signB as sign of number B.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A .8. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero.

So resultant exponent would be 2-3=-1. When the division of both significands are done then the quotient would be 1.3: Flow Chart For Floating Point Multiplication.3 and b= 0.3 0. Exponent of a is 2 and exponent of b is 3. Fig 2.. DEPARTMENT OF ECE PAGE NO.-27 . i.5.5. Hence the result can be given as 1. in general floating point division the exponents of both the numbers are subtracted and the significands are divided.8. The resultant sign bit would be the xor operation of sign bits of X and Y. 0.2 . .2 =1.e.3. 2.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned.8. Division Consider an example of dividing a=0.5 .4.

The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend.4. ExpB as exponent of number B and ManB as mantissa of number B. signB as sign of number B.-28 . ManA as mantissa of number A. Subtract the exponent of the divisor from the exponent of the dividend.8. The exponents are subtracted and biased using the bias value.8. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement.8. a 24 bit quotient is produced. ExpA as exponent of number A . overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. Special . The mantissa of both numbers A and B are divided. Normalize the result. If both the numbers are either positive or negative.1.4. In the first step. Block diagram for floating point division: Fig 2.32-BIT FLOATING POINT PROCESSOR TEC 2. If anyone number of the two are negative. As in floating point multiplication.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. then the result is also negative is represented by bit ‘1’. DEPARTMENT OF ECE PAGE NO. Set the sign of the result.4. When divided by a 24 bit divisor. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. 2. then the resultant sign is also positive and is represented by bit ‘0’.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .

or NaN.3 0. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned.-29 . . Considering a=0.4. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked. For this. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity .2 can be represented as M 010000001(0)11000000000000000000000 0.8.3.Then the steps that occur are: 1. DEPARTMENT OF ECE PAGE NO. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted. Number X and Y are checked. This value is called Not A Number. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero.3 S E and b= 0.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. 2. in this case as larger number has to be subtracted from smaller number.

rounding errors occur as a result of the limited precision of the mantissa .-30 . Fig 2.8. In some systems.127). • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit. .32-BIT FLOATING POINT PROCESSOR TEC 3. If they are present. • Significand underflow: In the process of aligning significands.9. this may be designated as +∞ or -∞. and it may be reported as 0. digits may flow off the right end of the significand.This means that the number is too small to be represented. then those conditions are reported.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. some form of rounding is required. As we shall discuss.4.. DEPARTMENT OF ECE PAGE NO.200 is less than . 2. If not the mantissas are divided and truncated and normalized result is given out.g. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. Rounding Error In floating point arithmetic.

For numbers in IEEE FPS format.-31 . DEPARTMENT OF ECE PAGE NO. However.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. For normalized floating point numbers. . Same as truncation in 2's complement. RZ: Round toward Zero. RP: Round toward Positive infinity. Normalization By normalization. To efficiently use the bits available for the significand. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. Break ties by choosing the least significant bit = 0.10. relative errors increase as the magnitude of the number decreases toward zero. RN is generally preferred and introduces less systematic error than the other rules. The least significant 24 bits are discarded. RM: Round toward minus infinity. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. highest precision can be achieved. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. The value can be kept unchanged by adjusting the exponent accordingly. the relative error is approximately since For denormalized numbers (E = 0). The size of the absolute error is proportional to the magnitude of the number. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. Same as truncation in sign-magnitude.

Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit. extra guard bits are kept during operation. multiplication). resulting 1. the bits need to be truncated to guard bit Chopping: simply drop all ..11.-32 .g. bits are used in final representation of a bits by one of the three methods. The first bit 1 before the decimal point is implicit. The actual value represented is However.32-BIT FLOATING POINT PROCESSOR TEC Moreover. as the MSB of the significand is always 1. Zero is represented by all 0's and is not (and cannot be) normalized. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. Truncation To retain maximum accuracy. in the following the default normalization does not assume this implicit 1 unless otherwise specified. a 4-bit exponent field and a 9-bit significand field): 2. By the end of the operation. DEPARTMENT OF ECE PAGE NO. all extra bits during operation (called guard bits) are kept (e. If we assume number. to avoid possible confusion. it does not need to be shown explicitly.

set whether it is originally 0 or 1). otherwise do nothing. is always greater than 0. the Von Neumann rounding error is unbiased. we say this truncation error is biased. DEPARTMENT OF ECE PAGE NO. Interpretation: Value represented by guard bits is greater than 0. Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. . (no matter Von Neumann Rounding: If at least one of the guard bits is 1. 3. . add 1 to LSB . Two worst cases Both two cases can be summarized as i.32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2.-33 ..e.5 round up.

DEPARTMENT OF ECE PAGE NO.5 either up or down with equal probability (50%). . the rounding depends on the LSB : if . round down: or if . Interpretation: Value represented by guard bits is smaller than 0. it is randomly rounded .-34 . c) If the highest guard bit is 1 and the rest guard bits are all 0. The rounding error of these cases can summarized as . drop all guard bits.32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0. round up: Interpretation: Value represented by guard bits is 0.5 round down.

1985 floating point standard representation before any sort of operations are conducted on them. Therefore zero is represented by 0111.e. which is capable of representing real and decimal numbers. The floating-point operations are incorporated into the design as functions.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . The exponent in this IEEE standard is represented in excess-127 format. 1111 and negative numbers are represented by binary values less than it. The numbers in contention have to be first converted into the standard IEEE 784. multiplication and division is presented in the following pages. The logic for these is different from the ordinary arithmetic functions. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number.e. the sign of the floating point number. The logic for floating point addition. I.-35 . The above representation is the IEEE-784 1985 standard representation. 1111. The next eight bits are that of the exponent. The MSB is the sign-bit i. . Positive numbers are represented by binary values greater than 0111.3 Floating Point Functions A floating-point number is the one. DEPARTMENT OF ECE PAGE NO. subtraction. 1111. the exponent obtained by balancing operations is added to 0111.

These numbers are stored into the memory from which they are read and processed. • • . namely Accumulator and the Temp register that loads the value appearing on the data bus. These numbers are distinct.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation.-36 . we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. Once the exponents are normalized. DEPARTMENT OF ECE PAGE NO. So to add their mantissa’s. So.32-BIT FLOATING POINT PROCESSOR TEC 3. This is done till the lower exponent becomes equal to the higher one. The mantissas are then added to each other and the result is then stored in a temporary register. we have to first normalize their exponents. Now the numbers from the memory are loaded into two registers.

These numbers are distinct.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. The mantissas are then subtracted and the result is stored in a temporary register. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. These numbers are stored into the memory from which they are read and processed. So. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately.-37 . we have to first normalize their exponents. Now the numbers from the memory are loaded into two registers. . Once the exponents are normalized.32-BIT FLOATING POINT PROCESSOR 3. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. This is done till the lower exponent becomes equal to the higher one. namely Accumulator and the Temp register that loads the value appearing on the data bus. DEPARTMENT OF ECE PAGE NO. So to add their mantissa’s.

-38 . In multiplication the operations are done simultaneously and separately on the mantissa and the exponent.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. The final output is obtained by concatenating the product of the mantissas.32-BIT FLOATING POINT PROCESSOR TEC 3. the resulting exponent and the sign of the result that is calculated separately. There is however a limitation to this operation. so that the result is restricted to not more than 24-bits. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. DEPARTMENT OF ECE PAGE NO. • • • . So each input should not exceed 12-bits in length.

if the MSB or the 49th bit is one than we add a one in the quotient. we put a zero in the quotient. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. till the quotient is full. This is to ensure that whatever comes as the result is after the decimal point. First the exponents are directly added or subtracted depending on which is bigger. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. We initiate a counter and carry this process for 24 times.-39 . The decimal is assumed to be before the MSB of the resulting quotient. Apart from that the final sign of the division is calculated separately. DEPARTMENT OF ECE PAGE NO. Now the first 24-bits from the MSB are compared with the divisor. Now since the greater of the two numbers is decided. we append it with the exponent value and the Sign of the division that are calculated separately. Now both the numbers in the IEEE-784 standard format are compared. The logic for floating point division is as follows.32-BIT FLOATING POINT PROCESSOR TEC 3.4 Floating Point Division • • • • This is more complicated then Multiplication. Once the quotient is full. And if it is zero. The result is stored in Temp. The convention here is that the Numerator should be always less than the denominator. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. • • • • • .

such as the size of the instruction set and how it interrupts are handled. however it is difficult or expensive to make a device that is optimized for both. competitive position. etc). 16.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. The clock speed (also called cycle). When the processor executes instructions. A<B . and so on. written in Hertz (Hz). Computers are extremely capable in two broad areas 1. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. These tasks are accomplished by moving data from one location to another. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. local memory locations of 8. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. the overall number of registers can vary from about ten to many hundreds. the program moves the data from . Data manipulation such as word processing and database management 2. For instance. corresponds to the number of pulses per second. data is temporarily stored in small. Consider another example of how a document is printed from a word processor. There are technical tradeoffs in the hardware design. There are marketing issues involved: development and manufacturing cost. 4. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). The basic task is to store the information. With each clock peak. and testing for inequalities (A=B. When this code is detected.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. Mathematical calculation used in science.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. Data manipulations involve storing and sorting information. the processor performs an action that corresponds to an instruction or a part thereof. finding use in everything from cellular telephones to advanced scientific instruments. Clock frequency is generally a multiple of the system frequency. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. 32 or 64 bits called registers. These devices have seen tremendous growth in the last decade.-40 . engineering and digital signal processing. Depending on the type of processor. meaning a multiple of the motherboard frequency. DSPs can perform the mathematical calculations needed in digital signal processing. DEPARTMENT OF ECE PAGE NO. consider a word processing program. product life time. All microprocessors can perform both tasks.

while the output signal is denoted by y [ ].. DEPARTMENT OF ECE PAGE NO. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: .. The task is to calculate the sample at location n in the output signal. the input signal is referred to by x [ ]. While there is some data transfer and inequality evaluation in this algorithm.32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. This is simply saying that the input signal has been convolved with a filter kernel consisting of: . depending on the application.. In comparison. For example... ... While mathematics is occasionally used in this type of application.... the most common DSP technique.. such as to keep track of the intermediate results and control the loops. it is infrequent and does not significantly affect the overall execution speed. y[n].-41 .e. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required.. the math operations dominate the execution time. there may only be a few coefficients in the filter kernel. i. consider the implementation of an FIR digital filter. Using standard notation.

Digital signal processors are designed to quickly carry out FIR filters and similar techniques. the information may be read into a computer and analysed in some way. Also. the entire input signal resides in the computer at the same time.32-BIT FLOATING POINT PROCESSOR TEC Fig4.3.000 samples per second. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers.000 samples per second. not having a defined start or end. so as the cost . DSPs must also have a predictable execution time.. There are a few reasons for why to not to make it faster than necessary because as speed increases. . as well as the algorithms that can be applied. You simply wait for the action to be completed before you give the computer its next assignment In comparison. say. but these items will appear as chip fabrication technology gets denser. . They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. and summing the products.-42 . The disadvantages of 32-bit processors are cost and system complexity. the traditional speed advantage of integer operations over floating point operations is decreasing. After shaking is over. Off-line processing is a realm of personal computers and mainframes. with the advent of very fast floating point processing hardware.. Floating point calculations also require a 32-bit processor for good efficiency.. whereas 32-bit processors are naturally suited to the size of the data elements. each sample in the output signal .x[n-1]. converting a word processing document from one form to another. a geophysicist might use a seismometer to record the ground movement during the earthquake. Difference between off-line processing and real time processing: In off-line processing. x[n]. If suppose you are launching your desktop computer on some task . 4. is found by multiplying samples from the input signal.. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors.x[n-2]. consider a designing of an audio signal in DSP system such as a hearing aid. For instance. For example. If the digital signal is being received at 20. However.by the filter kernel coefficients. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. In FIR filtering . Hence execution time is critical for selecting the proper device. the DSP must be able to maintain a sustained throughput of 20. The key point in off-line processing is that all of the information is simultaneously available to the processing program.2. most DSPs are used in applications where the processing is continuous. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. design difficulty and so on..1: Graphical representation of FIR digital filter design. This is common in scientific research and engineering. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. In addition to performing mathematical calculations very rapidly. and to support code written in high level languages. In these cases a 16-bit processor may suffice. There is less room on-chip for extra features such as hardware multipliers. power consumption.y[n]. floating point math must often be used to reduce the cost of programming a project. DEPARTMENT OF ECE PAGE NO.

the binary codes that go into the program sequencer. while keeping the input signal in data memory. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. This includes data. Super Harvard Architecture (SHARC). While the SHARC DSPs are optimized in dozens of ways. perform the algorithm and output a sample.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. Real time applications input a sample. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). program instructions and data can be fetched at the same time. Most of the computers are using this architecture today. . two binary values (the numbers) must be passed over the data memory bus. we might place the filter coefficients in program memory. When two numbers are multiplied. there are two serial ports that operate at 40 Mbits/second each. and an I/O controller.4. For example. Harvard Architecture. For instance. the output signal is produced at the same time that the input signal is acquired. we start by relocating part of the "data" to program memory. Different architectures available are: Von Neumann Architecture. Harvard architecture has separate memories for data and program instructions. Likewise. such as samples from the input signal and filter coefficients as well as program instructions. this is needed in telephone communication. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. Most present day DSPs use this dual bus architecture. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. 4. To improve upon this situation. improving the speed over the single bus design. Alternatively. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. The SHARC DSPs provides both serial and parallel communications ports. The basis of Harvard design is that the data memory bus is busier than the program memory bus. This is the world of digital signal processors. For instance. with separate buses for each. These are extremely high speed connections.-43 . two areas are important enough to be included are an instruction cache. hearing aids and radar. the data transfer rate is an incredible 240Mbytes/second. over and over. When all six parallel ports are used together. while six parallel ports each provide a 40 Mbytes/second data transfer. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. Since the buses operate independently. DEPARTMENT OF ECE PAGE NO. while only one binary value (the program instruction) is passed over the program memory bus. they may input a group of samples perform the algorithm and output a group of samples. at a 40 MHz clock speed. For example.

providing higher speed. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. the coefficient comes over the program memory bus. the program instructions must be passed over the program memory bus. providing an additional interface to off-chip memory and peripherals. the Harvard architecture uses separate memories for data and instructions. this efficient transfer of data is called a high memory-access bandwidth. In comparison. such as instructions. a feature called mixed signal. The first time through a loop. The main buses (program memory bus and data memory bus) are also accessible from outside the chip.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. the program instructions can be pulled from the instruction cache. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. and the program instruction comes from the instruction cache. This means that the same set of program instructions will continually pass from program memory to the CPU.-44 . The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. However. This allows . However. all DSPs can interface with external converters through serial or parallel ports. on additional executions of the loop.4. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. DSP algorithms generally spend most of their execution time in loops. DEPARTMENT OF ECE PAGE NO. Some DSPs have on-board analog-to-digital and digital-toanalog converters.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. In the jargon of the field. This is a small memory that contains about 32 of the most recent program instructions.

2: Typical DSP architecture. and is quite transparent to the programmer.-45 . Digital Signal Processors are designed to implement tasks in parallel. and similar functions.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. The math processing is broken into three sections. accessible at 40Mwords/second (160 Mbytes/second). OR. and the two results returned to any of the 16 registers. This simplified diagram is of the Analog Devices SHARC DSP. a multiplier. In a single clock cycle. absolute value. DEPARTMENT OF ECE PAGE NO. logical operations (AND. multiplies them. Fig 4. and a barrel shifter. All of the steps within the loop can be executed in a single clock cycle. These control the addresses sent to the program and data memories. for 32 bit data. specifying where the information is to be read from or written to. The multiplier takes the values from two registers. NOT). . At the top of the diagram are two blocks labelled Data Address Generator (DAG). conversion between fixed and floating point formats. The ALU performs addition. data from registers 8-15 can be passed to the ALU. one for each of the two memories.4. In simpler microprocessors this task is handled as an inherent part of the program sequencer. and so on. XOR. extracting and depositing segments. and places the result into another register. subtraction. data from registers 0-7 can be passed to the multiplier. rotating. an arithmetic logic unit (ALU). Elementary binary operations are carried out by the barrel shifter. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. Compare this architecture with the tasks needed to implement an FIR filter. such as shifting.

However. underflow and round-off. Tradeoffs of cost and ease of use often heavily influenced the fixed. All the registers and data buses must be 32 bits wide instead of only 16. By contrast. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. including a 53-bit mantissa and an 11-bit exponent). Double-width precision achieves much greater precision and dynamic range at the expense of speed. floating point programs often have a shorter development cycle.-46 . the multiplier and ALU must be able to quickly perform floating point arithmetic. In addition. respectively. DEPARTMENT OF ECE PAGE NO. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. the latter normalized in the form of scientific notation. TMS320C5x™ and TMS320C2x™ DSPs. and executes them with equal efficiency.For instance. The internal architecture of a floating point device is more complicated than for a fixed point device. since it requires multiple cycles for each operation. For this reason. However." fixed point arithmetic is much faster than floating point in general purpose computers. a necessity to implement counters. with DSPs the speed is about the same. since the programmer doesn’t generally need to worry about issues such as overflow. . and an 8-bit exponent. and signals coming from the ADC and going to the DAC. are based on single16-bit data paths.and floating-point indicate. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number." rather than just “Floating Point. with architectures designed for handheld and control applications. though. thus supporting a vastly greater dynamic range than is available with the fixedpoint format. the SHARC devices are often referred to as "32-bit DSPs.5. While fixed-point DSP hardware performs strictly integer arithmetic. a result of the hardware being highly optimized for math operations. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. Comparison between Fixed Point and Floating Point System: TEC Both fixed. the instruction set must be larger and so on. loops. the SHARC DSPs are optimized for both floating point and fixed point operations. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. Today.or floating-point decision in the past. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). floating-point DSPs support either integer or real arithmetic. All floating point DSPs can also handle fixed point numbers. Fixed point DSPs are cheaper than floating point devices. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. As the terms fixed. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. TMS320C64x™ DSPs.32-BIT FLOATING POINT PROCESSOR 4. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. the fundamental difference between the two types of DSPs is in their respective numeric representations of data.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. it depends on the internal architecture .

The gap between numbers is one ten-thousandth of the value of the number we are storing. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. Here's the problem. suppose we store the number 10. really bad. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. To do this. In other words.. It can be rated in the form of signal to noise ratio and quantisation noise. In comparison. we add noise to the signal. In the worst case. although it does limit how some algorithms must be carried out. in a 16 bit DSP it may have 32 to 40 bits. Suppose we implement an FIR filter in fixed point. Noise is signal is usually represented by its standard deviation. This extended range virtually eliminates round-off noise while the accumulation is in progress. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. while floating point devices have better precision. This is because the gaps between adjacent numbers are much larger. DSPs handle this problem by using an extended precision accumulator.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. Fixed point DSPs are generally cheaper. To avoid overflow. For instance. while in the SHARC DSPs it contains 80 bits for fixed point use. higher dynamic range. greatly lowering the signal-to-noise ratio of the system.-47 . .e. For instance. and will correspondingly add quantization noise on each step. Although this is an extreme case. it's bad. floating point has such low quantization noise that these techniques are usually not necessary. while for a fixed point number it is only about ten-thousand to one. and a shorter development cycle.000 as a signed integer. this quantization noise will simply add. this accumulator is just another 16 bit fixed point variable. we need to scale the values being added. For example.000 times less quantisation noise than fixed point. The same thing happens when a number is stored as a 16-bit fixed point value. it illustrates the main point when many operations are carried out on each sample.5. This strategy works very well. DEPARTMENT OF ECE PAGE NO. Suppose we store in a 32 bit floating point format. In traditional microprocessors. and add the product to an accumulator. it must be round up or down by a maximum of one-half the gap size i. except that the added noise is much worse. in a 500 coefficient FIR filter. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. floating point has roughly 3. each time we store a number in floating point notation. the noise on each output sample may be 500 times the noise on each input sample. This is a special register that has 2-3 times as many bits as the other memory locations. we loop through each coefficient. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. To store the number. multiply it by the appropriate sample from the input signal.1: Fixed versus floating point. Standard deviation of this quantisation noise is about one-third of the gap size.

12-14 bits per sample is the crossover for using fixed versus floating point. . floating point systems are also easier to develop algorithms for. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. the numbers take care of themselves. In comparison. but the development cost will probably be higher due to the more difficult algorithms. such as spectral analysis and FFT convolution. The next thing to look at is the complexity of the algorithm that will be run . television and other video signals typically use 8 bit ADC and DAC. and almost certainly need floating point to capture the large dynamic range.If it is relatively simple. The programmer needs to continuously understand the amplitude of the numbers. but a more expensive final product. FIR filtering and other operations in the time domain only require a few dozen lines of code. In the reverse manner. floating point will generally result in a quicker and cheaper development cycle. and the precision of fixed point is acceptable. the cost of the product will be reduced. think floating point. think fixed point. In many applications. For instance. professional audio applications can sample with as high as 20 or 24 bits.-48 . frequency domain algorithms. When fixed point is chosen. and what scaling needs to take place. these issues do not arise in floating point. making them suitable for fixed point. For example. In comparison. are very detailed and can be much more difficult to program. the possibility of an overflow or underflow needs to be considered after each operation. Most DSP techniques are based on repeated multiplications and additions. DEPARTMENT OF ECE PAGE NO. the development time will be greatly reduced if floating point is used.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. In fixed point. While they can be written in fixed point. In contrast. how the quantization errors are accumulating. if it is more complicated.

scaling. Fx. and MRF and MRB are 80 bit accumulators. This table also shows that the numbers may be either signed or unsigned (S or U). the value of any two registers can be multiplied and placed into another register. The vertical lines indicate options. the floating point programmer can spend his time concentrating on the algorithm. These are the many options needed to efficiently handle the problems of round-off.-49 . It could not be any simpler. In other words. Fn = Fx * Fy. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. MRF = Rx * Ry. and MRB = Rx * Ry. While only a single command is needed for floating point. These are the multiplication instructions used in the SHARC DSPs. Rn. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. .5. and Ry refer to any of the 16 data registers. In contrast. For instance. where Fn.2: Fixed versus floating point instructions. and format. DEPARTMENT OF ECE PAGE NO. In comparison. and may be fractional or integer (F or I). look at all the possible commands for fixed point multiplication. This describes the ways that multiplication can be carried out for both fixed and floating point formats. The RND and SAT options are ways of controlling rounding and register overflow. Rx. and Fy are any of the 16 data registers. or into one of the extended precision accumulators.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. many options are needed for fixed point.

32-BIT FLOATING POINT PROCESSOR 4. For instance. such a . and another 49% are considering the change. In (b). 32-bit floating point has a higher dynamic range. About twice as many engineers currently use fixed point as use floating point DSPs. as shown in (c). over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs . However.6. The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. In comparison. As illustrated in (a). This is mainly driven by consumer products that must have low cost electronics. meaning there is a greater difference between the largest number and the smallest number that can be represented. DEPARTMENT OF ECE PAGE NO. suppose you are designing a medical imaging system.-50 . over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. As shown in (c). A good example of this is cellular telephones. about twice as many engineers use fixed point as use floating point DSPs.6 Trends in DSP: TEC Figure 4. However. When you are in competition to sell millions of your product.1: Major trends in DSPs. a cost difference of only a few dollars can be the difference between success and failure. such as cellular telephones. this depends greatly on the application. floating point is the fastest growing segment. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low. floating point is more common when greater performance is needed and cost is not important.

iterated MACs require additional bits for overflow headroom.point devices. which is 24 bits for floating-point. ensuring greater accuracy in end results. at a price of several hundred-thousand dollars each.-51 . DEPARTMENT OF ECE PAGE NO.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. which would go beyond most application requirements in accuracy. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. While fixed-point coefficients are 16 bits. Second. Third. in integer as well as real values. the same as the signal data in DSPs. a 32-bit product would be needed. but the performance is critical. Only a few hundred of the model will ever be sold. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. First. and can be 8.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. In fixed. Three data word widths are important to consider in the internal architecture of a DSP. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. or 32 bits for fixed-point DSPs. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. exponentiation vastly increases the dynamic range available for the application. . the internal representations of data in floating-point DSPs are more exact than in fixed-point. For a single 16-bit by 16-bit multiplication. floating-point coefficients can be 24 bits or 53 bits of precision. the cost of the DSP is insignificant. The first is the I/O signal word width. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. 4. For this application. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). the floating point market is the fastest growing segment. However. 16 bits for fixed-point. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. In spite of the larger number of fixed point DSPs being used. The second word width is that of the coefficients used in multiplications. 16. depending whether single or double precision is used. this overflow headroom is 8 bits. Fortunately. or a 48-bit product for a single 24-bit by 24-bit multiplication. Finally.

using this scale of integration people succeeded to make digital subsystems (Microprocessor. CMOS (Complementary Metal Oxide Semiconductor) process technology. because of manual converting the design from one level to other. At this point design process started getting very complicated. Rapid advances in Software Technology and development of new higher level programming languages taken place. i. counters. This created new challenges to digital designers as well as circuit designers. This way of designing (using CAD tools) is certainly a revolution in electronic industry.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. At this point design process still became critical.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5.e. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. Designers felt need to automate these processes. Later Integrated Circuits (ICs) were invented. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. . and etc. One can fabricate a chip contains more than Million of gates. DEPARTMENT OF ECE PAGE NO. I/O peripheral devices and etc.e. one can create digital sub blocks (adders.-52 . Using design at this level.. With advent of new technology.) on an IC. This may be leading to development of sophisticated electronic products for both consumer as well as business. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. multiplexes. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. In this process. i. This level is LSI (Large Scale Integration). It became very easy to a designer to verify functionality of design at various levels.. for design electronics circuits with assistance of software programs. registers. Using latest CAD tools could solve the problem. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration).) on a chip.

2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5.32-BIT FLOATING POINT PROCESSOR 5.-53 . DEPARTMENT OF ECE PAGE NO.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language. .

has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard.1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). The language can be used as a communication medium between different CAD and CAE tools .The complete language. Reprocurement and reuse was also a big issue.3. The language can be used as exchange medium between chip vendors and CAD tool users.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. and verification of the digital systems was generated.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. this version of the language is known as the IEEE STD 1076-1987. It is a hardware description language that can be used to model a digital system at many levels of abstraction. This subset is usually sufficient to model most applications . 5. DEPARTMENT OF ECE PAGE NO. the language was upgraded with new features. This new version of the language is known as the IEEE STD 1076-1993. available from IEEE. The language has also been recognized as an American National Standards Institute (ANSI) standard. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. Thus. The official language description appears in the IEEE standard VHDL language Reference manual. models written in this language can be verified using a VHDL simulator. Consequently. 5.-54 . the syntax of many constructs was made more uniform. Therefore. Different chip vendors can provide VHDL descriptions of their components to system designers. a need for a standardized hardware description language for the design. The IEEE in the December 1987 standardized VHDL language. and many ambiguities present in the 1987 version of the language were resolved. According to IEEE rules. documentation. ranging from the algorithmic level to the gate level. however.3.

End component. Component And2 Port (L. Such a model for the HALF_ADDER entity.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. The language is publicly available. Z:out BIT). In VHDL each device model is treated as a distinct representation of a unique device.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. which contains one external view and one or more internal views. M: in BIT. The internal view of the device specifies functionality or structure. such as finite –state machine descriptions. It supports both synchronous and asynchronous timing models. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. DEPARTMENT OF ECE PAGE NO. As a set of interconnected components (to represent structure) 2. Dataflow. and there are no limitations imposed by the language on the size of the design. CARRY). 5. and behavioral. SUM) A1: AND2portmap (A. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. The language supports three basic different styles: Structural. Each Entity is described using one model. Arbitrarily large designs can be modeled using the language. End component. can be modeled using the language. As a set of concurrent assignment statements (to represent data flow) 3. each component. Structural style of modeling: In this one an entity is described as a set of interconnected components. can be modeled as a set of interconnected subcomponents. N:outBIT). in turn. . 1. and Boolean equations. B. that is a digital can be modeled as asset of interconnected components.3. human-readable.-55 . and machine-readable. This model specifies the external view of the device and one or more internal views. called an Entity. or mixed. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. The language supports flexible design methodologies: top-down. Various digital modeling techniques. Y: in BIT. The Entity is thus a hardware abstraction of the actual hardware device. Begin X1: Xor2portmap (A. B. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. bottom-up.

Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std.In a signal assignment statement. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. 1076-1993 standard. graphical and textual simulation output viewers. 5. It comprises three different design entry tools. and EDIF and mixed VHDL-Verilog-EDIF designs.the entity declaration for half adder specifies the interface ports for this architecture body. 5.1.32-BIT FLOATING POINT PROCESSOR TEC End ha.-56 . . Verilog compiler. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. Verilog. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std. The data flow model for the half adder is described using two concurrent signal assignment statements .3. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0. 13641995 standard. single simulation kernel.4. DEPARTMENT OF ECE PAGE NO. The name of the architecture body is ha . several debugging tools.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL.4. the symbol <=implies an assignment of a value to a signal. which are specified inside a process statement. A process statement is a concurrent statement that can appear with in an architecture body. and auxiliary utilities designed for easy management of resource files. SIMULATION TOOL 5. 5.1. 5. The declared components are instantiated in the statement part of the architecture body using component instantiation.4 DATAFLOW STYLE OF MODELING: In this modeling style. and libraries. do not explicitly specify the structure of the entity but merely its functionality.3.4. designs. Two component declarations are present in the declarative part of the architecture body. the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The architecture body is composed of two parts: the declaration part and the statement part. VHDL'93 compiler.2.4 INTRODUCTION TO HDL TOOLS 5. These sets of sequential statements.

. Perl scripts. DEPARTMENT OF ECE PAGE NO. The editor automatically translates graphically designed diagrams into VHDL or Verilog code.1.0. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI).-57 . 2. the communication of hardware design and test verification data.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language.1/D1. and Tcl scripts. 5. Resource files attached to the design. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. 1. HDL Editor: HDL Editor is a text editor designed for HDL source files. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. modification and procurement of hardware system. 4.4. The keyword coloring is also available when HDL Editor is used for editing macro files.0 May 1997). The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. The editor is tightly integrated with the simulator to enable debugging source code. that is: a. It allows you to graphically edit waveforms so as to create desired test vectors. 5. It displays specific syntax categories in different colors (keyword coloring). The contents of the default-working library of the design. the maintenance. 3. SDF files must comply with OVI Standard Delay Format Specification Version 2. Design Browser: The Design Browser window displays the contents of the current design. The VITAL-compliant models can be annotated with timing data from SDF files. b. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms.

4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. Verilog. VHDL. Active-HDL provides three compilers. a source file can be on of the following: • VHDL file (. When you choose a menu command or toolbar button for compilation. transistors or gates) and their interconnection.4. 6. Verilog. Cycle-based simulation is significantly faster than event-driven. Verilog. The structure of the design unit selected for simulation. All Active-HDL tools output their messages to Console. d. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. and EDIF. macros. 5.32-BIT FLOATING POINT PROCESSOR TEC c. the compiler analyzes the intermediate VHDL. . • The Active-HDL simulator provides two simulation engines.EDIF) • State diagram file (. DEPARTMENT OF ECE PAGE NO. or EDIF file containing HDL code (or net list) generated from the diagram. In Active-HDL.asf) • Block diagram file (. A net list is a set of statements that specifies the elements of a circuit (for example.bde) In the case of a block or state diagram file. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. Compilation: Compilation is a process of analysis of a source file. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands.v) • EDIF net list file (. and scripts. respectively for VHDL.vhd) • Verilog file (.-58 . or EDIF objects declared within a selected region of the current design. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator.

including: • HDL (VHDL.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.4. Verilog HDL. DEPARTMENT OF ECE PAGE NO.4.The ISE Text Editor is provided in ISE for entering design code and viewing reports. including ModelSim Xilinx Edition and the HDL Bencher test bench generator.6. 5.1: Simulation 5. ISE enables you to start your design with any of a number of different source types.-59 . This overview explains the general progression of a design through ISE from start to finish.6. and finally produce a bit stream for your device configuration.5. .6 SYNTHESIS TOOL: 5. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.3.32-BIT FLOATING POINT PROCESSOR TEC Fig4. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.4. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE.2 Design Entry: • ISE Text Editor . ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.

and to view and modify the placed design.The Constraints Editor allows you to create and modify the most commonly used timing constraints. Chip Viewer (CPLD only) .The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. Floor planner .6. places and routes the FPGA. Map .The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file.The PAR program accepts the mapped design. The state machine will be created in HDL. placing or routing an FPGA design.3 Implementation: • Translate .The FPGA Editor allows you view and modify the physical implementation.-60 .The Floor planner allows you to view a graphical representation of the FPGA. Global logic. With Timing Analyzer. Fit (CPLD only) .State CAD allows you to specify states. including routing. DEPARTMENT OF ECE PAGE NO.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. and actions in a graphical editor. • • • • • • • .The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. and after fitting and routing a CPLD design. Place and Route (PAR) . to system-level building blocks such as filters. transforms.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow. transitions. Timing Analyzer . and produces output for the bit stream generator.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor . and pin assignments. FIFOs. PACE . and Area Group constraints.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. CORE Generator .4. • • • • 5.The Chip Viewer tool provides a graphical view of the inputs and outputs. equations. Constraints Editor . macro cell details. and memories. FPGA Editor . analysis can be performed immediately after mapping. State CAD State Machine Editor .The Map program maps a logical design to a Xilinx FPGA. view.

XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices.4.-61 .6. XPower .4 Device Download and Program File Formatting: • BitGen .The iMPACT tool generates various programming file formats. Integration with ChipScope Pro. and subsequently allows you to configure your device.32-BIT FLOATING POINT PROCESSOR TEC 5. iMPACT . • • • . DEPARTMENT OF ECE PAGE NO.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration.

32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. subtraction. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. multiplication and division are done using active HDL tool and the results are as follows: 6.-62 .1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. .1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format. DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .

2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6. .32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form.-63 . DEPARTMENT OF ECE PAGE NO.

3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC 6. DEPARTMENT OF ECE PAGE NO.3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6.-64 . Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form. . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . .32-BIT FLOATING POINT PROCESSOR TEC 6.-65 . Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form.4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6. DEPARTMENT OF ECE PAGE NO.

• 7.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation. The Functional-simulation has been successfully carried out with the results matching with the expected ones. . DEPARTMENT OF ECE PAGE NO.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication.-66 . • • Procedures for performing basic arithmetic operations are been formed. Basic arithmetic operations such as addition.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. subtraction.

In these cases. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. The wide dynamic range of a floating-point DSP.-67 . The greater precision of signal data. However. however. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. Wide dynamic range also plays a part in robotic design. x-rays. The radar system may be tracking in a range from 0 to infinity. . Since the subset must be determined in real time during system operation. unpredictable events can occur on an assembly line. feedback is well out of the ordinary operating range. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. For instance. Normally. the robot might weld itself to an assembly unit. but need to use only a small subset of the range for target acquisition and identification.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. together with the device’s more accurate internal representations of data. DEPARTMENT OF ECE PAGE NO. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. or something might unexpectedly block its range of motion. enable imaging systems to achieve a much higher level of recognition and definition for the user. Many levels of signal input from light. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range.

1109/SNPD. Williams.-68 . M. Proc. (1986) A 32 bit processor architecture for direct execution of Forth. 14(7) 68-78 REFERENCES www. H. 1975. Hayes. 197-210 Jones.. J.com . Prentice-Hall. In: 1986 FORML Conf. Computer. pp. T.ieee. (1987) The Implementation of Functional Programming Languages. pp. July 1981.org www. W. DEPARTMENT OF ECE PAGE NO. Chicago.computer. S. 28-30 November 1986. P.. Pacific Grove CA. & Zaremba.2007. (Ed. R.) Introduction to Computer Architecture..ieeexplore. New York McKeeman.46 www. (1975) Stack computers. Science Research Associates. M. 281-317 Yamamoto.intel. (1981) A survey of high-level language machines in Japan.org/portal/web/csdl/doi/10.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman. In: Stone.

all.Compute Ea-Eb -2. use IEEE. --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop .all.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.-69 . b : in std_logic_vector(31 downto 0).Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE. use IEEE.std_logic_1164.std_logic_arith. DEPARTMENT OF ECE PAGE NO.std_logic_unsigned. end Fadd. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc. begin temp:=x.all. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0). y : out std_logic_vector(31 downto 0) ). variable Temp :Std_logic_vector(6 downto 0).Shift the that has lesser Exponent by Ea-Eb places to the right * -3. use IEEE.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1.

Z :=(a&b). return sum. -.Mangitude Of Two mantissas variable ES : std_logic. -. b :=Data(31). Eb :=Data(30 downto 23). -. --***************************************************************** --*Equalization of Exponents includes two steps --*1. --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i.Mb : std_logic_vector(22 downto 0). end loop.Subtraction of Exponents --*2.Resultant Exponent variable Ns : integer. else TEC Sum:=Sum.Internal Register variable MbIn : std_logic_vector(22 downto 0). -.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0).-70 .Z : std_logic_vector(1 downto 0). -.Internal Register variable Ea. end if.Eb : std_logic_vector(7 downto 0).Sign Of Resultant Mantissa variable W.Final Result begin MaIn:=Acc(22 downto 0).Resultant Mantissa variable IE : std_logic_vector(6 downto 0). DEPARTMENT OF ECE PAGE NO. -.Number Of Shifts variable Ma. -. a :=Acc(31). -. -. Ea :=Acc(30 downto 23). -.Sign Of Two mantissas variable Sign : std_logic. Ma:=MaIn.s2 : std_logic.Sign Of Two exponents variable s1. end function.Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. Es:=Eb(7) . MbIn:=Data(22 downto 0). -. end loop.b : std_logic. variable X : std_logic_vector(31 downto 0).Sign Of Resulant Exponent variable a. IE:=Eb(6 downto 0). -. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)).

when "11" => Mb:=MbIn. IE:=Eb(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). else NS:=Ns. end loop. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). .-71 . end if.32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). Ma:=MaIn. Ma:=MaIn. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). ES:=Ea(7). IE:=Ea(6 downto 0). ES:=Ea(7). ES:=Eb(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=IE. end loop. end loop. end loop. Ma:=MaIn. when "10" => Mb:=MbIn. ES:=Ea(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Es:=Ea(7). Mb:=Mb. when "01" => Mb:=MbIn. IE:=Ea(6 downto 0). DEPARTMENT OF ECE PAGE NO. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Ma:=Ma. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). IE:=Ea(6 downto 0).

elsif(Ma=Mb) then sign:='0'. IE:=IE. IE:=Eb(6 downto 0). when others => Null. Ma:=Ma. end if. elsif(Ea<Eb) then sign:='1'.-72 . ES:=Ea(7). else sign:=sign. --******************Addition of Mantissas**************************** IR:=Ma+Mb. else sign:=sign. if(Ea>Eb) then sign:='0'. end loop. end case. end if. case W is when "00" => when "11" => when "01" => when "10" => . s2:=Data(31). if(Ea>Eb) then sign:='1'. DEPARTMENT OF ECE sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. ES:=Eb(7). W :=(s1&s2). elsif(Ma<Mb) then sign:='1'.32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). sign:='1'. Mb:=Mb. end if. PAGE NO. else NS:=Ns. --***********logic for the sign of the mantissa********************** s1:=Acc(31).

elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. elsif(Ma<Mb) then sign:='0'.b) begin y<=float_add(a.-73 * . elsif(Ma=Mb) then sign:='0'.b). TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . begin process(a. end if. return X. when others => null.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. end Fadd. end case. end if. DEPARTMENT OF ECE PAGE NO. else sign:=sign. end function. else sign:=sign. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)). end process.

use ieee. begin temp:=x.all. use ieee.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.std_logic_1164. y : out std_logic_vector(31 downto 0)).std_logic_unsigned. b : in STD_LOGIC_VECTOR (31 downto 0).-74 .Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.all. use IEEE.std_logic_arith.all. end Fsub. DEPARTMENT OF ECE PAGE NO. .32-BIT FLOATING POINT PROCESSOR ----1. variable Temp : Std_logic_vector(6 downto 0). --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout.Shift the that has lesser Exponent by Ea-Eb places to the right * 3.Compute Ea-Eb 2.

Number Of Shifts variable Ma. MbIn:=Data(22 downto 0). -. end function.s2 : std_logic.Sign Of Resultant Mantissa variable W. end loop.Final Result begin MaIn:=Accout(22 downto 0).32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i.Sign Of Two Exponents variable s1. -. --*********************variable Declarations*********************** TEC variable MaIn.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). b :=Data(30). --***************************************************************** --*Equalization of Exponents includes two steps * * --*1.Resultant Mantissa variable IE : std_logic_vector(6 downto 0). -. -. -. -.Resultant Exponent variable Ns : integer.Subtraction of Exponents * * . Ea :=Accout(30 downto 23). -. else Sum:=Sum. a :=Accout(30). Eb :=Data(30 downto 23). Z :=(a&b). variable X : std_logic_vector(31 downto 0).Mangitude Of Two Mantissas variable ES : std_logic. -. -.Z : std_logic_vector(1 downto 0).Sign Of Resulant Exponent variable a. DEPARTMENT OF ECE PAGE NO.Sign Of Two Mantissas variable sign : std_logic.Mb : std_logic_vector(22 downto 0). return sum.MbIn: std_logic_vector(22 downto 0). -.b : std_logic.Eb : std_logic_vector(7 downto 0).Internal Register variable Ea.-75 . -. end if.

if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). Mb:=Mb. DEPARTMENT OF ECE PAGE NO. Ma:=MaIn.-76 . for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). IE:=Ea(6 downto 0). end loop. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). end if. ES:=Eb(7). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. ES:=Ea(7).32-BIT FLOATING POINT PROCESSOR --*2. IE:=Eb(6 downto 0). Ma:=MaIn. IE:=Ea(6 downto 0). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). Ma:=Ma. else NS:=Ns. IE:=IE. . ES:=Ea(7). end loop. when "01" => Mb:=MbIn. end loop.

end case. when "11" => Mb:=MbIn. ES:=Ea(7). .-77 . for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Mb:=Mb. IE:=Eb(6 downto 0). end loop. when others => null. Ma:=MaIn. Ma:=Ma. ES:=Eb(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). IE:=Ea(6 downto 0). DEPARTMENT OF ECE PAGE NO. --******************Subtraction of Mantissas************************ IR:=Ma-Mb. ES:=Eb(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). end loop. IE:=IE. end loop.32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). else NS:=Ns. IE:=Eb(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end if. TEC Ma:=MaIn.

elsif(Ma<Mb) then sign:='0'. s2:=Data(31). when "10"=> if (Ea>Eb)then sign:='1'. DEPARTMENT OF ECE PAGE NO. else sign:=sign. elsif (Ma=Mb) then sign:='0'. case W is when "00"=> sign:='0'. else sign:=sign. when "01"=> if(Ea>Eb)then sign:='0'. elsif(Ea<Eb) then sign:='1'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. else sign:=sign. elsif (Ma=Mb) then sign:='0'. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'.32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). when "11"=> sign:='1'. . end if. elsif(Ma<Mb) then sign:='1'. end if. end if.-78 . elsif (Ea<Eb) then sign:='0'. W:=(s1&s2). else sign:=sign. end if.

DEPARTMENT OF ECE PAGE NO. begin process(a. end function. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)). end Fmul.b) begin y<=float_sub(a. --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0).-79 .Multiplication of the Mantissas * * -************************************************************************** library IEEE. end f_sub. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. use IEEE.Addtion of the Exponents 5. end case.std_logic_unsigned.all. end process.32-BIT FLOATING POINT PROCESSOR TEC when others=> null. b: in STD_LOGIC_VECTOR (31 downto 0). return X. use IEEE. .b).all. y: out STD_LOGIC_VECTOR (31 downto 0) ).std_logic_1164.

-. -. when "11" => s:='0'. -.Sign Of Resultant Mantissa variable a.m2 : std_logic_vector(10 downto 0). DEPARTMENT OF ECE PAGE NO. -.-80 .Resultant Mantissa variable carry : std_logic. when others=> s:='1'. -.Final Result begin Carry:='0'.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout.sign Two Mantissas variable Ea. s2:=Data(31). .Carry variable W. m2 :=Data(10 downto 0).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. e1 :=Accout(30 downto 23).Eb : std_logic_vector(6 downto 0).e2 : std_logic_vector(7 downto 0). variable x : std_logic_vector(31 downto 0).Resultant exponent variable m : std_logic_vector(21 downto 0). -.Magnitude O Two Mantissas variable s : std_logic.Magnitude Of Two Exponents variable c : std_logic. -.s2 : std_logic.b : std_logic. e2 :=Data(30 downto 23). end case.Sign Two Exponents variable s1. Z :=(s1&s2). m1 :=Accout(10 downto 0). -. --************logic for the sign of the Mantissa******************* s1:=Accout(31). -. case Z is when "00" => s:='0'.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0). -.Z : std_logic_vector(1 downto 0). -.Two Exponents Icluding Sign variable m1.

e:=Eb-Ea. e:="0000000". c:='1'. DEPARTMENT OF ECE PAGE NO. end if. Eb:=e2(6 downto 0). when "01" => if(Ea>Eb) then c:='0'. case W is when "00" => c:='0'.-81 . a :=Accout(30). W :=(a&b). e:=Ea-Eb. elsif(Ea<Eb) then c:='1'. e:=Ea+Eb. --*************logic for multiplication************************* m:=m1*m2. elsif(Ea<Eb) then c:='0'. e:=Eb-Ea. end case. else c:='0'. end if. e:="0000000". b :=Data(30). when "10" => if(Ea>Eb) then c:='1'. else c:='0'.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). . when "11" => when others => null. e:=Ea+Eb. e:=Ea-Eb.

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

e:="0000000". else c:='0'. if(Ea>Eb) then c:='0'. . e:=Eb-Ea. e:="0000000". e:=Ea-Eb. if(Ea>Eb) then c:='1'. case Z is when "00" => if(Ea>Eb) then c:='0'. e:=Ea+Eb. e:=Eb-Ea. Z :=(a&b). when "10"=> if(Ea>Eb) then c:='1'.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0).-86 . e:="0000000". end if. e:=Ea-Eb. Eb:=e2(6 downto 0). elsif(Ea<Eb) then c:='0'. e:=Eb+Ea. elsif(Ea<Eb) then c:='0'. elsif(Ea<Eb) then c:='0'. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. a :=e1(7). else c:='0'. end if. end if. b :=e2(7). e:=Ea+Eb. else c:='0'. elsif(Ea<Eb) then c:='1'.

--***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). TEC . else c:='0'. end process. end F_div.b) begin Y<=float_div(a. end case. e:="0000000". end if. begin process(a. return X. end function.32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea.b). when others=> null.-87 . DEPARTMENT OF ECE PAGE NO.

C Syntax high-level data abstraction have a close relationship with the resulting object code, and yet
provide relatively high-level data abstraction. The development of this syntax was a major milestone in the history of
computer science as it was the first widely successful high-level language for operating-system development.

by Harshit Gupta

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