32-BIT FLOATING POINT PROCESSOR

TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

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32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1
INTRODUCTION
1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

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32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

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32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2.1: Binary Real Number System Because the size and number of registers that any computer can have is limited.1. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers. the real-number system comprises the continuum of real numbers from minus infinity (. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits. As shown in Figure 1.) to plus infinity (+ ). As shown at the bottom of Figure 1. DEPARTMENT OF ECE PAGE NO. only a subset of the real-number continuum can be used in real-number calculations. Figure 2. . the subset of real numbers that a particular FPU supports represents an approximation of the real number system. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations.-5 .

performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. from -32. some specific assumption is made about where the radix point is located in the string. the 65. although a different length can be used. In fixed-point systems. signed integer uses two's complement to make the range include negative numbers. Digital Signal Processing can be divided into two categories. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. the number is an integer). designers can identify the DSP that is best suited for an application.2. For instance. In unsigned integer. processor and system costs. Lastly. but decimal fixed point is common in commercial applications. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. Fixed-point Vs floating-point in digital signal processing Fig 2. 2.767. performance attributes. the signed fraction format allows . Fixed point DSPs usually represent each number with a minimum of 16 bits. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. Motorola manufactures a family of fixed point DSPs that use 24 bits. DEPARTMENT OF ECE PAGE NO.-6 . Software programmable for maximum flexibility and supported by easy-touse. In common mathematical notation. and ease of development. low-cost development tools. With unsigned fraction notation. fixed point and floating point. Balancing these factors together. the stored number can take on any integer value from 0 to 65.768 to 32.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. while floating-point DSPs support either integer or real arithmetic. Among the key factors to consider are the computational capabilities required for the application.535. DSPs enable designers to build innovative features and differentiating value into their products. the digit string can be of any length.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data.536 levels are spread uniformly between 0 and 1. Similarly.536 possible bit patterns can represent a number. These refer to the format used to store and manipulate numbers within the devices. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. There are four common ways that these 216 ' 65.

In the most common format (ANSI/IEEE Std.3. For instance. The radix point is not explicitly included.754-1985). but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most  . 2." 2.296 to be exact.However. floating point DSPs typically use a minimum of 32 bits to store each value. a necessity to implement counters.4 ×1038 and ±1. The floating-point operations are incorporated into the design as functions. and signals coming from the ADC and going to the DAC. This is known as the significand. A key feature of floating point notation is that the represented numbers are not uniformly spaced. The speed of floating-point operations is an important measure of performance for computers in many application domains. equally spaced between -1 and 1. The represented values are unequally spaced between these two extremes. loops. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. The term” floating point” refers to the fact that the radix point can "float".4.In comparison. This position is indicated separately in the internal representation. the SHARC DSPs are optimized for both floating point and fixed point operations. Floating point A floating-point number is the one. the SHARC devices are often referred to as "32-bit DSPs. it depends on the internal architecture. For this reason. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. DEPARTMENT OF ECE PAGE NO. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values." rather than just "Floating Point. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. and floating-point representation can thus be thought of as a computer realization of scientific notation. This is important because it places large gaps between large numbers. which is capable of representing real and decimal numbers. All floating point DSPs can also handle fixed point numbers.-7 . The logic for these is different from the ordinary arithmetic functions. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). but small gaps between small numbers. the largest and smallest numbers are ±3. 2324. or sometimes the mantissa (see below) or coefficient.967. it can be placed anywhere relative to the significant digits of the number. This results in many more bit patterns than for fixed point. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. and executes them with equal efficiency.2 ×1038.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. It is measured in” FLOPS”. that is. respectively.294.

also referred to as the characteristic or scale. 2. which modifies the magnitude of the number. and the rounding behaviour of operations. Significand is a real number. The floating-point format needs slightly more storage (to encode the position of the radix point). composed as integer. floating-point numbers achieve their greater range at the expense of precision. The significand is multiplied by the base raised to the power of the exponent. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2.Fraction. with an average error of about 3%. 10 or 16. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. b is the base. computers used many different forms of floating-point. so when stored in the same space. DEPARTMENT OF ECE PAGE NO. Prior to the IEEE-754 standard. or to the right of the rightmost digit. Symbolically.-8 . with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. The length of the significand determines the precision to which numbers can be represented. and e is the exponent. the format of the representations. 1 for negative values. These differing systems implemented different parts of the arithmetic in hardware and software. These differed in the word sizes.32-BIT FLOATING POINT PROCESSOR TEC significant digit.5. this final value is where s is the value of the significand (after taking into account the implied radix point). (This is because the exponent field is in . IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon.  A signed integer exponent.

0 denotes a positive number. To do this.) This can be exploited in some applications. or 1023 plus the true exponent for double precision. This means that at most 232 possible real numbers can be exactly represented. 1 denotes a negative number. A float is represented using 32 bits. the exponent. The exponent field contains 127 plus the true exponent for single-precision. The sign bit is 0 for positive. The Sign Bit: The sign bit is as simple as it gets. The Exponent: The exponent field needs to represent both positive and negative exponents.f. 4. and each possible combination of bits represents one real number. where f is the field of fraction bits. The exponent's base is two. DEPARTMENT OF ECE . 3. to sum up: 1.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. It is composed of an implicit leading bit and the fraction bits. represents the precision bits of the number. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. a bias is added to the actual exponent in order to get the stored exponent. even though there are infinitely many real numbers (even between 0 and 1). also known as the significand. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. and the mantissa. Flipping the value of this bit flips the sign of the number. IEEE-754 specifies binary representations for floating point numbers: Table 2. The Mantissa: The mantissa. The first bit of the mantissa is typically assumed to be 1. There are many formats that are used for representation of floating point number.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign.-9 . 1 for negative. such as volume ramping in digital sound processing. 2. So.

exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude.1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values.5. which may be represented as numbered from 0 to 31. then V=-Infinity If E=255 and F is zero and S is 0. DEPARTMENT OF ECE PAGE NO. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010).5. the next eight bits are the exponent bits. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero. 'E'.-10 . Table 2. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). left to right.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude.5. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. then V=NaN ("Not a number") If E=255 and F is zero and S is 1. S. then V=Infinity .

0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1. then V=0 In particular.0 The biased exponent is . then V=-0 If E=0 and F is zero and S is 0.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0. then V=(-1)**S * 2 ** (-126) * (0.101 = -6. If E=0 and F is zero and S is 1.3125 The biased exponent is -2+127=125= (01111101 • 1.F) where "1.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. If E=0 and F is nonzero.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.101 = 6.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.-11 . 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1. DEPARTMENT OF ECE PAGE NO.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.F) These are "unnormalized" values.

0 0 1 0 1 1313.625 × 2 = 1.203125 0.3125 0.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0.010010000101012 × 210.01012.1015625 0.5 The based exponent: 127+5= (10000100 .203125 × 2 = 0.312510 = 10100100001.3125 131310 = 101001000012 0. 10 + 127 = 137 = 100010012. .5 × 2 = 1. So -1313.1015625 × 2 = 0. DEPARTMENT OF ECE PAGE NO.8125 .25 × 2 = 0.40625 × 2 = 0. = 1.25 0.5 × 2 = 0.3125 is • 0.32-BIT FLOATING POINT PROCESSOR TEC • 37.-12 . sign bit is 1.8125 × 2 = 1.625 0.40625 0. • -78.25 The biased exponent: 127+6=133=(10000101 • -1313.

3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.5.1015625 is 0 00111101 110100000000000000000000 TEC 2.0 1 0. then V=NaN ("Not a number") PAGE NO.3. which may be represented as numbered from 0 to 63. S. 'E'. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0). The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero.5 × 2 = 1. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. left to right. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values. The first bit is the sign bit. DEPARTMENT OF ECE .-13 .00011012 = 1.101562510 = 0.32-BIT FLOATING POINT PROCESSOR 0. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001).5 0 × 2 = 1.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0.25 1 × 2 = 0.625 0.5. the next eleven bits are the exponent bits.25 0.

F) where "1. floating-point notation allows calculations over a wide range of magnitudes.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038. Table 2. 15 exponent bits and 112 significand bits. then V=-0 If E=0 and F is zero and S is 0.-14 .6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable. DEPARTMENT OF ECE PAGE NO. If E=0 and F is nonzero. . then V=(-1)**S * 2 ** (-1022) * (0. using a fixed number of digits. then V=-Infinity If E=2047 and F is zero and S is 0.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa).32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit .F) These are "unnormalized" values.6. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision.53 ~ 10308.5. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1. If E=0 and F is zero and S is 1. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. while maintaining good precision.

There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2.32-BIT FLOATING POINT PROCESSOR TEC Table 2. There is a largest floating point number. P. Negative numbers greater than -2-149 (negative underflow) 3. Normalized And Approximate Decimal Values.85 to ~1038.53 ~10-323. There is a smallest positive normalized floating-point number.6. Positive numbers less than 2-149 (positive underflow) .3 to ~10308. The number of normalized floating point numbers in a system F(B. Approximate Decimal 2127 21023 ~10-44. L is the smallest exponent represent able in the system.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1). Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand.-15 . the range for negative numbers is given by the negation of the above values. L. DEPARTMENT OF ECE PAGE NO. U) (where B is the base of the system. and the smallest possible value for the exponent. P is the precision of the system to P numbers. Zero 4. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent.2: Effective Range of IEEE Floating Point Number with Denormalized.

Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. Recently.-16 . 2.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. When this occurs. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . the exponent is set to -127 (E = 0). there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. the most negative value which is defined in bias-127 exponent representation. the largest value which is defined in bias-127 exponent representation. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. Underflow occurs when the sum of the exponents is more negative than -126.32-BIT FLOATING POINT PROCESSOR 5.infinity. DEPARTMENT OF ECE PAGE NO. the number is exactly zero. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. When this occurs. However the CPU will have to perform extra arithmetic to read the number when stored in this format. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . 2. If M = 0.

Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. let us consider two numbers a= 2. Floating point addition is analogous to addition using scientific notation. DEPARTMENT OF ECE PAGE NO. . Division 2. Now as both the exponent values are same. Subtraction 3. as the smaller number here is a=2. Multiplication 4. Addition 2. Normalize the result. But by using floating point addition this can be avoided to a little extent.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. They are: 1. i..340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.25x and b= 1. For example. Add the numbers with decimal points aligned.0225x .e.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.8. both the numbers are added. Hence the value of number ‘a’ becomes 0.-17 ..1.

But the normalised result may sometimes carry the required result.8. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value. ManA as mantissa of number A.00000009876543 x 2. 2. ExpA as exponent of number A . Thus this case can said to be having rounding errors..8. Now both the numbers are added. signB as sign of number B.876543x and if the addition has to be performed.8. b= 9. then the following result may occur: 1.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.-18 .e. DEPARTMENT OF ECE PAGE NO.876543x after shifting becomes b= 0.1. If the numbers are represented with both positive and negative sign.1.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .2345670 x in which the remaining part (9876543) which is discarded also carries the result. ExpB as exponent of number B and ManB as mantissa of number B. then sign of greater number is considered.234567x and b= 9. then bit 1 is represented for sign. i. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: . a =1. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. 2.1.1.e. Consider a example in which a =1..234567x b= 0.00000009876543 x c= 1. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.2. The mantissa of both numbers A and B are added.

32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. the significand is rounded to the appropriate number of bits required and again normalization is checked.1. Thus. If there is an underflow or overflow. 2. 6. Addition of significands is done.2: Flow Chart for Floating Point Adder. the exponent sum would have doubled the bias.8. Firstly. 4. . DEPARTMENT OF ECE PAGE NO. If not. the numbers are represented in IEEE floating point format. exception is made.-19 . the bias value must be subtracted from the sum 3. If the exponents are stored in biased form. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. 1. 5.

2.340625x . the result is converted back to signmagnitude form.-20 . 2. then the mantissa must be shifted one bit to the right and the exponent incremented. Subtraction .8. If the sum overflows the position of the hidden bit. DEPARTMENT OF ECE PAGE NO. The number 2. cancellation may occur.25 becomes: The mantissas are added using integer addition: The result is already in normal form.25x and 1. 2.0625 in IEEE Floating Point Standard is: To align the binary points.25 in IEEE Floating Point Standard is: The number 134. The mantissa is always less than 2. After the addition is performed. resulting in a large loss of accuracy. Consider addition of the numbers 2. resulting in a sum which is arbitrarily small.32-BIT FLOATING POINT PROCESSOR TEC 7. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. When adding numbers of opposite sign. Negative mantissas are handled by first converting to 2's complement and then performing the addition. so the hidden bits can sum to no more than 3 (11). or even zero if the numbers are equal in magnitude. Thus. Normalization in this case may require shifting by the total number of bits in the mantissa. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form.

Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2. The mantissa of both numbers A and B are subtracted. signB as sign of number B.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2.2.1. Hence the value of number ‘a’ becomes 0.. Subtract the numbers with decimal points aligned. The normalised result may contain the required number of digits discarding the unwanted part. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.8..340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.1.25x and b= 1. i. ManA as mantissa of number A. both the numbers are added. 2.0225x .8.2. ExpB as exponent of number B and ManB as mantissa of number B. Now as both the exponent values are same.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .e. DEPARTMENT OF ECE PAGE NO. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. as the smaller number here is a=2.-21 . ExpA as exponent of number A . Normalize the result.. then sign is represented according to the number i. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if .e.

DEPARTMENT OF ECE PAGE NO. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. If there is an underflow or overflow. the significand is rounded to the appropriate number of bits required and again normalization is checked.-22 . Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1.340625x . the exponent sum would have doubled the bias.8.25 become: The mantissas are subtracted using integer subtraction: . 5. The numbers are represented in IEEE floating point format. 2.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign. 2. exception is made. If the exponents are stored in biased form. 6. 2. Consider subtraction of the numbers 2. Thus.25 in IEEE Floating Point Standard is: The number 134.2.25x and 1. 4.0625 in IEEE Floating Point Standard is: To align the binary points. If not.2. the bias value must be subtracted from the sum 3. Subtraction of significands is done. Thus. The number 2. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.

then the mantissa must be shifted one bit to the right and the exponent incremented. then number Y is checked. If number X is not ‘0’. Z=Y. If overflow occurs. If the sum overflows the position of the hidden bit.e. If not then the result is normalized.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form. If both the numbers X and Y are non zeros. number X is checked. Flow chart for floating point subtraction: Subtract significand si Fig 2. consider two numbers X and Y and the resultant be Z. then the following steps can be followed: Exponents of both the numbers are checked. If overflow occurred then overflow is reported and returned.-23 .3. In the first step. If the exponents are same.2. If it is ‘0’ then the resultant solution Z would be Y i. then the result would be Z=X. If the significand is zero then it is returned if not significand overflow is checked. DEPARTMENT OF ECE PAGE NO.. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. 2. then the significands of numbers X and Y are subtracted. At this point.8.2.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. If it is ‘0’.8. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent .

10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result. 1. If underflow occurred then it is reported if not the normalized result is given out.1. If the exponents are not same. 2.8 x 9.3. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked.8x times 9. For example. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers. The number 18.8.8. 2. if the significand is not zero then subtraction and further process is carried out. to multiply 1.3.5x : Perform unsigned integer multiplication of the mantissas.-24 .0 in IEEE FPS format is: The number 9. DEPARTMENT OF ECE PAGE NO.5 in IEEE FPS format is: .5 ----17. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z.

If the position of the hidden bit overflows. The sign of the result is the xor of the sign bits of the two numbers.8.3. DEPARTMENT OF ECE PAGE NO.2. the mantissa must be shifted right and the exponent incremented. Block diagram of floating point multiplication: .-25 . Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in (). the result is: 2. When the fields are assembled in IEEE FPS format. the mantissa is: The biased-127 exponents are added.

The mantissa of both numbers A and B are multiplied.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. The exponents of both the numbers are added and subtracted from the bias 127.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. XOR operation for sign bit can be given as follows: Table 2.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . the exponent sum would have doubled the bias. . manA as mantissa of number A.8.8.3. DEPARTMENT OF ECE PAGE NO. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero. Thus. At the first step.3.3. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. Resultant mantissa is truncated and normalized to fit for the IEEE format.3. signB as sign of number B.-26 .8. If both the numbers X and Y are not zero. expB as exponent of number B and manB as mantissa of number B. Sign of the result is given by performing xor operation of signA and signB. If the exponents are stored in biased form. then the exponents are added and a bias of 127 is subtracted from the result. expA as exponent of number A .

3. Hence the result can be given as 1. i.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned.4. 0. Exponent of a is 2 and exponent of b is 3.2 =1.8. in general floating point division the exponents of both the numbers are subtracted and the significands are divided. 2.5. So resultant exponent would be 2-3=-1.-27 . DEPARTMENT OF ECE PAGE NO.3 and b= 0. The resultant sign bit would be the xor operation of sign bits of X and Y.. When the division of both significands are done then the quotient would be 1.5 .5. Division Consider an example of dividing a=0.8.3: Flow Chart For Floating Point Multiplication. Fig 2.2 .e. .3 0.

4. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. ExpB as exponent of number B and ManB as mantissa of number B. Block diagram for floating point division: Fig 2. In the first step. ManA as mantissa of number A.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . signB as sign of number B.32-BIT FLOATING POINT PROCESSOR TEC 2. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. Set the sign of the result. DEPARTMENT OF ECE PAGE NO. Special . Normalize the result. then the resultant sign is also positive and is represented by bit ‘0’. If both the numbers are either positive or negative. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend. 2.8.8.8. As in floating point multiplication. When divided by a 24 bit divisor.4.-28 . If anyone number of the two are negative. ExpA as exponent of number A . The mantissa of both numbers A and B are divided. then the result is also negative is represented by bit ‘1’.1.4.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. a 24 bit quotient is produced. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement. The exponents are subtracted and biased using the bias value. Subtract the exponent of the divisor from the exponent of the dividend.

. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity . Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard .Then the steps that occur are: 1. This value is called Not A Number.3.3 S E and b= 0.-29 . in this case as larger number has to be subtracted from smaller number.8.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned.4.2 can be represented as M 010000001(0)11000000000000000000000 0. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2. DEPARTMENT OF ECE PAGE NO.3 0.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. 2. Considering a=0. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked. For this. or NaN. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero. Number X and Y are checked.

-30 .3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value.9. If they are present. Rounding Error In floating point arithmetic. then those conditions are reported.32-BIT FLOATING POINT PROCESSOR TEC 3. some form of rounding is required. digits may flow off the right end of the significand.. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit. rounding errors occur as a result of the limited precision of the mantissa . and it may be reported as 0. this may be designated as +∞ or -∞.127). 2. .g. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. DEPARTMENT OF ECE PAGE NO. • Significand underflow: In the process of aligning significands.8.200 is less than . Fig 2. If not the mantissas are divided and truncated and normalized result is given out.This means that the number is too small to be represented. In some systems.4. As we shall discuss.

it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. RN is generally preferred and introduces less systematic error than the other rules.10. Break ties by choosing the least significant bit = 0. The size of the absolute error is proportional to the magnitude of the number.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. For numbers in IEEE FPS format. highest precision can be achieved. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2.-31 . Normalization By normalization. The least significant 24 bits are discarded. the relative error is approximately since For denormalized numbers (E = 0). Same as truncation in sign-magnitude. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. However. RZ: Round toward Zero. Same as truncation in 2's complement. DEPARTMENT OF ECE PAGE NO. . relative errors increase as the magnitude of the number decreases toward zero. The value can be kept unchanged by adjusting the exponent accordingly. RM: Round toward minus infinity. To efficiently use the bits available for the significand. For normalized floating point numbers. RP: Round toward Positive infinity. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation.

Truncation To retain maximum accuracy. Zero is represented by all 0's and is not (and cannot be) normalized. The first bit 1 before the decimal point is implicit.-32 . The significand could be further shifted to the left by 1 bit to gain one more bit for precision. bits are used in final representation of a bits by one of the three methods. in the following the default normalization does not assume this implicit 1 unless otherwise specified. extra guard bits are kept during operation. resulting 1. The actual value represented is However. it does not need to be shown explicitly. By the end of the operation. multiplication). the bits need to be truncated to guard bit Chopping: simply drop all .g. DEPARTMENT OF ECE PAGE NO. as the MSB of the significand is always 1. all extra bits during operation (called guard bits) are kept (e.32-BIT FLOATING POINT PROCESSOR TEC Moreover. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit.11. to avoid possible confusion.. If we assume number. a 4-bit exponent field and a 9-bit significand field): 2.

is always greater than 0. Interpretation: Value represented by guard bits is greater than 0. Two worst cases Both two cases can be summarized as i.e..32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. (no matter Von Neumann Rounding: If at least one of the guard bits is 1. otherwise do nothing. set whether it is originally 0 or 1).5 round up. .-33 . Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. the Von Neumann rounding error is unbiased. DEPARTMENT OF ECE PAGE NO. 3. . we say this truncation error is biased. add 1 to LSB .

5 round down. .-34 .5 either up or down with equal probability (50%). c) If the highest guard bit is 1 and the rest guard bits are all 0. Interpretation: Value represented by guard bits is smaller than 0. round down: or if .32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0. The rounding error of these cases can summarized as . drop all guard bits. DEPARTMENT OF ECE PAGE NO. it is randomly rounded . round up: Interpretation: Value represented by guard bits is 0. the rounding depends on the LSB : if .

1985 floating point standard representation before any sort of operations are conducted on them. I. The exponent in this IEEE standard is represented in excess-127 format. Therefore zero is represented by 0111.3 Floating Point Functions A floating-point number is the one. The logic for these is different from the ordinary arithmetic functions. The floating-point operations are incorporated into the design as functions. The above representation is the IEEE-784 1985 standard representation. The numbers in contention have to be first converted into the standard IEEE 784. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number. The logic for floating point addition. 1111. multiplication and division is presented in the following pages.e. the sign of the floating point number.e.-35 . subtraction. The MSB is the sign-bit i. the exponent obtained by balancing operations is added to 0111. Positive numbers are represented by binary values greater than 0111. which is capable of representing real and decimal numbers. The next eight bits are that of the exponent. DEPARTMENT OF ECE PAGE NO. 1111 and negative numbers are represented by binary values less than it. . 1111.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER .

These numbers are stored into the memory from which they are read and processed. These numbers are distinct. The mantissas are then added to each other and the result is then stored in a temporary register. we have to first normalize their exponents. This is done till the lower exponent becomes equal to the higher one. So to add their mantissa’s. So. namely Accumulator and the Temp register that loads the value appearing on the data bus.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. Once the exponents are normalized. Now the numbers from the memory are loaded into two registers. • • .-36 . The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately.32-BIT FLOATING POINT PROCESSOR TEC 3. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. DEPARTMENT OF ECE PAGE NO.

The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. This is done till the lower exponent becomes equal to the higher one. These numbers are stored into the memory from which they are read and processed. Now the numbers from the memory are loaded into two registers.32-BIT FLOATING POINT PROCESSOR 3. So. These numbers are distinct. The mantissas are then subtracted and the result is stored in a temporary register. Once the exponents are normalized. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. namely Accumulator and the Temp register that loads the value appearing on the data bus. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. . So to add their mantissa’s.-37 . we have to first normalize their exponents. DEPARTMENT OF ECE PAGE NO. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL.

DEPARTMENT OF ECE PAGE NO.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. the resulting exponent and the sign of the result that is calculated separately. The final output is obtained by concatenating the product of the mantissas.32-BIT FLOATING POINT PROCESSOR TEC 3. So each input should not exceed 12-bits in length. • • • . In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result.-38 . If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. There is however a limitation to this operation. so that the result is restricted to not more than 24-bits.

This is to ensure that whatever comes as the result is after the decimal point. Apart from that the final sign of the division is calculated separately. Now the first 24-bits from the MSB are compared with the divisor. The result is stored in Temp. • • • • • . We initiate a counter and carry this process for 24 times. we append it with the exponent value and the Sign of the division that are calculated separately. First the exponents are directly added or subtracted depending on which is bigger. if the MSB or the 49th bit is one than we add a one in the quotient. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. The logic for floating point division is as follows. DEPARTMENT OF ECE PAGE NO. till the quotient is full. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. The convention here is that the Numerator should be always less than the denominator. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. we put a zero in the quotient. Now since the greater of the two numbers is decided. And if it is zero.32-BIT FLOATING POINT PROCESSOR TEC 3. Once the quotient is full.-39 . The decimal is assumed to be before the MSB of the resulting quotient.4 Floating Point Division • • • • This is more complicated then Multiplication. Now both the numbers in the IEEE-784 standard format are compared.

A<B . the overall number of registers can vary from about ten to many hundreds. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). meaning a multiple of the motherboard frequency. These tasks are accomplished by moving data from one location to another. and testing for inequalities (A=B. Consider another example of how a document is printed from a word processor. These devices have seen tremendous growth in the last decade. Data manipulations involve storing and sorting information. 32 or 64 bits called registers.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. All microprocessors can perform both tasks. competitive position. corresponds to the number of pulses per second. There are marketing issues involved: development and manufacturing cost. 16. 4. When the processor executes instructions. DSPs can perform the mathematical calculations needed in digital signal processing. consider a word processing program. Computers are extremely capable in two broad areas 1. engineering and digital signal processing. the program moves the data from . Clock frequency is generally a multiple of the system frequency. finding use in everything from cellular telephones to advanced scientific instruments. The basic task is to store the information. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. the processor performs an action that corresponds to an instruction or a part thereof. Data manipulation such as word processing and database management 2. written in Hertz (Hz). etc). and so on. The clock speed (also called cycle). Mathematical calculation used in science. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. data is temporarily stored in small. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. When this code is detected.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. however it is difficult or expensive to make a device that is optimized for both. such as the size of the instruction set and how it interrupts are handled. Depending on the type of processor. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. For instance.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. With each clock peak. There are technical tradeoffs in the hardware design.-40 . organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. DEPARTMENT OF ECE PAGE NO. local memory locations of 8. product life time.

. i. In comparison. DEPARTMENT OF ECE PAGE NO..32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer.. the math operations dominate the execution time. While mathematics is occasionally used in this type of application. the input signal is referred to by x [ ]. This is simply saying that the input signal has been convolved with a filter kernel consisting of: .-41 . While there is some data transfer and inequality evaluation in this algorithm. Using standard notation. For example. The task is to calculate the sample at location n in the output signal. such as to keep track of the intermediate results and control the loops.... the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. it is infrequent and does not significantly affect the overall execution speed. ... the most common DSP technique. there may only be a few coefficients in the filter kernel. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: .. depending on the application. while the output signal is denoted by y [ ]. consider the implementation of an FIR digital filter.e. y[n]....

whereas 32-bit processors are naturally suited to the size of the data elements. In FIR filtering .by the filter kernel coefficients. This is common in scientific research and engineering.. DSPs must also have a predictable execution time.y[n]. converting a word processing document from one form to another. If the digital signal is being received at 20. .. However.x[n-2].2. so as the cost . Floating point calculations also require a 32-bit processor for good efficiency. After shaking is over. the information may be read into a computer and analysed in some way. but these items will appear as chip fabrication technology gets denser. For example. DEPARTMENT OF ECE PAGE NO. The key point in off-line processing is that all of the information is simultaneously available to the processing program. is found by multiplying samples from the input signal. consider a designing of an audio signal in DSP system such as a hearing aid.-42 . power consumption. Hence execution time is critical for selecting the proper device. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. not having a defined start or end. the entire input signal resides in the computer at the same time. with the advent of very fast floating point processing hardware. a geophysicist might use a seismometer to record the ground movement during the earthquake. each sample in the output signal . the DSP must be able to maintain a sustained throughput of 20. Difference between off-line processing and real time processing: In off-line processing.. .x[n-1]. Digital signal processors are designed to quickly carry out FIR filters and similar techniques. most DSPs are used in applications where the processing is continuous. Also. In addition to performing mathematical calculations very rapidly.000 samples per second.. You simply wait for the action to be completed before you give the computer its next assignment In comparison. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. 4. the traditional speed advantage of integer operations over floating point operations is decreasing. Off-line processing is a realm of personal computers and mainframes.000 samples per second.1: Graphical representation of FIR digital filter design. If suppose you are launching your desktop computer on some task . For instance. and summing the products. There is less room on-chip for extra features such as hardware multipliers. The disadvantages of 32-bit processors are cost and system complexity.32-BIT FLOATING POINT PROCESSOR TEC Fig4. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors. design difficulty and so on. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. and to support code written in high level languages. x[n]..3. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. In these cases a 16-bit processor may suffice. say. floating point math must often be used to reduce the cost of programming a project. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. There are a few reasons for why to not to make it faster than necessary because as speed increases. as well as the algorithms that can be applied.

Harvard Architecture. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. the data transfer rate is an incredible 240Mbytes/second. Most present day DSPs use this dual bus architecture. and an I/O controller. while keeping the input signal in data memory. The basis of Harvard design is that the data memory bus is busier than the program memory bus. program instructions and data can be fetched at the same time. two binary values (the numbers) must be passed over the data memory bus. while six parallel ports each provide a 40 Mbytes/second data transfer. When two numbers are multiplied. perform the algorithm and output a sample. This is the world of digital signal processors.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. Different architectures available are: Von Neumann Architecture. there are two serial ports that operate at 40 Mbits/second each. two areas are important enough to be included are an instruction cache. improving the speed over the single bus design. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. Harvard architecture has separate memories for data and program instructions. 4. To improve upon this situation. When all six parallel ports are used together. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. the binary codes that go into the program sequencer. while only one binary value (the program instruction) is passed over the program memory bus. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). hearing aids and radar. These are extremely high speed connections. . The SHARC DSPs provides both serial and parallel communications ports. This includes data. For example. this is needed in telephone communication. Most of the computers are using this architecture today. DEPARTMENT OF ECE PAGE NO. While the SHARC DSPs are optimized in dozens of ways. such as samples from the input signal and filter coefficients as well as program instructions. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput.4. For example. the output signal is produced at the same time that the input signal is acquired. Alternatively. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. Super Harvard Architecture (SHARC). we might place the filter coefficients in program memory.-43 . over and over. For instance. Since the buses operate independently. with separate buses for each. we start by relocating part of the "data" to program memory. Likewise. Real time applications input a sample. they may input a group of samples perform the algorithm and output a group of samples. For instance. at a 40 MHz clock speed.

1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. the program instructions can be pulled from the instruction cache. and the program instruction comes from the instruction cache.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. providing higher speed. on additional executions of the loop. This allows .-44 . In comparison. DEPARTMENT OF ECE PAGE NO. Some DSPs have on-board analog-to-digital and digital-toanalog converters. all DSPs can interface with external converters through serial or parallel ports. the coefficient comes over the program memory bus. providing an additional interface to off-chip memory and peripherals. DSP algorithms generally spend most of their execution time in loops. the Harvard architecture uses separate memories for data and instructions. a feature called mixed signal. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. such as instructions. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller.4. However. this efficient transfer of data is called a high memory-access bandwidth. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. This is a small memory that contains about 32 of the most recent program instructions. This means that the same set of program instructions will continually pass from program memory to the CPU. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. In the jargon of the field. the program instructions must be passed over the program memory bus. The first time through a loop. However.

for 32 bit data.-45 . specifying where the information is to be read from or written to. an arithmetic logic unit (ALU). OR. The multiplier takes the values from two registers. NOT). In a single clock cycle. Elementary binary operations are carried out by the barrel shifter. XOR. The ALU performs addition. and is quite transparent to the programmer. logical operations (AND. a multiplier. data from registers 8-15 can be passed to the ALU. rotating. accessible at 40Mwords/second (160 Mbytes/second). DEPARTMENT OF ECE PAGE NO. subtraction. and places the result into another register. and similar functions. and the two results returned to any of the 16 registers. The math processing is broken into three sections. conversion between fixed and floating point formats. Compare this architecture with the tasks needed to implement an FIR filter. absolute value. such as shifting. one for each of the two memories. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel.4. data from registers 0-7 can be passed to the multiplier. This simplified diagram is of the Analog Devices SHARC DSP. In simpler microprocessors this task is handled as an inherent part of the program sequencer. and so on. multiplies them. Fig 4.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. These control the addresses sent to the program and data memories. extracting and depositing segments. At the top of the diagram are two blocks labelled Data Address Generator (DAG). . All of the steps within the loop can be executed in a single clock cycle. and a barrel shifter.2: Typical DSP architecture. Digital Signal Processors are designed to implement tasks in parallel.

and an 8-bit exponent. thus supporting a vastly greater dynamic range than is available with the fixedpoint format. with DSPs the speed is about the same. All the registers and data buses must be 32 bits wide instead of only 16. TMS320C64x™ DSPs. As the terms fixed. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. . and executes them with equal efficiency. Double-width precision achieves much greater precision and dynamic range at the expense of speed. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. a necessity to implement counters. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. though. the instruction set must be larger and so on. floating point programs often have a shorter development cycle.32-BIT FLOATING POINT PROCESSOR 4. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent.or floating-point decision in the past. For this reason.and floating-point indicate. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. In addition." rather than just “Floating Point. loops. the SHARC DSPs are optimized for both floating point and fixed point operations." fixed point arithmetic is much faster than floating point in general purpose computers. with architectures designed for handheld and control applications. However. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. DEPARTMENT OF ECE PAGE NO. The internal architecture of a floating point device is more complicated than for a fixed point device. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. it depends on the internal architecture . While fixed-point DSP hardware performs strictly integer arithmetic. floating-point DSPs support either integer or real arithmetic. since it requires multiple cycles for each operation. since the programmer doesn’t generally need to worry about issues such as overflow. Fixed point DSPs are cheaper than floating point devices. including a 53-bit mantissa and an 11-bit exponent). the SHARC devices are often referred to as "32-bit DSPs. All floating point DSPs can also handle fixed point numbers.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. TMS320C5x™ and TMS320C2x™ DSPs. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. respectively.For instance. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. However. the latter normalized in the form of scientific notation. underflow and round-off.-46 . the multiplier and ALU must be able to quickly perform floating point arithmetic.5. and signals coming from the ADC and going to the DAC. are based on single16-bit data paths. Comparison between Fixed Point and Floating Point System: TEC Both fixed. a result of the hardware being highly optimized for math operations. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). Today. Tradeoffs of cost and ease of use often heavily influenced the fixed. By contrast.

DEPARTMENT OF ECE PAGE NO. Fixed point DSPs are generally cheaper. floating point has such low quantization noise that these techniques are usually not necessary. it must be round up or down by a maximum of one-half the gap size i. In the worst case. To avoid overflow. This is because the gaps between adjacent numbers are much larger. Suppose we implement an FIR filter in fixed point.000 times less quantisation noise than fixed point. higher dynamic range. Although this is an extreme case. we need to scale the values being added. It can be rated in the form of signal to noise ratio and quantisation noise. while for a fixed point number it is only about ten-thousand to one. For instance. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. while in the SHARC DSPs it contains 80 bits for fixed point use. greatly lowering the signal-to-noise ratio of the system. in a 16 bit DSP it may have 32 to 40 bits. In comparison. Suppose we store in a 32 bit floating point format. while floating point devices have better precision. this quantization noise will simply add. This is a special register that has 2-3 times as many bits as the other memory locations. For instance. DSPs handle this problem by using an extended precision accumulator.. it's bad. we add noise to the signal. and a shorter development cycle. In traditional microprocessors.-47 . we loop through each coefficient. except that the added noise is much worse. The gap between numbers is one ten-thousandth of the value of the number we are storing. floating point has roughly 3. and will correspondingly add quantization noise on each step. In other words.000 as a signed integer. Noise is signal is usually represented by its standard deviation. this accumulator is just another 16 bit fixed point variable. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. really bad. multiply it by the appropriate sample from the input signal. Standard deviation of this quantisation noise is about one-third of the gap size. For example. This extended range virtually eliminates round-off noise while the accumulation is in progress. the noise on each output sample may be 500 times the noise on each input sample. . although it does limit how some algorithms must be carried out. To store the number. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. it illustrates the main point when many operations are carried out on each sample.5. This strategy works very well.e.1: Fixed versus floating point. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. in a 500 coefficient FIR filter. suppose we store the number 10. Here's the problem. each time we store a number in floating point notation. The same thing happens when a number is stored as a 16-bit fixed point value. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. and add the product to an accumulator. To do this.

are very detailed and can be much more difficult to program. and what scaling needs to take place. making them suitable for fixed point. and almost certainly need floating point to capture the large dynamic range. In fixed point. the cost of the product will be reduced. how the quantization errors are accumulating. the development time will be greatly reduced if floating point is used. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. think fixed point. professional audio applications can sample with as high as 20 or 24 bits. In contrast. the numbers take care of themselves. In many applications. Most DSP techniques are based on repeated multiplications and additions.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. When fixed point is chosen. The programmer needs to continuously understand the amplitude of the numbers. The next thing to look at is the complexity of the algorithm that will be run . 12-14 bits per sample is the crossover for using fixed versus floating point. television and other video signals typically use 8 bit ADC and DAC. but the development cost will probably be higher due to the more difficult algorithms. In comparison. In comparison. FIR filtering and other operations in the time domain only require a few dozen lines of code. floating point systems are also easier to develop algorithms for. DEPARTMENT OF ECE PAGE NO. While they can be written in fixed point. In the reverse manner. these issues do not arise in floating point. and the precision of fixed point is acceptable. the possibility of an overflow or underflow needs to be considered after each operation. if it is more complicated. but a more expensive final product. floating point will generally result in a quicker and cheaper development cycle. frequency domain algorithms.-48 . For example.If it is relatively simple. such as spectral analysis and FFT convolution. think floating point. For instance. .

In contrast. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. Fn = Fx * Fy. The RND and SAT options are ways of controlling rounding and register overflow. In comparison. or into one of the extended precision accumulators.5. In other words. and MRB = Rx * Ry. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. For instance. the floating point programmer can spend his time concentrating on the algorithm. and format. Rn. These are the multiplication instructions used in the SHARC DSPs. scaling. and Ry refer to any of the 16 data registers. This describes the ways that multiplication can be carried out for both fixed and floating point formats. .32-BIT FLOATING POINT PROCESSOR TEC Figure 4. Fx. While only a single command is needed for floating point. many options are needed for fixed point. It could not be any simpler. The vertical lines indicate options. the value of any two registers can be multiplied and placed into another register. Rx.2: Fixed versus floating point instructions. where Fn. look at all the possible commands for fixed point multiplication. This table also shows that the numbers may be either signed or unsigned (S or U). DEPARTMENT OF ECE PAGE NO. and MRF and MRB are 80 bit accumulators. MRF = Rx * Ry. These are the many options needed to efficiently handle the problems of round-off. and may be fractional or integer (F or I).-49 . and Fy are any of the 16 data registers.

DEPARTMENT OF ECE PAGE NO. As illustrated in (a). This is mainly driven by consumer products that must have low cost electronics.32-BIT FLOATING POINT PROCESSOR 4.-50 . suppose you are designing a medical imaging system. In comparison. such as cellular telephones. over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs . However. About twice as many engineers currently use fixed point as use floating point DSPs.6. A good example of this is cellular telephones. as shown in (c).6 Trends in DSP: TEC Figure 4. For instance. this depends greatly on the application. such a . floating point is the fastest growing segment. meaning there is a greater difference between the largest number and the smallest number that can be represented. When you are in competition to sell millions of your product. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. a cost difference of only a few dollars can be the difference between success and failure. As shown in (c). The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs.1: Major trends in DSPs. However. 32-bit floating point has a higher dynamic range. about twice as many engineers use fixed point as use floating point DSPs. and another 49% are considering the change. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. floating point is more common when greater performance is needed and cost is not important. In (b). Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low.

For a single 16-bit by 16-bit multiplication. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. which would go beyond most application requirements in accuracy. the floating point market is the fastest growing segment. 16. or 32 bits for fixed-point DSPs. the internal representations of data in floating-point DSPs are more exact than in fixed-point. For this application. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). the same as the signal data in DSPs. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. While fixed-point coefficients are 16 bits. this overflow headroom is 8 bits.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. The first is the I/O signal word width. Three data word widths are important to consider in the internal architecture of a DSP. Only a few hundred of the model will ever be sold. DEPARTMENT OF ECE PAGE NO. The second word width is that of the coefficients used in multiplications. and can be 8. In fixed. which is 24 bits for floating-point. or a 48-bit product for a single 24-bit by 24-bit multiplication. floating-point coefficients can be 24 bits or 53 bits of precision. but the performance is critical.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). . Third. 16 bits for fixed-point. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. iterated MACs require additional bits for overflow headroom. depending whether single or double precision is used. a 32-bit product would be needed. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. the cost of the DSP is insignificant.-51 . exponentiation vastly increases the dynamic range available for the application. 4. However. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. Finally. Second. In spite of the larger number of fixed point DSPs being used. at a price of several hundred-thousand dollars each. Fortunately.point devices. in integer as well as real values. First. ensuring greater accuracy in end results.

. It became very easy to a designer to verify functionality of design at various levels. for design electronics circuits with assistance of software programs.-52 . Designers felt need to automate these processes. and etc.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5.e.) on an IC.) on a chip. i. This level is LSI (Large Scale Integration). Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. Using design at this level. counters. DEPARTMENT OF ECE PAGE NO. registers. . Rapid advances in Software Technology and development of new higher level programming languages taken place.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. I/O peripheral devices and etc. using this scale of integration people succeeded to make digital subsystems (Microprocessor. This created new challenges to digital designers as well as circuit designers. because of manual converting the design from one level to other. This may be leading to development of sophisticated electronic products for both consumer as well as business. Later Integrated Circuits (ICs) were invented. This way of designing (using CAD tools) is certainly a revolution in electronic industry. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. In this process. At this point design process started getting very complicated. One can fabricate a chip contains more than Million of gates. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration).. one can create digital sub blocks (adders. At this point design process still became critical. i. CMOS (Complementary Metal Oxide Semiconductor) process technology. Using latest CAD tools could solve the problem.e. With advent of new technology. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. multiplexes.

DEPARTMENT OF ECE PAGE NO. .2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5.-53 .32-BIT FLOATING POINT PROCESSOR 5.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.

5. and verification of the digital systems was generated. The IEEE in the December 1987 standardized VHDL language. It is a hardware description language that can be used to model a digital system at many levels of abstraction. available from IEEE. documentation.-54 . Thus.3. This subset is usually sufficient to model most applications . and many ambiguities present in the 1987 version of the language were resolved. however. Reprocurement and reuse was also a big issue.  The language can be used as a communication medium between different CAD and CAE tools .1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. Therefore.The complete language. the language was upgraded with new features.3. This new version of the language is known as the IEEE STD 1076-1993. The official language description appears in the IEEE standard VHDL language Reference manual.     5.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. ranging from the algorithmic level to the gate level. Different chip vendors can provide VHDL descriptions of their components to system designers. this version of the language is known as the IEEE STD 1076-1987.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. the syntax of many constructs was made more uniform. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language  VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. According to IEEE rules. models written in this language can be verified using a VHDL simulator. Consequently.  The language can be used as exchange medium between chip vendors and CAD tool users. a need for a standardized hardware description language for the design. The language has also been recognized as an American National Standards Institute (ANSI) standard. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. DEPARTMENT OF ECE PAGE NO.

As a set of concurrent assignment statements (to represent data flow) 3. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. SUM) A1: AND2portmap (A. B. This model specifies the external view of the device and one or more internal views.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. called an Entity. in turn. End component. As a set of sequential assignment statements (to represent behavior) As any combination of the above three.  The language supports flexible design methodologies: top-down.32-BIT FLOATING POINT PROCESSOR TEC  The language supports hierarchy. It supports both synchronous and asynchronous timing models. Begin X1: Xor2portmap (A. 1.  Arbitrarily large designs can be modeled using the language. Structural style of modeling: In this one an entity is described as a set of interconnected components.  The language is publicly available. In VHDL each device model is treated as a distinct representation of a unique device.  It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. such as finite –state machine descriptions. human-readable. or mixed. CARRY). and behavioral. which contains one external view and one or more internal views. and Boolean equations. M: in BIT. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. Y: in BIT. As a set of interconnected components (to represent structure) 2. Component And2 Port (L. can be modeled as a set of interconnected subcomponents.-55 . 5. can be modeled using the language. . and there are no limitations imposed by the language on the size of the design. B. bottom-up.  The language supports three basic different styles: Structural. End component. The internal view of the device specifies functionality or structure. DEPARTMENT OF ECE PAGE NO. that is a digital can be modeled as asset of interconnected components. The Entity is thus a hardware abstraction of the actual hardware device. Such a model for the HALF_ADDER entity. and machine-readable. Z:out BIT).3.  Various digital modeling techniques. each component. Dataflow. N:outBIT). Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. Each Entity is described using one model.

Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std. 5.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. which are specified inside a process statement. 13641995 standard. and EDIF and mixed VHDL-Verilog-EDIF designs.In a signal assignment statement. Two component declarations are present in the declarative part of the architecture body. single simulation kernel.4. The data flow model for the half adder is described using two concurrent signal assignment statements . 1076-1993 standard. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0.4.4. and auxiliary utilities designed for easy management of resource files. the flow of data through the entity is expressed primarily using concurrent signal assignment statements.3. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position.1.3. do not explicitly specify the structure of the entity but merely its functionality. The name of the architecture body is ha . VHDL'93 compiler. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. Verilog. DEPARTMENT OF ECE PAGE NO.4 INTRODUCTION TO HDL TOOLS 5. designs. graphical and textual simulation output viewers.the entity declaration for half adder specifies the interface ports for this architecture body.-56 .1. the symbol <=implies an assignment of a value to a signal. and libraries. A process statement is a concurrent statement that can appear with in an architecture body. The declared components are instantiated in the statement part of the architecture body using component instantiation.4 DATAFLOW STYLE OF MODELING: In this modeling style. 5. 5. . These sets of sequential statements. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. The architecture body is composed of two parts: the declaration part and the statement part.2. several debugging tools. It comprises three different design entry tools.32-BIT FLOATING POINT PROCESSOR TEC End ha. SIMULATION TOOL 5. 5. Verilog compiler.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL.

Design Browser: The Design Browser window displays the contents of the current design. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. The keyword coloring is also available when HDL Editor is used for editing macro files. 1. 5. 5. The editor is tightly integrated with the simulator to enable debugging source code. the maintenance. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). Resource files attached to the design. 2.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams.4. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams.1/D1. and Tcl scripts. Perl scripts. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. that is: a. DEPARTMENT OF ECE PAGE NO.0 May 1997).0. It allows you to graphically edit waveforms so as to create desired test vectors. HDL Editor: HDL Editor is a text editor designed for HDL source files. 4. . It displays specific syntax categories in different colors (keyword coloring). 3. The VITAL-compliant models can be annotated with timing data from SDF files. b.-57 . the communication of hardware design and test verification data. modification and procurement of hardware system.1. The contents of the default-working library of the design. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. SDF files must comply with OVI Standard Delay Format Specification Version 2.

All Active-HDL tools output their messages to Console. Compilation: Compilation is a process of analysis of a source file. DEPARTMENT OF ECE PAGE NO. • The Active-HDL simulator provides two simulation engines. Active-HDL provides three compilers.vhd) • Verilog file (. d. . In Active-HDL. Verilog. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. and scripts.-58 . a source file can be on of the following: • VHDL file (.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. When you choose a menu command or toolbar button for compilation. Cycle-based simulation is significantly faster than event-driven. or EDIF file containing HDL code (or net list) generated from the diagram.EDIF) • State diagram file (. Verilog. the compiler analyzes the intermediate VHDL.4. or EDIF objects declared within a selected region of the current design. The structure of the design unit selected for simulation. transistors or gates) and their interconnection.bde) In the case of a block or state diagram file. respectively for VHDL. VHDL. Verilog. 5. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands.v) • EDIF net list file (.asf) • Block diagram file (. macros. A net list is a set of statements that specifies the elements of a circuit (for example. and EDIF.32-BIT FLOATING POINT PROCESSOR TEC c. 6. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel.

1: Simulation 5.5.6.The ISE Text Editor is provided in ISE for entering design code and viewing reports. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE. Verilog HDL. including ModelSim Xilinx Edition and the HDL Bencher test bench generator.4.32-BIT FLOATING POINT PROCESSOR TEC Fig4. DEPARTMENT OF ECE PAGE NO. and finally produce a bit stream for your device configuration.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite. 5. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.4.2 Design Entry: • ISE Text Editor . . ISE enables you to start your design with any of a number of different source types.4.6. This overview explains the general progression of a design through ISE from start to finish. including: • HDL (VHDL.-59 .6 SYNTHESIS TOOL: 5.3. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.

and edit schematics and symbols for the Design Entry step of the Xilinx® design flow.The Map program maps a logical design to a Xilinx FPGA.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. transitions.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. including routing.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs.The Chip Viewer tool provides a graphical view of the inputs and outputs.The Floor planner allows you to view a graphical representation of the FPGA. Map . transforms.6. Timing Analyzer . to system-level building blocks such as filters.-60 .3 Implementation: • Translate .The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. CORE Generator . • • • • • • • . and pin assignments. FIFOs. and memories. analysis can be performed immediately after mapping. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor . Constraints Editor . and Area Group constraints. • • • • 5. State CAD State Machine Editor . macro cell details.The PAR program accepts the mapped design.4.State CAD allows you to specify states. Global logic. and to view and modify the placed design. and produces output for the bit stream generator. Place and Route (PAR) . places and routes the FPGA. Fit (CPLD only) . equations. placing or routing an FPGA design. and actions in a graphical editor. and after fitting and routing a CPLD design. view. PACE .The FPGA Editor allows you view and modify the physical implementation. Floor planner .The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. With Timing Analyzer. The state machine will be created in HDL.The Constraints Editor allows you to create and modify the most commonly used timing constraints. Chip Viewer (CPLD only) . FPGA Editor .The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O.

The iMPACT tool generates various programming file formats. • • • .-61 .6. Integration with ChipScope Pro.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices.32-BIT FLOATING POINT PROCESSOR TEC 5.4. DEPARTMENT OF ECE PAGE NO. XPower . and subsequently allows you to configure your device. iMPACT .4 Device Download and Program File Formatting: • BitGen .The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration.

1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. . DEPARTMENT OF ECE PAGE NO. multiplication and division are done using active HDL tool and the results are as follows: 6.-62 .32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. subtraction.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .

.-63 .32-BIT FLOATING POINT PROCESSOR TEC 6.2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format.2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form. DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .

3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form.32-BIT FLOATING POINT PROCESSOR TEC 6.-64 .3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6. . DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . .4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format.-65 .32-BIT FLOATING POINT PROCESSOR TEC 6. DEPARTMENT OF ECE PAGE NO. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6.

-66 . Basic arithmetic operations such as addition. The Functional-simulation has been successfully carried out with the results matching with the expected ones.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. • 7. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. . subtraction. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. • • Procedures for performing basic arithmetic operations are been formed. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation.

Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. Normally. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. However. unpredictable events can occur on an assembly line. Since the subset must be determined in real time during system operation. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. the robot might weld itself to an assembly unit. The wide dynamic range of a floating-point DSP. DEPARTMENT OF ECE PAGE NO. or something might unexpectedly block its range of motion. . enable imaging systems to achieve a much higher level of recognition and definition for the user. Many levels of signal input from light. together with the device’s more accurate internal representations of data. feedback is well out of the ordinary operating range.-67 . The radar system may be tracking in a range from 0 to infinity. For instance. The greater precision of signal data. x-rays.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. In these cases. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. but need to use only a small subset of the range for target acquisition and identification. Wide dynamic range also plays a part in robotic design. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. however.

M.computer.intel. Chicago. 197-210  Jones. H.46  www.org/portal/web/csdl/doi/10.. (1981) A survey of high-level language machines in Japan.1109/SNPD.) Introduction to Computer Architecture. Computer. In: Stone.org  www. Proc. Science Research Associates. July 1981. M. (1987) The Implementation of Functional Programming Languages. In: 1986 FORML Conf. 28-30 November 1986.com . 1975. pp. New York  McKeeman.2007. (1975) Stack computers.-68 . Hayes. Prentice-Hall. 281-317  Yamamoto. S. 14(7) 68-78 REFERENCES  www..32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY  Fraeman. R. pp. J. & Zaremba. (1986) A 32 bit processor architecture for direct execution of Forth.ieeexplore. W. (Ed.ieee. T. Pacific Grove CA. DEPARTMENT OF ECE PAGE NO. Williams. P..

--*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc.std_logic_unsigned. variable Temp :Std_logic_vector(6 downto 0). begin temp:=x.all. end Fadd.Compute Ea-Eb -2. use IEEE.std_logic_arith. use IEEE. b : in std_logic_vector(31 downto 0). DEPARTMENT OF ECE PAGE NO. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0).32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1.all.-69 .Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.all.Shift the that has lesser Exponent by Ea-Eb places to the right * -3. use IEEE. y : out std_logic_vector(31 downto 0) ).std_logic_1164.Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE.

Z :=(a&b). a :=Acc(31).Sign Of Two mantissas variable Sign : std_logic. --***************************************************************** --*Equalization of Exponents includes two steps --*1. Eb :=Data(30 downto 23).s2 : std_logic. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). -.b : std_logic. end loop.-70 . --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).Mangitude Of Two mantissas variable ES : std_logic. DEPARTMENT OF ECE PAGE NO. -.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. -.Sign Of Resultant Mantissa variable W.Number Of Shifts variable Ma. -. end if.Resultant Exponent variable Ns : integer. Ea :=Acc(30 downto 23).Internal Register variable Ea. -. variable X : std_logic_vector(31 downto 0). Es:=Eb(7) . else TEC Sum:=Sum.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0). -. -.Internal Register variable MbIn : std_logic_vector(22 downto 0).Eb : std_logic_vector(7 downto 0). -. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). -. IE:=Eb(6 downto 0). b :=Data(31).Sign Of Two exponents variable s1. MbIn:=Data(22 downto 0).Sign Of Resulant Exponent variable a.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. -. return sum.Mb : std_logic_vector(22 downto 0). -. -.Z : std_logic_vector(1 downto 0). Ma:=MaIn. end function.Subtraction of Exponents --*2.Final Result begin MaIn:=Acc(22 downto 0). end loop.

-71 . Ma:=MaIn. ES:=Ea(7). end if. Ma:=Ma. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). . IE:=IE. else NS:=Ns. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). DEPARTMENT OF ECE PAGE NO. when "10" => Mb:=MbIn. end loop. end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). IE:=Ea(6 downto 0). end loop. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). IE:=Ea(6 downto 0).32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). IE:=Ea(6 downto 0). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). when "01" => Mb:=MbIn. when "11" => Mb:=MbIn. Ma:=MaIn. Es:=Ea(7). end loop. Ma:=MaIn. Mb:=Mb. IE:=Eb(6 downto 0). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Ea(7). ES:=Eb(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7).

DEPARTMENT OF ECE sign:='0'. end if. s2:=Data(31). else sign:=sign. else NS:=Ns. end if. PAGE NO.-72 . IE:=Eb(6 downto 0). when others => Null. end if. IE:=IE. --******************Addition of Mantissas**************************** IR:=Ma+Mb. else sign:=sign. sign:='1'. if(Ea>Eb) then sign:='1'. Ma:=Ma. elsif(Ma=Mb) then sign:='0'. end case. elsif(Ma<Mb) then sign:='1'. ES:=Ea(7). ES:=Eb(7). if(Ea>Eb) then sign:='0'.32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). W :=(s1&s2). --***********logic for the sign of the mantissa********************** s1:=Acc(31). Mb:=Mb. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. case W is when "00" => when "11" => when "01" => when "10" => . elsif(Ea<Eb) then sign:='1'. end loop.

-73 * . else sign:=sign. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . begin process(a. return X.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. end function. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)). end if. elsif(Ma=Mb) then sign:='0'. elsif(Ma<Mb) then sign:='0'. end if. else sign:=sign. end case. when others => null.b). end Fadd. DEPARTMENT OF ECE PAGE NO.b) begin y<=float_add(a. end process. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'.

Compute Ea-Eb 2. .Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.std_logic_arith.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.Shift the that has lesser Exponent by Ea-Eb places to the right * 3.32-BIT FLOATING POINT PROCESSOR ----1.std_logic_1164. end Fsub.all.all.all. use ieee.-74 . variable Temp : Std_logic_vector(6 downto 0). use ieee. begin temp:=x. b : in STD_LOGIC_VECTOR (31 downto 0).std_logic_unsigned. DEPARTMENT OF ECE PAGE NO. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). use IEEE. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout. y : out std_logic_vector(31 downto 0)).

-.s2 : std_logic. Ea :=Accout(30 downto 23).MbIn: std_logic_vector(22 downto 0). -.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). -. Eb :=Data(30 downto 23).Mb : std_logic_vector(22 downto 0).Z : std_logic_vector(1 downto 0). variable X : std_logic_vector(31 downto 0). --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. -. end function. -.-75 . -.Final Result begin MaIn:=Accout(22 downto 0). --*********************variable Declarations*********************** TEC variable MaIn. -. return sum. -.32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i.b : std_logic. end if.Internal Register variable Ea.Sign Of Resultant Mantissa variable W. Z :=(a&b).Sign Of Resulant Exponent variable a.Resultant Exponent variable Ns : integer.Number Of Shifts variable Ma.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Sign Of Two Exponents variable s1. MbIn:=Data(22 downto 0).Sign Of Two Mantissas variable sign : std_logic. -.Subtraction of Exponents * * . a :=Accout(30). end loop. DEPARTMENT OF ECE PAGE NO. b :=Data(30). -. -.Eb : std_logic_vector(7 downto 0). else Sum:=Sum.Mangitude Of Two Mantissas variable ES : std_logic.

end if. Mb:=Mb.Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). . end loop.32-BIT FLOATING POINT PROCESSOR --*2. IE:=Ea(6 downto 0). IE:=IE. ES:=Ea(7). end loop. else NS:=Ns. TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). Ma:=Ma.-76 . when "01" => Mb:=MbIn. IE:=Eb(6 downto 0). ES:=Ea(7). IE:=Ea(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Eb(7). Ma:=MaIn. DEPARTMENT OF ECE PAGE NO. Ma:=MaIn.

-77 . end loop. TEC Ma:=MaIn. end loop. ES:=Eb(7).32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. DEPARTMENT OF ECE PAGE NO. --******************Subtraction of Mantissas************************ IR:=Ma-Mb. IE:=Eb(6 downto 0). else NS:=Ns. . NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). end case. ES:=Eb(7). IE:=IE. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end if. IE:=Ea(6 downto 0). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Ea(7). Ma:=MaIn. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). when "11" => Mb:=MbIn. Mb:=Mb. end loop. Ma:=Ma. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). when others => null. ES:=Ea(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=Eb(6 downto 0).

elsif (Ma=Mb) then sign:='0'. else sign:=sign. end if. elsif(Ma<Mb) then sign:='0'. end if. when "10"=> if (Ea>Eb)then sign:='1'.32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). W:=(s1&s2). elsif (Ea<Eb) then sign:='0'. case W is when "00"=> sign:='0'. else sign:=sign. end if. DEPARTMENT OF ECE PAGE NO.-78 . else sign:=sign. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. end if. elsif(Ea<Eb) then sign:='1'. s2:=Data(31). elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. else sign:=sign. elsif(Ma<Mb) then sign:='1'. when "11"=> sign:='1'. . when "01"=> if(Ea>Eb)then sign:='0'. elsif (Ma=Mb) then sign:='0'.

DEPARTMENT OF ECE PAGE NO. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)). b: in STD_LOGIC_VECTOR (31 downto 0).b). --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0). -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. use IEEE. end Fmul.-79 . y: out STD_LOGIC_VECTOR (31 downto 0) ). end case.std_logic_1164. begin process(a. end f_sub.32-BIT FLOATING POINT PROCESSOR TEC when others=> null.Addtion of the Exponents 5. end function. use IEEE. . end process.Multiplication of the Mantissas * * -************************************************************************** library IEEE.std_logic_unsigned.all.b) begin y<=float_sub(a.all. return X.

e2 :=Data(30 downto 23).Z : std_logic_vector(1 downto 0).Two Exponents Icluding Sign variable m1.Resultant Mantissa variable carry : std_logic. -.m2 : std_logic_vector(10 downto 0).s2 : std_logic. when "11" => s:='0'. -.Final Result begin Carry:='0'. -.Sign Two Exponents variable s1. .-80 .Magnitude O Two Mantissas variable s : std_logic.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout. -. variable x : std_logic_vector(31 downto 0). s2:=Data(31).Sign Of Resultant Mantissa variable a. -. -.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0).Resultant exponent variable m : std_logic_vector(21 downto 0).Carry variable W. case Z is when "00" => s:='0'.Magnitude Of Two Exponents variable c : std_logic. --************logic for the sign of the Mantissa******************* s1:=Accout(31).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. -. -.b : std_logic. DEPARTMENT OF ECE PAGE NO. -. -. end case. -.sign Two Mantissas variable Ea.e2 : std_logic_vector(7 downto 0). m1 :=Accout(10 downto 0).Eb : std_logic_vector(6 downto 0). when others=> s:='1'. m2 :=Data(10 downto 0). Z :=(s1&s2). e1 :=Accout(30 downto 23).

end case. e:="0000000". else c:='0'. e:="0000000". DEPARTMENT OF ECE PAGE NO. when "10" => if(Ea>Eb) then c:='1'. Eb:=e2(6 downto 0). end if. a :=Accout(30). --*************logic for multiplication************************* m:=m1*m2. case W is when "00" => c:='0'. e:=Ea-Eb. b :=Data(30). else c:='0'. e:=Ea+Eb. end if. when "01" => if(Ea>Eb) then c:='0'. W :=(a&b). e:=Ea+Eb. e:=Eb-Ea. c:='1'. when "11" => when others => null. e:=Ea-Eb. elsif(Ea<Eb) then c:='0'.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). . e:=Eb-Ea. elsif(Ea<Eb) then c:='1'.-81 .

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

e:=Ea+Eb. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. end if. else c:='0'. e:=Ea-Eb. else c:='0'. e:=Eb-Ea. end if. end if. a :=e1(7). b :=e2(7). e:="0000000". . if(Ea>Eb) then c:='1'. e:=Ea-Eb. case Z is when "00" => if(Ea>Eb) then c:='0'. elsif(Ea<Eb) then c:='0'. e:=Eb+Ea. e:="0000000". e:=Eb-Ea. elsif(Ea<Eb) then c:='1'. e:="0000000". Eb:=e2(6 downto 0). if(Ea>Eb) then c:='0'. elsif(Ea<Eb) then c:='0'.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). when "10"=> if(Ea>Eb) then c:='1'. e:=Ea+Eb. Z :=(a&b). else c:='0'.-86 . elsif(Ea<Eb) then c:='0'.

return X. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. end process. e:="0000000". --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). end function. TEC . when others=> null.b) begin Y<=float_div(a. end F_div. end case.-87 .b). begin process(a. end if. else c:='0'.

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