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TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

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32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

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32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

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DEPARTMENT OF ECE PAGE NO. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits.1: Binary Real Number System Because the size and number of registers that any computer can have is limited. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations. the subset of real numbers that a particular FPU supports represents an approximation of the real number system.) to plus infinity (+ ). As shown at the bottom of Figure 1.-5 .1. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers. the real-number system comprises the continuum of real numbers from minus infinity (. only a subset of the real-number continuum can be used in real-number calculations.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. Figure 2. . As shown in Figure 1.

Software programmable for maximum flexibility and supported by easy-touse. Among the key factors to consider are the computational capabilities required for the application. the signed fraction format allows . and ease of development. designers can identify the DSP that is best suited for an application. the number is an integer).32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers.536 possible bit patterns can represent a number. while floating-point DSPs support either integer or real arithmetic. but decimal fixed point is common in commercial applications. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. Motorola manufactures a family of fixed point DSPs that use 24 bits. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. In common mathematical notation. some specific assumption is made about where the radix point is located in the string. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation.768 to 32.535. fixed point and floating point. These refer to the format used to store and manipulate numbers within the devices. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. Fixed-point Vs floating-point in digital signal processing Fig 2. the stored number can take on any integer value from 0 to 65.-6 . processor and system costs. Fixed point DSPs usually represent each number with a minimum of 16 bits. Lastly. DEPARTMENT OF ECE PAGE NO. the 65.536 levels are spread uniformly between 0 and 1. 2.767. signed integer uses two's complement to make the range include negative numbers. Similarly. With unsigned fraction notation. For instance. although a different length can be used.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data. DSPs enable designers to build innovative features and differentiating value into their products. In fixed-point systems. In unsigned integer. the digit string can be of any length. low-cost development tools. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. There are four common ways that these 216 ' 65. performance attributes. from -32. Balancing these factors together. Digital Signal Processing can be divided into two categories.2.

The represented values are unequally spaced between these two extremes. This is known as the significand. For this reason.296 to be exact. the largest and smallest numbers are ±3." 2.In comparison. and floating-point representation can thus be thought of as a computer realization of scientific notation.-7 . such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. For instance. The radix point is not explicitly included. it depends on the internal architecture. The speed of floating-point operations is an important measure of performance for computers in many application domains. and executes them with equal efficiency. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). floating point DSPs typically use a minimum of 32 bits to store each value. but small gaps between small numbers. The logic for these is different from the ordinary arithmetic functions. DEPARTMENT OF ECE PAGE NO. that is. This position is indicated separately in the internal representation.967. equally spaced between -1 and 1. respectively. The floating-point operations are incorporated into the design as functions.4.3. 2324. This results in many more bit patterns than for fixed point. It is measured in” FLOPS”. or sometimes the mantissa (see below) or coefficient. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations.4 ×1038 and ±1. a necessity to implement counters.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. which is capable of representing real and decimal numbers. loops. The term” floating point” refers to the fact that the radix point can "float".However. the SHARC devices are often referred to as "32-bit DSPs. In the most common format (ANSI/IEEE Std.754-1985). but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. A key feature of floating point notation is that the represented numbers are not uniformly spaced. All floating point DSPs can also handle fixed point numbers. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. Floating point A floating-point number is the one. the SHARC DSPs are optimized for both floating point and fixed point operations. This is important because it places large gaps between large numbers." rather than just "Floating Point. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. and signals coming from the ADC and going to the DAC. 2. it can be placed anywhere relative to the significant digits of the number.294.2 ×1038.

The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. These differed in the word sizes.32-BIT FLOATING POINT PROCESSOR TEC significant digit. 10 or 16. this final value is where s is the value of the significand (after taking into account the implied radix point). with an average error of about 3%. Symbolically. floating-point numbers achieve their greater range at the expense of precision. The length of the significand determines the precision to which numbers can be represented. 2. composed as integer. which modifies the magnitude of the number. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. and the rounding behaviour of operations. These differing systems implemented different parts of the arithmetic in hardware and software.5. A signed integer exponent. The significand is multiplied by the base raised to the power of the exponent. DEPARTMENT OF ECE PAGE NO. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. computers used many different forms of floating-point. The floating-point format needs slightly more storage (to encode the position of the radix point). the format of the representations.Fraction. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. Prior to the IEEE-754 standard. 1 for negative values. also referred to as the characteristic or scale.-8 . Significand is a real number. (This is because the exponent field is in . and e is the exponent. or to the right of the rightmost digit. b is the base. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. so when stored in the same space.

also known as the significand. and each possible combination of bits represents one real number. DEPARTMENT OF ECE .32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. A float is represented using 32 bits. to sum up: 1. 1 denotes a negative number. This means that at most 232 possible real numbers can be exactly represented. the exponent. So. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. where f is the field of fraction bits. To do this. IEEE-754 specifies binary representations for floating point numbers: Table 2. represents the precision bits of the number.) This can be exploited in some applications. The Mantissa: The mantissa. 2. It is composed of an implicit leading bit and the fraction bits. The sign bit is 0 for positive. a bias is added to the actual exponent in order to get the stored exponent. The exponent's base is two. The Sign Bit: The sign bit is as simple as it gets. The exponent field contains 127 plus the true exponent for single-precision. 0 denotes a positive number. The Exponent: The exponent field needs to represent both positive and negative exponents. 1 for negative.-9 . IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. or 1023 plus the true exponent for double precision. even though there are infinitely many real numbers (even between 0 and 1). and the mantissa. such as volume ramping in digital sound processing.f. The first bit of the mantissa is typically assumed to be 1.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. 3. 4. Flipping the value of this bit flips the sign of the number. There are many formats that are used for representation of floating point number.

which may be represented as numbered from 0 to 31.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude. then V=-Infinity If E=255 and F is zero and S is 0. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. left to right. then V=Infinity . S. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude. 'E'. DEPARTMENT OF ECE PAGE NO.5.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010).1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values.5. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero.5. then V=NaN ("Not a number") If E=255 and F is zero and S is 1. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.-10 . Table 2. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). the next eight bits are the exponent bits.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word.

If E=0 and F is zero and S is 1.-11 . then V=(-1)**S * 2 ** (-126) * (0. DEPARTMENT OF ECE PAGE NO. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.F) These are "unnormalized" values. then V=-0 If E=0 and F is zero and S is 0.3125 The biased exponent is -2+127=125= (01111101 • 1.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.101 = 6. If E=0 and F is nonzero.101 = -6.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0. then V=0 In particular.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.0 The biased exponent is .0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.F) where "1.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.

3125 is • 0.25 0.25 The biased exponent: 127+6=133=(10000101 • -1313.312510 = 10100100001. • -78. sign bit is 1. DEPARTMENT OF ECE PAGE NO.5 × 2 = 1.40625 × 2 = 0.010010000101012 × 210.3125 0.625 0.8125 × 2 = 1.40625 0.5 × 2 = 0.1015625 0.1015625 × 2 = 0.203125 × 2 = 0.01012.5 The based exponent: 127+5= (10000100 .32-BIT FLOATING POINT PROCESSOR TEC • 37.3125 131310 = 101001000012 0.0 0 1 0 1 1313.625 × 2 = 1.-12 . .625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0.25 × 2 = 0. 10 + 127 = 137 = 100010012.203125 0. So -1313.8125 . = 1.

3. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001).625 0.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0. The first bit is the sign bit.5. which may be represented as numbered from 0 to 63.25 0. then V=NaN ("Not a number") PAGE NO. S. the next eleven bits are the exponent bits. left to right.-13 .32-BIT FLOATING POINT PROCESSOR 0.101562510 = 0. 'E'.5 0 × 2 = 1.0 1 0. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.1015625 is 0 00111101 110100000000000000000000 TEC 2. The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero.5 × 2 = 1. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.00011012 = 1. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0).5.25 1 × 2 = 0. DEPARTMENT OF ECE .3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.

F) where "1.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038. Table 2. . while maintaining good precision.6. using a fixed number of digits.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit .4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2.F) These are "unnormalized" values. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. DEPARTMENT OF ECE PAGE NO. then V=-Infinity If E=2047 and F is zero and S is 0. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa).5.53 ~ 10308. floating-point notation allows calculations over a wide range of magnitudes.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. If E=0 and F is zero and S is 1. 15 exponent bits and 112 significand bits. then V=(-1)**S * 2 ** (-1022) * (0. If E=0 and F is nonzero. then V=-0 If E=0 and F is zero and S is 0.-14 . then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent.

Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent. Approximate Decimal 2127 21023 ~10-44.85 to ~1038. U) (where B is the base of the system. P is the precision of the system to P numbers.-15 . the range for negative numbers is given by the negation of the above values. There is a smallest positive normalized floating-point number. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1).6. Zero 4. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand. and the smallest possible value for the exponent.53 ~10-323.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. Negative numbers greater than -2-149 (negative underflow) 3. L is the smallest exponent represent able in the system. There is a largest floating point number. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. The number of normalized floating point numbers in a system F(B.2: Effective Range of IEEE Floating Point Number with Denormalized.32-BIT FLOATING POINT PROCESSOR TEC Table 2. Positive numbers less than 2-149 (positive underflow) . DEPARTMENT OF ECE PAGE NO. Normalized And Approximate Decimal Values. L.3 to ~10308. P.

When this occurs.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. 2. Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers.infinity. Recently. the number is exactly zero. DEPARTMENT OF ECE PAGE NO. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. the largest value which is defined in bias-127 exponent representation. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. However the CPU will have to perform extra arithmetic to read the number when stored in this format. If M = 0. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or .32-BIT FLOATING POINT PROCESSOR 5.-16 . Underflow occurs when the sum of the exponents is more negative than -126. 2. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. the exponent is set to -127 (E = 0). When this occurs. the most negative value which is defined in bias-127 exponent representation.

as the smaller number here is a=2.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.-17 . But by using floating point addition this can be avoided to a little extent. DEPARTMENT OF ECE PAGE NO. Multiplication 4. They are: 1. Floating point addition is analogous to addition using scientific notation. Add the numbers with decimal points aligned. Division 2. Addition 2.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points.. Subtraction 3. Now as both the exponent values are same.1.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.8. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded.e. let us consider two numbers a= 2. both the numbers are added. Normalize the result.0225x . Hence the value of number ‘a’ becomes 0. For example. . i.25x and b= 1..

1. 2. 2. DEPARTMENT OF ECE PAGE NO. i.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .00000009876543 x 2. a =1. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value.234567x and b= 9. ManA as mantissa of number A. ExpA as exponent of number A . Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2.8. The mantissa of both numbers A and B are added. But the normalised result may sometimes carry the required result.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i.8. then bit 1 is represented for sign.8.e. If the numbers are represented with both positive and negative sign.876543x after shifting becomes b= 0. signB as sign of number B.2. then sign of greater number is considered. b= 9. ExpB as exponent of number B and ManB as mantissa of number B.00000009876543 x c= 1.2345670 x in which the remaining part (9876543) which is discarded also carries the result.1. Consider a example in which a =1.876543x and if the addition has to be performed.1.1.-18 .23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. then the following result may occur: 1.. Thus this case can said to be having rounding errors. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.234567x b= 0.e. Now both the numbers are added. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: .

6. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. Addition of significands is done.2: Flow Chart for Floating Point Adder. the bias value must be subtracted from the sum 3. Thus.8. exception is made. the numbers are represented in IEEE floating point format. 2.-19 . If not. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. 4. the exponent sum would have doubled the bias. DEPARTMENT OF ECE PAGE NO. 1. If the exponents are stored in biased form. 5. .1. Firstly. If there is an underflow or overflow. the significand is rounded to the appropriate number of bits required and again normalization is checked.

2. Normalization in this case may require shifting by the total number of bits in the mantissa. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal.32-BIT FLOATING POINT PROCESSOR TEC 7. Thus. 2. then the mantissa must be shifted one bit to the right and the exponent incremented.-20 . resulting in a large loss of accuracy. The number 2. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form.2. DEPARTMENT OF ECE PAGE NO. the result is converted back to signmagnitude form.25 in IEEE Floating Point Standard is: The number 134. so the hidden bits can sum to no more than 3 (11).340625x . Negative mantissas are handled by first converting to 2's complement and then performing the addition. resulting in a sum which is arbitrarily small. If the sum overflows the position of the hidden bit.25 becomes: The mantissas are added using integer addition: The result is already in normal form.0625 in IEEE Floating Point Standard is: To align the binary points. After the addition is performed. cancellation may occur. The mantissa is always less than 2.8. Subtraction . Consider addition of the numbers 2. or even zero if the numbers are equal in magnitude.25x and 1. When adding numbers of opposite sign.

ManA as mantissa of number A.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. signB as sign of number B.1. Subtract the numbers with decimal points aligned. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if . ExpA as exponent of number A . The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2. ExpB as exponent of number B and ManB as mantissa of number B..0225x . Now as both the exponent values are same.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .e. both the numbers are added.-21 . If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.e.2.25x and b= 1. i. then sign is represented according to the number i. Hence the value of number ‘a’ becomes 0. Normalize the result.. The mantissa of both numbers A and B are subtracted.2. DEPARTMENT OF ECE PAGE NO..32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2. The normalised result may contain the required number of digits discarding the unwanted part.8.8.340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal.1. 2. as the smaller number here is a=2.

If there is an underflow or overflow. The numbers are represented in IEEE floating point format.0625 in IEEE Floating Point Standard is: To align the binary points. 4. 2.-22 .2. exception is made. 5. Thus.8. Consider subtraction of the numbers 2.25 in IEEE Floating Point Standard is: The number 134. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1.340625x .25 become: The mantissas are subtracted using integer subtraction: . If the exponents are stored in biased form. The number 2. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. If not. Subtraction of significands is done. 2. Thus. the significand is rounded to the appropriate number of bits required and again normalization is checked.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign.2. 6. the exponent sum would have doubled the bias. DEPARTMENT OF ECE PAGE NO. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. 2. the bias value must be subtracted from the sum 3.25x and 1.

then the following steps can be followed: Exponents of both the numbers are checked.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. 2.8.2. Flow chart for floating point subtraction: Subtract significand si Fig 2.2. If it is ‘0’ then the resultant solution Z would be Y i. number X is checked. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked.3. If number X is not ‘0’. then the mantissa must be shifted one bit to the right and the exponent incremented. then number Y is checked. If not then the result is normalized. then the result would be Z=X. If the significand is zero then it is returned if not significand overflow is checked. If both the numbers X and Y are non zeros. If overflow occurs. If the sum overflows the position of the hidden bit.. At this point. Z=Y. If overflow occurred then overflow is reported and returned.8. If the exponents are same. In the first step. then the significands of numbers X and Y are subtracted. consider two numbers X and Y and the resultant be Z.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form.-23 . If it is ‘0’. DEPARTMENT OF ECE PAGE NO.e. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent .

Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.8 x 9.-24 .3.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result. 1. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z.8. If underflow occurred then it is reported if not the normalized result is given out. If the exponents are not same. DEPARTMENT OF ECE PAGE NO. 2.1.5 in IEEE FPS format is: . The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.5 ----17.8x times 9.8. 2. The number 18. if the significand is not zero then subtraction and further process is carried out.0 in IEEE FPS format is: The number 9.5x : Perform unsigned integer multiplication of the mantissas.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked.3. For example. to multiply 1.

DEPARTMENT OF ECE PAGE NO. the mantissa must be shifted right and the exponent incremented.8.-25 . the mantissa is: The biased-127 exponents are added. Block diagram of floating point multiplication: .32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in (). If the position of the hidden bit overflows. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form.2.3. The sign of the result is the xor of the sign bits of the two numbers. When the fields are assembled in IEEE FPS format. the result is: 2.

The exponents of both the numbers are added and subtracted from the bias 127. .8. Resultant mantissa is truncated and normalized to fit for the IEEE format.3.3. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero. the exponent sum would have doubled the bias.3. manA as mantissa of number A. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. expA as exponent of number A . signB as sign of number B.3.8. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. XOR operation for sign bit can be given as follows: Table 2. At the first step.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. expB as exponent of number B and manB as mantissa of number B. If the exponents are stored in biased form. The mantissa of both numbers A and B are multiplied.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . If both the numbers X and Y are not zero. DEPARTMENT OF ECE PAGE NO.8.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. Sign of the result is given by performing xor operation of signA and signB.-26 . Thus. then the exponents are added and a bias of 127 is subtracted from the result.

2 =1. 0. The resultant sign bit would be the xor operation of sign bits of X and Y. DEPARTMENT OF ECE PAGE NO. Division Consider an example of dividing a=0.8. . So resultant exponent would be 2-3=-1.2 . Exponent of a is 2 and exponent of b is 3.5 .32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned.5.4.3. Hence the result can be given as 1. Fig 2. i.3 0.e. in general floating point division the exponents of both the numbers are subtracted and the significands are divided.5.3: Flow Chart For Floating Point Multiplication.3 and b= 0. 2. When the division of both significands are done then the quotient would be 1.8.-27 ..

-28 .1. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit.8. In the first step. If both the numbers are either positive or negative.4.4.32-BIT FLOATING POINT PROCESSOR TEC 2. ExpB as exponent of number B and ManB as mantissa of number B.4. then the resultant sign is also positive and is represented by bit ‘0’. ExpA as exponent of number A . Block diagram for floating point division: Fig 2. a 24 bit quotient is produced. As in floating point multiplication. Set the sign of the result. Normalize the result. ManA as mantissa of number A. When divided by a 24 bit divisor.8. then the result is also negative is represented by bit ‘1’.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. If anyone number of the two are negative.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . DEPARTMENT OF ECE PAGE NO.8. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement. The mantissa of both numbers A and B are divided. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. signB as sign of number B. Special . The exponents are subtracted and biased using the bias value. 2. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend. Subtract the exponent of the divisor from the exponent of the dividend.

Then the steps that occur are: 1. .3 0. This value is called Not A Number. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard .3 S E and b= 0. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked. DEPARTMENT OF ECE PAGE NO.-29 . in this case as larger number has to be subtracted from smaller number.2 can be represented as M 010000001(0)11000000000000000000000 0. or NaN. 2.4.3. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity .2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. Considering a=0.8. For this. Number X and Y are checked.

this may be designated as +∞ or -∞.4.g.. . As we shall discuss.This means that the number is too small to be represented. and it may be reported as 0. DEPARTMENT OF ECE PAGE NO. Fig 2. If not the mantissas are divided and truncated and normalized result is given out.127). • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit.8.32-BIT FLOATING POINT PROCESSOR TEC 3. • Significand underflow: In the process of aligning significands. some form of rounding is required.9. digits may flow off the right end of the significand. 2. rounding errors occur as a result of the limited precision of the mantissa . Rounding Error In floating point arithmetic.200 is less than .3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. In some systems.-30 . • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. then those conditions are reported. If they are present.

RM: Round toward minus infinity. RP: Round toward Positive infinity. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). . The value can be kept unchanged by adjusting the exponent accordingly. Same as truncation in sign-magnitude. For normalized floating point numbers. DEPARTMENT OF ECE PAGE NO. For numbers in IEEE FPS format. RZ: Round toward Zero. Same as truncation in 2's complement. However. relative errors increase as the magnitude of the number decreases toward zero. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. To efficiently use the bits available for the significand.-31 . RN is generally preferred and introduces less systematic error than the other rules. Break ties by choosing the least significant bit = 0. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. The size of the absolute error is proportional to the magnitude of the number. Normalization By normalization. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. highest precision can be achieved. the relative error is approximately since For denormalized numbers (E = 0). The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest.10. The least significant 24 bits are discarded.

a 4-bit exponent field and a 9-bit significand field): 2. Truncation To retain maximum accuracy.11. extra guard bits are kept during operation..g. as the MSB of the significand is always 1. If we assume number.32-BIT FLOATING POINT PROCESSOR TEC Moreover. The first bit 1 before the decimal point is implicit. resulting 1. By the end of the operation. DEPARTMENT OF ECE PAGE NO. in the following the default normalization does not assume this implicit 1 unless otherwise specified. Zero is represented by all 0's and is not (and cannot be) normalized. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. it does not need to be shown explicitly. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit. all extra bits during operation (called guard bits) are kept (e. bits are used in final representation of a bits by one of the three methods. the bits need to be truncated to guard bit Chopping: simply drop all . to avoid possible confusion. The actual value represented is However.-32 . multiplication).

-33 . the Von Neumann rounding error is unbiased.. otherwise do nothing. Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0.32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. DEPARTMENT OF ECE PAGE NO.5 round up. 3. set whether it is originally 0 or 1). . . Two worst cases Both two cases can be summarized as i.e. add 1 to LSB . is always greater than 0. we say this truncation error is biased. (no matter Von Neumann Rounding: If at least one of the guard bits is 1. Interpretation: Value represented by guard bits is greater than 0.

-34 . DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0. round down: or if . round up: Interpretation: Value represented by guard bits is 0. drop all guard bits.5 round down. . Interpretation: Value represented by guard bits is smaller than 0. the rounding depends on the LSB : if .5 either up or down with equal probability (50%). it is randomly rounded . The rounding error of these cases can summarized as . c) If the highest guard bit is 1 and the rest guard bits are all 0.

3 Floating Point Functions A floating-point number is the one. Positive numbers are represented by binary values greater than 0111. I. The floating-point operations are incorporated into the design as functions. The next eight bits are that of the exponent. The logic for these is different from the ordinary arithmetic functions.e. subtraction. . the exponent obtained by balancing operations is added to 0111.e.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number. DEPARTMENT OF ECE PAGE NO. multiplication and division is presented in the following pages. 1985 floating point standard representation before any sort of operations are conducted on them. The exponent in this IEEE standard is represented in excess-127 format. 1111. 1111. Therefore zero is represented by 0111. The MSB is the sign-bit i. the sign of the floating point number.-35 . The logic for floating point addition. The above representation is the IEEE-784 1985 standard representation. which is capable of representing real and decimal numbers. 1111 and negative numbers are represented by binary values less than it. The numbers in contention have to be first converted into the standard IEEE 784.

32-BIT FLOATING POINT PROCESSOR TEC 3.-36 . Now the numbers from the memory are loaded into two registers. The mantissas are then added to each other and the result is then stored in a temporary register. These numbers are distinct. Once the exponents are normalized. These numbers are stored into the memory from which they are read and processed. namely Accumulator and the Temp register that loads the value appearing on the data bus.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. This is done till the lower exponent becomes equal to the higher one. DEPARTMENT OF ECE PAGE NO. So to add their mantissa’s. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. we have to first normalize their exponents. • • . So.

DEPARTMENT OF ECE PAGE NO. This is done till the lower exponent becomes equal to the higher one. . Once the exponents are normalized. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. The mantissas are then subtracted and the result is stored in a temporary register.-37 . These numbers are distinct. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. namely Accumulator and the Temp register that loads the value appearing on the data bus.32-BIT FLOATING POINT PROCESSOR 3. These numbers are stored into the memory from which they are read and processed. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. So. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. we have to first normalize their exponents. So to add their mantissa’s. Now the numbers from the memory are loaded into two registers. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL.

DEPARTMENT OF ECE PAGE NO.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. so that the result is restricted to not more than 24-bits. the resulting exponent and the sign of the result that is calculated separately.32-BIT FLOATING POINT PROCESSOR TEC 3. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. • • • .-38 . In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. So each input should not exceed 12-bits in length. There is however a limitation to this operation. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. The final output is obtained by concatenating the product of the mantissas.

The convention here is that the Numerator should be always less than the denominator. DEPARTMENT OF ECE PAGE NO. we put a zero in the quotient. First the exponents are directly added or subtracted depending on which is bigger. And if it is zero. Apart from that the final sign of the division is calculated separately. we append it with the exponent value and the Sign of the division that are calculated separately. if the MSB or the 49th bit is one than we add a one in the quotient. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. Now the first 24-bits from the MSB are compared with the divisor. The result is stored in Temp. The logic for floating point division is as follows. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. • • • • • . Now both the numbers in the IEEE-784 standard format are compared.-39 .4 Floating Point Division • • • • This is more complicated then Multiplication. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. The decimal is assumed to be before the MSB of the resulting quotient. We initiate a counter and carry this process for 24 times. Now since the greater of the two numbers is decided. till the quotient is full. This is to ensure that whatever comes as the result is after the decimal point.32-BIT FLOATING POINT PROCESSOR TEC 3. Once the quotient is full.

data is temporarily stored in small. competitive position. local memory locations of 8. Consider another example of how a document is printed from a word processor.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). Clock frequency is generally a multiple of the system frequency. written in Hertz (Hz). engineering and digital signal processing.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. All microprocessors can perform both tasks. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. product life time. The clock speed (also called cycle). and so on. These tasks are accomplished by moving data from one location to another. such as the size of the instruction set and how it interrupts are handled. There are technical tradeoffs in the hardware design. These devices have seen tremendous growth in the last decade. meaning a multiple of the motherboard frequency. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. 16. Mathematical calculation used in science. For instance. corresponds to the number of pulses per second. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction.-40 . and testing for inequalities (A=B. A<B . finding use in everything from cellular telephones to advanced scientific instruments. Data manipulation such as word processing and database management 2. however it is difficult or expensive to make a device that is optimized for both. DEPARTMENT OF ECE PAGE NO. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. With each clock peak. Computers are extremely capable in two broad areas 1. consider a word processing program. Depending on the type of processor. the program moves the data from . 32 or 64 bits called registers. When this code is detected. DSPs can perform the mathematical calculations needed in digital signal processing. When the processor executes instructions. etc). 4. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. the overall number of registers can vary from about ten to many hundreds. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. The basic task is to store the information. There are marketing issues involved: development and manufacturing cost. Data manipulations involve storing and sorting information. the processor performs an action that corresponds to an instruction or a part thereof.

. consider the implementation of an FIR digital filter. Using standard notation.. For example. While there is some data transfer and inequality evaluation in this algorithm...32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. such as to keep track of the intermediate results and control the loops. the math operations dominate the execution time. while the output signal is denoted by y [ ]. In comparison. This is simply saying that the input signal has been convolved with a filter kernel consisting of: ... . While mathematics is occasionally used in this type of application.. The task is to calculate the sample at location n in the output signal... it is infrequent and does not significantly affect the overall execution speed. there may only be a few coefficients in the filter kernel.e. y[n]. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: ... the input signal is referred to by x [ ]. i. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. the most common DSP technique. depending on the application.. DEPARTMENT OF ECE PAGE NO.-41 .

3. and to support code written in high level languages. There are a few reasons for why to not to make it faster than necessary because as speed increases. floating point math must often be used to reduce the cost of programming a project. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. There is less room on-chip for extra features such as hardware multipliers. 4. In FIR filtering . consider a designing of an audio signal in DSP system such as a hearing aid. The key point in off-line processing is that all of the information is simultaneously available to the processing program. the traditional speed advantage of integer operations over floating point operations is decreasing.... as well as the algorithms that can be applied. If the digital signal is being received at 20. For example. . If suppose you are launching your desktop computer on some task . a geophysicist might use a seismometer to record the ground movement during the earthquake.. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. the DSP must be able to maintain a sustained throughput of 20. The disadvantages of 32-bit processors are cost and system complexity. . Off-line processing is a realm of personal computers and mainframes. power consumption. the entire input signal resides in the computer at the same time. and summing the products. most DSPs are used in applications where the processing is continuous. each sample in the output signal . 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. Floating point calculations also require a 32-bit processor for good efficiency. say. whereas 32-bit processors are naturally suited to the size of the data elements. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors. with the advent of very fast floating point processing hardware. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. x[n]. the information may be read into a computer and analysed in some way.-42 . Digital signal processors are designed to quickly carry out FIR filters and similar techniques. so as the cost . A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path.x[n-1]. DSPs must also have a predictable execution time. This is common in scientific research and engineering.000 samples per second.by the filter kernel coefficients.. DEPARTMENT OF ECE PAGE NO. design difficulty and so on. but these items will appear as chip fabrication technology gets denser. Hence execution time is critical for selecting the proper device. Also.1: Graphical representation of FIR digital filter design. not having a defined start or end.32-BIT FLOATING POINT PROCESSOR TEC Fig4. Difference between off-line processing and real time processing: In off-line processing. For instance. is found by multiplying samples from the input signal. converting a word processing document from one form to another. However. In these cases a 16-bit processor may suffice. You simply wait for the action to be completed before you give the computer its next assignment In comparison.2.x[n-2]. After shaking is over.000 samples per second. In addition to performing mathematical calculations very rapidly.y[n].

such as samples from the input signal and filter coefficients as well as program instructions. This includes data. This is the world of digital signal processors. we start by relocating part of the "data" to program memory. Alternatively. there are two serial ports that operate at 40 Mbits/second each. the output signal is produced at the same time that the input signal is acquired. For example. The von Neumann design is satisfactory when the contents of the task to be executed must be serial.4. 4. we might place the filter coefficients in program memory. with separate buses for each. Different architectures available are: Von Neumann Architecture. program instructions and data can be fetched at the same time. When two numbers are multiplied. and an I/O controller. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. Super Harvard Architecture (SHARC). Real time applications input a sample. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. perform the algorithm and output a sample. While the SHARC DSPs are optimized in dozens of ways. DEPARTMENT OF ECE PAGE NO. improving the speed over the single bus design. For instance. the binary codes that go into the program sequencer. this is needed in telephone communication. two binary values (the numbers) must be passed over the data memory bus. The basis of Harvard design is that the data memory bus is busier than the program memory bus. Most present day DSPs use this dual bus architecture. while six parallel ports each provide a 40 Mbytes/second data transfer. they may input a group of samples perform the algorithm and output a group of samples. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. while keeping the input signal in data memory. . the data transfer rate is an incredible 240Mbytes/second. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU).-43 . Harvard architecture has separate memories for data and program instructions. Harvard Architecture. Since the buses operate independently. Most of the computers are using this architecture today. over and over. The SHARC DSPs provides both serial and parallel communications ports. To improve upon this situation. while only one binary value (the program instruction) is passed over the program memory bus. These are extremely high speed connections. When all six parallel ports are used together. at a 40 MHz clock speed. hearing aids and radar.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. For example. two areas are important enough to be included are an instruction cache. For instance. Likewise.

a feature called mixed signal. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. and the program instruction comes from the instruction cache. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. The main buses (program memory bus and data memory bus) are also accessible from outside the chip.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. In the jargon of the field. However. the program instructions can be pulled from the instruction cache. However. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. the Harvard architecture uses separate memories for data and instructions. on additional executions of the loop. The first time through a loop.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. This means that the same set of program instructions will continually pass from program memory to the CPU. providing an additional interface to off-chip memory and peripherals. the coefficient comes over the program memory bus. DSP algorithms generally spend most of their execution time in loops. DEPARTMENT OF ECE PAGE NO. Some DSPs have on-board analog-to-digital and digital-toanalog converters. providing higher speed.4. In comparison. the program instructions must be passed over the program memory bus. This allows . This is a small memory that contains about 32 of the most recent program instructions.-44 . all DSPs can interface with external converters through serial or parallel ports. such as instructions. this efficient transfer of data is called a high memory-access bandwidth.

NOT).2: Typical DSP architecture. such as shifting. for 32 bit data. These control the addresses sent to the program and data memories. and so on. a multiplier. absolute value.4. multiplies them. Fig 4. Compare this architecture with the tasks needed to implement an FIR filter. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. . and is quite transparent to the programmer. At the top of the diagram are two blocks labelled Data Address Generator (DAG). In simpler microprocessors this task is handled as an inherent part of the program sequencer. an arithmetic logic unit (ALU). and a barrel shifter. DEPARTMENT OF ECE PAGE NO. extracting and depositing segments. and the two results returned to any of the 16 registers. data from registers 8-15 can be passed to the ALU. In a single clock cycle.-45 . one for each of the two memories. The multiplier takes the values from two registers. accessible at 40Mwords/second (160 Mbytes/second).32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. This simplified diagram is of the Analog Devices SHARC DSP. and places the result into another register. Digital Signal Processors are designed to implement tasks in parallel. subtraction. specifying where the information is to be read from or written to. OR. rotating. The ALU performs addition. data from registers 0-7 can be passed to the multiplier. All of the steps within the loop can be executed in a single clock cycle. conversion between fixed and floating point formats. logical operations (AND. and similar functions. XOR. Elementary binary operations are carried out by the barrel shifter. The math processing is broken into three sections.

For this reason. However.and floating-point indicate. loops. the latter normalized in the form of scientific notation.or floating-point decision in the past.5. Comparison between Fixed Point and Floating Point System: TEC Both fixed. it depends on the internal architecture . though. and executes them with equal efficiency. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. thus supporting a vastly greater dynamic range than is available with the fixedpoint format. underflow and round-off. Today. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing.For instance. the multiplier and ALU must be able to quickly perform floating point arithmetic. a result of the hardware being highly optimized for math operations. a necessity to implement counters. the instruction set must be larger and so on. By contrast. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. The internal architecture of a floating point device is more complicated than for a fixed point device. TMS320C5x™ and TMS320C2x™ DSPs. All the registers and data buses must be 32 bits wide instead of only 16.-46 . DEPARTMENT OF ECE PAGE NO. . However. the SHARC devices are often referred to as "32-bit DSPs. the SHARC DSPs are optimized for both floating point and fixed point operations. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. In addition. floating point programs often have a shorter development cycle.32-BIT FLOATING POINT PROCESSOR 4. All floating point DSPs can also handle fixed point numbers. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. floating-point DSPs support either integer or real arithmetic. since it requires multiple cycles for each operation. While fixed-point DSP hardware performs strictly integer arithmetic. As the terms fixed. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. and an 8-bit exponent. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). Tradeoffs of cost and ease of use often heavily influenced the fixed. are based on single16-bit data paths. with architectures designed for handheld and control applications. and signals coming from the ADC and going to the DAC." fixed point arithmetic is much faster than floating point in general purpose computers. with DSPs the speed is about the same. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. Double-width precision achieves much greater precision and dynamic range at the expense of speed. including a 53-bit mantissa and an 11-bit exponent). Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. TMS320C64x™ DSPs. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. since the programmer doesn’t generally need to worry about issues such as overflow. respectively. Fixed point DSPs are cheaper than floating point devices." rather than just “Floating Point.

suppose we store the number 10. in a 16 bit DSP it may have 32 to 40 bits.e. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. In other words. Here's the problem. we loop through each coefficient. . and will correspondingly add quantization noise on each step. floating point has such low quantization noise that these techniques are usually not necessary. This is because the gaps between adjacent numbers are much larger. although it does limit how some algorithms must be carried out. For instance.000 as a signed integer. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. except that the added noise is much worse. while for a fixed point number it is only about ten-thousand to one. Noise is signal is usually represented by its standard deviation. Standard deviation of this quantisation noise is about one-third of the gap size. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. To avoid overflow. while floating point devices have better precision. this quantization noise will simply add. To do this. To store the number. higher dynamic range. and add the product to an accumulator. The gap between numbers is one ten-thousandth of the value of the number we are storing. This strategy works very well. Fixed point DSPs are generally cheaper. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. In comparison. Suppose we implement an FIR filter in fixed point. DEPARTMENT OF ECE PAGE NO.000 times less quantisation noise than fixed point.-47 . Suppose we store in a 32 bit floating point format. In traditional microprocessors. this accumulator is just another 16 bit fixed point variable. really bad. This extended range virtually eliminates round-off noise while the accumulation is in progress. The same thing happens when a number is stored as a 16-bit fixed point value. In the worst case. while in the SHARC DSPs it contains 80 bits for fixed point use. multiply it by the appropriate sample from the input signal.. floating point has roughly 3. it must be round up or down by a maximum of one-half the gap size i. we add noise to the signal. This is a special register that has 2-3 times as many bits as the other memory locations. DSPs handle this problem by using an extended precision accumulator. and a shorter development cycle. For instance.1: Fixed versus floating point. each time we store a number in floating point notation. For example.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. it illustrates the main point when many operations are carried out on each sample. It can be rated in the form of signal to noise ratio and quantisation noise. greatly lowering the signal-to-noise ratio of the system. it's bad. in a 500 coefficient FIR filter. we need to scale the values being added.5. the noise on each output sample may be 500 times the noise on each input sample. Although this is an extreme case.

if it is more complicated. but the development cost will probably be higher due to the more difficult algorithms. For instance. these issues do not arise in floating point. Most DSP techniques are based on repeated multiplications and additions. think floating point. and the precision of fixed point is acceptable. think fixed point. but a more expensive final product. the development time will be greatly reduced if floating point is used. In the reverse manner. In fixed point. The programmer needs to continuously understand the amplitude of the numbers. making them suitable for fixed point.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. and what scaling needs to take place. how the quantization errors are accumulating. floating point systems are also easier to develop algorithms for. In comparison. professional audio applications can sample with as high as 20 or 24 bits. such as spectral analysis and FFT convolution. the numbers take care of themselves. 12-14 bits per sample is the crossover for using fixed versus floating point. When fixed point is chosen. DEPARTMENT OF ECE PAGE NO. frequency domain algorithms. For example. television and other video signals typically use 8 bit ADC and DAC. floating point will generally result in a quicker and cheaper development cycle. and almost certainly need floating point to capture the large dynamic range. The next thing to look at is the complexity of the algorithm that will be run .-48 . In many applications. .If it is relatively simple. In comparison. the cost of the product will be reduced. are very detailed and can be much more difficult to program. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. In contrast. the possibility of an overflow or underflow needs to be considered after each operation. FIR filtering and other operations in the time domain only require a few dozen lines of code. While they can be written in fixed point.

Rx. and MRF and MRB are 80 bit accumulators. the value of any two registers can be multiplied and placed into another register. where Fn. many options are needed for fixed point.5. scaling. Fn = Fx * Fy. The vertical lines indicate options. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. and Fy are any of the 16 data registers.-49 . In comparison. The RND and SAT options are ways of controlling rounding and register overflow. MRF = Rx * Ry. or into one of the extended precision accumulators.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. In contrast. These are the many options needed to efficiently handle the problems of round-off. and MRB = Rx * Ry. . It could not be any simpler. DEPARTMENT OF ECE PAGE NO. Fx. and Ry refer to any of the 16 data registers. This table also shows that the numbers may be either signed or unsigned (S or U). the floating point programmer can spend his time concentrating on the algorithm. In other words.2: Fixed versus floating point instructions. These are the multiplication instructions used in the SHARC DSPs. and may be fractional or integer (F or I). Rn. This describes the ways that multiplication can be carried out for both fixed and floating point formats. For instance. and format. While only a single command is needed for floating point. look at all the possible commands for fixed point multiplication.

as shown in (c). The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. This is mainly driven by consumer products that must have low cost electronics. floating point is the fastest growing segment.6 Trends in DSP: TEC Figure 4. meaning there is a greater difference between the largest number and the smallest number that can be represented. about twice as many engineers use fixed point as use floating point DSPs.32-BIT FLOATING POINT PROCESSOR 4. such a . a cost difference of only a few dollars can be the difference between success and failure. In (b).6. suppose you are designing a medical imaging system.1: Major trends in DSPs. floating point is more common when greater performance is needed and cost is not important. such as cellular telephones. 32-bit floating point has a higher dynamic range. About twice as many engineers currently use fixed point as use floating point DSPs.-50 . When you are in competition to sell millions of your product. As illustrated in (a). this depends greatly on the application. DEPARTMENT OF ECE PAGE NO. However. As shown in (c). over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs . and another 49% are considering the change. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low. For instance. However. In comparison. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. A good example of this is cellular telephones.

Third. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. Second. the floating point market is the fastest growing segment.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner.point devices. In fixed. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. floating-point coefficients can be 24 bits or 53 bits of precision. The second word width is that of the coefficients used in multiplications. The first is the I/O signal word width. which is 24 bits for floating-point. First.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. the cost of the DSP is insignificant. 16. at a price of several hundred-thousand dollars each. 16 bits for fixed-point.-51 . Three data word widths are important to consider in the internal architecture of a DSP. depending whether single or double precision is used. a 32-bit product would be needed. or 32 bits for fixed-point DSPs. exponentiation vastly increases the dynamic range available for the application. For this application. which would go beyond most application requirements in accuracy. in integer as well as real values. 4. However. the same as the signal data in DSPs. and can be 8. While fixed-point coefficients are 16 bits. Fortunately. ensuring greater accuracy in end results. but the performance is critical. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. In spite of the larger number of fixed point DSPs being used. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. the internal representations of data in floating-point DSPs are more exact than in fixed-point. Finally. For a single 16-bit by 16-bit multiplication. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). iterated MACs require additional bits for overflow headroom. this overflow headroom is 8 bits. or a 48-bit product for a single 24-bit by 24-bit multiplication. DEPARTMENT OF ECE PAGE NO. . The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). Only a few hundred of the model will ever be sold.

CMOS (Complementary Metal Oxide Semiconductor) process technology. At this point design process started getting very complicated. It became very easy to a designer to verify functionality of design at various levels.) on a chip. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels..32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. i. This level is LSI (Large Scale Integration). Using latest CAD tools could solve the problem. for design electronics circuits with assistance of software programs. multiplexes. registers.e. one can create digital sub blocks (adders. In this process.e.-52 . This created new challenges to digital designers as well as circuit designers. because of manual converting the design from one level to other. With advent of new technology. At this point design process still became critical. I/O peripheral devices and etc. This may be leading to development of sophisticated electronic products for both consumer as well as business. using this scale of integration people succeeded to make digital subsystems (Microprocessor. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. This way of designing (using CAD tools) is certainly a revolution in electronic industry. and etc.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors.) on an IC. Rapid advances in Software Technology and development of new higher level programming languages taken place. counters.. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). i. Designers felt need to automate these processes. Later Integrated Circuits (ICs) were invented. Using design at this level. . DEPARTMENT OF ECE PAGE NO. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. One can fabricate a chip contains more than Million of gates. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical.

DEPARTMENT OF ECE PAGE NO.-53 .3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5. .32-BIT FLOATING POINT PROCESSOR 5.

and verification of the digital systems was generated. documentation.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system.3. According to IEEE rules. this version of the language is known as the IEEE STD 1076-1987. and many ambiguities present in the 1987 version of the language were resolved. available from IEEE. models written in this language can be verified using a VHDL simulator. The language can be used as exchange medium between chip vendors and CAD tool users. Different chip vendors can provide VHDL descriptions of their components to system designers. the language was upgraded with new features.The complete language.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. It is a hardware description language that can be used to model a digital system at many levels of abstraction. The IEEE in the December 1987 standardized VHDL language. a need for a standardized hardware description language for the design.-54 . however. This subset is usually sufficient to model most applications . Reprocurement and reuse was also a big issue. the syntax of many constructs was made more uniform. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. ranging from the algorithmic level to the gate level. The language can be used as a communication medium between different CAD and CAE tools .1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD).3. Consequently. 5. This new version of the language is known as the IEEE STD 1076-1993. The language has also been recognized as an American National Standards Institute (ANSI) standard. DEPARTMENT OF ECE PAGE NO. 5. Therefore. The official language description appears in the IEEE standard VHDL language Reference manual. Thus.

The language supports flexible design methodologies: top-down. Arbitrarily large designs can be modeled using the language. As a set of concurrent assignment statements (to represent data flow) 3. This model specifies the external view of the device and one or more internal views. In VHDL each device model is treated as a distinct representation of a unique device. CARRY). that is a digital can be modeled as asset of interconnected components. The language supports three basic different styles: Structural. and Boolean equations. B. Dataflow. M: in BIT. human-readable. such as finite –state machine descriptions. can be modeled using the language.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. and machine-readable. N:outBIT).3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. Z:out BIT). The internal view of the device specifies functionality or structure. Structural style of modeling: In this one an entity is described as a set of interconnected components. Begin X1: Xor2portmap (A. called an Entity. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. which contains one external view and one or more internal views. each component. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. and there are no limitations imposed by the language on the size of the design. Y: in BIT. can be modeled as a set of interconnected subcomponents. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. and behavioral. SUM) A1: AND2portmap (A. Such a model for the HALF_ADDER entity. 5. Various digital modeling techniques. Each Entity is described using one model. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. DEPARTMENT OF ECE PAGE NO. .-55 . End component.3. As a set of interconnected components (to represent structure) 2. B. 1. The language is publicly available. or mixed. It supports both synchronous and asynchronous timing models. in turn. Component And2 Port (L. bottom-up. End component. The Entity is thus a hardware abstraction of the actual hardware device.

the flow of data through the entity is expressed primarily using concurrent signal assignment statements. graphical and textual simulation output viewers. A process statement is a concurrent statement that can appear with in an architecture body.1.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. 5. . EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0. 5. Two component declarations are present in the declarative part of the architecture body. and EDIF and mixed VHDL-Verilog-EDIF designs.4 DATAFLOW STYLE OF MODELING: In this modeling style. single simulation kernel.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. several debugging tools. do not explicitly specify the structure of the entity but merely its functionality. the symbol <=implies an assignment of a value to a signal.4. The name of the architecture body is ha . The declared components are instantiated in the statement part of the architecture body using component instantiation. Verilog.3.1. 5. These sets of sequential statements. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. SIMULATION TOOL 5.the entity declaration for half adder specifies the interface ports for this architecture body.-56 . which are specified inside a process statement.2. 1076-1993 standard. The architecture body is composed of two parts: the declaration part and the statement part. VHDL'93 compiler.32-BIT FLOATING POINT PROCESSOR TEC End ha.4. Verilog compiler. and libraries.4 INTRODUCTION TO HDL TOOLS 5.In a signal assignment statement.3. and auxiliary utilities designed for easy management of resource files. designs. It comprises three different design entry tools. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std. 5. 13641995 standard.4. DEPARTMENT OF ECE PAGE NO. The data flow model for the half adder is described using two concurrent signal assignment statements .

Design Browser: The Design Browser window displays the contents of the current design. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. It allows you to graphically edit waveforms so as to create desired test vectors. the maintenance. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI).32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. Resource files attached to the design.4. 1. The editor is tightly integrated with the simulator to enable debugging source code. 5. modification and procurement of hardware system. It displays specific syntax categories in different colors (keyword coloring). The editor automatically translates graphically designed diagrams into VHDL or Verilog code. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. The contents of the default-working library of the design. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. The VITAL-compliant models can be annotated with timing data from SDF files. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. and Tcl scripts. the communication of hardware design and test verification data. 4. Perl scripts. The keyword coloring is also available when HDL Editor is used for editing macro files.1. .3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. SDF files must comply with OVI Standard Delay Format Specification Version 2. HDL Editor: HDL Editor is a text editor designed for HDL source files. 5.0 May 1997).1/D1. 2. b. 3.0. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. DEPARTMENT OF ECE PAGE NO.-57 . that is: a.

or EDIF file containing HDL code (or net list) generated from the diagram. macros. a source file can be on of the following: • VHDL file (.vhd) • Verilog file (. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator.4. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC c.bde) In the case of a block or state diagram file. d.-58 . Verilog. • The Active-HDL simulator provides two simulation engines. Cycle-based simulation is significantly faster than event-driven. and EDIF. In Active-HDL. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. Compilation: Compilation is a process of analysis of a source file. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. the compiler analyzes the intermediate VHDL. . 5. All Active-HDL tools output their messages to Console.EDIF) • State diagram file (. Active-HDL provides three compilers. VHDL. Verilog. and scripts.v) • EDIF net list file (. transistors or gates) and their interconnection. When you choose a menu command or toolbar button for compilation.asf) • Block diagram file (. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. A net list is a set of statements that specifies the elements of a circuit (for example. or EDIF objects declared within a selected region of the current design. 6. The structure of the design unit selected for simulation. Verilog. respectively for VHDL.

. including ModelSim Xilinx Edition and the HDL Bencher test bench generator. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.-59 . 5. This overview explains the general progression of a design through ISE from start to finish. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.2 Design Entry: • ISE Text Editor . DEPARTMENT OF ECE PAGE NO.6 SYNTHESIS TOOL: 5. and finally produce a bit stream for your device configuration. ISE enables you to start your design with any of a number of different source types. Verilog HDL.6.3.6.32-BIT FLOATING POINT PROCESSOR TEC Fig4.1: Simulation 5. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE. including: • HDL (VHDL.The ISE Text Editor is provided in ISE for entering design code and viewing reports. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.4.4.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.4.5.

• • • • 5. transitions. The state machine will be created in HDL. equations. transforms. places and routes the FPGA. With Timing Analyzer. macro cell details.-60 .The FPGA Editor allows you view and modify the physical implementation.The Floor planner allows you to view a graphical representation of the FPGA. FIFOs.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file.6. and actions in a graphical editor. DEPARTMENT OF ECE PAGE NO. Fit (CPLD only) .State CAD allows you to specify states. State CAD State Machine Editor . and produces output for the bit stream generator. view. Global logic.The Constraints Editor allows you to create and modify the most commonly used timing constraints.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O. Timing Analyzer . Constraints Editor . and memories.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor . and after fitting and routing a CPLD design. CORE Generator . to system-level building blocks such as filters. and pin assignments. Chip Viewer (CPLD only) . FPGA Editor .The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders.The Map program maps a logical design to a Xilinx FPGA.3 Implementation: • Translate . and to view and modify the placed design. Place and Route (PAR) .The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs.4. placing or routing an FPGA design. analysis can be performed immediately after mapping. and Area Group constraints. Map . including routing. • • • • • • • .The PAR program accepts the mapped design. Floor planner . PACE .The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow.The Chip Viewer tool provides a graphical view of the inputs and outputs.

iMPACT .6.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices. XPower .4.32-BIT FLOATING POINT PROCESSOR TEC 5. Integration with ChipScope Pro. • • • .-61 .The iMPACT tool generates various programming file formats.4 Device Download and Program File Formatting: • BitGen . DEPARTMENT OF ECE PAGE NO. and subsequently allows you to configure your device.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration.

.1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. multiplication and division are done using active HDL tool and the results are as follows: 6.-62 . DEPARTMENT OF ECE PAGE NO.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. subtraction. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form.

.2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format.2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6. DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form.-63 .32-BIT FLOATING POINT PROCESSOR TEC 6.

-64 .3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form.32-BIT FLOATING POINT PROCESSOR TEC 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . . DEPARTMENT OF ECE PAGE NO.3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format.

32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form. DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6. .-65 .4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format.

32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7.-66 . .2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. The Functional-simulation has been successfully carried out with the results matching with the expected ones. Basic arithmetic operations such as addition. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. • 7. • • Procedures for performing basic arithmetic operations are been formed. subtraction.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation. DEPARTMENT OF ECE PAGE NO.

but need to use only a small subset of the range for target acquisition and identification. The wide dynamic range of a floating-point DSP. DEPARTMENT OF ECE PAGE NO. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. however. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. x-rays. Normally. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions.-67 . feedback is well out of the ordinary operating range. The greater precision of signal data. Wide dynamic range also plays a part in robotic design. Many levels of signal input from light.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. the robot might weld itself to an assembly unit. In these cases. unpredictable events can occur on an assembly line. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. together with the device’s more accurate internal representations of data. However. For instance. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. Since the subset must be determined in real time during system operation. The radar system may be tracking in a range from 0 to infinity. enable imaging systems to achieve a much higher level of recognition and definition for the user. . or something might unexpectedly block its range of motion.

In: Stone.2007... W. Williams. S. 14(7) 68-78 REFERENCES www. H. In: 1986 FORML Conf. T. (Ed. Science Research Associates. 1975. pp. & Zaremba. M. P. 281-317 Yamamoto.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman.46 www. Prentice-Hall. (1987) The Implementation of Functional Programming Languages. R. 197-210 Jones. Chicago. July 1981. J.1109/SNPD. DEPARTMENT OF ECE PAGE NO. Pacific Grove CA.intel. (1986) A 32 bit processor architecture for direct execution of Forth. 28-30 November 1986.ieeexplore.org www.) Introduction to Computer Architecture. M.computer.org/portal/web/csdl/doi/10. Hayes. pp.. Proc. New York McKeeman.-68 .com . (1981) A survey of high-level language machines in Japan. (1975) Stack computers.ieee. Computer.

-69 . y : out std_logic_vector(31 downto 0) ). begin temp:=x. use IEEE.std_logic_unsigned.all. DEPARTMENT OF ECE PAGE NO.all.std_logic_1164. end Fadd.Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE.std_logic_arith.Compute Ea-Eb -2. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0). use IEEE. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc.Shift the that has lesser Exponent by Ea-Eb places to the right * -3. use IEEE.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1. variable Temp :Std_logic_vector(6 downto 0).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0. b : in std_logic_vector(31 downto 0).all. --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop .

end loop.Final Result begin MaIn:=Acc(22 downto 0).Sign Of Resultant Mantissa variable W. -. -. Es:=Eb(7) . variable X : std_logic_vector(31 downto 0). --***************************************************************** --*Equalization of Exponents includes two steps --*1. end if. -. else TEC Sum:=Sum. -. -. -.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. -. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)).Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn.Mb : std_logic_vector(22 downto 0).Subtraction of Exponents --*2.Resultant Mantissa variable IE : std_logic_vector(6 downto 0). MbIn:=Data(22 downto 0).Z : std_logic_vector(1 downto 0).Eb : std_logic_vector(7 downto 0). DEPARTMENT OF ECE PAGE NO.Sign Of Resulant Exponent variable a. Ma:=MaIn. a :=Acc(31). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). -. end function.Internal Register variable Ea.Internal Register variable MbIn : std_logic_vector(22 downto 0). -.Sign Of Two mantissas variable Sign : std_logic.-70 .s2 : std_logic.Resultant Exponent variable Ns : integer. -. -.Number Of Shifts variable Ma.Mangitude Of Two mantissas variable ES : std_logic.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0).Sign Of Two exponents variable s1. end loop. b :=Data(31). --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0). Z :=(a&b). -. Eb :=Data(30 downto 23). return sum. Ea :=Acc(30 downto 23).b : std_logic. IE:=Eb(6 downto 0).

IE:=IE. Ma:=MaIn. end loop. ES:=Eb(7). end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). .32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). IE:=Ea(6 downto 0). when "10" => Mb:=MbIn. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). DEPARTMENT OF ECE PAGE NO. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). Ma:=MaIn. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). Es:=Ea(7). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). IE:=Ea(6 downto 0). when "01" => Mb:=MbIn. Ma:=MaIn.-71 . Mb:=Mb. Ma:=Ma. IE:=Eb(6 downto 0). else NS:=Ns. end if. IE:=Ea(6 downto 0). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end loop. when "11" => Mb:=MbIn. ES:=Ea(7). end loop. ES:=Ea(7).

end if. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. if(Ea>Eb) then sign:='1'. case W is when "00" => when "11" => when "01" => when "10" => .-72 . Ma:=Ma. DEPARTMENT OF ECE sign:='0'. else NS:=Ns. --***********logic for the sign of the mantissa********************** s1:=Acc(31). end loop. elsif(Ma=Mb) then sign:='0'. elsif(Ea<Eb) then sign:='1'. end if. IE:=IE. end if.32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). s2:=Data(31). ES:=Ea(7). PAGE NO. IE:=Eb(6 downto 0). else sign:=sign. --******************Addition of Mantissas**************************** IR:=Ma+Mb. if(Ea>Eb) then sign:='0'. when others => Null. sign:='1'. Mb:=Mb. else sign:=sign. ES:=Eb(7). end case. elsif(Ma<Mb) then sign:='1'. W :=(s1&s2).

b). end process. elsif(Ma=Mb) then sign:='0'. else sign:=sign. DEPARTMENT OF ECE PAGE NO. when others => null. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. end if.-73 * . end if. elsif(Ma<Mb) then sign:='0'.b) begin y<=float_add(a. begin process(a.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. end function. end case. return X. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)). else sign:=sign. end Fadd.

-74 .std_logic_unsigned.std_logic_arith. DEPARTMENT OF ECE PAGE NO. y : out std_logic_vector(31 downto 0)). use ieee.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.all. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.std_logic_1164.all.Shift the that has lesser Exponent by Ea-Eb places to the right * 3. use ieee.Compute Ea-Eb 2. use IEEE. begin temp:=x. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). .all. b : in STD_LOGIC_VECTOR (31 downto 0). end Fsub.32-BIT FLOATING POINT PROCESSOR ----1. variable Temp : Std_logic_vector(6 downto 0).

-.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Sign Of Resultant Mantissa variable W. end loop. MbIn:=Data(22 downto 0).s2 : std_logic. -.Sign Of Resulant Exponent variable a.Z : std_logic_vector(1 downto 0). end function. variable X : std_logic_vector(31 downto 0). DEPARTMENT OF ECE PAGE NO. -. Eb :=Data(30 downto 23).Eb : std_logic_vector(7 downto 0). a :=Accout(30). end if.Mangitude Of Two Mantissas variable ES : std_logic.Mb : std_logic_vector(22 downto 0). --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. -.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). Ea :=Accout(30 downto 23). b :=Data(30). -.-75 .MbIn: std_logic_vector(22 downto 0). --*********************variable Declarations*********************** TEC variable MaIn. -. -. -.Sign Of Two Exponents variable s1. else Sum:=Sum.32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i. -. return sum.Final Result begin MaIn:=Accout(22 downto 0).b : std_logic.Number Of Shifts variable Ma.Internal Register variable Ea. -.Resultant Exponent variable Ns : integer.Sign Of Two Mantissas variable sign : std_logic.Subtraction of Exponents * * . Z :=(a&b). -.

IE:=IE. Ma:=Ma. IE:=Ea(6 downto 0). when "01" => Mb:=MbIn. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)).-76 . for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). end loop. end if. ES:=Ea(7).32-BIT FLOATING POINT PROCESSOR --*2. Mb:=Mb. Ma:=MaIn. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=Eb(6 downto 0). end loop. TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end loop. DEPARTMENT OF ECE PAGE NO. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Eb(7). Ma:=MaIn. ES:=Ea(7).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. else NS:=Ns. ES:=Ea(7). IE:=Ea(6 downto 0). .

end loop. DEPARTMENT OF ECE PAGE NO. Ma:=MaIn. IE:=IE. ES:=Eb(7). IE:=Eb(6 downto 0). TEC Ma:=MaIn. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). else NS:=Ns. end loop. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Eb(7). ES:=Ea(7). end if. . for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Mb:=Mb.-77 . ES:=Ea(7). end case. IE:=Ea(6 downto 0). when others => null. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). when "11" => Mb:=MbIn.32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). Ma:=Ma. IE:=Eb(6 downto 0). end loop. --******************Subtraction of Mantissas************************ IR:=Ma-Mb.

elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. when "01"=> if(Ea>Eb)then sign:='0'. elsif (Ea<Eb) then sign:='0'. else sign:=sign. else sign:=sign. elsif (Ma=Mb) then sign:='0'.32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). when "11"=> sign:='1'. else sign:=sign. end if.-78 . W:=(s1&s2). end if. else sign:=sign. elsif(Ma<Mb) then sign:='1'. elsif(Ma<Mb) then sign:='0'. . elsif (Ma=Mb) then sign:='0'. end if. end if. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. DEPARTMENT OF ECE PAGE NO. case W is when "00"=> sign:='0'. when "10"=> if (Ea>Eb)then sign:='1'. s2:=Data(31). elsif(Ea<Eb) then sign:='1'.

-79 .all. end process. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)). end function. begin process(a. y: out STD_LOGIC_VECTOR (31 downto 0) ).std_logic_1164.b).std_logic_unsigned.Multiplication of the Mantissas * * -************************************************************************** library IEEE.all. . --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0). end f_sub. return X. use IEEE. b: in STD_LOGIC_VECTOR (31 downto 0). end Fmul. use IEEE.32-BIT FLOATING POINT PROCESSOR TEC when others=> null. end case.Addtion of the Exponents 5. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1.b) begin y<=float_sub(a. DEPARTMENT OF ECE PAGE NO.

s2:=Data(31). -. when "11" => s:='0'.Magnitude Of Two Exponents variable c : std_logic.sign Two Mantissas variable Ea.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0). -. -. m2 :=Data(10 downto 0). -. DEPARTMENT OF ECE PAGE NO. e2 :=Data(30 downto 23). -. case Z is when "00" => s:='0'.Sign Two Exponents variable s1.Resultant exponent variable m : std_logic_vector(21 downto 0).s2 : std_logic.Eb : std_logic_vector(6 downto 0). -.Final Result begin Carry:='0'.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout. -.Z : std_logic_vector(1 downto 0). e1 :=Accout(30 downto 23).Two Exponents Icluding Sign variable m1.m2 : std_logic_vector(10 downto 0).e2 : std_logic_vector(7 downto 0). -.Resultant Mantissa variable carry : std_logic. -. --************logic for the sign of the Mantissa******************* s1:=Accout(31).-80 . -. Z :=(s1&s2).Carry variable W.Sign Of Resultant Mantissa variable a. variable x : std_logic_vector(31 downto 0).Magnitude O Two Mantissas variable s : std_logic. -. end case. m1 :=Accout(10 downto 0).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. .b : std_logic. when others=> s:='1'.

elsif(Ea<Eb) then c:='0'. e:=Eb-Ea. e:=Eb-Ea.-81 . end if. end if.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). b :=Data(30). e:=Ea+Eb. c:='1'. when "11" => when others => null. else c:='0'. e:=Ea-Eb. --*************logic for multiplication************************* m:=m1*m2. e:="0000000". DEPARTMENT OF ECE PAGE NO. case W is when "00" => c:='0'. e:="0000000". else c:='0'. W :=(a&b). Eb:=e2(6 downto 0). a :=Accout(30). e:=Ea-Eb. . when "01" => if(Ea>Eb) then c:='0'. end case. elsif(Ea<Eb) then c:='1'. e:=Ea+Eb. when "10" => if(Ea>Eb) then c:='1'.

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

if(Ea>Eb) then c:='0'. elsif(Ea<Eb) then c:='0'. . elsif(Ea<Eb) then c:='0'. e:=Eb-Ea. e:=Ea-Eb. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. elsif(Ea<Eb) then c:='1'.-86 . e:="0000000". Eb:=e2(6 downto 0). when "10"=> if(Ea>Eb) then c:='1'. else c:='0'. b :=e2(7).32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). e:=Ea+Eb. e:="0000000". e:=Eb-Ea. end if. else c:='0'. e:=Ea-Eb. if(Ea>Eb) then c:='1'. end if. else c:='0'. elsif(Ea<Eb) then c:='0'. a :=e1(7). case Z is when "00" => if(Ea>Eb) then c:='0'. e:="0000000". e:=Eb+Ea. e:=Ea+Eb. Z :=(a&b). end if.

begin process(a. TEC . else c:='0'. return X. end case. e:="0000000". --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). when others=> null.b). DEPARTMENT OF ECE PAGE NO. end if.-87 . end process.32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. end F_div. end function.b) begin Y<=float_div(a.

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