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TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

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32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

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32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

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Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits.-5 .) to plus infinity (+ ). As shown at the bottom of Figure 1.1: Binary Real Number System Because the size and number of registers that any computer can have is limited. DEPARTMENT OF ECE PAGE NO. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. only a subset of the real-number continuum can be used in real-number calculations.1. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations. Figure 2. . As shown in Figure 1. the real-number system comprises the continuum of real numbers from minus infinity (.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2.

designers can identify the DSP that is best suited for an application. from -32. 2. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. processor and system costs. and ease of development.2. fixed point and floating point.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data.535. Balancing these factors together. the digit string can be of any length.536 levels are spread uniformly between 0 and 1. With unsigned fraction notation. the stored number can take on any integer value from 0 to 65. In common mathematical notation. Digital Signal Processing can be divided into two categories. the number is an integer).768 to 32. Among the key factors to consider are the computational capabilities required for the application. some specific assumption is made about where the radix point is located in the string. low-cost development tools. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications.-6 . DEPARTMENT OF ECE PAGE NO. Fixed point DSPs usually represent each number with a minimum of 16 bits. There are four common ways that these 216 ' 65. Software programmable for maximum flexibility and supported by easy-touse. Lastly. while floating-point DSPs support either integer or real arithmetic.536 possible bit patterns can represent a number. DSPs enable designers to build innovative features and differentiating value into their products. signed integer uses two's complement to make the range include negative numbers. Similarly. but decimal fixed point is common in commercial applications.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. the signed fraction format allows . Fixed-point Vs floating-point in digital signal processing Fig 2. For instance. In fixed-point systems. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. These refer to the format used to store and manipulate numbers within the devices. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is.767. In unsigned integer. Motorola manufactures a family of fixed point DSPs that use 24 bits. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. the 65. although a different length can be used. performance attributes.

It is measured in” FLOPS”.967. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. loops. The speed of floating-point operations is an important measure of performance for computers in many application domains. Floating point A floating-point number is the one. which is capable of representing real and decimal numbers. it can be placed anywhere relative to the significant digits of the number. This is known as the significand. floating point DSPs typically use a minimum of 32 bits to store each value.754-1985). The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. the largest and smallest numbers are ±3. but small gaps between small numbers. All floating point DSPs can also handle fixed point numbers.296 to be exact. DEPARTMENT OF ECE PAGE NO. respectively. that is. it depends on the internal architecture. The radix point is not explicitly included.3. the SHARC devices are often referred to as "32-bit DSPs. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). This results in many more bit patterns than for fixed point. and signals coming from the ADC and going to the DAC.-7 .4 ×1038 and ±1. A key feature of floating point notation is that the represented numbers are not uniformly spaced. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . In the most common format (ANSI/IEEE Std. The term” floating point” refers to the fact that the radix point can "float". such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. 2. and floating-point representation can thus be thought of as a computer realization of scientific notation. a necessity to implement counters. For this reason. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. and executes them with equal efficiency. For instance. the SHARC DSPs are optimized for both floating point and fixed point operations.2 ×1038. 2324.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. This position is indicated separately in the internal representation.4." rather than just "Floating Point." 2. The floating-point operations are incorporated into the design as functions. The represented values are unequally spaced between these two extremes.294.In comparison.However. This is important because it places large gaps between large numbers. equally spaced between -1 and 1. or sometimes the mantissa (see below) or coefficient. The logic for these is different from the ordinary arithmetic functions. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations.

The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. and e is the exponent. or to the right of the rightmost digit. The significand is multiplied by the base raised to the power of the exponent. computers used many different forms of floating-point. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. DEPARTMENT OF ECE PAGE NO. also referred to as the characteristic or scale. so when stored in the same space. Symbolically. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. The length of the significand determines the precision to which numbers can be represented. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. Prior to the IEEE-754 standard.Fraction. which modifies the magnitude of the number. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent.32-BIT FLOATING POINT PROCESSOR TEC significant digit.-8 . floating-point numbers achieve their greater range at the expense of precision. composed as integer. 10 or 16. A signed integer exponent. b is the base. with an average error of about 3%. this final value is where s is the value of the significand (after taking into account the implied radix point). the format of the representations.5. The floating-point format needs slightly more storage (to encode the position of the radix point). These differing systems implemented different parts of the arithmetic in hardware and software. These differed in the word sizes. 1 for negative values. Significand is a real number. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. and the rounding behaviour of operations. (This is because the exponent field is in . 2.

The Exponent: The exponent field needs to represent both positive and negative exponents. such as volume ramping in digital sound processing. To do this. also known as the significand. or 1023 plus the true exponent for double precision. So. The first bit of the mantissa is typically assumed to be 1. and the mantissa. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. to sum up: 1. The Sign Bit: The sign bit is as simple as it gets. A float is represented using 32 bits.f. a bias is added to the actual exponent in order to get the stored exponent. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. It is composed of an implicit leading bit and the fraction bits. The exponent's base is two. 1 denotes a negative number. The exponent field contains 127 plus the true exponent for single-precision. even though there are infinitely many real numbers (even between 0 and 1). 4. The sign bit is 0 for positive. 1 for negative. 0 denotes a positive number. This means that at most 232 possible real numbers can be exactly represented. Flipping the value of this bit flips the sign of the number. DEPARTMENT OF ECE . There are many formats that are used for representation of floating point number. the exponent. 3.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign.) This can be exploited in some applications. 2. where f is the field of fraction bits. and each possible combination of bits represents one real number.-9 . The Mantissa: The mantissa. IEEE-754 specifies binary representations for floating point numbers: Table 2. represents the precision bits of the number.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum.

Table 2. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude. which may be represented as numbered from 0 to 31.-10 .5. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. then V=NaN ("Not a number") If E=255 and F is zero and S is 1.5.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2.1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010).5. S. left to right. then V=Infinity . IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. the next eight bits are the exponent bits. then V=-Infinity If E=255 and F is zero and S is 0. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). 'E'.

00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1. then V=0 In particular. then V=(-1)**S * 2 ** (-126) * (0.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.101 = -6.101 = 6.-11 .5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.F) These are "unnormalized" values. then V=-0 If E=0 and F is zero and S is 0.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.0 The biased exponent is . 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0. If E=0 and F is zero and S is 1.3125 The biased exponent is -2+127=125= (01111101 • 1. If E=0 and F is nonzero. DEPARTMENT OF ECE PAGE NO.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.F) where "1.

25 The biased exponent: 127+6=133=(10000101 • -1313.8125 .5 × 2 = 0.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0.32-BIT FLOATING POINT PROCESSOR TEC • 37.0 0 1 0 1 1313.8125 × 2 = 1.5 × 2 = 1.25 0. • -78. DEPARTMENT OF ECE PAGE NO.203125 0.-12 .25 × 2 = 0.40625 × 2 = 0.40625 0.625 × 2 = 1.203125 × 2 = 0.3125 131310 = 101001000012 0.1015625 × 2 = 0. 10 + 127 = 137 = 100010012.3125 is • 0.5 The based exponent: 127+5= (10000100 .010010000101012 × 210.312510 = 10100100001. .625 0.01012.1015625 0.3125 0. sign bit is 1. = 1. So -1313.

The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero. DEPARTMENT OF ECE .1015625 is 0 00111101 110100000000000000000000 TEC 2. the next eleven bits are the exponent bits.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.5 × 2 = 1.-13 .25 1 × 2 = 0.5.3. left to right.0 1 0.625 0. then V=NaN ("Not a number") PAGE NO.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0.00011012 = 1. which may be represented as numbered from 0 to 63. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.32-BIT FLOATING POINT PROCESSOR 0.101562510 = 0. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001). 'E'.25 0. S.5 0 × 2 = 1. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0). The number of bits for each field are shown (bit ranges are in square brackets): Table 2. The first bit is the sign bit.5.

DEPARTMENT OF ECE PAGE NO. 15 exponent bits and 112 significand bits. Table 2. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit . Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2. then V=-0 If E=0 and F is zero and S is 0. while maintaining good precision. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa).5.53 ~ 10308. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. then V=-Infinity If E=2047 and F is zero and S is 0. . floating-point notation allows calculations over a wide range of magnitudes.F) These are "unnormalized" values.-14 .32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. If E=0 and F is zero and S is 1. If E=0 and F is nonzero.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable.6.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038.F) where "1. using a fixed number of digits. then V=(-1)**S * 2 ** (-1022) * (0.

and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1). and the smallest possible value for the exponent. DEPARTMENT OF ECE PAGE NO. P is the precision of the system to P numbers. There is a largest floating point number. Zero 4. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2.85 to ~1038. P. U) (where B is the base of the system. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent.6. The number of normalized floating point numbers in a system F(B.3 to ~10308.2: Effective Range of IEEE Floating Point Number with Denormalized. Positive numbers less than 2-149 (positive underflow) .53 ~10-323. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand. There is a smallest positive normalized floating-point number.32-BIT FLOATING POINT PROCESSOR TEC Table 2. the range for negative numbers is given by the negation of the above values.-15 . Negative numbers greater than -2-149 (negative underflow) 3. Approximate Decimal 2127 21023 ~10-44. L. L is the smallest exponent represent able in the system. Normalized And Approximate Decimal Values.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit.

It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. 2. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . Recently. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. Underflow occurs when the sum of the exponents is more negative than -126. 2. the most negative value which is defined in bias-127 exponent representation.32-BIT FLOATING POINT PROCESSOR 5. the exponent is set to -127 (E = 0). Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. When this occurs.-16 . the number is exactly zero.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . the largest value which is defined in bias-127 exponent representation. When this occurs.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. DEPARTMENT OF ECE PAGE NO. If M = 0.infinity. However the CPU will have to perform extra arithmetic to read the number when stored in this format.

1.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. let us consider two numbers a= 2.. Normalize the result. i. . Now as both the exponent values are same. Multiplication 4. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded.25x and b= 1.-17 . both the numbers are added. But by using floating point addition this can be avoided to a little extent. Division 2. Addition 2. They are: 1. DEPARTMENT OF ECE PAGE NO.e. Subtraction 3. Add the numbers with decimal points aligned. as the smaller number here is a=2.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points.8. Hence the value of number ‘a’ becomes 0.0225x .. For example. Floating point addition is analogous to addition using scientific notation.

ExpB as exponent of number B and ManB as mantissa of number B.e. 2.1. DEPARTMENT OF ECE PAGE NO.00000009876543 x 2. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. If the numbers are represented with both positive and negative sign. 2.234567x and b= 9. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. then the following result may occur: 1. a =1.8.876543x and if the addition has to be performed.2345670 x in which the remaining part (9876543) which is discarded also carries the result. then bit 1 is represented for sign.8.-18 .234567x b= 0.. But the normalised result may sometimes carry the required result.8. ExpA as exponent of number A . signB as sign of number B. Now both the numbers are added.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part. b= 9.876543x after shifting becomes b= 0. then sign of greater number is considered.e.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: .2. Thus this case can said to be having rounding errors.1. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.00000009876543 x c= 1.1.1. Consider a example in which a =1. i. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2.. The mantissa of both numbers A and B are added. ManA as mantissa of number A.

4. 6. exception is made. the numbers are represented in IEEE floating point format.1.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. If not.2: Flow Chart for Floating Point Adder. the exponent sum would have doubled the bias.-19 . If the exponents are stored in biased form. the significand is rounded to the appropriate number of bits required and again normalization is checked. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. Thus. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. If there is an underflow or overflow.8. 1. 2. 5. . Firstly. the bias value must be subtracted from the sum 3. Addition of significands is done. DEPARTMENT OF ECE PAGE NO.

DEPARTMENT OF ECE PAGE NO. the result is converted back to signmagnitude form. Subtraction .340625x . cancellation may occur. If the sum overflows the position of the hidden bit. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. resulting in a large loss of accuracy.32-BIT FLOATING POINT PROCESSOR TEC 7. The mantissa is always less than 2. When adding numbers of opposite sign. resulting in a sum which is arbitrarily small.2. Normalization in this case may require shifting by the total number of bits in the mantissa. After the addition is performed.25 becomes: The mantissas are added using integer addition: The result is already in normal form. Thus. 2. Consider addition of the numbers 2. so the hidden bits can sum to no more than 3 (11). The number 2.-20 . or even zero if the numbers are equal in magnitude.25x and 1.25 in IEEE Floating Point Standard is: The number 134.8. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. then the mantissa must be shifted one bit to the right and the exponent incremented.0625 in IEEE Floating Point Standard is: To align the binary points. 2. Negative mantissas are handled by first converting to 2's complement and then performing the addition.

e. DEPARTMENT OF ECE PAGE NO. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if .0225x .2. ExpA as exponent of number A . ManA as mantissa of number A. The normalised result may contain the required number of digits discarding the unwanted part. as the smaller number here is a=2.1. 2.25x and b= 1.1.340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal.e. Normalize the result. Now as both the exponent values are same. then sign is represented according to the number i. Subtract the numbers with decimal points aligned. Hence the value of number ‘a’ becomes 0. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.8..-21 .8. signB as sign of number B.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2.. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2. The mantissa of both numbers A and B are subtracted. both the numbers are added. ExpB as exponent of number B and ManB as mantissa of number B. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. i..1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .2.

2.2. the bias value must be subtracted from the sum 3. 2.-22 . 4. the exponent sum would have doubled the bias.8. Consider subtraction of the numbers 2.340625x . Thus. 6.25 become: The mantissas are subtracted using integer subtraction: . exception is made. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. 2. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. Subtraction of significands is done.0625 in IEEE Floating Point Standard is: To align the binary points. 2. the significand is rounded to the appropriate number of bits required and again normalization is checked. Thus. If the exponents are stored in biased form. The number 2. If not. The numbers are represented in IEEE floating point format. If there is an underflow or overflow. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. 5.25x and 1.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign.25 in IEEE Floating Point Standard is: The number 134. DEPARTMENT OF ECE PAGE NO.

DEPARTMENT OF ECE PAGE NO. consider two numbers X and Y and the resultant be Z. If the exponents are same. At this point. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent . then the following steps can be followed: Exponents of both the numbers are checked. Z=Y.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form.8.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. If the significand is zero then it is returned if not significand overflow is checked. then the significands of numbers X and Y are subtracted.8. In the first step. If overflow occurs. If both the numbers X and Y are non zeros.3. then the mantissa must be shifted one bit to the right and the exponent incremented. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. If overflow occurred then overflow is reported and returned.2. then number Y is checked. If it is ‘0’. Flow chart for floating point subtraction: Subtract significand si Fig 2. If not then the result is normalized.. number X is checked. then the result would be Z=X.e. If number X is not ‘0’.-23 . If the sum overflows the position of the hidden bit. If it is ‘0’ then the resultant solution Z would be Y i.2. 2.

8. to multiply 1.5x : Perform unsigned integer multiplication of the mantissas. if the significand is not zero then subtraction and further process is carried out. 2. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers. 1.1.8.3. The number 18.5 in IEEE FPS format is: . If underflow occurred then it is reported if not the normalized result is given out. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.5 ----17.8 x 9. DEPARTMENT OF ECE PAGE NO.8x times 9.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result.0 in IEEE FPS format is: The number 9. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign. 2. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z. For example.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked.-24 . If the exponents are not same.3.

the mantissa is: The biased-127 exponents are added. the result is: 2. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form. the mantissa must be shifted right and the exponent incremented.3.-25 .8.2. The sign of the result is the xor of the sign bits of the two numbers. Block diagram of floating point multiplication: . If the position of the hidden bit overflows.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in (). When the fields are assembled in IEEE FPS format. DEPARTMENT OF ECE PAGE NO.

.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . the exponent sum would have doubled the bias.3. If both the numbers X and Y are not zero.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.8. The exponents of both the numbers are added and subtracted from the bias 127. DEPARTMENT OF ECE PAGE NO. signB as sign of number B.3.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. then the exponents are added and a bias of 127 is subtracted from the result. expA as exponent of number A . the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. XOR operation for sign bit can be given as follows: Table 2. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard.3. expB as exponent of number B and manB as mantissa of number B.-26 . number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero.8. If the exponents are stored in biased form.8. Thus.3. At the first step. The mantissa of both numbers A and B are multiplied. Resultant mantissa is truncated and normalized to fit for the IEEE format. Sign of the result is given by performing xor operation of signA and signB. manA as mantissa of number A.

8. i.5..3. Hence the result can be given as 1. Fig 2. Division Consider an example of dividing a=0.e.5.2 =1. . The resultant sign bit would be the xor operation of sign bits of X and Y.3 and b= 0.5 .3 0.4.2 . So resultant exponent would be 2-3=-1.8. DEPARTMENT OF ECE PAGE NO. 0.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned. When the division of both significands are done then the quotient would be 1. 2. Exponent of a is 2 and exponent of b is 3. in general floating point division the exponents of both the numbers are subtracted and the significands are divided.3: Flow Chart For Floating Point Multiplication.-27 .

1.4. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend. DEPARTMENT OF ECE PAGE NO.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .-28 . ManA as mantissa of number A. 2. ExpA as exponent of number A . If anyone number of the two are negative. In the first step. Subtract the exponent of the divisor from the exponent of the dividend.8. The mantissa of both numbers A and B are divided.8. then the result is also negative is represented by bit ‘1’. Set the sign of the result.4. Special . If both the numbers are either positive or negative. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. When divided by a 24 bit divisor.8.4. then the resultant sign is also positive and is represented by bit ‘0’. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement.32-BIT FLOATING POINT PROCESSOR TEC 2. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. ExpB as exponent of number B and ManB as mantissa of number B. The exponents are subtracted and biased using the bias value. a 24 bit quotient is produced. Block diagram for floating point division: Fig 2. signB as sign of number B. As in floating point multiplication. Normalize the result.

. 2. in this case as larger number has to be subtracted from smaller number. Number X and Y are checked.2 can be represented as M 010000001(0)11000000000000000000000 0. For this.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow.3 S E and b= 0.8. Considering a=0. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity .-29 . Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked.3 0. or NaN.Then the steps that occur are: 1. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned.3.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted. This value is called Not A Number. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero. DEPARTMENT OF ECE PAGE NO.4. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2.

Fig 2.g.9.-30 . If they are present.200 is less than . digits may flow off the right end of the significand.8. As we shall discuss. DEPARTMENT OF ECE PAGE NO. this may be designated as +∞ or -∞. then those conditions are reported. 2. and it may be reported as 0. In some systems.This means that the number is too small to be represented. some form of rounding is required. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e.32-BIT FLOATING POINT PROCESSOR TEC 3. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit.. . If not the mantissas are divided and truncated and normalized result is given out.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value.4. • Significand underflow: In the process of aligning significands. Rounding Error In floating point arithmetic. rounding errors occur as a result of the limited precision of the mantissa .127).

The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. RZ: Round toward Zero. For numbers in IEEE FPS format. the relative error is approximately since For denormalized numbers (E = 0). RM: Round toward minus infinity. The size of the absolute error is proportional to the magnitude of the number. RN is generally preferred and introduces less systematic error than the other rules. highest precision can be achieved. relative errors increase as the magnitude of the number decreases toward zero. Same as truncation in 2's complement. . RP: Round toward Positive infinity. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. However. DEPARTMENT OF ECE PAGE NO. For normalized floating point numbers.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. Normalization By normalization. The value can be kept unchanged by adjusting the exponent accordingly. The least significant 24 bits are discarded. Same as truncation in sign-magnitude. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. To efficiently use the bits available for the significand. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision).-31 .10. Break ties by choosing the least significant bit = 0.

Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit.g. resulting 1. extra guard bits are kept during operation. By the end of the operation. The actual value represented is However.32-BIT FLOATING POINT PROCESSOR TEC Moreover. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. If we assume number. all extra bits during operation (called guard bits) are kept (e.. it does not need to be shown explicitly. as the MSB of the significand is always 1. a 4-bit exponent field and a 9-bit significand field): 2. to avoid possible confusion. bits are used in final representation of a bits by one of the three methods. multiplication). DEPARTMENT OF ECE PAGE NO. The first bit 1 before the decimal point is implicit. in the following the default normalization does not assume this implicit 1 unless otherwise specified. Truncation To retain maximum accuracy.-32 . the bits need to be truncated to guard bit Chopping: simply drop all .11. Zero is represented by all 0's and is not (and cannot be) normalized.

. we say this truncation error is biased. Two worst cases Both two cases can be summarized as i. is always greater than 0. add 1 to LSB . (no matter Von Neumann Rounding: If at least one of the guard bits is 1. DEPARTMENT OF ECE PAGE NO.e..5 round up. otherwise do nothing. Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. set whether it is originally 0 or 1). the Von Neumann rounding error is unbiased. Interpretation: Value represented by guard bits is greater than 0. .-33 .32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. 3.

32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0.-34 . . round up: Interpretation: Value represented by guard bits is 0.5 either up or down with equal probability (50%). the rounding depends on the LSB : if . round down: or if . it is randomly rounded . c) If the highest guard bit is 1 and the rest guard bits are all 0. The rounding error of these cases can summarized as . drop all guard bits. DEPARTMENT OF ECE PAGE NO.5 round down. Interpretation: Value represented by guard bits is smaller than 0.

The next eight bits are that of the exponent. The MSB is the sign-bit i. The above representation is the IEEE-784 1985 standard representation.e.e.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . The floating-point operations are incorporated into the design as functions.3 Floating Point Functions A floating-point number is the one.-35 . multiplication and division is presented in the following pages. which is capable of representing real and decimal numbers. Positive numbers are represented by binary values greater than 0111. DEPARTMENT OF ECE PAGE NO. 1985 floating point standard representation before any sort of operations are conducted on them. 1111. the sign of the floating point number. The logic for floating point addition. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number. I. The exponent in this IEEE standard is represented in excess-127 format. The numbers in contention have to be first converted into the standard IEEE 784. Therefore zero is represented by 0111. . 1111. The logic for these is different from the ordinary arithmetic functions. the exponent obtained by balancing operations is added to 0111. subtraction. 1111 and negative numbers are represented by binary values less than it.

Once the exponents are normalized. • • . The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately.32-BIT FLOATING POINT PROCESSOR TEC 3. These numbers are distinct. This is done till the lower exponent becomes equal to the higher one. So to add their mantissa’s. These numbers are stored into the memory from which they are read and processed. The mantissas are then added to each other and the result is then stored in a temporary register. DEPARTMENT OF ECE PAGE NO. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. namely Accumulator and the Temp register that loads the value appearing on the data bus. So.-36 . we have to first normalize their exponents. Now the numbers from the memory are loaded into two registers.

Now the numbers from the memory are loaded into two registers. . Once the exponents are normalized. So to add their mantissa’s.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. This is done till the lower exponent becomes equal to the higher one. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately.-37 . The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. we have to first normalize their exponents. So. DEPARTMENT OF ECE PAGE NO. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. These numbers are stored into the memory from which they are read and processed. The mantissas are then subtracted and the result is stored in a temporary register. namely Accumulator and the Temp register that loads the value appearing on the data bus. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. These numbers are distinct.32-BIT FLOATING POINT PROCESSOR 3.

the resulting exponent and the sign of the result that is calculated separately. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. There is however a limitation to this operation. The final output is obtained by concatenating the product of the mantissas. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result.-38 . so that the result is restricted to not more than 24-bits. • • • . So each input should not exceed 12-bits in length.32-BIT FLOATING POINT PROCESSOR TEC 3. DEPARTMENT OF ECE PAGE NO. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized.

Now both the numbers in the IEEE-784 standard format are compared. we put a zero in the quotient.-39 . The convention here is that the Numerator should be always less than the denominator. Apart from that the final sign of the division is calculated separately. We initiate a counter and carry this process for 24 times. we append it with the exponent value and the Sign of the division that are calculated separately.32-BIT FLOATING POINT PROCESSOR TEC 3.4 Floating Point Division • • • • This is more complicated then Multiplication. Once the quotient is full. The decimal is assumed to be before the MSB of the resulting quotient. if the MSB or the 49th bit is one than we add a one in the quotient. The result is stored in Temp. The logic for floating point division is as follows. till the quotient is full. Now since the greater of the two numbers is decided. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. This is to ensure that whatever comes as the result is after the decimal point. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. Now the first 24-bits from the MSB are compared with the divisor. • • • • • . First the exponents are directly added or subtracted depending on which is bigger. DEPARTMENT OF ECE PAGE NO. And if it is zero.

data is temporarily stored in small.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. meaning a multiple of the motherboard frequency. DSPs can perform the mathematical calculations needed in digital signal processing. DEPARTMENT OF ECE PAGE NO. competitive position. engineering and digital signal processing. The basic task is to store the information. When this code is detected. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). Computers are extremely capable in two broad areas 1. the overall number of registers can vary from about ten to many hundreds. etc). Clock frequency is generally a multiple of the system frequency. the program moves the data from . Consider another example of how a document is printed from a word processor. When the processor executes instructions.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. Data manipulation such as word processing and database management 2. and testing for inequalities (A=B. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. finding use in everything from cellular telephones to advanced scientific instruments. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. and so on.-40 . All microprocessors can perform both tasks. such as the size of the instruction set and how it interrupts are handled. 4. the processor performs an action that corresponds to an instruction or a part thereof. consider a word processing program. Depending on the type of processor. These devices have seen tremendous growth in the last decade.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. For instance. 32 or 64 bits called registers. corresponds to the number of pulses per second. 16. local memory locations of 8. product life time. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. however it is difficult or expensive to make a device that is optimized for both. A<B . written in Hertz (Hz). A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. These tasks are accomplished by moving data from one location to another. The clock speed (also called cycle). There are technical tradeoffs in the hardware design. Data manipulations involve storing and sorting information. With each clock peak. Mathematical calculation used in science. There are marketing issues involved: development and manufacturing cost.

An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: . While mathematics is occasionally used in this type of application.. The task is to calculate the sample at location n in the output signal.. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required..32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. In comparison.. For example. i.....-41 .. . depending on the application. This is simply saying that the input signal has been convolved with a filter kernel consisting of: . the math operations dominate the execution time. it is infrequent and does not significantly affect the overall execution speed. the input signal is referred to by x [ ]. the most common DSP technique... consider the implementation of an FIR digital filter.e.. while the output signal is denoted by y [ ]. Using standard notation. such as to keep track of the intermediate results and control the loops. While there is some data transfer and inequality evaluation in this algorithm. DEPARTMENT OF ECE PAGE NO. there may only be a few coefficients in the filter kernel. y[n].

The key point in off-line processing is that all of the information is simultaneously available to the processing program. After shaking is over.. In FIR filtering . 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. with the advent of very fast floating point processing hardware. each sample in the output signal . For example. The disadvantages of 32-bit processors are cost and system complexity. x[n]..by the filter kernel coefficients.1: Graphical representation of FIR digital filter design. There are a few reasons for why to not to make it faster than necessary because as speed increases. a geophysicist might use a seismometer to record the ground movement during the earthquake. If the digital signal is being received at 20. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. whereas 32-bit processors are naturally suited to the size of the data elements. You simply wait for the action to be completed before you give the computer its next assignment In comparison.32-BIT FLOATING POINT PROCESSOR TEC Fig4.2. For instance. is found by multiplying samples from the input signal. the traditional speed advantage of integer operations over floating point operations is decreasing. . This is common in scientific research and engineering. design difficulty and so on. not having a defined start or end. 4. Floating point calculations also require a 32-bit processor for good efficiency. Difference between off-line processing and real time processing: In off-line processing. DEPARTMENT OF ECE PAGE NO.000 samples per second. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. If suppose you are launching your desktop computer on some task . There is less room on-chip for extra features such as hardware multipliers. say. However. the entire input signal resides in the computer at the same time. the information may be read into a computer and analysed in some way. power consumption. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors. but these items will appear as chip fabrication technology gets denser. Digital signal processors are designed to quickly carry out FIR filters and similar techniques. Off-line processing is a realm of personal computers and mainframes. . so as the cost . floating point math must often be used to reduce the cost of programming a project. most DSPs are used in applications where the processing is continuous. the DSP must be able to maintain a sustained throughput of 20.. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. Hence execution time is critical for selecting the proper device. and summing the products..x[n-2].3.y[n]. In these cases a 16-bit processor may suffice.-42 . converting a word processing document from one form to another. In addition to performing mathematical calculations very rapidly. consider a designing of an audio signal in DSP system such as a hearing aid.x[n-1].000 samples per second. as well as the algorithms that can be applied. DSPs must also have a predictable execution time. and to support code written in high level languages. Also..

For example. For example. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. they may input a group of samples perform the algorithm and output a group of samples. such as samples from the input signal and filter coefficients as well as program instructions. Harvard Architecture. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. Harvard architecture has separate memories for data and program instructions. The SHARC DSPs provides both serial and parallel communications ports. while six parallel ports each provide a 40 Mbytes/second data transfer.4. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. hearing aids and radar. the data transfer rate is an incredible 240Mbytes/second. perform the algorithm and output a sample. DEPARTMENT OF ECE PAGE NO. When all six parallel ports are used together. this is needed in telephone communication. while keeping the input signal in data memory. 4. the output signal is produced at the same time that the input signal is acquired. with separate buses for each. When two numbers are multiplied.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. we might place the filter coefficients in program memory. Real time applications input a sample. Likewise. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. For instance. two binary values (the numbers) must be passed over the data memory bus. Different architectures available are: Von Neumann Architecture. Since the buses operate independently. These are extremely high speed connections. the binary codes that go into the program sequencer. there are two serial ports that operate at 40 Mbits/second each.-43 . program instructions and data can be fetched at the same time. and an I/O controller. Alternatively. To improve upon this situation. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). while only one binary value (the program instruction) is passed over the program memory bus. two areas are important enough to be included are an instruction cache. Most of the computers are using this architecture today. . we start by relocating part of the "data" to program memory. improving the speed over the single bus design. Super Harvard Architecture (SHARC). This includes data. For instance. This is the world of digital signal processors. While the SHARC DSPs are optimized in dozens of ways. Most present day DSPs use this dual bus architecture. The basis of Harvard design is that the data memory bus is busier than the program memory bus. over and over. at a 40 MHz clock speed.

4. such as instructions. a feature called mixed signal. This means that the same set of program instructions will continually pass from program memory to the CPU. In comparison. this efficient transfer of data is called a high memory-access bandwidth. providing higher speed. all DSPs can interface with external converters through serial or parallel ports. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. and the program instruction comes from the instruction cache.-44 . However. In the jargon of the field. the Harvard architecture uses separate memories for data and instructions. Some DSPs have on-board analog-to-digital and digital-toanalog converters. the coefficient comes over the program memory bus. providing an additional interface to off-chip memory and peripherals. The first time through a loop. This allows . the program instructions must be passed over the program memory bus. DEPARTMENT OF ECE PAGE NO. DSP algorithms generally spend most of their execution time in loops. the program instructions can be pulled from the instruction cache. on additional executions of the loop. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. This is a small memory that contains about 32 of the most recent program instructions. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. However. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path.

The multiplier takes the values from two registers. Compare this architecture with the tasks needed to implement an FIR filter. subtraction. and so on. and the two results returned to any of the 16 registers. In a single clock cycle. extracting and depositing segments. rotating. DEPARTMENT OF ECE PAGE NO. absolute value. XOR. and is quite transparent to the programmer.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. Digital Signal Processors are designed to implement tasks in parallel. accessible at 40Mwords/second (160 Mbytes/second). an arithmetic logic unit (ALU). All of the steps within the loop can be executed in a single clock cycle.4. and a barrel shifter. The ALU performs addition. NOT). At the top of the diagram are two blocks labelled Data Address Generator (DAG). Fig 4.-45 . for 32 bit data. data from registers 0-7 can be passed to the multiplier. OR. multiplies them. one for each of the two memories. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. data from registers 8-15 can be passed to the ALU. In simpler microprocessors this task is handled as an inherent part of the program sequencer. conversion between fixed and floating point formats.2: Typical DSP architecture. such as shifting. and similar functions. The math processing is broken into three sections. These control the addresses sent to the program and data memories. specifying where the information is to be read from or written to. a multiplier. . and places the result into another register. Elementary binary operations are carried out by the barrel shifter. This simplified diagram is of the Analog Devices SHARC DSP. logical operations (AND.

this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. including a 53-bit mantissa and an 11-bit exponent). and an 8-bit exponent.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. the SHARC DSPs are optimized for both floating point and fixed point operations. the multiplier and ALU must be able to quickly perform floating point arithmetic. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. and signals coming from the ADC and going to the DAC. the SHARC devices are often referred to as "32-bit DSPs. However. are based on single16-bit data paths. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. All the registers and data buses must be 32 bits wide instead of only 16. a necessity to implement counters. Today. loops. with DSPs the speed is about the same. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel.or floating-point decision in the past. However. TMS320C5x™ and TMS320C2x™ DSPs.For instance. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits.32-BIT FLOATING POINT PROCESSOR 4. TMS320C64x™ DSPs. Double-width precision achieves much greater precision and dynamic range at the expense of speed. In addition. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. While fixed-point DSP hardware performs strictly integer arithmetic. The internal architecture of a floating point device is more complicated than for a fixed point device. . a result of the hardware being highly optimized for math operations. Tradeoffs of cost and ease of use often heavily influenced the fixed. and executes them with equal efficiency. Comparison between Fixed Point and Floating Point System: TEC Both fixed. For this reason. though. floating-point DSPs support either integer or real arithmetic.5. since it requires multiple cycles for each operation. thus supporting a vastly greater dynamic range than is available with the fixedpoint format. All floating point DSPs can also handle fixed point numbers." fixed point arithmetic is much faster than floating point in general purpose computers." rather than just “Floating Point. since the programmer doesn’t generally need to worry about issues such as overflow. the instruction set must be larger and so on. As the terms fixed. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. Fixed point DSPs are cheaper than floating point devices. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. it depends on the internal architecture . the latter normalized in the form of scientific notation. DEPARTMENT OF ECE PAGE NO. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit).-46 . respectively.and floating-point indicate. floating point programs often have a shorter development cycle. By contrast. underflow and round-off. with architectures designed for handheld and control applications.

In traditional microprocessors. This strategy works very well. the noise on each output sample may be 500 times the noise on each input sample.000 as a signed integer. This is because the gaps between adjacent numbers are much larger.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. This is a special register that has 2-3 times as many bits as the other memory locations.000 times less quantisation noise than fixed point. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. higher dynamic range. floating point has roughly 3. Noise is signal is usually represented by its standard deviation. The gap between numbers is one ten-thousandth of the value of the number we are storing. It can be rated in the form of signal to noise ratio and quantisation noise. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. it illustrates the main point when many operations are carried out on each sample. while for a fixed point number it is only about ten-thousand to one.5. while floating point devices have better precision. while in the SHARC DSPs it contains 80 bits for fixed point use. it must be round up or down by a maximum of one-half the gap size i. really bad. greatly lowering the signal-to-noise ratio of the system.1: Fixed versus floating point. Fixed point DSPs are generally cheaper. In comparison. in a 500 coefficient FIR filter. multiply it by the appropriate sample from the input signal. we loop through each coefficient. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. Although this is an extreme case. and add the product to an accumulator. each time we store a number in floating point notation. DEPARTMENT OF ECE PAGE NO. and will correspondingly add quantization noise on each step. In other words. Standard deviation of this quantisation noise is about one-third of the gap size. suppose we store the number 10.-47 . we need to scale the values being added. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. in a 16 bit DSP it may have 32 to 40 bits. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. For example. DSPs handle this problem by using an extended precision accumulator. Suppose we store in a 32 bit floating point format. this accumulator is just another 16 bit fixed point variable. . In the worst case. To store the number. floating point has such low quantization noise that these techniques are usually not necessary. and a shorter development cycle. it's bad. Here's the problem. although it does limit how some algorithms must be carried out.e. For instance. we add noise to the signal. To do this. The same thing happens when a number is stored as a 16-bit fixed point value. For instance. Suppose we implement an FIR filter in fixed point. This extended range virtually eliminates round-off noise while the accumulation is in progress. except that the added noise is much worse. To avoid overflow.. this quantization noise will simply add.

professional audio applications can sample with as high as 20 or 24 bits. if it is more complicated. are very detailed and can be much more difficult to program. The programmer needs to continuously understand the amplitude of the numbers. such as spectral analysis and FFT convolution. the development time will be greatly reduced if floating point is used.If it is relatively simple. . and what scaling needs to take place. In fixed point. the numbers take care of themselves. but the development cost will probably be higher due to the more difficult algorithms. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. television and other video signals typically use 8 bit ADC and DAC. making them suitable for fixed point. floating point will generally result in a quicker and cheaper development cycle. In many applications. In contrast. think fixed point. 12-14 bits per sample is the crossover for using fixed versus floating point. floating point systems are also easier to develop algorithms for. When fixed point is chosen.-48 . The next thing to look at is the complexity of the algorithm that will be run . For instance. For example. While they can be written in fixed point. the possibility of an overflow or underflow needs to be considered after each operation. the cost of the product will be reduced. think floating point. how the quantization errors are accumulating. and almost certainly need floating point to capture the large dynamic range.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. frequency domain algorithms. FIR filtering and other operations in the time domain only require a few dozen lines of code. these issues do not arise in floating point. In comparison. In comparison. DEPARTMENT OF ECE PAGE NO. Most DSP techniques are based on repeated multiplications and additions. but a more expensive final product. In the reverse manner. and the precision of fixed point is acceptable.

or into one of the extended precision accumulators.-49 . and MRB = Rx * Ry. In other words. many options are needed for fixed point. The RND and SAT options are ways of controlling rounding and register overflow.5. For instance. While only a single command is needed for floating point. These are the many options needed to efficiently handle the problems of round-off. and MRF and MRB are 80 bit accumulators. the value of any two registers can be multiplied and placed into another register. and format. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. and Fy are any of the 16 data registers. MRF = Rx * Ry. DEPARTMENT OF ECE PAGE NO. Rx. This describes the ways that multiplication can be carried out for both fixed and floating point formats. the floating point programmer can spend his time concentrating on the algorithm. Rn. Fn = Fx * Fy. look at all the possible commands for fixed point multiplication. This table also shows that the numbers may be either signed or unsigned (S or U). The vertical lines indicate options. These are the multiplication instructions used in the SHARC DSPs. .32-BIT FLOATING POINT PROCESSOR TEC Figure 4. where Fn. and Ry refer to any of the 16 data registers.2: Fixed versus floating point instructions. In comparison. and may be fractional or integer (F or I). Fx. It could not be any simpler. In contrast. scaling.

DEPARTMENT OF ECE PAGE NO. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low.6 Trends in DSP: TEC Figure 4.6. a cost difference of only a few dollars can be the difference between success and failure. meaning there is a greater difference between the largest number and the smallest number that can be represented. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. About twice as many engineers currently use fixed point as use floating point DSPs. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. such a .-50 . However. as shown in (c). this depends greatly on the application. In comparison. As shown in (c). When you are in competition to sell millions of your product.1: Major trends in DSPs. This is mainly driven by consumer products that must have low cost electronics. For instance. floating point is more common when greater performance is needed and cost is not important. However. and another 49% are considering the change. suppose you are designing a medical imaging system. floating point is the fastest growing segment. over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs .32-BIT FLOATING POINT PROCESSOR 4. In (b). 32-bit floating point has a higher dynamic range. such as cellular telephones. about twice as many engineers use fixed point as use floating point DSPs. As illustrated in (a). A good example of this is cellular telephones.

through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. the cost of the DSP is insignificant. Fortunately. ensuring greater accuracy in end results. 16 bits for fixed-point. The first is the I/O signal word width.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. at a price of several hundred-thousand dollars each. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow).point devices. which is 24 bits for floating-point. Second. 4. Third. 16. However. depending whether single or double precision is used. the internal representations of data in floating-point DSPs are more exact than in fixed-point. While fixed-point coefficients are 16 bits. The second word width is that of the coefficients used in multiplications. in integer as well as real values. and can be 8. Three data word widths are important to consider in the internal architecture of a DSP. exponentiation vastly increases the dynamic range available for the application. Only a few hundred of the model will ever be sold. the floating point market is the fastest growing segment. iterated MACs require additional bits for overflow headroom. In fixed. . The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. For this application. the same as the signal data in DSPs. Finally. For a single 16-bit by 16-bit multiplication. or a 48-bit product for a single 24-bit by 24-bit multiplication. which would go beyond most application requirements in accuracy. floating-point coefficients can be 24 bits or 53 bits of precision. First. or 32 bits for fixed-point DSPs. DEPARTMENT OF ECE PAGE NO. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). but the performance is critical. In spite of the larger number of fixed point DSPs being used. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. a 32-bit product would be needed. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations.-51 . this overflow headroom is 8 bits.

DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. Rapid advances in Software Technology and development of new higher level programming languages taken place. i. I/O peripheral devices and etc. Using design at this level. counters. because of manual converting the design from one level to other. Using latest CAD tools could solve the problem. for design electronics circuits with assistance of software programs. With advent of new technology. Designers felt need to automate these processes. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. It became very easy to a designer to verify functionality of design at various levels. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration).. This created new challenges to digital designers as well as circuit designers.) on an IC. . and etc. using this scale of integration people succeeded to make digital subsystems (Microprocessor. This may be leading to development of sophisticated electronic products for both consumer as well as business. This level is LSI (Large Scale Integration). registers. At this point design process started getting very complicated.) on a chip.-52 . i. one can create digital sub blocks (adders. One can fabricate a chip contains more than Million of gates.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. Later Integrated Circuits (ICs) were invented. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. At this point design process still became critical.e.e. This way of designing (using CAD tools) is certainly a revolution in electronic industry.. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. CMOS (Complementary Metal Oxide Semiconductor) process technology. multiplexes. In this process. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency.

.32-BIT FLOATING POINT PROCESSOR 5.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.-53 .2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5. DEPARTMENT OF ECE PAGE NO.

however. Reprocurement and reuse was also a big issue.The complete language. Therefore. Consequently. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. this version of the language is known as the IEEE STD 1076-1987. The language has also been recognized as an American National Standards Institute (ANSI) standard. the syntax of many constructs was made more uniform. the language was upgraded with new features. DEPARTMENT OF ECE PAGE NO. 5. and many ambiguities present in the 1987 version of the language were resolved.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard.1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. Thus. According to IEEE rules. This subset is usually sufficient to model most applications . documentation.3. This new version of the language is known as the IEEE STD 1076-1993.3.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. available from IEEE. ranging from the algorithmic level to the gate level. The IEEE in the December 1987 standardized VHDL language. Different chip vendors can provide VHDL descriptions of their components to system designers. It is a hardware description language that can be used to model a digital system at many levels of abstraction. 5. The official language description appears in the IEEE standard VHDL language Reference manual. models written in this language can be verified using a VHDL simulator. The language can be used as a communication medium between different CAD and CAE tools . and verification of the digital systems was generated. a need for a standardized hardware description language for the design.-54 . The language can be used as exchange medium between chip vendors and CAD tool users.

Component And2 Port (L. CARRY). which contains one external view and one or more internal views. Y: in BIT. Such a model for the HALF_ADDER entity. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. can be modeled as a set of interconnected subcomponents. The internal view of the device specifies functionality or structure. in turn. Arbitrarily large designs can be modeled using the language. that is a digital can be modeled as asset of interconnected components. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. Structural style of modeling: In this one an entity is described as a set of interconnected components. Dataflow. M: in BIT. B. End component. 1. 5. called an Entity. As a set of interconnected components (to represent structure) 2.-55 . In VHDL each device model is treated as a distinct representation of a unique device. The language supports three basic different styles: Structural. SUM) A1: AND2portmap (A. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. Z:out BIT). It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. and machine-readable. human-readable. B. N:outBIT). such as finite –state machine descriptions. each component. . and Boolean equations.3. This model specifies the external view of the device and one or more internal views.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. The language is publicly available. DEPARTMENT OF ECE PAGE NO. The Entity is thus a hardware abstraction of the actual hardware device. As a set of concurrent assignment statements (to represent data flow) 3. It supports both synchronous and asynchronous timing models. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. and behavioral. or mixed. Each Entity is described using one model. and there are no limitations imposed by the language on the size of the design. bottom-up. Various digital modeling techniques. Begin X1: Xor2portmap (A. End component. can be modeled using the language. The language supports flexible design methodologies: top-down.

EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0. the symbol <=implies an assignment of a value to a signal.2. Two component declarations are present in the declarative part of the architecture body.1. do not explicitly specify the structure of the entity but merely its functionality.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. and auxiliary utilities designed for easy management of resource files.In a signal assignment statement. VHDL'93 compiler. The name of the architecture body is ha . Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. SIMULATION TOOL 5. 13641995 standard.3. and EDIF and mixed VHDL-Verilog-EDIF designs. DEPARTMENT OF ECE PAGE NO. and libraries.32-BIT FLOATING POINT PROCESSOR TEC End ha. 5. Verilog compiler. 5. several debugging tools. graphical and textual simulation output viewers. single simulation kernel. The data flow model for the half adder is described using two concurrent signal assignment statements . Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL.4. . the flow of data through the entity is expressed primarily using concurrent signal assignment statements. A process statement is a concurrent statement that can appear with in an architecture body. which are specified inside a process statement.4 INTRODUCTION TO HDL TOOLS 5.the entity declaration for half adder specifies the interface ports for this architecture body. 5.3.4.4. Verilog. It comprises three different design entry tools. designs.1. The declared components are instantiated in the statement part of the architecture body using component instantiation.-56 . The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position. These sets of sequential statements. 5.4 DATAFLOW STYLE OF MODELING: In this modeling style. 1076-1993 standard. The architecture body is composed of two parts: the declaration part and the statement part.

3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. DEPARTMENT OF ECE PAGE NO.1/D1. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams.-57 . 1. HDL Editor: HDL Editor is a text editor designed for HDL source files. .0 May 1997).0. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). SDF files must comply with OVI Standard Delay Format Specification Version 2. Resource files attached to the design. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. the communication of hardware design and test verification data. The VITAL-compliant models can be annotated with timing data from SDF files. 4. It displays specific syntax categories in different colors (keyword coloring). 3. The editor is tightly integrated with the simulator to enable debugging source code. It allows you to graphically edit waveforms so as to create desired test vectors.4. Design Browser: The Design Browser window displays the contents of the current design. 5.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. modification and procurement of hardware system. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. b. the maintenance. and Tcl scripts.1. 2. Perl scripts. The keyword coloring is also available when HDL Editor is used for editing macro files. that is: a. 5. The contents of the default-working library of the design.

bde) In the case of a block or state diagram file. a source file can be on of the following: • VHDL file (.vhd) • Verilog file (. VHDL.v) • EDIF net list file (. macros.EDIF) • State diagram file (. . In Active-HDL. DEPARTMENT OF ECE PAGE NO. When you choose a menu command or toolbar button for compilation. Cycle-based simulation is significantly faster than event-driven. 6.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. All Active-HDL tools output their messages to Console.asf) • Block diagram file (. respectively for VHDL. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator.4. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. The structure of the design unit selected for simulation.-58 . Compilation: Compilation is a process of analysis of a source file. or EDIF file containing HDL code (or net list) generated from the diagram. and EDIF. • The Active-HDL simulator provides two simulation engines. 5. A net list is a set of statements that specifies the elements of a circuit (for example. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. the compiler analyzes the intermediate VHDL.32-BIT FLOATING POINT PROCESSOR TEC c. Verilog. Active-HDL provides three compilers. Verilog. transistors or gates) and their interconnection. or EDIF objects declared within a selected region of the current design. and scripts. d. Verilog.

4.6 SYNTHESIS TOOL: 5. including ModelSim Xilinx Edition and the HDL Bencher test bench generator. Verilog HDL. including: • HDL (VHDL.-59 . HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE.4.2 Design Entry: • ISE Text Editor .3.5. ISE enables you to start your design with any of a number of different source types. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.1: Simulation 5. DEPARTMENT OF ECE PAGE NO. This overview explains the general progression of a design through ISE from start to finish.6. 5. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.4. . ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.The ISE Text Editor is provided in ISE for entering design code and viewing reports. and finally produce a bit stream for your device configuration.6.32-BIT FLOATING POINT PROCESSOR TEC Fig4.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.

3 Implementation: • Translate .-60 .The Chip Viewer tool provides a graphical view of the inputs and outputs. FIFOs.The Constraints Editor allows you to create and modify the most commonly used timing constraints.State CAD allows you to specify states.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. and after fitting and routing a CPLD design. view. Chip Viewer (CPLD only) .The FPGA Editor allows you view and modify the physical implementation.4. Place and Route (PAR) .32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor . and actions in a graphical editor. analysis can be performed immediately after mapping. Constraints Editor . Floor planner . and Area Group constraints.6. With Timing Analyzer. CORE Generator .The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file.The Floor planner allows you to view a graphical representation of the FPGA.The PAR program accepts the mapped design. and pin assignments.The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. Map . places and routes the FPGA. • • • • • • • . and memories. DEPARTMENT OF ECE PAGE NO. including routing.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. transforms. macro cell details. placing or routing an FPGA design. and to view and modify the placed design.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O. Fit (CPLD only) . State CAD State Machine Editor . The state machine will be created in HDL. • • • • 5. FPGA Editor . PACE . and edit schematics and symbols for the Design Entry step of the Xilinx® design flow. and produces output for the bit stream generator. transitions. Timing Analyzer .The Map program maps a logical design to a Xilinx FPGA. equations. to system-level building blocks such as filters. Global logic.

XPower .XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices. Integration with ChipScope Pro.The iMPACT tool generates various programming file formats. • • • .6. DEPARTMENT OF ECE PAGE NO.4 Device Download and Program File Formatting: • BitGen . iMPACT .-61 .32-BIT FLOATING POINT PROCESSOR TEC 5. and subsequently allows you to configure your device.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration.4.

Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. DEPARTMENT OF ECE PAGE NO.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6.-62 . . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . multiplication and division are done using active HDL tool and the results are as follows: 6.1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format. subtraction.

2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC 6.-63 . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . DEPARTMENT OF ECE PAGE NO. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form. .2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6.

-64 .3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form. .32-BIT FLOATING POINT PROCESSOR TEC 6. DEPARTMENT OF ECE PAGE NO.3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .

. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format.-65 .32-BIT FLOATING POINT PROCESSOR TEC 6.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6. DEPARTMENT OF ECE PAGE NO.

2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. • • Procedures for performing basic arithmetic operations are been formed. subtraction. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. The Functional-simulation has been successfully carried out with the results matching with the expected ones. .-66 . Basic arithmetic operations such as addition. • 7.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. DEPARTMENT OF ECE PAGE NO.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard.

but need to use only a small subset of the range for target acquisition and identification. Since the subset must be determined in real time during system operation. however. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. DEPARTMENT OF ECE PAGE NO. feedback is well out of the ordinary operating range. Many levels of signal input from light. For instance. The greater precision of signal data. In these cases. or something might unexpectedly block its range of motion.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. The wide dynamic range of a floating-point DSP. x-rays. together with the device’s more accurate internal representations of data. enable imaging systems to achieve a much higher level of recognition and definition for the user. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. unpredictable events can occur on an assembly line. . However. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner.-67 . Wide dynamic range also plays a part in robotic design. the robot might weld itself to an assembly unit. Normally. The radar system may be tracking in a range from 0 to infinity. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions.

& Zaremba.org www. R. Science Research Associates. Pacific Grove CA. 14(7) 68-78 REFERENCES www. July 1981. Prentice-Hall.) Introduction to Computer Architecture. pp.. 1975.intel. (1987) The Implementation of Functional Programming Languages. T.org/portal/web/csdl/doi/10. M.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman. J.1109/SNPD. M. Proc. P. DEPARTMENT OF ECE PAGE NO. Computer. (Ed..computer. In: 1986 FORML Conf.2007.com . New York McKeeman.ieee. Williams. pp.-68 . Chicago.. (1986) A 32 bit processor architecture for direct execution of Forth.ieeexplore.46 www. S. Hayes. (1975) Stack computers. H. 28-30 November 1986. In: Stone. W. 281-317 Yamamoto. (1981) A survey of high-level language machines in Japan. 197-210 Jones.

std_logic_unsigned. use IEEE. begin temp:=x. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc.std_logic_arith. variable Temp :Std_logic_vector(6 downto 0).all.all.Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1. end Fadd. use IEEE. b : in std_logic_vector(31 downto 0).all.Compute Ea-Eb -2.Shift the that has lesser Exponent by Ea-Eb places to the right * -3. DEPARTMENT OF ECE PAGE NO.-69 .std_logic_1164. use IEEE. y : out std_logic_vector(31 downto 0) ).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0. --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0).

end loop. return sum.Sign Of Two exponents variable s1. -.Resultant Mantissa variable IE : std_logic_vector(6 downto 0). -.Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). else TEC Sum:=Sum.Sign Of Resultant Mantissa variable W.Sign Of Two mantissas variable Sign : std_logic.Mangitude Of Two mantissas variable ES : std_logic. -.Internal Register variable MbIn : std_logic_vector(22 downto 0). --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).-70 .s2 : std_logic. DEPARTMENT OF ECE PAGE NO.Eb : std_logic_vector(7 downto 0). Es:=Eb(7) .Final Result begin MaIn:=Acc(22 downto 0). variable X : std_logic_vector(31 downto 0). end loop.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. Ea :=Acc(30 downto 23).Mb : std_logic_vector(22 downto 0). a :=Acc(31).Internal Register variable Ea. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). Z :=(a&b). -. IE:=Eb(6 downto 0). Ma:=MaIn. Eb :=Data(30 downto 23). -.Sign Of Resulant Exponent variable a.Number Of Shifts variable Ma. -.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0). end if.b : std_logic. -. -. -. -.Subtraction of Exponents --*2.Resultant Exponent variable Ns : integer. -. end function. b :=Data(31). --***************************************************************** --*Equalization of Exponents includes two steps --*1.Z : std_logic_vector(1 downto 0). MbIn:=Data(22 downto 0). -.

IE:=Ea(6 downto 0). end loop. when "01" => Mb:=MbIn. ES:=Ea(7). ES:=Eb(7). DEPARTMENT OF ECE PAGE NO. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). . NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). ES:=Ea(7). Ma:=MaIn. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end if. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). when "11" => Mb:=MbIn. IE:=Ea(6 downto 0). else NS:=Ns. Ma:=MaIn.32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end loop. Ma:=MaIn. Es:=Ea(7). IE:=Ea(6 downto 0). ES:=Ea(7). end loop.-71 . end loop. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). IE:=Eb(6 downto 0). Mb:=Mb. Ma:=Ma. when "10" => Mb:=MbIn. IE:=IE.

end if. IE:=IE. end case. DEPARTMENT OF ECE sign:='0'. Ma:=Ma. elsif(Ma=Mb) then sign:='0'. case W is when "00" => when "11" => when "01" => when "10" => . elsif(Ma<Mb) then sign:='1'. IE:=Eb(6 downto 0). Mb:=Mb. end if. end loop.-72 . elsif(Ea<Eb) then sign:='1'. --***********logic for the sign of the mantissa********************** s1:=Acc(31). PAGE NO. when others => Null. s2:=Data(31).32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). if(Ea>Eb) then sign:='0'. else NS:=Ns. end if. else sign:=sign. else sign:=sign. W :=(s1&s2). if(Ea>Eb) then sign:='1'. sign:='1'. ES:=Eb(7). ES:=Ea(7). --******************Addition of Mantissas**************************** IR:=Ma+Mb. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'.

DEPARTMENT OF ECE PAGE NO. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)).-73 * . end Fadd. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. end if. elsif(Ma<Mb) then sign:='0'. end if. else sign:=sign.b) begin y<=float_add(a. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . elsif(Ma=Mb) then sign:='0'. when others => null.b).32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. return X. end case. end function. else sign:=sign. end process. begin process(a.

use ieee.Shift the that has lesser Exponent by Ea-Eb places to the right * 3. .Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.std_logic_1164.all.std_logic_unsigned. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout.32-BIT FLOATING POINT PROCESSOR ----1. DEPARTMENT OF ECE PAGE NO. b : in STD_LOGIC_VECTOR (31 downto 0). --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0. use ieee. end Fsub. y : out std_logic_vector(31 downto 0)).-74 .all.Compute Ea-Eb 2.all. begin temp:=x. use IEEE. variable Temp : Std_logic_vector(6 downto 0).std_logic_arith.

-.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). a :=Accout(30).Resultant Mantissa variable IE : std_logic_vector(6 downto 0). Ea :=Accout(30 downto 23). else Sum:=Sum. Z :=(a&b). -. Eb :=Data(30 downto 23).Final Result begin MaIn:=Accout(22 downto 0). -.Mangitude Of Two Mantissas variable ES : std_logic.Number Of Shifts variable Ma. variable X : std_logic_vector(31 downto 0). -.MbIn: std_logic_vector(22 downto 0).s2 : std_logic. end function.Resultant Exponent variable Ns : integer. -. DEPARTMENT OF ECE PAGE NO. -.Eb : std_logic_vector(7 downto 0).Subtraction of Exponents * * .32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i. MbIn:=Data(22 downto 0). end loop. -.Mb : std_logic_vector(22 downto 0).Z : std_logic_vector(1 downto 0). -.Internal Register variable Ea. end if. return sum.Sign Of Resultant Mantissa variable W. --*********************variable Declarations*********************** TEC variable MaIn.Sign Of Two Mantissas variable sign : std_logic. -. --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. -. b :=Data(30).-75 . -.b : std_logic.Sign Of Resulant Exponent variable a.Sign Of Two Exponents variable s1.

for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). IE:=Ea(6 downto 0). ES:=Ea(7). Ma:=Ma. ES:=Eb(7). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)).-76 . when "01" => Mb:=MbIn. Mb:=Mb. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). . NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). Ma:=MaIn. Ma:=MaIn. end loop. IE:=Ea(6 downto 0). TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. end loop. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). end loop. end if. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR --*2. IE:=Eb(6 downto 0). IE:=IE. else NS:=Ns.

IE:=Eb(6 downto 0). Ma:=MaIn. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). DEPARTMENT OF ECE PAGE NO. ES:=Eb(7). ES:=Eb(7). end loop. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). . for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). when others => null. --******************Subtraction of Mantissas************************ IR:=Ma-Mb. end if. IE:=IE. IE:=Ea(6 downto 0). end loop. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). ES:=Ea(7). Mb:=Mb. TEC Ma:=MaIn. end loop. else NS:=Ns.-77 . NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). end case. ES:=Ea(7).32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. when "11" => Mb:=MbIn. IE:=Eb(6 downto 0). Ma:=Ma. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)).

elsif(Ea<Eb) then sign:='1'. else sign:=sign. else sign:=sign. end if. elsif (Ma=Mb) then sign:='0'. s2:=Data(31).32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). elsif(Ma<Mb) then sign:='0'. DEPARTMENT OF ECE PAGE NO. when "01"=> if(Ea>Eb)then sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. else sign:=sign. . end if. when "10"=> if (Ea>Eb)then sign:='1'.-78 . end if. W:=(s1&s2). else sign:=sign. when "11"=> sign:='1'. case W is when "00"=> sign:='0'. elsif (Ma=Mb) then sign:='0'. end if. elsif(Ma<Mb) then sign:='1'. elsif (Ea<Eb) then sign:='0'.

begin process(a.Addtion of the Exponents 5. end process. use IEEE.32-BIT FLOATING POINT PROCESSOR TEC when others=> null. DEPARTMENT OF ECE PAGE NO.b) begin y<=float_sub(a. end Fmul. return X. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1.std_logic_1164. y: out STD_LOGIC_VECTOR (31 downto 0) ). --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0).b). use IEEE. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)).Multiplication of the Mantissas * * -************************************************************************** library IEEE.all. end function. b: in STD_LOGIC_VECTOR (31 downto 0). end f_sub.all. end case.-79 .std_logic_unsigned. .

sign Two Mantissas variable Ea.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout.Sign Of Resultant Mantissa variable a.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0). when "11" => s:='0'. -. -. -.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. -.Magnitude Of Two Exponents variable c : std_logic. when others=> s:='1'. m2 :=Data(10 downto 0). m1 :=Accout(10 downto 0). -. . case Z is when "00" => s:='0'.Two Exponents Icluding Sign variable m1. -. Z :=(s1&s2). variable x : std_logic_vector(31 downto 0). --************logic for the sign of the Mantissa******************* s1:=Accout(31).Resultant Mantissa variable carry : std_logic.s2 : std_logic.Final Result begin Carry:='0'. DEPARTMENT OF ECE PAGE NO. -.Carry variable W.Sign Two Exponents variable s1.Z : std_logic_vector(1 downto 0).Eb : std_logic_vector(6 downto 0). -. -.-80 . s2:=Data(31). -. e2 :=Data(30 downto 23).b : std_logic.Resultant exponent variable m : std_logic_vector(21 downto 0).e2 : std_logic_vector(7 downto 0). e1 :=Accout(30 downto 23). end case.m2 : std_logic_vector(10 downto 0).Magnitude O Two Mantissas variable s : std_logic. -.

DEPARTMENT OF ECE PAGE NO. case W is when "00" => c:='0'. end if. c:='1'. e:=Ea+Eb. end case. e:="0000000". else c:='0'. e:=Ea-Eb. W :=(a&b).-81 . elsif(Ea<Eb) then c:='1'. --*************logic for multiplication************************* m:=m1*m2. e:=Ea-Eb. when "11" => when others => null. e:="0000000". Eb:=e2(6 downto 0). else c:='0'. when "01" => if(Ea>Eb) then c:='0'. e:=Eb-Ea. e:=Ea+Eb. b :=Data(30). end if. e:=Eb-Ea. a :=Accout(30). .32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). when "10" => if(Ea>Eb) then c:='1'. elsif(Ea<Eb) then c:='0'.

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

e:=Eb-Ea. else c:='0'. Eb:=e2(6 downto 0). if(Ea>Eb) then c:='0'. e:=Ea+Eb. e:=Ea-Eb.-86 . when "10"=> if(Ea>Eb) then c:='1'. else c:='0'. e:=Ea-Eb. elsif(Ea<Eb) then c:='0'. end if. case Z is when "00" => if(Ea>Eb) then c:='0'. e:=Eb+Ea. Z :=(a&b). . elsif(Ea<Eb) then c:='1'. end if.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). b :=e2(7). if(Ea>Eb) then c:='1'. elsif(Ea<Eb) then c:='0'. a :=e1(7). e:="0000000". elsif(Ea<Eb) then c:='0'. e:="0000000". e:=Ea+Eb. e:=Eb-Ea. end if. else c:='0'. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. e:="0000000".

else c:='0'. TEC . end function.b) begin Y<=float_div(a. DEPARTMENT OF ECE PAGE NO. return X. when others=> null. end case. end F_div. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). e:="0000000".32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. end if. end process.b). begin process(a.-87 .

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