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TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

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the real-number system comprises the continuum of real numbers from minus infinity (. As shown at the bottom of Figure 1. Figure 2.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. . As shown in Figure 1. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits.-5 .) to plus infinity (+ ). The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers.1: Binary Real Number System Because the size and number of registers that any computer can have is limited.1. only a subset of the real-number continuum can be used in real-number calculations. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. DEPARTMENT OF ECE PAGE NO.

Digital Signal Processing can be divided into two categories. Fixed-point Vs floating-point in digital signal processing Fig 2. signed integer uses two's complement to make the range include negative numbers. DEPARTMENT OF ECE PAGE NO. the 65. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. while floating-point DSPs support either integer or real arithmetic. performance attributes.536 possible bit patterns can represent a number. fixed point and floating point. These refer to the format used to store and manipulate numbers within the devices. Motorola manufactures a family of fixed point DSPs that use 24 bits.535. Lastly. For instance.2. 2. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. Fixed point DSPs usually represent each number with a minimum of 16 bits. the number is an integer).-6 .536 levels are spread uniformly between 0 and 1.768 to 32. Software programmable for maximum flexibility and supported by easy-touse. Similarly. processor and system costs. With unsigned fraction notation. although a different length can be used. from -32. and ease of development. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. DSPs enable designers to build innovative features and differentiating value into their products. the signed fraction format allows . some specific assumption is made about where the radix point is located in the string. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. low-cost development tools. In common mathematical notation. but decimal fixed point is common in commercial applications.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. In unsigned integer. There are four common ways that these 216 ' 65. Among the key factors to consider are the computational capabilities required for the application. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic.767. the digit string can be of any length.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data. Balancing these factors together. designers can identify the DSP that is best suited for an application. the stored number can take on any integer value from 0 to 65. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. In fixed-point systems.

2 ×1038. This position is indicated separately in the internal representation. the largest and smallest numbers are ±3." rather than just "Floating Point. the SHARC devices are often referred to as "32-bit DSPs. This results in many more bit patterns than for fixed point. The represented values are unequally spaced between these two extremes. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. Floating point A floating-point number is the one. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . The radix point is not explicitly included. The term” floating point” refers to the fact that the radix point can "float".754-1985). For instance. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. The logic for these is different from the ordinary arithmetic functions. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. respectively.967.In comparison.3.4 ×1038 and ±1. The floating-point operations are incorporated into the design as functions. but small gaps between small numbers. the SHARC DSPs are optimized for both floating point and fixed point operations. a necessity to implement counters.294.-7 . or sometimes the mantissa (see below) or coefficient. and executes them with equal efficiency. 2324. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). it depends on the internal architecture. The speed of floating-point operations is an important measure of performance for computers in many application domains.However. equally spaced between -1 and 1. DEPARTMENT OF ECE PAGE NO. which is capable of representing real and decimal numbers. A key feature of floating point notation is that the represented numbers are not uniformly spaced. For this reason. This is important because it places large gaps between large numbers. that is. and signals coming from the ADC and going to the DAC. This is known as the significand. In the most common format (ANSI/IEEE Std. All floating point DSPs can also handle fixed point numbers. 2." 2. It is measured in” FLOPS”. and floating-point representation can thus be thought of as a computer realization of scientific notation.4. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values.296 to be exact. it can be placed anywhere relative to the significant digits of the number. floating point DSPs typically use a minimum of 32 bits to store each value.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. loops.

Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. computers used many different forms of floating-point. this final value is where s is the value of the significand (after taking into account the implied radix point). These differed in the word sizes. 10 or 16. which modifies the magnitude of the number. so when stored in the same space. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. and e is the exponent. composed as integer. and the rounding behaviour of operations.Fraction. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2.32-BIT FLOATING POINT PROCESSOR TEC significant digit. the format of the representations. 1 for negative values. b is the base. These differing systems implemented different parts of the arithmetic in hardware and software. with an average error of about 3%. (This is because the exponent field is in . IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. 2. A signed integer exponent. The length of the significand determines the precision to which numbers can be represented. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. also referred to as the characteristic or scale. or to the right of the rightmost digit.-8 . Significand is a real number. The floating-point format needs slightly more storage (to encode the position of the radix point).5. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. Symbolically. The significand is multiplied by the base raised to the power of the exponent. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. Prior to the IEEE-754 standard. floating-point numbers achieve their greater range at the expense of precision. DEPARTMENT OF ECE PAGE NO.

0 denotes a positive number. To do this. 2. The Mantissa: The mantissa. So. There are many formats that are used for representation of floating point number. The exponent field contains 127 plus the true exponent for single-precision.-9 . a bias is added to the actual exponent in order to get the stored exponent. 1 for negative. the exponent. even though there are infinitely many real numbers (even between 0 and 1). The exponent's base is two. IEEE-754 specifies binary representations for floating point numbers: Table 2. to sum up: 1. where f is the field of fraction bits.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. The first bit of the mantissa is typically assumed to be 1. This means that at most 232 possible real numbers can be exactly represented. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. 1 denotes a negative number.f. 4. Flipping the value of this bit flips the sign of the number. 3. The Exponent: The exponent field needs to represent both positive and negative exponents.) This can be exploited in some applications. also known as the significand. The Sign Bit: The sign bit is as simple as it gets. and the mantissa. or 1023 plus the true exponent for double precision. It is composed of an implicit leading bit and the fraction bits.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. A float is represented using 32 bits. The sign bit is 0 for positive. represents the precision bits of the number. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. and each possible combination of bits represents one real number. such as volume ramping in digital sound processing. DEPARTMENT OF ECE .

-10 . IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0).5. Table 2.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2. then V=-Infinity If E=255 and F is zero and S is 0. which may be represented as numbered from 0 to 31. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude.32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude.5. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010). the next eight bits are the exponent bits. then V=Infinity . DEPARTMENT OF ECE PAGE NO. S.1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values. left to right.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. then V=NaN ("Not a number") If E=255 and F is zero and S is 1.5. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. 'E'. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero.

101 = 6. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1. If E=0 and F is nonzero. then V=-0 If E=0 and F is zero and S is 0.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. then V=(-1)**S * 2 ** (-126) * (0.F) These are "unnormalized" values.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.101 = -6. If E=0 and F is zero and S is 1. then V=0 In particular.F) where "1.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.3125 The biased exponent is -2+127=125= (01111101 • 1. DEPARTMENT OF ECE PAGE NO.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.0 The biased exponent is .-11 .

3125 131310 = 101001000012 0.010010000101012 × 210.8125 × 2 = 1.3125 0.40625 × 2 = 0.25 × 2 = 0.-12 . • -78. sign bit is 1.5 The based exponent: 127+5= (10000100 .01012.1015625 × 2 = 0.8125 .203125 × 2 = 0. DEPARTMENT OF ECE PAGE NO.25 The biased exponent: 127+6=133=(10000101 • -1313.625 × 2 = 1.1015625 0. .625 0. So -1313.32-BIT FLOATING POINT PROCESSOR TEC • 37. 10 + 127 = 137 = 100010012.25 0.0 0 1 0 1 1313.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0. = 1.5 × 2 = 1.312510 = 10100100001.5 × 2 = 0.203125 0.3125 is • 0.40625 0.

S. then V=NaN ("Not a number") PAGE NO. the next eleven bits are the exponent bits.25 0.625 0. 'E'.5.5.5 0 × 2 = 1.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word. which may be represented as numbered from 0 to 63.25 1 × 2 = 0.101562510 = 0. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values. DEPARTMENT OF ECE .1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001). The number of bits for each field are shown (bit ranges are in square brackets): Table 2. left to right.00011012 = 1.5 × 2 = 1.-13 .1015625 is 0 00111101 110100000000000000000000 TEC 2.32-BIT FLOATING POINT PROCESSOR 0.0 1 0. The first bit is the sign bit.3. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0). The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero.

F) These are "unnormalized" values.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. using a fixed number of digits.6.-14 . Table 2. 15 exponent bits and 112 significand bits.5.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2.53 ~ 10308.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1. DEPARTMENT OF ECE PAGE NO. then V=(-1)**S * 2 ** (-1022) * (0. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2. If E=0 and F is zero and S is 1.F) where "1. floating-point notation allows calculations over a wide range of magnitudes. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. . then V=-Infinity If E=2047 and F is zero and S is 0. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit . then V=-0 If E=0 and F is zero and S is 0.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). If E=0 and F is nonzero. while maintaining good precision.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable.

Normalized And Approximate Decimal Values.85 to ~1038. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand.32-BIT FLOATING POINT PROCESSOR TEC Table 2. U) (where B is the base of the system. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent. L is the smallest exponent represent able in the system. and the smallest possible value for the exponent. Negative numbers greater than -2-149 (negative underflow) 3.-15 .2: Effective Range of IEEE Floating Point Number with Denormalized.3 to ~10308. P. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1). The number of normalized floating point numbers in a system F(B. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2. P is the precision of the system to P numbers. Approximate Decimal 2127 21023 ~10-44. Positive numbers less than 2-149 (positive underflow) . L. There is a largest floating point number.53 ~10-323. DEPARTMENT OF ECE PAGE NO. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. Zero 4. There is a smallest positive normalized floating-point number.6. the range for negative numbers is given by the negation of the above values.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit.

Recently. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. If M = 0.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. DEPARTMENT OF ECE PAGE NO. 2. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. the number is exactly zero. 2. the largest value which is defined in bias-127 exponent representation.infinity. the most negative value which is defined in bias-127 exponent representation. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately.32-BIT FLOATING POINT PROCESSOR 5. the exponent is set to -127 (E = 0). the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . However the CPU will have to perform extra arithmetic to read the number when stored in this format.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit . When this occurs. Underflow occurs when the sum of the exponents is more negative than -126. When this occurs. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127.-16 . These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers.

let us consider two numbers a= 2. both the numbers are added. They are: 1.. DEPARTMENT OF ECE PAGE NO.0225x .1. Add the numbers with decimal points aligned. Division 2. Subtraction 3.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. But by using floating point addition this can be avoided to a little extent. i.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. Multiplication 4. Hence the value of number ‘a’ becomes 0.e..25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.25x and b= 1. For example. .340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal. Now as both the exponent values are same.8. Floating point addition is analogous to addition using scientific notation. as the smaller number here is a=2.-17 . Addition 2. Normalize the result.

23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value. If the numbers are represented with both positive and negative sign. Consider a example in which a =1.1..e. ManA as mantissa of number A.1.. then bit 1 is represented for sign.8. a =1.00000009876543 x c= 1. Now both the numbers are added. 2.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .e.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part. signB as sign of number B.876543x after shifting becomes b= 0.876543x and if the addition has to be performed.8.2345670 x in which the remaining part (9876543) which is discarded also carries the result. DEPARTMENT OF ECE PAGE NO. The mantissa of both numbers A and B are added. then the following result may occur: 1. But the normalised result may sometimes carry the required result. then sign of greater number is considered. i.1.2.234567x and b= 9. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. ExpB as exponent of number B and ManB as mantissa of number B. b= 9.00000009876543 x 2. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: . If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2.-18 . Thus this case can said to be having rounding errors.234567x b= 0.8.1. 2. ExpA as exponent of number A .

-19 . The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. Addition of significands is done.1. DEPARTMENT OF ECE PAGE NO. If the exponents are stored in biased form. Firstly. 6.2: Flow Chart for Floating Point Adder.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. . exception is made. If not. the numbers are represented in IEEE floating point format. 5. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. the exponent sum would have doubled the bias. the significand is rounded to the appropriate number of bits required and again normalization is checked. 4.8. 2. If there is an underflow or overflow. the bias value must be subtracted from the sum 3. 1. Thus.

the result is converted back to signmagnitude form.25 in IEEE Floating Point Standard is: The number 134. then the mantissa must be shifted one bit to the right and the exponent incremented. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. Consider addition of the numbers 2. After the addition is performed.0625 in IEEE Floating Point Standard is: To align the binary points.25 becomes: The mantissas are added using integer addition: The result is already in normal form. resulting in a sum which is arbitrarily small. Subtraction . so the hidden bits can sum to no more than 3 (11).-20 . The mantissa is always less than 2. When adding numbers of opposite sign. The number 2.8. If the sum overflows the position of the hidden bit.32-BIT FLOATING POINT PROCESSOR TEC 7. 2.25x and 1. Thus. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal.2. Negative mantissas are handled by first converting to 2's complement and then performing the addition. Normalization in this case may require shifting by the total number of bits in the mantissa. resulting in a large loss of accuracy. cancellation may occur. 2. or even zero if the numbers are equal in magnitude. DEPARTMENT OF ECE PAGE NO.340625x .

340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal. Now as both the exponent values are same. The mantissa of both numbers A and B are subtracted.e.8.25x and b= 1.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .2. ManA as mantissa of number A. then sign is represented according to the number i. Normalize the result. signB as sign of number B. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if .32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2. as the smaller number here is a=2. ExpA as exponent of number A . i.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal.2. The normalised result may contain the required number of digits discarding the unwanted part. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.. Hence the value of number ‘a’ becomes 0. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2.8.1. both the numbers are added. DEPARTMENT OF ECE PAGE NO. 2. Subtract the numbers with decimal points aligned.-21 .e.1. ExpB as exponent of number B and ManB as mantissa of number B...0225x .

25 in IEEE Floating Point Standard is: The number 134. The number 2. If there is an underflow or overflow.340625x .2. the exponent sum would have doubled the bias. 4. Thus. Consider subtraction of the numbers 2. 6. The numbers are represented in IEEE floating point format. Subtraction of significands is done. 2. the significand is rounded to the appropriate number of bits required and again normalization is checked. exception is made. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal.25 become: The mantissas are subtracted using integer subtraction: .0625 in IEEE Floating Point Standard is: To align the binary points. If not.8.2. 2. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.25x and 1. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign. DEPARTMENT OF ECE PAGE NO.-22 . If the exponents are stored in biased form. Thus. 2. 5. the bias value must be subtracted from the sum 3.

then the mantissa must be shifted one bit to the right and the exponent incremented.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form. If it is ‘0’. then number Y is checked. If overflow occurs.-23 . If the exponents are same. consider two numbers X and Y and the resultant be Z. If the significand is zero then it is returned if not significand overflow is checked.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. If it is ‘0’ then the resultant solution Z would be Y i. If both the numbers X and Y are non zeros. If number X is not ‘0’. 2. If the sum overflows the position of the hidden bit.. number X is checked. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent .2. Z=Y. then the result would be Z=X. If not then the result is normalized.8. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked.8.e. then the significands of numbers X and Y are subtracted. then the following steps can be followed: Exponents of both the numbers are checked. Flow chart for floating point subtraction: Subtract significand si Fig 2.3. DEPARTMENT OF ECE PAGE NO. If overflow occurred then overflow is reported and returned. In the first step.2. At this point.

For example.8x times 9. 2. If underflow occurred then it is reported if not the normalized result is given out.3.1. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.3. If the exponents are not same.8. to multiply 1. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.5 ----17. The number 18.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked.8 x 9. if the significand is not zero then subtraction and further process is carried out. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result.0 in IEEE FPS format is: The number 9. 1.8. 2.5 in IEEE FPS format is: . then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z. DEPARTMENT OF ECE PAGE NO.5x : Perform unsigned integer multiplication of the mantissas.-24 .

the mantissa is: The biased-127 exponents are added.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in (). When the fields are assembled in IEEE FPS format.-25 . The sign of the result is the xor of the sign bits of the two numbers. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form.8.2. Block diagram of floating point multiplication: . the mantissa must be shifted right and the exponent incremented.3. DEPARTMENT OF ECE PAGE NO. the result is: 2. If the position of the hidden bit overflows.

. Sign of the result is given by performing xor operation of signA and signB.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard.8. XOR operation for sign bit can be given as follows: Table 2. The exponents of both the numbers are added and subtracted from the bias 127. expA as exponent of number A .3.8.-26 . the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported.3.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2.8.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. then the exponents are added and a bias of 127 is subtracted from the result. the exponent sum would have doubled the bias.3. Thus. At the first step.3. expB as exponent of number B and manB as mantissa of number B. DEPARTMENT OF ECE PAGE NO. signB as sign of number B. If both the numbers X and Y are not zero. Resultant mantissa is truncated and normalized to fit for the IEEE format. If the exponents are stored in biased form. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero. manA as mantissa of number A. The mantissa of both numbers A and B are multiplied.

3 0. Hence the result can be given as 1.5.5 .8. So resultant exponent would be 2-3=-1.3: Flow Chart For Floating Point Multiplication. in general floating point division the exponents of both the numbers are subtracted and the significands are divided.3 and b= 0.3. Fig 2. . i.2 =1.-27 .e. Exponent of a is 2 and exponent of b is 3.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned. DEPARTMENT OF ECE PAGE NO.4. Division Consider an example of dividing a=0. 2.8.2 . The resultant sign bit would be the xor operation of sign bits of X and Y. When the division of both significands are done then the quotient would be 1.. 0.5.

the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. As in floating point multiplication.4. Block diagram for floating point division: Fig 2. 2.8. Special .32-BIT FLOATING POINT PROCESSOR TEC 2. signB as sign of number B. then the result is also negative is represented by bit ‘1’. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement. a 24 bit quotient is produced. Subtract the exponent of the divisor from the exponent of the dividend. If anyone number of the two are negative.4.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. The exponents are subtracted and biased using the bias value. ExpB as exponent of number B and ManB as mantissa of number B.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .1. then the resultant sign is also positive and is represented by bit ‘0’. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend.8. The mantissa of both numbers A and B are divided. In the first step. When divided by a 24 bit divisor. ExpA as exponent of number A .-28 . Normalize the result.8. ManA as mantissa of number A. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. Set the sign of the result. DEPARTMENT OF ECE PAGE NO.4. If both the numbers are either positive or negative.

This value is called Not A Number. in this case as larger number has to be subtracted from smaller number.3 S E and b= 0.8. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero. or NaN. .2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted. 2. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity . For this.4. Number X and Y are checked. Considering a=0.3 0. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard .Then the steps that occur are: 1.-29 .3. DEPARTMENT OF ECE PAGE NO.2 can be represented as M 010000001(0)11000000000000000000000 0.

32-BIT FLOATING POINT PROCESSOR TEC 3. DEPARTMENT OF ECE PAGE NO.8.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. digits may flow off the right end of the significand. If they are present.4. Fig 2.This means that the number is too small to be represented.9. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. If not the mantissas are divided and truncated and normalized result is given out. this may be designated as +∞ or -∞.g. In some systems..-30 .127). • Significand underflow: In the process of aligning significands. As we shall discuss. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit. and it may be reported as 0. . Rounding Error In floating point arithmetic. then those conditions are reported. some form of rounding is required. rounding errors occur as a result of the limited precision of the mantissa . 2.200 is less than .

RN is generally preferred and introduces less systematic error than the other rules. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. The least significant 24 bits are discarded. Same as truncation in 2's complement. The size of the absolute error is proportional to the magnitude of the number.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. Break ties by choosing the least significant bit = 0. The value can be kept unchanged by adjusting the exponent accordingly.-31 . it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. To efficiently use the bits available for the significand. highest precision can be achieved. For normalized floating point numbers.10. Same as truncation in sign-magnitude. DEPARTMENT OF ECE PAGE NO. However. the relative error is approximately since For denormalized numbers (E = 0). relative errors increase as the magnitude of the number decreases toward zero. For numbers in IEEE FPS format. . Normalization By normalization. RP: Round toward Positive infinity. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2. RZ: Round toward Zero. RM: Round toward minus infinity.

Truncation To retain maximum accuracy.-32 . The first bit 1 before the decimal point is implicit. The actual value represented is However. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. it does not need to be shown explicitly. as the MSB of the significand is always 1. DEPARTMENT OF ECE PAGE NO. bits are used in final representation of a bits by one of the three methods. in the following the default normalization does not assume this implicit 1 unless otherwise specified. Zero is represented by all 0's and is not (and cannot be) normalized. all extra bits during operation (called guard bits) are kept (e.. If we assume number. resulting 1. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit.11.g. a 4-bit exponent field and a 9-bit significand field): 2. multiplication). to avoid possible confusion. By the end of the operation. the bits need to be truncated to guard bit Chopping: simply drop all .32-BIT FLOATING POINT PROCESSOR TEC Moreover. extra guard bits are kept during operation.

. DEPARTMENT OF ECE PAGE NO.-33 . (no matter Von Neumann Rounding: If at least one of the guard bits is 1. add 1 to LSB . the Von Neumann rounding error is unbiased. .5 round up. Interpretation: Value represented by guard bits is greater than 0. 3. set whether it is originally 0 or 1). Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. is always greater than 0. Two worst cases Both two cases can be summarized as i. .e.32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. we say this truncation error is biased. otherwise do nothing.

the rounding depends on the LSB : if .5 either up or down with equal probability (50%). c) If the highest guard bit is 1 and the rest guard bits are all 0.32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0.5 round down. The rounding error of these cases can summarized as . drop all guard bits. Interpretation: Value represented by guard bits is smaller than 0. .-34 . DEPARTMENT OF ECE PAGE NO. round up: Interpretation: Value represented by guard bits is 0. it is randomly rounded . round down: or if .

32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . The numbers in contention have to be first converted into the standard IEEE 784. multiplication and division is presented in the following pages. The floating-point operations are incorporated into the design as functions. the exponent obtained by balancing operations is added to 0111. the sign of the floating point number. 1111. The above representation is the IEEE-784 1985 standard representation. Positive numbers are represented by binary values greater than 0111. subtraction.e. The MSB is the sign-bit i. DEPARTMENT OF ECE PAGE NO. . The logic for these is different from the ordinary arithmetic functions. The exponent in this IEEE standard is represented in excess-127 format. I.3 Floating Point Functions A floating-point number is the one. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number.e. Therefore zero is represented by 0111. which is capable of representing real and decimal numbers. 1111 and negative numbers are represented by binary values less than it. 1111.-35 . 1985 floating point standard representation before any sort of operations are conducted on them. The logic for floating point addition. The next eight bits are that of the exponent.

1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. These numbers are distinct. we have to first normalize their exponents. • • . Now the numbers from the memory are loaded into two registers. This is done till the lower exponent becomes equal to the higher one. The mantissas are then added to each other and the result is then stored in a temporary register.32-BIT FLOATING POINT PROCESSOR TEC 3. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately.-36 . namely Accumulator and the Temp register that loads the value appearing on the data bus. Once the exponents are normalized. These numbers are stored into the memory from which they are read and processed. DEPARTMENT OF ECE PAGE NO. So. So to add their mantissa’s. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa.

The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. This is done till the lower exponent becomes equal to the higher one. So to add their mantissa’s. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. These numbers are stored into the memory from which they are read and processed.32-BIT FLOATING POINT PROCESSOR 3. The mantissas are then subtracted and the result is stored in a temporary register. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. DEPARTMENT OF ECE PAGE NO.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. So. namely Accumulator and the Temp register that loads the value appearing on the data bus. we have to first normalize their exponents. Now the numbers from the memory are loaded into two registers. These numbers are distinct. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. .-37 . Once the exponents are normalized.

There is however a limitation to this operation. the resulting exponent and the sign of the result that is calculated separately. DEPARTMENT OF ECE PAGE NO.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result.-38 . If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. so that the result is restricted to not more than 24-bits. The final output is obtained by concatenating the product of the mantissas. So each input should not exceed 12-bits in length. • • • .32-BIT FLOATING POINT PROCESSOR TEC 3. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent.

The result is stored in Temp. till the quotient is full. Now since the greater of the two numbers is decided. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. Now the first 24-bits from the MSB are compared with the divisor. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. And if it is zero. • • • • • . The convention here is that the Numerator should be always less than the denominator.32-BIT FLOATING POINT PROCESSOR TEC 3. The decimal is assumed to be before the MSB of the resulting quotient. we put a zero in the quotient. we append it with the exponent value and the Sign of the division that are calculated separately. if the MSB or the 49th bit is one than we add a one in the quotient.4 Floating Point Division • • • • This is more complicated then Multiplication.-39 . This is to ensure that whatever comes as the result is after the decimal point. The logic for floating point division is as follows. First the exponents are directly added or subtracted depending on which is bigger. We initiate a counter and carry this process for 24 times. Once the quotient is full. Apart from that the final sign of the division is calculated separately. Now both the numbers in the IEEE-784 standard format are compared. DEPARTMENT OF ECE PAGE NO.

etc). competitive position. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. product life time.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. Consider another example of how a document is printed from a word processor. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). With each clock peak. For instance. Depending on the type of processor.-40 . The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. Data manipulation such as word processing and database management 2. A<B . and so on. data is temporarily stored in small. The basic task is to store the information. corresponds to the number of pulses per second. and testing for inequalities (A=B. These devices have seen tremendous growth in the last decade. the overall number of registers can vary from about ten to many hundreds. DSPs can perform the mathematical calculations needed in digital signal processing. however it is difficult or expensive to make a device that is optimized for both. DEPARTMENT OF ECE PAGE NO. The clock speed (also called cycle).32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. consider a word processing program. Data manipulations involve storing and sorting information. local memory locations of 8.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. Mathematical calculation used in science. When the processor executes instructions. finding use in everything from cellular telephones to advanced scientific instruments. When this code is detected. Computers are extremely capable in two broad areas 1. meaning a multiple of the motherboard frequency. engineering and digital signal processing. 4. There are marketing issues involved: development and manufacturing cost. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. Clock frequency is generally a multiple of the system frequency. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. written in Hertz (Hz). A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. There are technical tradeoffs in the hardware design. the processor performs an action that corresponds to an instruction or a part thereof. 16. These tasks are accomplished by moving data from one location to another. the program moves the data from . All microprocessors can perform both tasks. 32 or 64 bits called registers. such as the size of the instruction set and how it interrupts are handled. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer.

the most common DSP technique. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. there may only be a few coefficients in the filter kernel. depending on the application.. consider the implementation of an FIR digital filter. the input signal is referred to by x [ ]. In comparison. i. The task is to calculate the sample at location n in the output signal.e. such as to keep track of the intermediate results and control the loops.. it is infrequent and does not significantly affect the overall execution speed.32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. This is simply saying that the input signal has been convolved with a filter kernel consisting of: . Using standard notation.. the math operations dominate the execution time.. y[n].... An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: .. While mathematics is occasionally used in this type of application.. . For example.. while the output signal is denoted by y [ ]. DEPARTMENT OF ECE PAGE NO. While there is some data transfer and inequality evaluation in this algorithm..-41 ..

It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. is found by multiplying samples from the input signal. Difference between off-line processing and real time processing: In off-line processing.32-BIT FLOATING POINT PROCESSOR TEC Fig4. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. consider a designing of an audio signal in DSP system such as a hearing aid. the information may be read into a computer and analysed in some way. but these items will appear as chip fabrication technology gets denser. say. design difficulty and so on. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors.x[n-2]. the traditional speed advantage of integer operations over floating point operations is decreasing. There is less room on-chip for extra features such as hardware multipliers. the DSP must be able to maintain a sustained throughput of 20. There are a few reasons for why to not to make it faster than necessary because as speed increases..3. Floating point calculations also require a 32-bit processor for good efficiency. Digital signal processors are designed to quickly carry out FIR filters and similar techniques. and to support code written in high level languages. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips.... This is common in scientific research and engineering. For instance. Hence execution time is critical for selecting the proper device. However. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. so as the cost . each sample in the output signal . 4. Also.x[n-1]. If suppose you are launching your desktop computer on some task . DEPARTMENT OF ECE PAGE NO. a geophysicist might use a seismometer to record the ground movement during the earthquake. with the advent of very fast floating point processing hardware. . not having a defined start or end.2.y[n].by the filter kernel coefficients. and summing the products. You simply wait for the action to be completed before you give the computer its next assignment In comparison. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. If the digital signal is being received at 20. as well as the algorithms that can be applied. For example.-42 . power consumption. DSPs must also have a predictable execution time.1: Graphical representation of FIR digital filter design. . After shaking is over. floating point math must often be used to reduce the cost of programming a project. whereas 32-bit processors are naturally suited to the size of the data elements. x[n].000 samples per second. the entire input signal resides in the computer at the same time. In these cases a 16-bit processor may suffice. In addition to performing mathematical calculations very rapidly.. converting a word processing document from one form to another.000 samples per second. most DSPs are used in applications where the processing is continuous. The key point in off-line processing is that all of the information is simultaneously available to the processing program. Off-line processing is a realm of personal computers and mainframes. The disadvantages of 32-bit processors are cost and system complexity. In FIR filtering .

For example. For example. the binary codes that go into the program sequencer. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). they may input a group of samples perform the algorithm and output a group of samples. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. the data transfer rate is an incredible 240Mbytes/second. over and over. This is the world of digital signal processors. hearing aids and radar. with separate buses for each. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. For instance. This includes data. When all six parallel ports are used together. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. Real time applications input a sample. while six parallel ports each provide a 40 Mbytes/second data transfer. there are two serial ports that operate at 40 Mbits/second each. DEPARTMENT OF ECE PAGE NO. Alternatively. These are extremely high speed connections. Different architectures available are: Von Neumann Architecture. Harvard Architecture. while only one binary value (the program instruction) is passed over the program memory bus. the output signal is produced at the same time that the input signal is acquired.4. two binary values (the numbers) must be passed over the data memory bus. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. Super Harvard Architecture (SHARC). and an I/O controller. The SHARC DSPs provides both serial and parallel communications ports. . Most present day DSPs use this dual bus architecture. Most of the computers are using this architecture today. Since the buses operate independently. 4. For instance.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. we might place the filter coefficients in program memory. Likewise. two areas are important enough to be included are an instruction cache. this is needed in telephone communication. program instructions and data can be fetched at the same time. perform the algorithm and output a sample. The basis of Harvard design is that the data memory bus is busier than the program memory bus.-43 . Harvard architecture has separate memories for data and program instructions. while keeping the input signal in data memory. at a 40 MHz clock speed. improving the speed over the single bus design. While the SHARC DSPs are optimized in dozens of ways. When two numbers are multiplied. such as samples from the input signal and filter coefficients as well as program instructions. To improve upon this situation. we start by relocating part of the "data" to program memory. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener.

DEPARTMENT OF ECE PAGE NO. the program instructions can be pulled from the instruction cache. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. Some DSPs have on-board analog-to-digital and digital-toanalog converters. all DSPs can interface with external converters through serial or parallel ports. on additional executions of the loop. providing higher speed. the coefficient comes over the program memory bus. the program instructions must be passed over the program memory bus. a feature called mixed signal. This means that the same set of program instructions will continually pass from program memory to the CPU. the Harvard architecture uses separate memories for data and instructions. DSP algorithms generally spend most of their execution time in loops. and the program instruction comes from the instruction cache. This is a small memory that contains about 32 of the most recent program instructions. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. This allows .4. this efficient transfer of data is called a high memory-access bandwidth. In the jargon of the field. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. However.-44 . providing an additional interface to off-chip memory and peripherals. such as instructions. However. In comparison. The first time through a loop.32-BIT FLOATING POINT PROCESSOR TEC Figure 4.

logical operations (AND.-45 . one for each of the two memories. All of the steps within the loop can be executed in a single clock cycle. such as shifting. and places the result into another register.4. Digital Signal Processors are designed to implement tasks in parallel. and is quite transparent to the programmer. and similar functions. specifying where the information is to be read from or written to. DEPARTMENT OF ECE PAGE NO. In a single clock cycle. accessible at 40Mwords/second (160 Mbytes/second). absolute value. In simpler microprocessors this task is handled as an inherent part of the program sequencer. This simplified diagram is of the Analog Devices SHARC DSP. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. a multiplier. and the two results returned to any of the 16 registers. The math processing is broken into three sections. extracting and depositing segments. data from registers 8-15 can be passed to the ALU. conversion between fixed and floating point formats. multiplies them. OR. NOT). XOR. an arithmetic logic unit (ALU).32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. These control the addresses sent to the program and data memories. Fig 4. The ALU performs addition. Compare this architecture with the tasks needed to implement an FIR filter. At the top of the diagram are two blocks labelled Data Address Generator (DAG). .2: Typical DSP architecture. subtraction. data from registers 0-7 can be passed to the multiplier. and so on. for 32 bit data. Elementary binary operations are carried out by the barrel shifter. rotating. The multiplier takes the values from two registers. and a barrel shifter.

Fixed point DSPs are cheaper than floating point devices. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. since it requires multiple cycles for each operation. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. Today. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits.-46 . the multiplier and ALU must be able to quickly perform floating point arithmetic. a necessity to implement counters. However. a result of the hardware being highly optimized for math operations. TMS320C5x™ and TMS320C2x™ DSPs. However." rather than just “Floating Point.or floating-point decision in the past. respectively. including a 53-bit mantissa and an 11-bit exponent). floating point programs often have a shorter development cycle. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. Double-width precision achieves much greater precision and dynamic range at the expense of speed. TMS320C64x™ DSPs. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. DEPARTMENT OF ECE PAGE NO. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. loops. it depends on the internal architecture .and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. since the programmer doesn’t generally need to worry about issues such as overflow. the latter normalized in the form of scientific notation.32-BIT FLOATING POINT PROCESSOR 4. and an 8-bit exponent. the instruction set must be larger and so on. are based on single16-bit data paths. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). thus supporting a vastly greater dynamic range than is available with the fixedpoint format. with architectures designed for handheld and control applications. and signals coming from the ADC and going to the DAC. As the terms fixed. Comparison between Fixed Point and Floating Point System: TEC Both fixed. All floating point DSPs can also handle fixed point numbers. By contrast. the SHARC devices are often referred to as "32-bit DSPs. and executes them with equal efficiency.and floating-point indicate. . with DSPs the speed is about the same. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15.For instance. underflow and round-off. though. floating-point DSPs support either integer or real arithmetic. Tradeoffs of cost and ease of use often heavily influenced the fixed. For this reason." fixed point arithmetic is much faster than floating point in general purpose computers. the SHARC DSPs are optimized for both floating point and fixed point operations.5. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. All the registers and data buses must be 32 bits wide instead of only 16. While fixed-point DSP hardware performs strictly integer arithmetic. The internal architecture of a floating point device is more complicated than for a fixed point device. In addition.

we need to scale the values being added. really bad.. while for a fixed point number it is only about ten-thousand to one. suppose we store the number 10. Although this is an extreme case. and add the product to an accumulator. floating point has such low quantization noise that these techniques are usually not necessary. .000 as a signed integer. Standard deviation of this quantisation noise is about one-third of the gap size. This strategy works very well. For instance. The gap between numbers is one ten-thousandth of the value of the number we are storing. although it does limit how some algorithms must be carried out. and will correspondingly add quantization noise on each step.e. This is a special register that has 2-3 times as many bits as the other memory locations. In other words. This is because the gaps between adjacent numbers are much larger.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. floating point has roughly 3. each time we store a number in floating point notation. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. To avoid overflow. The same thing happens when a number is stored as a 16-bit fixed point value. in a 16 bit DSP it may have 32 to 40 bits. higher dynamic range. this accumulator is just another 16 bit fixed point variable. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance.5. Suppose we store in a 32 bit floating point format. in a 500 coefficient FIR filter. To store the number. we loop through each coefficient. except that the added noise is much worse. For example. this quantization noise will simply add. In traditional microprocessors. In comparison. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. it illustrates the main point when many operations are carried out on each sample. multiply it by the appropriate sample from the input signal. while floating point devices have better precision. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one.000 times less quantisation noise than fixed point. DSPs handle this problem by using an extended precision accumulator. it must be round up or down by a maximum of one-half the gap size i.-47 . Here's the problem. For instance. Fixed point DSPs are generally cheaper. while in the SHARC DSPs it contains 80 bits for fixed point use. it's bad. It can be rated in the form of signal to noise ratio and quantisation noise. Noise is signal is usually represented by its standard deviation. To do this. In the worst case. we add noise to the signal. DEPARTMENT OF ECE PAGE NO. and a shorter development cycle. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. This extended range virtually eliminates round-off noise while the accumulation is in progress. greatly lowering the signal-to-noise ratio of the system.1: Fixed versus floating point. the noise on each output sample may be 500 times the noise on each input sample. Suppose we implement an FIR filter in fixed point.

While they can be written in fixed point. the numbers take care of themselves. if it is more complicated. such as spectral analysis and FFT convolution. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. In comparison. In comparison. television and other video signals typically use 8 bit ADC and DAC. are very detailed and can be much more difficult to program. For instance. but a more expensive final product.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. The next thing to look at is the complexity of the algorithm that will be run . how the quantization errors are accumulating. the cost of the product will be reduced. think floating point. . Most DSP techniques are based on repeated multiplications and additions. In many applications. these issues do not arise in floating point.If it is relatively simple. floating point will generally result in a quicker and cheaper development cycle. and what scaling needs to take place. and the precision of fixed point is acceptable. frequency domain algorithms. When fixed point is chosen. In fixed point. In contrast. The programmer needs to continuously understand the amplitude of the numbers. but the development cost will probably be higher due to the more difficult algorithms. and almost certainly need floating point to capture the large dynamic range. think fixed point. the possibility of an overflow or underflow needs to be considered after each operation. In the reverse manner. professional audio applications can sample with as high as 20 or 24 bits. making them suitable for fixed point. the development time will be greatly reduced if floating point is used. 12-14 bits per sample is the crossover for using fixed versus floating point. FIR filtering and other operations in the time domain only require a few dozen lines of code. DEPARTMENT OF ECE PAGE NO. floating point systems are also easier to develop algorithms for.-48 . For example.

The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. Rn. or into one of the extended precision accumulators. In contrast. many options are needed for fixed point. DEPARTMENT OF ECE PAGE NO. This table also shows that the numbers may be either signed or unsigned (S or U). the value of any two registers can be multiplied and placed into another register. Fx. The vertical lines indicate options. MRF = Rx * Ry. and MRB = Rx * Ry.5. Rx. and Fy are any of the 16 data registers. While only a single command is needed for floating point. where Fn.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. and Ry refer to any of the 16 data registers. This describes the ways that multiplication can be carried out for both fixed and floating point formats.-49 . In other words. The RND and SAT options are ways of controlling rounding and register overflow. For instance. . These are the many options needed to efficiently handle the problems of round-off. These are the multiplication instructions used in the SHARC DSPs. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. look at all the possible commands for fixed point multiplication.2: Fixed versus floating point instructions. It could not be any simpler. and may be fractional or integer (F or I). Fn = Fx * Fy. scaling. and format. the floating point programmer can spend his time concentrating on the algorithm. In comparison. and MRF and MRB are 80 bit accumulators.

DEPARTMENT OF ECE PAGE NO. 32-bit floating point has a higher dynamic range. as shown in (c). The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. However. A good example of this is cellular telephones. This is mainly driven by consumer products that must have low cost electronics.6. a cost difference of only a few dollars can be the difference between success and failure. As illustrated in (a).1: Major trends in DSPs. In comparison. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. and another 49% are considering the change. About twice as many engineers currently use fixed point as use floating point DSPs. such a . floating point is more common when greater performance is needed and cost is not important. When you are in competition to sell millions of your product.32-BIT FLOATING POINT PROCESSOR 4. such as cellular telephones. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low. this depends greatly on the application. suppose you are designing a medical imaging system. However. meaning there is a greater difference between the largest number and the smallest number that can be represented. floating point is the fastest growing segment. about twice as many engineers use fixed point as use floating point DSPs. In (b).-50 . For instance. As shown in (c). over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs .6 Trends in DSP: TEC Figure 4.

a 32-bit product would be needed. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. 16. The first is the I/O signal word width. exponentiation vastly increases the dynamic range available for the application. First. or a 48-bit product for a single 24-bit by 24-bit multiplication. Second.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. which would go beyond most application requirements in accuracy. ensuring greater accuracy in end results. Fortunately. Three data word widths are important to consider in the internal architecture of a DSP. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. this overflow headroom is 8 bits. Finally. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. 4. the floating point market is the fastest growing segment. iterated MACs require additional bits for overflow headroom. Third. floating-point coefficients can be 24 bits or 53 bits of precision. While fixed-point coefficients are 16 bits.point devices. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. but the performance is critical. and can be 8. 16 bits for fixed-point. the same as the signal data in DSPs. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow).-51 . depending whether single or double precision is used. the cost of the DSP is insignificant. For a single 16-bit by 16-bit multiplication. in integer as well as real values. In fixed. However. or 32 bits for fixed-point DSPs. The second word width is that of the coefficients used in multiplications. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. which is 24 bits for floating-point. at a price of several hundred-thousand dollars each. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). In spite of the larger number of fixed point DSPs being used. the internal representations of data in floating-point DSPs are more exact than in fixed-point. . DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. Only a few hundred of the model will ever be sold. For this application.

manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. One can fabricate a chip contains more than Million of gates. This created new challenges to digital designers as well as circuit designers. Designers felt need to automate these processes. because of manual converting the design from one level to other.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. Later Integrated Circuits (ICs) were invented. Rapid advances in Software Technology and development of new higher level programming languages taken place. DEPARTMENT OF ECE PAGE NO. i. multiplexes. This may be leading to development of sophisticated electronic products for both consumer as well as business. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools.e. In this process.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. At this point design process started getting very complicated.. I/O peripheral devices and etc. counters. i. This way of designing (using CAD tools) is certainly a revolution in electronic industry. Using latest CAD tools could solve the problem. one can create digital sub blocks (adders. and etc. At this point design process still became critical. With advent of new technology.) on an IC. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. CMOS (Complementary Metal Oxide Semiconductor) process technology. Using design at this level. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration).-52 . . for design electronics circuits with assistance of software programs. This level is LSI (Large Scale Integration). using this scale of integration people succeeded to make digital subsystems (Microprocessor. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale.. registers.e. It became very easy to a designer to verify functionality of design at various levels.) on a chip.

. DEPARTMENT OF ECE PAGE NO.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.32-BIT FLOATING POINT PROCESSOR 5.2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5.-53 .

documentation. however.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. available from IEEE. This new version of the language is known as the IEEE STD 1076-1993. and verification of the digital systems was generated. DEPARTMENT OF ECE PAGE NO.-54 .The complete language.3. According to IEEE rules. Therefore. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. The language can be used as a communication medium between different CAD and CAE tools . the language was upgraded with new features.1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). The language can be used as exchange medium between chip vendors and CAD tool users. Thus. this version of the language is known as the IEEE STD 1076-1987. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. 5. models written in this language can be verified using a VHDL simulator. the syntax of many constructs was made more uniform. ranging from the algorithmic level to the gate level. Consequently. a need for a standardized hardware description language for the design.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. Reprocurement and reuse was also a big issue. This subset is usually sufficient to model most applications . 5. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. and many ambiguities present in the 1987 version of the language were resolved. The official language description appears in the IEEE standard VHDL language Reference manual. Different chip vendors can provide VHDL descriptions of their components to system designers. It is a hardware description language that can be used to model a digital system at many levels of abstraction. The language has also been recognized as an American National Standards Institute (ANSI) standard.3. The IEEE in the December 1987 standardized VHDL language.

Each Entity is described using one model. that is a digital can be modeled as asset of interconnected components. Component And2 Port (L.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. DEPARTMENT OF ECE PAGE NO. It supports both synchronous and asynchronous timing models. can be modeled as a set of interconnected subcomponents. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. B. Z:out BIT). It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. M: in BIT. . 1. The Entity is thus a hardware abstraction of the actual hardware device. The language is publicly available. can be modeled using the language. Such a model for the HALF_ADDER entity. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. Structural style of modeling: In this one an entity is described as a set of interconnected components. which contains one external view and one or more internal views. and machine-readable. The language supports three basic different styles: Structural. Various digital modeling techniques. such as finite –state machine descriptions. 5. each component. bottom-up. called an Entity. human-readable. and behavioral. End component. The internal view of the device specifies functionality or structure. Dataflow. and Boolean equations. N:outBIT). As a set of sequential assignment statements (to represent behavior) As any combination of the above three. Begin X1: Xor2portmap (A. SUM) A1: AND2portmap (A. This model specifies the external view of the device and one or more internal views. and there are no limitations imposed by the language on the size of the design. B. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. In VHDL each device model is treated as a distinct representation of a unique device. CARRY). or mixed.3.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. As a set of interconnected components (to represent structure) 2. Arbitrarily large designs can be modeled using the language. in turn.-55 . The language supports flexible design methodologies: top-down. As a set of concurrent assignment statements (to represent data flow) 3. Y: in BIT. End component.

the symbol <=implies an assignment of a value to a signal. graphical and textual simulation output viewers. do not explicitly specify the structure of the entity but merely its functionality.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. The data flow model for the half adder is described using two concurrent signal assignment statements .3. and auxiliary utilities designed for easy management of resource files. several debugging tools. which are specified inside a process statement. 5. SIMULATION TOOL 5. These sets of sequential statements. Two component declarations are present in the declarative part of the architecture body. 5. designs.In a signal assignment statement.4 DATAFLOW STYLE OF MODELING: In this modeling style. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. 5. single simulation kernel. 13641995 standard.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0.3. and EDIF and mixed VHDL-Verilog-EDIF designs. The declared components are instantiated in the statement part of the architecture body using component instantiation. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position. 5. The architecture body is composed of two parts: the declaration part and the statement part.2.1. 1076-1993 standard.32-BIT FLOATING POINT PROCESSOR TEC End ha. the flow of data through the entity is expressed primarily using concurrent signal assignment statements. Verilog. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL.-56 . . Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std. It comprises three different design entry tools.4.4 INTRODUCTION TO HDL TOOLS 5. The name of the architecture body is ha . VHDL'93 compiler. and libraries.the entity declaration for half adder specifies the interface ports for this architecture body. Verilog compiler. A process statement is a concurrent statement that can appear with in an architecture body.4.4. DEPARTMENT OF ECE PAGE NO.1.

2. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. the maintenance. Perl scripts. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. 1. HDL Editor: HDL Editor is a text editor designed for HDL source files. 5. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029. It displays specific syntax categories in different colors (keyword coloring). The contents of the default-working library of the design. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. 4. Design Browser: The Design Browser window displays the contents of the current design.-57 . The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). 3. It allows you to graphically edit waveforms so as to create desired test vectors. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. 5. the communication of hardware design and test verification data. b. The VITAL-compliant models can be annotated with timing data from SDF files.0 May 1997). Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams.1. The editor automatically translates graphically designed diagrams into VHDL or Verilog code.0. DEPARTMENT OF ECE PAGE NO. that is: a.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. .1/D1. The keyword coloring is also available when HDL Editor is used for editing macro files.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. SDF files must comply with OVI Standard Delay Format Specification Version 2. The editor is tightly integrated with the simulator to enable debugging source code. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. Resource files attached to the design. and Tcl scripts.4. modification and procurement of hardware system.

Verilog. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. VHDL. Verilog. Active-HDL provides three compilers. A net list is a set of statements that specifies the elements of a circuit (for example. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator. a source file can be on of the following: • VHDL file (.vhd) • Verilog file (. The structure of the design unit selected for simulation. macros. . the compiler analyzes the intermediate VHDL. Verilog. 6. or EDIF file containing HDL code (or net list) generated from the diagram. DEPARTMENT OF ECE PAGE NO. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands.4. 5. When you choose a menu command or toolbar button for compilation. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel.32-BIT FLOATING POINT PROCESSOR TEC c.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. d. and scripts.bde) In the case of a block or state diagram file. Compilation: Compilation is a process of analysis of a source file. In Active-HDL. Cycle-based simulation is significantly faster than event-driven. and EDIF.-58 .asf) • Block diagram file (. All Active-HDL tools output their messages to Console. or EDIF objects declared within a selected region of the current design.EDIF) • State diagram file (. transistors or gates) and their interconnection.v) • EDIF net list file (. respectively for VHDL. • The Active-HDL simulator provides two simulation engines.

32-BIT FLOATING POINT PROCESSOR TEC Fig4.4. ISE enables you to start your design with any of a number of different source types.6 SYNTHESIS TOOL: 5. DEPARTMENT OF ECE PAGE NO. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.6. 5. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.4.4.5. .3. Verilog HDL.1: Simulation 5. and finally produce a bit stream for your device configuration. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.-59 . This overview explains the general progression of a design through ISE from start to finish. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE.6.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.The ISE Text Editor is provided in ISE for entering design code and viewing reports.2 Design Entry: • ISE Text Editor . including ModelSim Xilinx Edition and the HDL Bencher test bench generator. including: • HDL (VHDL.

4.The Map program maps a logical design to a Xilinx FPGA. equations. view.The Chip Viewer tool provides a graphical view of the inputs and outputs. macro cell details. PACE .The Constraints Editor allows you to create and modify the most commonly used timing constraints. Timing Analyzer .6.State CAD allows you to specify states. With Timing Analyzer. and after fitting and routing a CPLD design.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. Chip Viewer (CPLD only) .The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. CORE Generator . and to view and modify the placed design. analysis can be performed immediately after mapping.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. DEPARTMENT OF ECE PAGE NO.The FPGA Editor allows you view and modify the physical implementation.-60 . and produces output for the bit stream generator. FIFOs. Constraints Editor . Place and Route (PAR) . and actions in a graphical editor. The state machine will be created in HDL. transitions. Floor planner . Fit (CPLD only) .3 Implementation: • Translate . State CAD State Machine Editor .32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor .The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. places and routes the FPGA.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. and pin assignments. transforms.The PAR program accepts the mapped design. • • • • 5. including routing. • • • • • • • . placing or routing an FPGA design. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O. and Area Group constraints. and memories. Global logic.The Floor planner allows you to view a graphical representation of the FPGA. Map . to system-level building blocks such as filters. FPGA Editor .

4 Device Download and Program File Formatting: • BitGen . and subsequently allows you to configure your device.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices.4.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration.6.32-BIT FLOATING POINT PROCESSOR TEC 5. DEPARTMENT OF ECE PAGE NO.The iMPACT tool generates various programming file formats. XPower . • • • .-61 . Integration with ChipScope Pro. iMPACT .

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . DEPARTMENT OF ECE PAGE NO. subtraction.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition.1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. . multiplication and division are done using active HDL tool and the results are as follows: 6.-62 .

. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form.32-BIT FLOATING POINT PROCESSOR TEC 6.2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format.-63 . DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6.

32-BIT FLOATING POINT PROCESSOR TEC 6. DEPARTMENT OF ECE PAGE NO.3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form. .-64 . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6.

-65 . Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form.4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .32-BIT FLOATING POINT PROCESSOR TEC 6. . DEPARTMENT OF ECE PAGE NO.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6.

. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication.-66 . subtraction. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. Basic arithmetic operations such as addition.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. • • Procedures for performing basic arithmetic operations are been formed.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation. DEPARTMENT OF ECE PAGE NO. The Functional-simulation has been successfully carried out with the results matching with the expected ones.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. • 7.

-67 . x-rays. Wide dynamic range also plays a part in robotic design. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. feedback is well out of the ordinary operating range. however. Normally. However. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. enable imaging systems to achieve a much higher level of recognition and definition for the user. together with the device’s more accurate internal representations of data. The radar system may be tracking in a range from 0 to infinity. but need to use only a small subset of the range for target acquisition and identification. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. DEPARTMENT OF ECE PAGE NO. The wide dynamic range of a floating-point DSP. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. For instance. or something might unexpectedly block its range of motion. In these cases. Since the subset must be determined in real time during system operation. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. Many levels of signal input from light. The greater precision of signal data. unpredictable events can occur on an assembly line. . the robot might weld itself to an assembly unit. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information.

(1986) A 32 bit processor architecture for direct execution of Forth. Science Research Associates.. pp. (1981) A survey of high-level language machines in Japan. (Ed.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman. New York McKeeman.org/portal/web/csdl/doi/10. 28-30 November 1986.com . July 1981.ieeexplore. 197-210 Jones. (1975) Stack computers. In: 1986 FORML Conf. W. M.46 www. Pacific Grove CA. T. M. H. 14(7) 68-78 REFERENCES www. & Zaremba. Chicago. J. Prentice-Hall. 1975..2007.org www. Williams. pp.-68 . DEPARTMENT OF ECE PAGE NO.. Hayes. Computer. (1987) The Implementation of Functional Programming Languages. In: Stone.1109/SNPD. 281-317 Yamamoto.computer.ieee.) Introduction to Computer Architecture. P. S. Proc.intel. R.

variable Temp :Std_logic_vector(6 downto 0).Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE. --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc.std_logic_unsigned.-69 . end Fadd.all. b : in std_logic_vector(31 downto 0). begin temp:=x. use IEEE. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0). use IEEE. DEPARTMENT OF ECE PAGE NO. y : out std_logic_vector(31 downto 0) ).Shift the that has lesser Exponent by Ea-Eb places to the right * -3.std_logic_arith.std_logic_1164.all.all.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1. use IEEE.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.Compute Ea-Eb -2.

-.Resultant Exponent variable Ns : integer. return sum. IE:=Eb(6 downto 0). Es:=Eb(7) . end loop.Sign Of Resultant Mantissa variable W.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. else TEC Sum:=Sum. --***************************************************************** --*Equalization of Exponents includes two steps --*1. end loop. -. variable X : std_logic_vector(31 downto 0). -. a :=Acc(31).Internal Register variable MbIn : std_logic_vector(22 downto 0). end if.Subtraction of Exponents --*2. b :=Data(31). --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).b : std_logic. -. -.Final Result begin MaIn:=Acc(22 downto 0). -. end function. MbIn:=Data(22 downto 0). -.Z : std_logic_vector(1 downto 0). -. Z :=(a&b). for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)).Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Two Exponents including Sign variable IR : std_logic_vector(22 downto 0).Mb : std_logic_vector(22 downto 0). -. Ea :=Acc(30 downto 23).Eb : std_logic_vector(7 downto 0). Eb :=Data(30 downto 23).Mangitude Of Two mantissas variable ES : std_logic. -.Sign Of Resulant Exponent variable a. Ma:=MaIn.Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn.Sign Of Two mantissas variable Sign : std_logic.Number Of Shifts variable Ma.s2 : std_logic. -.Internal Register variable Ea.-70 .Sign Of Two exponents variable s1. -. DEPARTMENT OF ECE PAGE NO. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).

DEPARTMENT OF ECE PAGE NO. end loop. when "11" => Mb:=MbIn. end loop. Ma:=MaIn. IE:=IE. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). . Ma:=Ma. Mb:=Mb. ES:=Ea(7). IE:=Eb(6 downto 0). IE:=Ea(6 downto 0). IE:=Ea(6 downto 0). ES:=Ea(7). else NS:=Ns. Es:=Ea(7). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end loop.-71 . IE:=Ea(6 downto 0). Ma:=MaIn. Ma:=MaIn. end if. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). when "10" => Mb:=MbIn. end loop. ES:=Eb(7). ES:=Ea(7). NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)).32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). when "01" => Mb:=MbIn.

if(Ea>Eb) then sign:='0'. else sign:=sign. W :=(s1&s2). Ma:=Ma. else NS:=Ns. IE:=IE. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. sign:='1'. DEPARTMENT OF ECE sign:='0'. --***********logic for the sign of the mantissa********************** s1:=Acc(31). elsif(Ma=Mb) then sign:='0'. s2:=Data(31). PAGE NO. end loop. end if. if(Ea>Eb) then sign:='1'. else sign:=sign. end case. IE:=Eb(6 downto 0). --******************Addition of Mantissas**************************** IR:=Ma+Mb. elsif(Ma<Mb) then sign:='1'. elsif(Ea<Eb) then sign:='1'. case W is when "00" => when "11" => when "01" => when "10" => . ES:=Ea(7).-72 .32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end if. Mb:=Mb. ES:=Eb(7). end if. when others => Null.

end function. begin process(a. else sign:=sign. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. end case.-73 * . end if. elsif(Ma=Mb) then sign:='0'. end if.b) begin y<=float_add(a. end Fadd. DEPARTMENT OF ECE PAGE NO. when others => null.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)). else sign:=sign. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . end process. return X.b). elsif(Ma<Mb) then sign:='0'.

. begin temp:=x. use ieee. b : in STD_LOGIC_VECTOR (31 downto 0).std_logic_1164.Compute Ea-Eb 2. use ieee.all.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.std_logic_unsigned.all. variable Temp : Std_logic_vector(6 downto 0).-74 .Shift the that has lesser Exponent by Ea-Eb places to the right * 3.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.32-BIT FLOATING POINT PROCESSOR ----1. end Fsub. DEPARTMENT OF ECE PAGE NO. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout.std_logic_arith.all. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). use IEEE. y : out std_logic_vector(31 downto 0)).

-.s2 : std_logic.Subtraction of Exponents * * . --*********************variable Declarations*********************** TEC variable MaIn. DEPARTMENT OF ECE PAGE NO. MbIn:=Data(22 downto 0). -. -. -.b : std_logic.Sign Of Resultant Mantissa variable W.Z : std_logic_vector(1 downto 0). variable X : std_logic_vector(31 downto 0). b :=Data(30).-75 .Internal Register variable Ea.32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i.Mangitude Of Two Mantissas variable ES : std_logic. -. end function.Sign Of Two Mantissas variable sign : std_logic.Sign Of Two Exponents variable s1.MbIn: std_logic_vector(22 downto 0). Z :=(a&b). -. -.Eb : std_logic_vector(7 downto 0). end if.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Sign Of Resulant Exponent variable a. else Sum:=Sum. -. a :=Accout(30). -. end loop. Ea :=Accout(30 downto 23).Resultant Exponent variable Ns : integer. return sum. --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. -. -.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0).Mb : std_logic_vector(22 downto 0).Final Result begin MaIn:=Accout(22 downto 0).Number Of Shifts variable Ma. Eb :=Data(30 downto 23).

IE:=Eb(6 downto 0). DEPARTMENT OF ECE PAGE NO. end if. end loop.32-BIT FLOATING POINT PROCESSOR --*2. Mb:=Mb. Ma:=Ma. IE:=IE. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). ES:=Eb(7). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). else NS:=Ns. Ma:=MaIn. end loop. . TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). ES:=Ea(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)).-76 . Ma:=MaIn. IE:=Ea(6 downto 0). IE:=Ea(6 downto 0). when "01" => Mb:=MbIn. ES:=Ea(7). ES:=Ea(7). end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn.

if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). . TEC Ma:=MaIn. IE:=Eb(6 downto 0). IE:=Ea(6 downto 0). end if. Ma:=Ma. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end case.32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. ES:=Ea(7).-77 . end loop. Ma:=MaIn. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Eb(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end loop. ES:=Eb(7). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). else NS:=Ns. ES:=Ea(7). when "11" => Mb:=MbIn. DEPARTMENT OF ECE PAGE NO. end loop. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). when others => null. --******************Subtraction of Mantissas************************ IR:=Ma-Mb. IE:=Eb(6 downto 0). Mb:=Mb. IE:=IE.

end if. DEPARTMENT OF ECE PAGE NO. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. elsif (Ma=Mb) then sign:='0'. else sign:=sign. elsif(Ma<Mb) then sign:='1'. end if.32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). . s2:=Data(31). end if. elsif (Ea<Eb) then sign:='0'. elsif(Ma<Mb) then sign:='0'. when "11"=> sign:='1'. case W is when "00"=> sign:='0'. elsif (Ma=Mb) then sign:='0'.-78 . else sign:=sign. else sign:=sign. when "10"=> if (Ea>Eb)then sign:='1'. else sign:=sign. elsif(Ea<Eb) then sign:='1'. when "01"=> if(Ea>Eb)then sign:='0'. W:=(s1&s2). end if. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'.

DEPARTMENT OF ECE PAGE NO. end f_sub. b: in STD_LOGIC_VECTOR (31 downto 0). -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1.b).std_logic_unsigned. y: out STD_LOGIC_VECTOR (31 downto 0) ).all.Multiplication of the Mantissas * * -************************************************************************** library IEEE.Addtion of the Exponents 5. end function.-79 . use IEEE. . --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0).b) begin y<=float_sub(a.all.32-BIT FLOATING POINT PROCESSOR TEC when others=> null. use IEEE. end process. begin process(a. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)). return X. end Fmul.std_logic_1164. end case.

-. -.e2 : std_logic_vector(7 downto 0). . -. e1 :=Accout(30 downto 23).Carry variable W.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. Z :=(s1&s2). s2:=Data(31). m2 :=Data(10 downto 0).Final Result begin Carry:='0'.Sign Two Exponents variable s1.s2 : std_logic.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout. -.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0). -.Sign Of Resultant Mantissa variable a.Two Exponents Icluding Sign variable m1.Resultant exponent variable m : std_logic_vector(21 downto 0).sign Two Mantissas variable Ea. end case. --************logic for the sign of the Mantissa******************* s1:=Accout(31). m1 :=Accout(10 downto 0). -. case Z is when "00" => s:='0'. -.b : std_logic. -.m2 : std_logic_vector(10 downto 0). DEPARTMENT OF ECE PAGE NO. -.Magnitude O Two Mantissas variable s : std_logic.Magnitude Of Two Exponents variable c : std_logic. variable x : std_logic_vector(31 downto 0).Resultant Mantissa variable carry : std_logic. when "11" => s:='0'.-80 . when others=> s:='1'. -. -.Eb : std_logic_vector(6 downto 0).Z : std_logic_vector(1 downto 0). e2 :=Data(30 downto 23).

elsif(Ea<Eb) then c:='0'. W :=(a&b). e:="0000000". else c:='0'. e:=Ea-Eb. e:=Ea+Eb.-81 . case W is when "00" => c:='0'. --*************logic for multiplication************************* m:=m1*m2. when "10" => if(Ea>Eb) then c:='1'. Eb:=e2(6 downto 0). end case. a :=Accout(30). when "01" => if(Ea>Eb) then c:='0'. elsif(Ea<Eb) then c:='1'. e:=Ea-Eb.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). b :=Data(30). when "11" => when others => null. e:=Ea+Eb. e:="0000000". end if. . DEPARTMENT OF ECE PAGE NO. e:=Eb-Ea. else c:='0'. end if. e:=Eb-Ea. c:='1'.

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

elsif(Ea<Eb) then c:='0'. b :=e2(7). when "10"=> if(Ea>Eb) then c:='1'. e:="0000000". if(Ea>Eb) then c:='0'. else c:='0'. e:=Ea+Eb. elsif(Ea<Eb) then c:='0'. if(Ea>Eb) then c:='1'. e:="0000000". end if. elsif(Ea<Eb) then c:='0'. e:=Ea+Eb. e:=Ea-Eb. Eb:=e2(6 downto 0). Z :=(a&b). end if. a :=e1(7).-86 . else c:='0'. e:=Eb-Ea. else c:='0'. end if. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. . e:=Eb-Ea. e:="0000000". case Z is when "00" => if(Ea>Eb) then c:='0'. e:=Eb+Ea.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). e:=Ea-Eb. elsif(Ea<Eb) then c:='1'.

b) begin Y<=float_div(a. end process. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). end case.b). return X. DEPARTMENT OF ECE PAGE NO.-87 . end F_div. TEC . end function. e:="0000000". else c:='0'. when others=> null.32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. begin process(a. end if.

- C Syntax high-level data abstraction have a close relationship with the resulting object code, and yet provide relatively high-level data abstraction. The development of this syntax was a major milestone in the history of computer science as it was the first widely successful high-level language for operating-system development.by Harshit Gupta

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