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TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

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. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations.) to plus infinity (+ ). As shown in Figure 1. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2. the real-number system comprises the continuum of real numbers from minus infinity (.-5 . only a subset of the real-number continuum can be used in real-number calculations. DEPARTMENT OF ECE PAGE NO. Figure 2.1: Binary Real Number System Because the size and number of registers that any computer can have is limited. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. As shown at the bottom of Figure 1.1.

signed integer uses two's complement to make the range include negative numbers. the digit string can be of any length. 2. performance attributes.767. processor and system costs. and ease of development. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data. the stored number can take on any integer value from 0 to 65. although a different length can be used. Digital Signal Processing can be divided into two categories. In unsigned integer. In fixed-point systems. low-cost development tools. the 65. while floating-point DSPs support either integer or real arithmetic. DEPARTMENT OF ECE PAGE NO.2. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. There are four common ways that these 216 ' 65.535. Similarly. but decimal fixed point is common in commercial applications. In common mathematical notation. Software programmable for maximum flexibility and supported by easy-touse.-6 . With unsigned fraction notation.536 possible bit patterns can represent a number. the signed fraction format allows . from -32. Motorola manufactures a family of fixed point DSPs that use 24 bits. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic.536 levels are spread uniformly between 0 and 1. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. Lastly. Among the key factors to consider are the computational capabilities required for the application. Fixed-point Vs floating-point in digital signal processing Fig 2. the number is an integer). These refer to the format used to store and manipulate numbers within the devices. Balancing these factors together. For instance. DSPs enable designers to build innovative features and differentiating value into their products.768 to 32. some specific assumption is made about where the radix point is located in the string.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. designers can identify the DSP that is best suited for an application. Fixed point DSPs usually represent each number with a minimum of 16 bits. fixed point and floating point.

but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . A key feature of floating point notation is that the represented numbers are not uniformly spaced. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. 2324. the SHARC devices are often referred to as "32-bit DSPs." 2. the largest and smallest numbers are ±3.4 ×1038 and ±1.2 ×1038. This is known as the significand. but small gaps between small numbers. it depends on the internal architecture. The speed of floating-point operations is an important measure of performance for computers in many application domains.296 to be exact. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. This is important because it places large gaps between large numbers. This results in many more bit patterns than for fixed point. The logic for these is different from the ordinary arithmetic functions." rather than just "Floating Point. and executes them with equal efficiency. The radix point is not explicitly included. it can be placed anywhere relative to the significant digits of the number. 2. and signals coming from the ADC and going to the DAC. DEPARTMENT OF ECE PAGE NO.754-1985). which is capable of representing real and decimal numbers. equally spaced between -1 and 1. All floating point DSPs can also handle fixed point numbers. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. It is measured in” FLOPS”. respectively.However. In the most common format (ANSI/IEEE Std.4. the SHARC DSPs are optimized for both floating point and fixed point operations. For this reason. loops. or sometimes the mantissa (see below) or coefficient.32-BIT FLOATING POINT PROCESSOR TEC negative numbers.967. a necessity to implement counters. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix).-7 . The floating-point operations are incorporated into the design as functions. This position is indicated separately in the internal representation. floating point DSPs typically use a minimum of 32 bits to store each value. For instance. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. that is.294. The represented values are unequally spaced between these two extremes. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. Floating point A floating-point number is the one.3. The term” floating point” refers to the fact that the radix point can "float".In comparison. and floating-point representation can thus be thought of as a computer realization of scientific notation.

IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. which modifies the magnitude of the number. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. Symbolically. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. DEPARTMENT OF ECE PAGE NO. so when stored in the same space.Fraction. and the rounding behaviour of operations. The length of the significand determines the precision to which numbers can be represented. 1 for negative values. with an average error of about 3%. or to the right of the rightmost digit. composed as integer.-8 . the format of the representations. floating-point numbers achieve their greater range at the expense of precision. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. this final value is where s is the value of the significand (after taking into account the implied radix point).5. The significand is multiplied by the base raised to the power of the exponent. 10 or 16. 2. computers used many different forms of floating-point. These differing systems implemented different parts of the arithmetic in hardware and software. These differed in the word sizes.32-BIT FLOATING POINT PROCESSOR TEC significant digit. Prior to the IEEE-754 standard. (This is because the exponent field is in . A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. b is the base. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. and e is the exponent. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. A signed integer exponent. Significand is a real number. also referred to as the characteristic or scale. The floating-point format needs slightly more storage (to encode the position of the radix point).

-9 . IEEE-754 specifies binary representations for floating point numbers: Table 2. and the mantissa. represents the precision bits of the number. the exponent. a bias is added to the actual exponent in order to get the stored exponent.) This can be exploited in some applications. 0 denotes a positive number. 1 denotes a negative number. also known as the significand. Flipping the value of this bit flips the sign of the number. So.f.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. To do this. 3. to sum up: 1. It is composed of an implicit leading bit and the fraction bits. The first bit of the mantissa is typically assumed to be 1. The Mantissa: The mantissa. 2. The Exponent: The exponent field needs to represent both positive and negative exponents. even though there are infinitely many real numbers (even between 0 and 1). The sign bit is 0 for positive. 1 for negative. 4. where f is the field of fraction bits. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. such as volume ramping in digital sound processing.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. The exponent's base is two. There are many formats that are used for representation of floating point number. This means that at most 232 possible real numbers can be exactly represented. A float is represented using 32 bits. DEPARTMENT OF ECE . and each possible combination of bits represents one real number. A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. The Sign Bit: The sign bit is as simple as it gets. or 1023 plus the true exponent for double precision. The exponent field contains 127 plus the true exponent for single-precision.

DEPARTMENT OF ECE PAGE NO. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. S. which may be represented as numbered from 0 to 31.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2.5. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude. then V=-Infinity If E=255 and F is zero and S is 0.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero. left to right. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010).32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude. then V=NaN ("Not a number") If E=255 and F is zero and S is 1. the next eight bits are the exponent bits. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). 'E'.-10 . Table 2. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. then V=Infinity .1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values.5.5.

F) These are "unnormalized" values. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1. then V=-0 If E=0 and F is zero and S is 0.101 = 6.-11 .32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.101 = -6.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1. DEPARTMENT OF ECE PAGE NO.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0. If E=0 and F is zero and S is 1. If E=0 and F is nonzero.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.F) where "1. then V=0 In particular.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. then V=(-1)**S * 2 ** (-126) * (0.0 The biased exponent is .0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.3125 The biased exponent is -2+127=125= (01111101 • 1.

8125 × 2 = 1.01012. 10 + 127 = 137 = 100010012.203125 × 2 = 0.25 × 2 = 0. So -1313.25 0.1015625 0.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0.312510 = 10100100001.3125 is • 0.5 × 2 = 1. • -78.0 0 1 0 1 1313.203125 0. . sign bit is 1.625 × 2 = 1.625 0.3125 0. = 1.5 × 2 = 0.25 The biased exponent: 127+6=133=(10000101 • -1313.40625 0.5 The based exponent: 127+5= (10000100 .8125 .32-BIT FLOATING POINT PROCESSOR TEC • 37.010010000101012 × 210.40625 × 2 = 0.-12 .3125 131310 = 101001000012 0. DEPARTMENT OF ECE PAGE NO.1015625 × 2 = 0.

'E'. S. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values.25 0.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0). left to right.101562510 = 0. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.1015625 is 0 00111101 110100000000000000000000 TEC 2.5. The first bit is the sign bit. DEPARTMENT OF ECE .625 0.00011012 = 1.25 1 × 2 = 0.3.5 × 2 = 1.-13 .1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0. the next eleven bits are the exponent bits. then V=NaN ("Not a number") PAGE NO.32-BIT FLOATING POINT PROCESSOR 0.5 0 × 2 = 1.5. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001).0 1 0. which may be represented as numbered from 0 to 63. The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero.

F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038. If E=0 and F is nonzero. then V=-0 If E=0 and F is zero and S is 0.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2.F) where "1.53 ~ 10308. Table 2.-14 .5.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable.6. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. using a fixed number of digits. .F) These are "unnormalized" values. then V=-Infinity If E=2047 and F is zero and S is 0. If E=0 and F is zero and S is 1. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit . The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. DEPARTMENT OF ECE PAGE NO. 15 exponent bits and 112 significand bits. then V=(-1)**S * 2 ** (-1022) * (0. floating-point notation allows calculations over a wide range of magnitudes. while maintaining good precision. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1.

2: Effective Range of IEEE Floating Point Number with Denormalized.6.-15 . Positive numbers less than 2-149 (positive underflow) . Approximate Decimal 2127 21023 ~10-44.32-BIT FLOATING POINT PROCESSOR TEC Table 2. P. U) (where B is the base of the system. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1.53 ~10-323. The number of normalized floating point numbers in a system F(B. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent. L is the smallest exponent represent able in the system. and the smallest possible value for the exponent. L. Negative numbers less than -(2-2-23) 2127 (negative overflow) 2. Negative numbers greater than -2-149 (negative underflow) 3. Normalized And Approximate Decimal Values. Zero 4. There is a largest floating point number. the range for negative numbers is given by the negation of the above values. P is the precision of the system to P numbers. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1). Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand.3 to ~10308. DEPARTMENT OF ECE PAGE NO.3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit.85 to ~1038. There is a smallest positive normalized floating-point number.

the exponent is set to -127 (E = 0). the most negative value which is defined in bias-127 exponent representation. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format.32-BIT FLOATING POINT PROCESSOR 5. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. Recently.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit .infinity. Underflow occurs when the sum of the exponents is more negative than -126. Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . If M = 0. 2. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. When this occurs. When this occurs. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations.-16 . there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127. 2. the number is exactly zero. DEPARTMENT OF ECE PAGE NO. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. the largest value which is defined in bias-127 exponent representation. However the CPU will have to perform extra arithmetic to read the number when stored in this format.

Addition 2..25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. .. For example. Floating point addition is analogous to addition using scientific notation. They are: 1. Division 2. Add the numbers with decimal points aligned. as the smaller number here is a=2. both the numbers are added. let us consider two numbers a= 2. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. Normalize the result. i.8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points. Multiplication 4. Hence the value of number ‘a’ becomes 0. Now as both the exponent values are same.0225x .8.25x and b= 1.1.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.e. But by using floating point addition this can be avoided to a little extent.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.-17 . DEPARTMENT OF ECE PAGE NO. Subtraction 3.

1. 2.876543x after shifting becomes b= 0. Thus this case can said to be having rounding errors. i. ManA as mantissa of number A. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. a =1. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number..23456709876543 x In this case the normalised result after rounding to seven digits becomes 1.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . ExpB as exponent of number B and ManB as mantissa of number B.2.-18 . If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.1. then sign of greater number is considered. b= 9. But the normalised result may sometimes carry the required result. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: .234567x and b= 9.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part.2345670 x in which the remaining part (9876543) which is discarded also carries the result. then the following result may occur: 1. 2. Now both the numbers are added.1.e. DEPARTMENT OF ECE PAGE NO.e. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value.00000009876543 x c= 1. If the numbers are represented with both positive and negative sign. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2. Consider a example in which a =1.8.8.00000009876543 x 2. The mantissa of both numbers A and B are added.8.1. signB as sign of number B. ExpA as exponent of number A .234567x b= 0. then bit 1 is represented for sign.876543x and if the addition has to be performed..

Addition of significands is done.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. 5. If not. If there is an underflow or overflow. 6. . 2. the exponent sum would have doubled the bias. Thus.2: Flow Chart for Floating Point Adder. the numbers are represented in IEEE floating point format. 4. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.1. exception is made.8. the bias value must be subtracted from the sum 3.-19 . If the exponents are stored in biased form. 1. DEPARTMENT OF ECE PAGE NO. the significand is rounded to the appropriate number of bits required and again normalization is checked. Firstly.

If the sum overflows the position of the hidden bit.2. Subtraction .32-BIT FLOATING POINT PROCESSOR TEC 7. or even zero if the numbers are equal in magnitude. When adding numbers of opposite sign.8. Consider addition of the numbers 2. Negative mantissas are handled by first converting to 2's complement and then performing the addition. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. After the addition is performed.-20 .25 becomes: The mantissas are added using integer addition: The result is already in normal form. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. cancellation may occur. resulting in a sum which is arbitrarily small. the result is converted back to signmagnitude form.340625x . Normalization in this case may require shifting by the total number of bits in the mantissa. Thus.25 in IEEE Floating Point Standard is: The number 134. The number 2. so the hidden bits can sum to no more than 3 (11). resulting in a large loss of accuracy.0625 in IEEE Floating Point Standard is: To align the binary points. 2. 2. DEPARTMENT OF ECE PAGE NO.25x and 1. then the mantissa must be shifted one bit to the right and the exponent incremented. The mantissa is always less than 2.

e.1.0225x .e.2.8. Hence the value of number ‘a’ becomes 0. both the numbers are added. Subtract the numbers with decimal points aligned.1. ExpA as exponent of number A .340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal. 2. ExpB as exponent of number B and ManB as mantissa of number B.. Normalize the result. signB as sign of number B. The mantissa of both numbers A and B are subtracted. The normalised result may contain the required number of digits discarding the unwanted part. ManA as mantissa of number A. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative..25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. then sign is represented according to the number i. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if ..-21 . i. DEPARTMENT OF ECE PAGE NO. as the smaller number here is a=2.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2.2.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . Now as both the exponent values are same.25x and b= 1.8.

340625x . 2. 4. The number 2. 6.32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign.2. 2. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. Consider subtraction of the numbers 2.25 in IEEE Floating Point Standard is: The number 134. exception is made. If the exponents are stored in biased form. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. 2. Subtraction of significands is done.-22 . 5. the exponent sum would have doubled the bias.0625 in IEEE Floating Point Standard is: To align the binary points.2.25 become: The mantissas are subtracted using integer subtraction: . Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. Thus. If not. The numbers are represented in IEEE floating point format.25x and 1. the significand is rounded to the appropriate number of bits required and again normalization is checked. DEPARTMENT OF ECE PAGE NO. Thus. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. the bias value must be subtracted from the sum 3. If there is an underflow or overflow.8.

2. then the result would be Z=X. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent . DEPARTMENT OF ECE PAGE NO. 2. then the mantissa must be shifted one bit to the right and the exponent incremented. If both the numbers X and Y are non zeros. If overflow occurs. then the significands of numbers X and Y are subtracted. Flow chart for floating point subtraction: Subtract significand si Fig 2. Z=Y.8.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. In the first step. If the significand is zero then it is returned if not significand overflow is checked. consider two numbers X and Y and the resultant be Z. If not then the result is normalized. number X is checked.2. If number X is not ‘0’.-23 . then the following steps can be followed: Exponents of both the numbers are checked.e. If overflow occurred then overflow is reported and returned.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form. If it is ‘0’ then the resultant solution Z would be Y i.3. If it is ‘0’. At this point. If the sum overflows the position of the hidden bit..8. then number Y is checked. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. If the exponents are same.

5 ----17.5 in IEEE FPS format is: . if the significand is not zero then subtraction and further process is carried out. 2.3.8.1. If underflow occurred then it is reported if not the normalized result is given out. For example. DEPARTMENT OF ECE PAGE NO. If the exponents are not same.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result. The number 18. 1. to multiply 1.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers.8.8x times 9.3. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.-24 . then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z.8 x 9. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly. 2.0 in IEEE FPS format is: The number 9.5x : Perform unsigned integer multiplication of the mantissas.

the mantissa is: The biased-127 exponents are added. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in (). When the fields are assembled in IEEE FPS format.3.-25 . The sign of the result is the xor of the sign bits of the two numbers. If the position of the hidden bit overflows. DEPARTMENT OF ECE PAGE NO.2. Block diagram of floating point multiplication: .8. the mantissa must be shifted right and the exponent incremented. the result is: 2.

-26 . At the first step. then the exponents are added and a bias of 127 is subtracted from the result. manA as mantissa of number A.8. If both the numbers X and Y are not zero. DEPARTMENT OF ECE PAGE NO. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. Thus.3. signB as sign of number B. The exponents of both the numbers are added and subtracted from the bias 127. .2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A .8. the exponent sum would have doubled the bias. If the exponents are stored in biased form.8.3.3.3. Resultant mantissa is truncated and normalized to fit for the IEEE format. Sign of the result is given by performing xor operation of signA and signB. The mantissa of both numbers A and B are multiplied. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero. XOR operation for sign bit can be given as follows: Table 2. expB as exponent of number B and manB as mantissa of number B. expA as exponent of number A .

Hence the result can be given as 1..5.8. DEPARTMENT OF ECE PAGE NO. i. Fig 2.-27 . . 2. Division Consider an example of dividing a=0.2 . When the division of both significands are done then the quotient would be 1.5.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned. So resultant exponent would be 2-3=-1.3 and b= 0.3.8.4.3 0.5 . Exponent of a is 2 and exponent of b is 3.2 =1.3: Flow Chart For Floating Point Multiplication. The resultant sign bit would be the xor operation of sign bits of X and Y. 0. in general floating point division the exponents of both the numbers are subtracted and the significands are divided.e.

8. ExpA as exponent of number A .4.4. ExpB as exponent of number B and ManB as mantissa of number B. ManA as mantissa of number A.4.1. a 24 bit quotient is produced. signB as sign of number B. If both the numbers are either positive or negative.8. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . If anyone number of the two are negative. Block diagram for floating point division: Fig 2. In the first step.-28 . The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement. then the resultant sign is also positive and is represented by bit ‘0’. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. The mantissa of both numbers A and B are divided. Normalize the result. DEPARTMENT OF ECE PAGE NO. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. 2. Special .32-BIT FLOATING POINT PROCESSOR TEC 2. Subtract the exponent of the divisor from the exponent of the dividend. Set the sign of the result. The exponents are subtracted and biased using the bias value. then the result is also negative is represented by bit ‘1’. As in floating point multiplication. When divided by a 24 bit divisor.8.

8. Considering a=0. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked.2 can be represented as M 010000001(0)11000000000000000000000 0. Number X and Y are checked.3 0.3. . If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity .2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted. For this.3 S E and b= 0. 2.Then the steps that occur are: 1.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow.-29 . 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2. DEPARTMENT OF ECE PAGE NO. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned.4. This value is called Not A Number. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero. in this case as larger number has to be subtracted from smaller number. or NaN.

DEPARTMENT OF ECE PAGE NO. If they are present..8.200 is less than . . digits may flow off the right end of the significand. If not the mantissas are divided and truncated and normalized result is given out.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. • Significand underflow: In the process of aligning significands. then those conditions are reported. 2. In some systems. As we shall discuss. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e.4.127). and it may be reported as 0. some form of rounding is required.-30 . Rounding Error In floating point arithmetic.g.This means that the number is too small to be represented. Fig 2.9.32-BIT FLOATING POINT PROCESSOR TEC 3. this may be designated as +∞ or -∞. rounding errors occur as a result of the limited precision of the mantissa .

RZ: Round toward Zero. highest precision can be achieved. Same as truncation in sign-magnitude. Normalization By normalization. For normalized floating point numbers. To efficiently use the bits available for the significand.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. Same as truncation in 2's complement.-31 . The least significant 24 bits are discarded. . RP: Round toward Positive infinity. relative errors increase as the magnitude of the number decreases toward zero. RM: Round toward minus infinity. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. The value can be kept unchanged by adjusting the exponent accordingly.10. Break ties by choosing the least significant bit = 0. The size of the absolute error is proportional to the magnitude of the number. For numbers in IEEE FPS format. the relative error is approximately since For denormalized numbers (E = 0). The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). However. RN is generally preferred and introduces less systematic error than the other rules. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. DEPARTMENT OF ECE PAGE NO. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2.

a 4-bit exponent field and a 9-bit significand field): 2.32-BIT FLOATING POINT PROCESSOR TEC Moreover. to avoid possible confusion. DEPARTMENT OF ECE PAGE NO.11. multiplication). If we assume number.-32 .g. The actual value represented is However. in the following the default normalization does not assume this implicit 1 unless otherwise specified. resulting 1.. it does not need to be shown explicitly. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. The first bit 1 before the decimal point is implicit. the bits need to be truncated to guard bit Chopping: simply drop all . extra guard bits are kept during operation. By the end of the operation. all extra bits during operation (called guard bits) are kept (e. bits are used in final representation of a bits by one of the three methods. as the MSB of the significand is always 1. Zero is represented by all 0's and is not (and cannot be) normalized. Truncation To retain maximum accuracy.

Interpretation: Value represented by guard bits is greater than 0. . the Von Neumann rounding error is unbiased. DEPARTMENT OF ECE PAGE NO. Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0.-33 . (no matter Von Neumann Rounding: If at least one of the guard bits is 1. set whether it is originally 0 or 1).. Two worst cases Both two cases can be summarized as i. add 1 to LSB . is always greater than 0. otherwise do nothing. we say this truncation error is biased.32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2.e. 3.5 round up. .

5 either up or down with equal probability (50%). . c) If the highest guard bit is 1 and the rest guard bits are all 0. it is randomly rounded . round up: Interpretation: Value represented by guard bits is 0.32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0.5 round down. DEPARTMENT OF ECE PAGE NO.-34 . the rounding depends on the LSB : if . drop all guard bits. Interpretation: Value represented by guard bits is smaller than 0. The rounding error of these cases can summarized as . round down: or if .

The logic for floating point addition. 1111. the exponent obtained by balancing operations is added to 0111. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number.e. The numbers in contention have to be first converted into the standard IEEE 784. The logic for these is different from the ordinary arithmetic functions. 1111. which is capable of representing real and decimal numbers. DEPARTMENT OF ECE PAGE NO. the sign of the floating point number. 1985 floating point standard representation before any sort of operations are conducted on them. The floating-point operations are incorporated into the design as functions. Therefore zero is represented by 0111. subtraction.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER . The exponent in this IEEE standard is represented in excess-127 format. multiplication and division is presented in the following pages. Positive numbers are represented by binary values greater than 0111.-35 . 1111 and negative numbers are represented by binary values less than it. The MSB is the sign-bit i. I.3 Floating Point Functions A floating-point number is the one.e. The next eight bits are that of the exponent. The above representation is the IEEE-784 1985 standard representation. .

• • . Once the exponents are normalized. So. The mantissas are then added to each other and the result is then stored in a temporary register. we have to first normalize their exponents. These numbers are stored into the memory from which they are read and processed. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. namely Accumulator and the Temp register that loads the value appearing on the data bus.-36 . So to add their mantissa’s.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. This is done till the lower exponent becomes equal to the higher one. These numbers are distinct.32-BIT FLOATING POINT PROCESSOR TEC 3. DEPARTMENT OF ECE PAGE NO. Now the numbers from the memory are loaded into two registers. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately.

32-BIT FLOATING POINT PROCESSOR 3.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. namely Accumulator and the Temp register that loads the value appearing on the data bus. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. These numbers are distinct. This is done till the lower exponent becomes equal to the higher one.-37 . So to add their mantissa’s. we have to first normalize their exponents. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. . Now the numbers from the memory are loaded into two registers. The mantissas are then subtracted and the result is stored in a temporary register. These numbers are stored into the memory from which they are read and processed. Once the exponents are normalized. So. DEPARTMENT OF ECE PAGE NO. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa.

the resulting exponent and the sign of the result that is calculated separately. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. So each input should not exceed 12-bits in length. so that the result is restricted to not more than 24-bits. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent.32-BIT FLOATING POINT PROCESSOR TEC 3. DEPARTMENT OF ECE PAGE NO.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. The final output is obtained by concatenating the product of the mantissas. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result.-38 . There is however a limitation to this operation. • • • .

Now both the numbers in the IEEE-784 standard format are compared. if the MSB or the 49th bit is one than we add a one in the quotient. And if it is zero. The convention here is that the Numerator should be always less than the denominator.-39 .32-BIT FLOATING POINT PROCESSOR TEC 3. we put a zero in the quotient.4 Floating Point Division • • • • This is more complicated then Multiplication. The result is stored in Temp. First the exponents are directly added or subtracted depending on which is bigger. we append it with the exponent value and the Sign of the division that are calculated separately. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. till the quotient is full. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. This is to ensure that whatever comes as the result is after the decimal point. Now since the greater of the two numbers is decided. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. Once the quotient is full. DEPARTMENT OF ECE PAGE NO. Now the first 24-bits from the MSB are compared with the divisor. The logic for floating point division is as follows. Apart from that the final sign of the division is calculated separately. We initiate a counter and carry this process for 24 times. • • • • • . The decimal is assumed to be before the MSB of the resulting quotient.

organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. DSPs can perform the mathematical calculations needed in digital signal processing. finding use in everything from cellular telephones to advanced scientific instruments. engineering and digital signal processing. There are technical tradeoffs in the hardware design. Depending on the type of processor. corresponds to the number of pulses per second. Mathematical calculation used in science.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. the processor performs an action that corresponds to an instruction or a part thereof. data is temporarily stored in small. such as the size of the instruction set and how it interrupts are handled. 32 or 64 bits called registers. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. All microprocessors can perform both tasks. written in Hertz (Hz). however it is difficult or expensive to make a device that is optimized for both. The clock speed (also called cycle). For instance. A<B . With each clock peak. local memory locations of 8. and testing for inequalities (A=B. meaning a multiple of the motherboard frequency. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). These tasks are accomplished by moving data from one location to another. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction.-40 . Clock frequency is generally a multiple of the system frequency. Data manipulations involve storing and sorting information. competitive position. These devices have seen tremendous growth in the last decade. When the processor executes instructions. the overall number of registers can vary from about ten to many hundreds. When this code is detected. the program moves the data from . Consider another example of how a document is printed from a word processor. consider a word processing program. etc). Data manipulation such as word processing and database management 2. and so on. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. 4. The basic task is to store the information. 16. DEPARTMENT OF ECE PAGE NO. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. Computers are extremely capable in two broad areas 1. There are marketing issues involved: development and manufacturing cost. product life time.

. The task is to calculate the sample at location n in the output signal.. the math operations dominate the execution time. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: ... y[n]. it is infrequent and does not significantly affect the overall execution speed. while the output signal is denoted by y [ ]. DEPARTMENT OF ECE PAGE NO. This is simply saying that the input signal has been convolved with a filter kernel consisting of: ..32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer..e.. such as to keep track of the intermediate results and control the loops... depending on the application. the most common DSP technique. For example. Using standard notation.-41 . the input signal is referred to by x [ ]. consider the implementation of an FIR digital filter. i. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required.. In comparison.. there may only be a few coefficients in the filter kernel.. . While there is some data transfer and inequality evaluation in this algorithm. While mathematics is occasionally used in this type of application.

x[n].x[n-2]. the traditional speed advantage of integer operations over floating point operations is decreasing.000 samples per second. You simply wait for the action to be completed before you give the computer its next assignment In comparison. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. each sample in the output signal . a geophysicist might use a seismometer to record the ground movement during the earthquake. is found by multiplying samples from the input signal. The disadvantages of 32-bit processors are cost and system complexity. For instance. This is common in scientific research and engineering. the entire input signal resides in the computer at the same time.3. the DSP must be able to maintain a sustained throughput of 20.2.y[n]. . floating point math must often be used to reduce the cost of programming a project. In these cases a 16-bit processor may suffice.. Digital signal processors are designed to quickly carry out FIR filters and similar techniques. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. Difference between off-line processing and real time processing: In off-line processing. but these items will appear as chip fabrication technology gets denser.. and summing the products.32-BIT FLOATING POINT PROCESSOR TEC Fig4.by the filter kernel coefficients. After shaking is over. Hence execution time is critical for selecting the proper device. the information may be read into a computer and analysed in some way. In addition to performing mathematical calculations very rapidly.000 samples per second. not having a defined start or end. 4. Off-line processing is a realm of personal computers and mainframes. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. If the digital signal is being received at 20.1: Graphical representation of FIR digital filter design.x[n-1]. with the advent of very fast floating point processing hardware. There are a few reasons for why to not to make it faster than necessary because as speed increases.. . so as the cost . There is less room on-chip for extra features such as hardware multipliers. If suppose you are launching your desktop computer on some task . most DSPs are used in applications where the processing is continuous. Floating point calculations also require a 32-bit processor for good efficiency. consider a designing of an audio signal in DSP system such as a hearing aid.. converting a word processing document from one form to another. However. and to support code written in high level languages. power consumption.. The key point in off-line processing is that all of the information is simultaneously available to the processing program. In FIR filtering . as well as the algorithms that can be applied. DEPARTMENT OF ECE PAGE NO. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. Also. design difficulty and so on. DSPs must also have a predictable execution time. whereas 32-bit processors are naturally suited to the size of the data elements.-42 . For example. say.

Since the buses operate independently. 4. While the SHARC DSPs are optimized in dozens of ways.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. while only one binary value (the program instruction) is passed over the program memory bus. Harvard architecture has separate memories for data and program instructions. with separate buses for each. while keeping the input signal in data memory. there are two serial ports that operate at 40 Mbits/second each.4. . The SHARC DSPs provides both serial and parallel communications ports. Harvard Architecture. two areas are important enough to be included are an instruction cache. this is needed in telephone communication. When two numbers are multiplied. Alternatively. two binary values (the numbers) must be passed over the data memory bus. For example.-43 . Real time applications input a sample. perform the algorithm and output a sample. while six parallel ports each provide a 40 Mbytes/second data transfer. Likewise. the binary codes that go into the program sequencer. we might place the filter coefficients in program memory. and an I/O controller. For example. over and over. we start by relocating part of the "data" to program memory. For instance. improving the speed over the single bus design. Different architectures available are: Von Neumann Architecture. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). hearing aids and radar. This is the world of digital signal processors. The basis of Harvard design is that the data memory bus is busier than the program memory bus. at a 40 MHz clock speed. This includes data. Most of the computers are using this architecture today. When all six parallel ports are used together. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. the data transfer rate is an incredible 240Mbytes/second. such as samples from the input signal and filter coefficients as well as program instructions. the output signal is produced at the same time that the input signal is acquired. Super Harvard Architecture (SHARC). For instance. Most present day DSPs use this dual bus architecture. These are extremely high speed connections. To improve upon this situation. DEPARTMENT OF ECE PAGE NO. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. they may input a group of samples perform the algorithm and output a group of samples. program instructions and data can be fetched at the same time. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator.

This allows . This is a small memory that contains about 32 of the most recent program instructions. the coefficient comes over the program memory bus.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. The first time through a loop. In comparison. the program instructions must be passed over the program memory bus. such as instructions. DEPARTMENT OF ECE PAGE NO. Some DSPs have on-board analog-to-digital and digital-toanalog converters. the Harvard architecture uses separate memories for data and instructions. This means that the same set of program instructions will continually pass from program memory to the CPU.4. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. In the jargon of the field. DSP algorithms generally spend most of their execution time in loops. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. a feature called mixed signal. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. on additional executions of the loop. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. However. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. all DSPs can interface with external converters through serial or parallel ports. providing an additional interface to off-chip memory and peripherals. and the program instruction comes from the instruction cache. However. providing higher speed. the program instructions can be pulled from the instruction cache.-44 .1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. this efficient transfer of data is called a high memory-access bandwidth.

and the two results returned to any of the 16 registers. The ALU performs addition. The math processing is broken into three sections. and places the result into another register. data from registers 8-15 can be passed to the ALU. such as shifting. specifying where the information is to be read from or written to. an arithmetic logic unit (ALU). logical operations (AND. data from registers 0-7 can be passed to the multiplier. The multiplier takes the values from two registers.4. Elementary binary operations are carried out by the barrel shifter. Digital Signal Processors are designed to implement tasks in parallel. multiplies them. and so on. and similar functions. All of the steps within the loop can be executed in a single clock cycle. . XOR. This simplified diagram is of the Analog Devices SHARC DSP.2: Typical DSP architecture. absolute value. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. rotating. Fig 4. At the top of the diagram are two blocks labelled Data Address Generator (DAG). These control the addresses sent to the program and data memories. conversion between fixed and floating point formats. OR. subtraction.-45 . Compare this architecture with the tasks needed to implement an FIR filter. accessible at 40Mwords/second (160 Mbytes/second). for 32 bit data.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. and a barrel shifter. In simpler microprocessors this task is handled as an inherent part of the program sequencer. In a single clock cycle. extracting and depositing segments. one for each of the two memories. a multiplier. and is quite transparent to the programmer. NOT). DEPARTMENT OF ECE PAGE NO.

The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. the instruction set must be larger and so on.-46 . the latter normalized in the form of scientific notation. the fundamental difference between the two types of DSPs is in their respective numeric representations of data.5." rather than just “Floating Point. TMS320C5x™ and TMS320C2x™ DSPs. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). While fixed-point DSP hardware performs strictly integer arithmetic. However. respectively. Today. TMS320C64x™ DSPs. though.and floating-point indicate. with architectures designed for handheld and control applications.32-BIT FLOATING POINT PROCESSOR 4. Tradeoffs of cost and ease of use often heavily influenced the fixed. Comparison between Fixed Point and Floating Point System: TEC Both fixed. are based on single16-bit data paths. underflow and round-off. loops. All the registers and data buses must be 32 bits wide instead of only 16. including a 53-bit mantissa and an 11-bit exponent). By contrast. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel. DEPARTMENT OF ECE PAGE NO. a result of the hardware being highly optimized for math operations. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. and an 8-bit exponent. .and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. the SHARC devices are often referred to as "32-bit DSPs. floating-point DSPs support either integer or real arithmetic. floating point programs often have a shorter development cycle. As the terms fixed. All floating point DSPs can also handle fixed point numbers. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. with DSPs the speed is about the same." fixed point arithmetic is much faster than floating point in general purpose computers. the SHARC DSPs are optimized for both floating point and fixed point operations. Double-width precision achieves much greater precision and dynamic range at the expense of speed. Fixed point DSPs are cheaper than floating point devices. it depends on the internal architecture . thus supporting a vastly greater dynamic range than is available with the fixedpoint format. since it requires multiple cycles for each operation. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. For this reason. since the programmer doesn’t generally need to worry about issues such as overflow. The internal architecture of a floating point device is more complicated than for a fixed point device.or floating-point decision in the past. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. However. a necessity to implement counters. the multiplier and ALU must be able to quickly perform floating point arithmetic.For instance. and executes them with equal efficiency. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. In addition. and signals coming from the ADC and going to the DAC.

Here's the problem. The same thing happens when a number is stored as a 16-bit fixed point value. The gap between numbers is one ten-thousandth of the value of the number we are storing. To do this. In comparison. and add the product to an accumulator. For instance. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. greatly lowering the signal-to-noise ratio of the system.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. For example.-47 . it's bad. this accumulator is just another 16 bit fixed point variable. while for a fixed point number it is only about ten-thousand to one. DSPs handle this problem by using an extended precision accumulator. floating point has roughly 3. For instance. This is because the gaps between adjacent numbers are much larger. while in the SHARC DSPs it contains 80 bits for fixed point use. DEPARTMENT OF ECE PAGE NO. it must be round up or down by a maximum of one-half the gap size i. Standard deviation of this quantisation noise is about one-third of the gap size. multiply it by the appropriate sample from the input signal. suppose we store the number 10. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one..000 as a signed integer. This strategy works very well. this quantization noise will simply add. In the worst case. and will correspondingly add quantization noise on each step. while floating point devices have better precision. and a shorter development cycle. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. higher dynamic range. This is a special register that has 2-3 times as many bits as the other memory locations. This extended range virtually eliminates round-off noise while the accumulation is in progress. in a 500 coefficient FIR filter. although it does limit how some algorithms must be carried out.e.1: Fixed versus floating point. in a 16 bit DSP it may have 32 to 40 bits. we loop through each coefficient.000 times less quantisation noise than fixed point. floating point has such low quantization noise that these techniques are usually not necessary. we add noise to the signal. really bad. It can be rated in the form of signal to noise ratio and quantisation noise. we need to scale the values being added. Suppose we store in a 32 bit floating point format. In other words. the noise on each output sample may be 500 times the noise on each input sample. except that the added noise is much worse. . Although this is an extreme case.5. Noise is signal is usually represented by its standard deviation. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. In traditional microprocessors. it illustrates the main point when many operations are carried out on each sample. Suppose we implement an FIR filter in fixed point. To store the number. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. each time we store a number in floating point notation. Fixed point DSPs are generally cheaper. To avoid overflow.

The programmer needs to continuously understand the amplitude of the numbers. DEPARTMENT OF ECE PAGE NO. how the quantization errors are accumulating. the development time will be greatly reduced if floating point is used. and the precision of fixed point is acceptable. but the development cost will probably be higher due to the more difficult algorithms. such as spectral analysis and FFT convolution.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. In comparison.-48 . are very detailed and can be much more difficult to program.If it is relatively simple. frequency domain algorithms. making them suitable for fixed point. The next thing to look at is the complexity of the algorithm that will be run . and what scaling needs to take place. In comparison. think fixed point. In the reverse manner. . For example. professional audio applications can sample with as high as 20 or 24 bits. In many applications. these issues do not arise in floating point. the cost of the product will be reduced. In contrast. Most DSP techniques are based on repeated multiplications and additions. think floating point. floating point will generally result in a quicker and cheaper development cycle. and almost certainly need floating point to capture the large dynamic range. the possibility of an overflow or underflow needs to be considered after each operation. In fixed point. FIR filtering and other operations in the time domain only require a few dozen lines of code. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. but a more expensive final product. 12-14 bits per sample is the crossover for using fixed versus floating point. floating point systems are also easier to develop algorithms for. television and other video signals typically use 8 bit ADC and DAC. When fixed point is chosen. if it is more complicated. the numbers take care of themselves. While they can be written in fixed point. For instance.

or into one of the extended precision accumulators. many options are needed for fixed point. This describes the ways that multiplication can be carried out for both fixed and floating point formats.-49 . the floating point programmer can spend his time concentrating on the algorithm. and Ry refer to any of the 16 data registers. Rn. For instance. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. While only a single command is needed for floating point. MRF = Rx * Ry. scaling.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. In comparison. Fn = Fx * Fy. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication.5. It could not be any simpler. where Fn. These are the multiplication instructions used in the SHARC DSPs. and MRF and MRB are 80 bit accumulators. Fx. look at all the possible commands for fixed point multiplication. These are the many options needed to efficiently handle the problems of round-off. . In contrast. The RND and SAT options are ways of controlling rounding and register overflow. and may be fractional or integer (F or I). and MRB = Rx * Ry. and Fy are any of the 16 data registers. DEPARTMENT OF ECE PAGE NO.2: Fixed versus floating point instructions. This table also shows that the numbers may be either signed or unsigned (S or U). Rx. The vertical lines indicate options. In other words. and format. the value of any two registers can be multiplied and placed into another register.

Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low.-50 . over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. However. and another 49% are considering the change. In comparison. floating point is the fastest growing segment. A good example of this is cellular telephones. as shown in (c). about 38% of embedded designers have already switched from conventional microprocessors to DSPs. This is mainly driven by consumer products that must have low cost electronics. In (b). floating point is more common when greater performance is needed and cost is not important. As illustrated in (a). About twice as many engineers currently use fixed point as use floating point DSPs. this depends greatly on the application. For instance. about twice as many engineers use fixed point as use floating point DSPs. such a .6 Trends in DSP: TEC Figure 4.6. When you are in competition to sell millions of your product. over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs . DEPARTMENT OF ECE PAGE NO. a cost difference of only a few dollars can be the difference between success and failure.1: Major trends in DSPs. As shown in (c). 32-bit floating point has a higher dynamic range. However. suppose you are designing a medical imaging system. meaning there is a greater difference between the largest number and the smallest number that can be represented.32-BIT FLOATING POINT PROCESSOR 4. The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. such as cellular telephones.

which is 24 bits for floating-point. Third. . this overflow headroom is 8 bits. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow).7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. the cost of the DSP is insignificant. In spite of the larger number of fixed point DSPs being used. The second word width is that of the coefficients used in multiplications. the same as the signal data in DSPs. While fixed-point coefficients are 16 bits. in integer as well as real values. floating-point coefficients can be 24 bits or 53 bits of precision. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. a 32-bit product would be needed. and can be 8. However. iterated MACs require additional bits for overflow headroom. at a price of several hundred-thousand dollars each. For this application. Finally. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. ensuring greater accuracy in end results. or 32 bits for fixed-point DSPs. First. the floating point market is the fastest growing segment. For a single 16-bit by 16-bit multiplication. the internal representations of data in floating-point DSPs are more exact than in fixed-point. Fortunately. but the performance is critical. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). 4. In fixed. which would go beyond most application requirements in accuracy. DEPARTMENT OF ECE PAGE NO. 16. The first is the I/O signal word width. exponentiation vastly increases the dynamic range available for the application. Three data word widths are important to consider in the internal architecture of a DSP. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width. or a 48-bit product for a single 24-bit by 24-bit multiplication. Second. 16 bits for fixed-point. depending whether single or double precision is used. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations.32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner.-51 . Only a few hundred of the model will ever be sold. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products.point devices.

This may be leading to development of sophisticated electronic products for both consumer as well as business. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. Later Integrated Circuits (ICs) were invented.e. i. DEPARTMENT OF ECE PAGE NO. This created new challenges to digital designers as well as circuit designers.. This level is LSI (Large Scale Integration). multiplexes. .32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. One can fabricate a chip contains more than Million of gates. Using latest CAD tools could solve the problem. using this scale of integration people succeeded to make digital subsystems (Microprocessor. and etc. In this process. CMOS (Complementary Metal Oxide Semiconductor) process technology.-52 . With advent of new technology.. It became very easy to a designer to verify functionality of design at various levels. Designers felt need to automate these processes. At this point design process still became critical. Rapid advances in Software Technology and development of new higher level programming languages taken place. At this point design process started getting very complicated. registers. i. I/O peripheral devices and etc. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale. because of manual converting the design from one level to other. counters.e. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). for design electronics circuits with assistance of software programs. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools.) on an IC. Using design at this level. This way of designing (using CAD tools) is certainly a revolution in electronic industry. one can create digital sub blocks (adders.) on a chip.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency.

.32-BIT FLOATING POINT PROCESSOR 5. DEPARTMENT OF ECE PAGE NO.-53 .3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5.

The complete language. According to IEEE rules. 5.3. Different chip vendors can provide VHDL descriptions of their components to system designers. The language can be used as exchange medium between chip vendors and CAD tool users. documentation.-54 . The IEEE in the December 1987 standardized VHDL language.32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. the syntax of many constructs was made more uniform. The language can be used as a communication medium between different CAD and CAE tools . and many ambiguities present in the 1987 version of the language were resolved. this version of the language is known as the IEEE STD 1076-1987. Consequently. The official language description appears in the IEEE standard VHDL language Reference manual. It is a hardware description language that can be used to model a digital system at many levels of abstraction. models written in this language can be verified using a VHDL simulator. DEPARTMENT OF ECE PAGE NO. ranging from the algorithmic level to the gate level. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. and verification of the digital systems was generated. Therefore. the language was upgraded with new features. 5. a need for a standardized hardware description language for the design. This subset is usually sufficient to model most applications .1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). The language has also been recognized as an American National Standards Institute (ANSI) standard.3. available from IEEE. Thus. however.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. This new version of the language is known as the IEEE STD 1076-1993. Reprocurement and reuse was also a big issue. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct.

Each Entity is described using one model. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. End component. can be modeled as a set of interconnected subcomponents. Structural style of modeling: In this one an entity is described as a set of interconnected components. M: in BIT. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. Component And2 Port (L. or mixed. N:outBIT). Begin X1: Xor2portmap (A. B. The language supports three basic different styles: Structural. Dataflow. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. and there are no limitations imposed by the language on the size of the design. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. Y: in BIT. It supports both synchronous and asynchronous timing models. 5. bottom-up. each component.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. This model specifies the external view of the device and one or more internal views. and Boolean equations. and behavioral. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. CARRY). DEPARTMENT OF ECE PAGE NO. . End component. human-readable. Various digital modeling techniques.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. Such a model for the HALF_ADDER entity. The language supports flexible design methodologies: top-down. In VHDL each device model is treated as a distinct representation of a unique device. Z:out BIT).3. The language is publicly available. 1. such as finite –state machine descriptions. that is a digital can be modeled as asset of interconnected components. called an Entity. SUM) A1: AND2portmap (A. As a set of concurrent assignment statements (to represent data flow) 3. Arbitrarily large designs can be modeled using the language. and machine-readable. The internal view of the device specifies functionality or structure. which contains one external view and one or more internal views. B. in turn.-55 . can be modeled using the language. The Entity is thus a hardware abstraction of the actual hardware device. As a set of interconnected components (to represent structure) 2.

and libraries.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL.4 DATAFLOW STYLE OF MODELING: In this modeling style. It comprises three different design entry tools. and auxiliary utilities designed for easy management of resource files.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. The data flow model for the half adder is described using two concurrent signal assignment statements .the entity declaration for half adder specifies the interface ports for this architecture body.2. designs. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std.3. graphical and textual simulation output viewers. Verilog compiler. 5.1.-56 . The architecture body is composed of two parts: the declaration part and the statement part. The declared components are instantiated in the statement part of the architecture body using component instantiation.1. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std. which are specified inside a process statement. 13641995 standard. These sets of sequential statements.3.4. do not explicitly specify the structure of the entity but merely its functionality. 5.4 INTRODUCTION TO HDL TOOLS 5. A process statement is a concurrent statement that can appear with in an architecture body. The name of the architecture body is ha . 5. .4. Two component declarations are present in the declarative part of the architecture body. Verilog.In a signal assignment statement. DEPARTMENT OF ECE PAGE NO. the flow of data through the entity is expressed primarily using concurrent signal assignment statements. 5. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. SIMULATION TOOL 5. 1076-1993 standard. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0. the symbol <=implies an assignment of a value to a signal. and EDIF and mixed VHDL-Verilog-EDIF designs.4. several debugging tools. single simulation kernel.32-BIT FLOATING POINT PROCESSOR TEC End ha. VHDL'93 compiler.

5. The contents of the default-working library of the design.1. the communication of hardware design and test verification data.0 May 1997).-57 .0. It allows you to graphically edit waveforms so as to create desired test vectors. HDL Editor: HDL Editor is a text editor designed for HDL source files. the maintenance. 2. Design Browser: The Design Browser window displays the contents of the current design. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). The VITAL-compliant models can be annotated with timing data from SDF files. modification and procurement of hardware system. 5. 1.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. b. SDF files must comply with OVI Standard Delay Format Specification Version 2. 3. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. DEPARTMENT OF ECE PAGE NO. and Tcl scripts. . The editor automatically translates graphically designed diagrams into VHDL or Verilog code. Perl scripts. The keyword coloring is also available when HDL Editor is used for editing macro files. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs.1/D1. The editor is tightly integrated with the simulator to enable debugging source code. Resource files attached to the design. It displays specific syntax categories in different colors (keyword coloring). that is: a. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams.4. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. 4.

Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator.-58 . Active-HDL provides three compilers.EDIF) • State diagram file (.vhd) • Verilog file (. 5. or EDIF file containing HDL code (or net list) generated from the diagram. d. DEPARTMENT OF ECE PAGE NO. Verilog. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. Cycle-based simulation is significantly faster than event-driven. All Active-HDL tools output their messages to Console. Compilation: Compilation is a process of analysis of a source file. 6. the compiler analyzes the intermediate VHDL. or EDIF objects declared within a selected region of the current design. and scripts.32-BIT FLOATING POINT PROCESSOR TEC c. VHDL. respectively for VHDL. The structure of the design unit selected for simulation. A net list is a set of statements that specifies the elements of a circuit (for example. Verilog.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired.asf) • Block diagram file (. and EDIF. • The Active-HDL simulator provides two simulation engines. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. macros.v) • EDIF net list file (. a source file can be on of the following: • VHDL file (.4. . transistors or gates) and their interconnection. When you choose a menu command or toolbar button for compilation. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands. Verilog. In Active-HDL.bde) In the case of a block or state diagram file.

4.3. This overview explains the general progression of a design through ISE from start to finish. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.2 Design Entry: • ISE Text Editor . ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.The ISE Text Editor is provided in ISE for entering design code and viewing reports.6 SYNTHESIS TOOL: 5. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD. Verilog HDL. DEPARTMENT OF ECE PAGE NO. and finally produce a bit stream for your device configuration.1: Simulation 5.32-BIT FLOATING POINT PROCESSOR TEC Fig4.-59 .6. including ModelSim Xilinx Edition and the HDL Bencher test bench generator. . 5.4.4.5. including: • HDL (VHDL.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite.6. ISE enables you to start your design with any of a number of different source types.

The state machine will be created in HDL.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor .-60 . FPGA Editor .The PAR program accepts the mapped design.4.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. • • • • 5. and memories.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs.The Floor planner allows you to view a graphical representation of the FPGA. Chip Viewer (CPLD only) . and edit schematics and symbols for the Design Entry step of the Xilinx® design flow.The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. Place and Route (PAR) . placing or routing an FPGA design. and Area Group constraints.The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O. and produces output for the bit stream generator.The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. transitions. and pin assignments. analysis can be performed immediately after mapping.The Chip Viewer tool provides a graphical view of the inputs and outputs. equations. State CAD State Machine Editor .The FPGA Editor allows you view and modify the physical implementation. • • • • • • • .3 Implementation: • Translate . FIFOs.The Map program maps a logical design to a Xilinx FPGA. Constraints Editor .The Constraints Editor allows you to create and modify the most commonly used timing constraints. PACE . DEPARTMENT OF ECE PAGE NO. and to view and modify the placed design. to system-level building blocks such as filters. With Timing Analyzer. and after fitting and routing a CPLD design. Floor planner . Map . CORE Generator .6.State CAD allows you to specify states. macro cell details. view. Timing Analyzer . including routing. Global logic. and actions in a graphical editor. Fit (CPLD only) . places and routes the FPGA. transforms.

-61 . XPower . DEPARTMENT OF ECE PAGE NO.4 Device Download and Program File Formatting: • BitGen . Integration with ChipScope Pro.The iMPACT tool generates various programming file formats. iMPACT . • • • .32-BIT FLOATING POINT PROCESSOR TEC 5.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration. and subsequently allows you to configure your device.6.4.

. multiplication and division are done using active HDL tool and the results are as follows: 6.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. subtraction. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition.1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format.-62 .

2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6.2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC 6. . DEPARTMENT OF ECE PAGE NO. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form.-63 .

-64 . DEPARTMENT OF ECE PAGE NO.3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC 6. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form. .3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6.

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . DEPARTMENT OF ECE PAGE NO.-65 . .4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6.32-BIT FLOATING POINT PROCESSOR TEC 6.

• • Procedures for performing basic arithmetic operations are been formed. .2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations.-66 . Basic arithmetic operations such as addition. • 7. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. subtraction. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation. The Functional-simulation has been successfully carried out with the results matching with the expected ones.

. but need to use only a small subset of the range for target acquisition and identification. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. or something might unexpectedly block its range of motion. In these cases. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. however. together with the device’s more accurate internal representations of data. Many levels of signal input from light. The radar system may be tracking in a range from 0 to infinity. The greater precision of signal data. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. Wide dynamic range also plays a part in robotic design. For instance. Since the subset must be determined in real time during system operation. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. enable imaging systems to achieve a much higher level of recognition and definition for the user. x-rays. DEPARTMENT OF ECE PAGE NO. However. The wide dynamic range of a floating-point DSP.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs.-67 . Normally. the robot might weld itself to an assembly unit. feedback is well out of the ordinary operating range. unpredictable events can occur on an assembly line. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information.

com . Computer. In: 1986 FORML Conf. T. Prentice-Hall. Science Research Associates. R. W.ieeexplore. In: Stone.. J. DEPARTMENT OF ECE PAGE NO. S..46 www.org www.2007.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman.org/portal/web/csdl/doi/10. 197-210 Jones. M. (1987) The Implementation of Functional Programming Languages. & Zaremba. H.intel.-68 . M.ieee. Chicago. New York McKeeman. Hayes. (1981) A survey of high-level language machines in Japan. Williams. (1975) Stack computers. (1986) A 32 bit processor architecture for direct execution of Forth. (Ed.computer. Proc. 28-30 November 1986. pp.1109/SNPD. P. Pacific Grove CA. 281-317 Yamamoto. 1975.. pp. July 1981. 14(7) 68-78 REFERENCES www.) Introduction to Computer Architecture.

all.-69 .std_logic_1164. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0). end Fadd.Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc. use IEEE. y : out std_logic_vector(31 downto 0) ). --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . use IEEE.std_logic_unsigned. DEPARTMENT OF ECE PAGE NO. variable Temp :Std_logic_vector(6 downto 0).Shift the that has lesser Exponent by Ea-Eb places to the right * -3.all.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.all. begin temp:=x.std_logic_arith. use IEEE.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1. b : in std_logic_vector(31 downto 0).Compute Ea-Eb -2.

Ma:=MaIn.Final Result begin MaIn:=Acc(22 downto 0). -. DEPARTMENT OF ECE PAGE NO. -. -. -.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0). -.Number Of Shifts variable Ma.b : std_logic. -. -.Z : std_logic_vector(1 downto 0). variable X : std_logic_vector(31 downto 0).Sign Of Resultant Mantissa variable W. Z :=(a&b). end if.Subtraction of Exponents --*2. end loop.s2 : std_logic. --***************************************************************** --*Equalization of Exponents includes two steps --*1. -.Mangitude Of Two mantissas variable ES : std_logic. Eb :=Data(30 downto 23). else TEC Sum:=Sum.Internal Register variable MbIn : std_logic_vector(22 downto 0). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). end loop.Eb : std_logic_vector(7 downto 0). -. MbIn:=Data(22 downto 0). return sum.32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i.Mb : std_logic_vector(22 downto 0).Sign Of Two mantissas variable Sign : std_logic.Internal Register variable Ea. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). end function.Sign Of Resulant Exponent variable a.Resultant Mantissa variable IE : std_logic_vector(6 downto 0). -.Sign Of Two exponents variable s1. a :=Acc(31). -. IE:=Eb(6 downto 0). -.-70 .Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. b :=Data(31). Es:=Eb(7) . --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).Resultant Exponent variable Ns : integer. Ea :=Acc(30 downto 23).

NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Ma:=Ma. DEPARTMENT OF ECE PAGE NO. end loop. Ma:=MaIn. Ma:=MaIn. Mb:=Mb. end if. end loop. IE:=Ea(6 downto 0). . when "10" => Mb:=MbIn.32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end loop. ES:=Eb(7). ES:=Ea(7). when "01" => Mb:=MbIn. ES:=Ea(7). when "11" => Mb:=MbIn. IE:=Ea(6 downto 0). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Ma:=MaIn. IE:=Eb(6 downto 0). else NS:=Ns. ES:=Ea(7). Es:=Ea(7). IE:=Ea(6 downto 0).-71 . NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=IE.

else sign:=sign.32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end if. else sign:=sign. end if. elsif(Ma<Mb) then sign:='1'. Ma:=Ma. end loop. end case. --***********logic for the sign of the mantissa********************** s1:=Acc(31). end if. else NS:=Ns. when others => Null. Mb:=Mb. ES:=Ea(7). W :=(s1&s2). elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. case W is when "00" => when "11" => when "01" => when "10" => .-72 . IE:=IE. sign:='1'. elsif(Ma=Mb) then sign:='0'. ES:=Eb(7). PAGE NO. IE:=Eb(6 downto 0). DEPARTMENT OF ECE sign:='0'. if(Ea>Eb) then sign:='1'. --******************Addition of Mantissas**************************** IR:=Ma+Mb. elsif(Ea<Eb) then sign:='1'. s2:=Data(31). if(Ea>Eb) then sign:='0'.

else sign:=sign.-73 * . end process.b) begin y<=float_add(a. else sign:=sign. begin process(a. when others => null. elsif(Ma=Mb) then sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . end case. end if. end Fadd. elsif(Ma<Mb) then sign:='0'.b).32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. end if. DEPARTMENT OF ECE PAGE NO. end function. return X. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)).

Shift the that has lesser Exponent by Ea-Eb places to the right * 3.std_logic_arith. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout.-74 .std_logic_1164. use IEEE. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). variable Temp : Std_logic_vector(6 downto 0).Compute Ea-Eb 2.std_logic_unsigned. DEPARTMENT OF ECE PAGE NO. begin temp:=x.32-BIT FLOATING POINT PROCESSOR ----1. .all. use ieee.all.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE. y : out std_logic_vector(31 downto 0)).all. use ieee. end Fsub.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0. b : in STD_LOGIC_VECTOR (31 downto 0).

-.Internal Register variable Ea.Sign Of Two Mantissas variable sign : std_logic.Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). return sum.32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i. -.-75 . -. end function.Z : std_logic_vector(1 downto 0).Mangitude Of Two Mantissas variable ES : std_logic.Final Result begin MaIn:=Accout(22 downto 0). -.MbIn: std_logic_vector(22 downto 0).Resultant Mantissa variable IE : std_logic_vector(6 downto 0). --*********************variable Declarations*********************** TEC variable MaIn. -. Z :=(a&b). end loop. MbIn:=Data(22 downto 0). end if.Sign Of Two Exponents variable s1.Mb : std_logic_vector(22 downto 0). -. -.Sign Of Resultant Mantissa variable W. a :=Accout(30). -. b :=Data(30). Ea :=Accout(30 downto 23). DEPARTMENT OF ECE PAGE NO.s2 : std_logic. else Sum:=Sum. -.Subtraction of Exponents * * . -.Sign Of Resulant Exponent variable a. -.Eb : std_logic_vector(7 downto 0).Number Of Shifts variable Ma.b : std_logic. Eb :=Data(30 downto 23). --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. variable X : std_logic_vector(31 downto 0).Resultant Exponent variable Ns : integer.

when "01" => Mb:=MbIn. . Ma:=MaIn. IE:=Ea(6 downto 0). TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)).Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. Ma:=Ma. IE:=IE. ES:=Ea(7). else NS:=Ns. Mb:=Mb. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). ES:=Eb(7). IE:=Ea(6 downto 0). ES:=Ea(7). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end loop.32-BIT FLOATING POINT PROCESSOR --*2. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). DEPARTMENT OF ECE PAGE NO. end if. end loop. ES:=Ea(7). Ma:=MaIn. end loop.-76 . if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=Eb(6 downto 0).

NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). ES:=Eb(7). Ma:=MaIn. IE:=Eb(6 downto 0). Ma:=Ma. else NS:=Ns. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Ea(7). when others => null. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). IE:=Eb(6 downto 0). when "11" => Mb:=MbIn. ES:=Ea(7). end case. IE:=Ea(6 downto 0). IE:=IE. end loop. end loop. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). . for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). ES:=Eb(7). end loop. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end if. TEC Ma:=MaIn.-77 . Mb:=Mb. DEPARTMENT OF ECE PAGE NO. --******************Subtraction of Mantissas************************ IR:=Ma-Mb.32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn.

end if. elsif (Ma=Mb) then sign:='0'. end if. else sign:=sign. elsif (Ea<Eb) then sign:='0'. . end if. elsif(Ma<Mb) then sign:='1'. s2:=Data(31). elsif(Ma<Mb) then sign:='0'. else sign:=sign. W:=(s1&s2). elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. when "11"=> sign:='1'. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. when "10"=> if (Ea>Eb)then sign:='1'. when "01"=> if(Ea>Eb)then sign:='0'. elsif (Ma=Mb) then sign:='0'.32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). elsif(Ea<Eb) then sign:='1'. DEPARTMENT OF ECE PAGE NO. else sign:=sign. else sign:=sign. case W is when "00"=> sign:='0'.-78 . end if.

Multiplication of the Mantissas * * -************************************************************************** library IEEE. return X. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. end process. --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0).32-BIT FLOATING POINT PROCESSOR TEC when others=> null. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)).std_logic_unsigned.Addtion of the Exponents 5. y: out STD_LOGIC_VECTOR (31 downto 0) ). end function. use IEEE. end case. . end Fmul.b) begin y<=float_sub(a.-79 . b: in STD_LOGIC_VECTOR (31 downto 0).all. end f_sub.all. DEPARTMENT OF ECE PAGE NO.b).std_logic_1164. begin process(a. use IEEE.

Resultant exponent variable m : std_logic_vector(21 downto 0). m1 :=Accout(10 downto 0).Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1.32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0).Resultant Mantissa variable carry : std_logic. e2 :=Data(30 downto 23). -. when others=> s:='1'.sign Two Mantissas variable Ea. variable x : std_logic_vector(31 downto 0).Two Exponents Icluding Sign variable m1. -. -. DEPARTMENT OF ECE PAGE NO.Sign Two Exponents variable s1. --************logic for the sign of the Mantissa******************* s1:=Accout(31).Eb : std_logic_vector(6 downto 0). case Z is when "00" => s:='0'.-80 . -.Final Result begin Carry:='0'.Z : std_logic_vector(1 downto 0). -. -. Z :=(s1&s2).b : std_logic. s2:=Data(31). -.e2 : std_logic_vector(7 downto 0).m2 : std_logic_vector(10 downto 0). e1 :=Accout(30 downto 23).s2 : std_logic. -. -. -. m2 :=Data(10 downto 0).Sign Of Resultant Mantissa variable a.Magnitude O Two Mantissas variable s : std_logic.Magnitude Of Two Exponents variable c : std_logic. -. end case. when "11" => s:='0'.Carry variable W. .

c:='1'. when "01" => if(Ea>Eb) then c:='0'. b :=Data(30). when "10" => if(Ea>Eb) then c:='1'.-81 . else c:='0'. end if. a :=Accout(30). else c:='0'. DEPARTMENT OF ECE PAGE NO. end if. elsif(Ea<Eb) then c:='0'. case W is when "00" => c:='0'. W :=(a&b). when "11" => when others => null. . e:="0000000". end case. --*************logic for multiplication************************* m:=m1*m2. e:=Ea+Eb. e:=Eb-Ea. e:=Ea+Eb. e:="0000000". e:=Eb-Ea.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). e:=Ea-Eb. elsif(Ea<Eb) then c:='1'. Eb:=e2(6 downto 0). e:=Ea-Eb.

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

e:=Ea+Eb. elsif(Ea<Eb) then c:='0'. end if. e:=Eb-Ea.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). e:=Eb-Ea. e:="0000000". Z :=(a&b). elsif(Ea<Eb) then c:='1'. else c:='0'. end if. elsif(Ea<Eb) then c:='0'. a :=e1(7). e:=Ea+Eb. end if. if(Ea>Eb) then c:='1'.-86 . if(Ea>Eb) then c:='0'. . b :=e2(7). e:=Ea-Eb. e:=Ea-Eb. else c:='0'. when "10"=> if(Ea>Eb) then c:='1'. elsif(Ea<Eb) then c:='0'. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO. e:="0000000". case Z is when "00" => if(Ea>Eb) then c:='0'. e:=Eb+Ea. Eb:=e2(6 downto 0). e:="0000000". else c:='0'.

TEC . end case. end F_div. begin process(a. e:="0000000". end function. when others=> null. end if. end process. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). return X. else c:='0'.b).b) begin Y<=float_div(a.-87 .

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