# 32-BIT FLOATING POINT PROCESSOR

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Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

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32-BIT FLOATING POINT PROCESSOR

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CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

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When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

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32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

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Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

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) to plus infinity (+ ). Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations.
. As shown in Figure 1. As shown at the bottom of Figure 1.1: Binary Real Number System Because the size and number of registers that any computer can have is limited. DEPARTMENT OF ECE PAGE NO.
Figure 2. only a subset of the real-number continuum can be used in real-number calculations. the real-number system comprises the continuum of real numbers from minus infinity (. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers.32-BIT FLOATING POINT PROCESSOR
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CHAPTER 2
FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT
2.1.-5
.

processor and system costs. In common mathematical notation. while floating-point DSPs support either integer or real arithmetic. designers can identify the DSP that is best suited for an application.2. Similarly. the 65. although a different length can be used. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation.767. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. but decimal fixed point is common in commercial applications. and ease of development. Balancing these factors together. In fixed-point systems.768 to 32.32-BIT FLOATING POINT PROCESSOR
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There are several mechanisms by which strings of digits can represent numbers. the signed fraction format allows . the number is an integer). Fixed point DSPs usually represent each number with a minimum of 16 bits. Among the key factors to consider are the computational capabilities required for the application. performance attributes. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. the digit string can be of any length.536 possible bit patterns can represent a number. fixed point and floating point. These refer to the format used to store and manipulate numbers within the devices. In unsigned integer. Digital Signal Processing can be divided into two categories.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data.536 levels are spread uniformly between 0 and 1.-6
. signed integer uses two's complement to make the range include negative numbers. from -32. Fixed-point Vs floating-point in digital signal processing
Fig 2. Lastly. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. DEPARTMENT OF ECE PAGE NO. The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. With unsigned fraction notation. There are four common ways that these 216 ' 65. low-cost development tools. the stored number can take on any integer value from 0 to 65. For instance. Software programmable for maximum flexibility and supported by easy-touse. DSPs enable designers to build innovative features and differentiating value into their products. some specific assumption is made about where the radix point is located in the string. Motorola manufactures a family of fixed point DSPs that use 24 bits.535. 2.

2324. It is measured in” FLOPS”. This results in many more bit patterns than for fixed point. The speed of floating-point operations is an important measure of performance for computers in many application domains. The logic for these is different from the ordinary arithmetic functions. The radix point is not explicitly included. and signals coming from the ADC and going to the DAC. which is capable of representing real and decimal numbers. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers. it can be placed anywhere relative to the significant digits of the number. DEPARTMENT OF ECE PAGE NO. This position is indicated separately in the internal representation. This is important because it places large gaps between large numbers. 2. the largest and smallest numbers are ±3.4 ×1038 and ±1.32-BIT FLOATING POINT PROCESSOR
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negative numbers.967.3. Floating point A floating-point number is the one. the SHARC DSPs are optimized for both floating point and fixed point operations. All floating point DSPs can also handle fixed point numbers.296 to be exact. For instance. equally spaced between -1 and 1. General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). This is known as the significand. loops. The term” floating point” refers to the fact that the radix point can "float". floating point DSPs typically use a minimum of 32 bits to store each value. The represented values are unequally spaced between these two extremes. A key feature of floating point notation is that the represented numbers are not uniformly spaced. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. For this reason."
2. and floating-point representation can thus be thought of as a computer realization of scientific notation. the SHARC devices are often referred to as "32-bit DSPs. it depends on the internal architecture. a necessity to implement counters. but small gaps between small numbers." rather than just "Floating Point. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most
. that is. or sometimes the mantissa (see below) or coefficient.754-1985). The floating-point operations are incorporated into the design as functions.In comparison. In the most common format (ANSI/IEEE Std.294.However.-7
. respectively.2 ×1038. and executes them with equal efficiency.4. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers.

The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. 1 for negative values. DEPARTMENT OF ECE PAGE NO. computers used many different forms of floating-point. floating-point numbers achieve their greater range at the expense of precision. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. A signed integer exponent. this final value is where s is the value of the significand (after taking into account the implied radix point).-8
. (This is because the exponent field is in . or to the right of the rightmost digit. These differed in the word sizes. the format of the representations. These differing systems implemented different parts of the arithmetic in hardware and software. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm.
2. and the rounding behaviour of operations. Exponent is an integer value
The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. Prior to the IEEE-754 standard. The length of the significand determines the precision to which numbers can be represented. also referred to as the characteristic or scale. The significand is multiplied by the base raised to the power of the exponent.Fraction. Symbolically. The floating-point format needs slightly more storage (to encode the position of the radix point). b is the base. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. so when stored in the same space. 10 or 16. which modifies the magnitude of the number. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where:
• • •
Sign is 0 for positive values.5. with an average error of about 3%. composed as integer.32-BIT FLOATING POINT PROCESSOR
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significant digit. and e is the exponent. Significand is a real number.

also known as the significand. To do this. or 1023 plus the true exponent for double precision. The sign bit is 0 for positive. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. a bias is added to the actual exponent in order to get the stored exponent. IEEE-754 specifies binary representations for floating point numbers: Table 2.) This can be exploited in some applications. This means that at most 232 possible real numbers can be exactly represented.5 : representations for floating point numbers Sign Exponent Mantissa
IEEE floating point numbers have three basic components: the sign. such as volume ramping in digital sound processing. The Sign Bit: The sign bit is as simple as it gets. to sum up: 1. So.32-BIT FLOATING POINT PROCESSOR
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the more significant part of the datum. represents the precision bits of the number. and the mantissa. Flipping the value of this bit flips the sign of the number. The first bit of the mantissa is typically assumed to be 1.-9
. The exponent field contains 127 plus the true exponent for single-precision. 1 denotes a negative number. A float is represented using 32 bits. There are many formats that are used for representation of floating point number. the exponent. 2. 1 for negative. 4. The exponent's base is two.
3. even though there are infinitely many real numbers (even between 0 and 1).f. A few among them are: • 16-bit: Half (binary16)
• • •
32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. It is composed of an implicit leading bit and the fraction bits. DEPARTMENT OF ECE
. The Exponent: The exponent field needs to represent both positive and negative exponents. and each possible combination of bits represents one real number. 0 denotes a positive number. where f is the field of fraction bits. The Mantissa: The mantissa.

then V=Infinity
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Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude.5. the next eight bits are the exponent bits. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude.2: Single (32-Bit) Precision Floating-Point Format
Type
Sign
Exponent
Fraction
Total Bits 32
Bits precision 24
Exponent Bias 127
Single Precision 1 [31] 8 [30-23] 23 [22-00]
The IEEE single precision floating point standard representation requires a 32 bit word. The value V represented by the word may be determined as follows:
• • •
If E=255 and F is nonzero. S. 'E'. which may be represented as numbered from 0 to 31.5. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010).1 Single Precision Format:
The following figures show the layout for single (32-bit) precision floating-point values. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. then V=-Infinity If E=255 and F is zero and S is 0. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15
Half Precision 1 [15] 5 [14-08] 8 [07-00]
2. then V=NaN ("Not a number") If E=255 and F is zero and S is 1. Table 2. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0). left to right. DEPARTMENT OF ECE PAGE NO.-10
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then V=(-1)**S * 2 ** (-126) * (0.101 = -6.101 = 6.
0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1. DEPARTMENT OF ECE PAGE NO. If E=0 and F is nonzero.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point.F) These are "unnormalized" values.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.00000000000000000000001 = 2**(-149) (Smallest positive value)
Examples of IEEE 754 single precision format:
•
-0.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.3125
The biased exponent is -2+127=125= (01111101
•
1.0
The biased exponent is .5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.-11
.F) where "1.32-BIT FLOATING POINT PROCESSOR
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• • •
If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1. then V=0
In particular. If E=0 and F is zero and S is 1. then V=-0 If E=0 and F is zero and S is 0.

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•
37. = 1. 10 + 127 = 137 = 100010012.0
0 1 0 1
1313.1015625 × 2 = 0.8125 .312510 = 10100100001.
.25 × 2 = 0. So -1313.40625 × 2 = 0.01012.3125 is • 0.-12
.203125 × 2 = 0.
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PAGE NO.010010000101012 × 210.
•
-78.3125 0.5 × 2 = 1.203125 0.625 × 2 = 1.5
The based exponent: 127+5= (10000100
.25 0.5
× 2 = 0.3125 131310 = 101001000012
0.625 0 0 0 1
1
1000 1001
10001001010010000101010000000
0.1015625 0. sign bit is 1.625 0.25
The biased exponent: 127+6=133=(10000101
•
-1313.40625 0.8125 × 2 = 1.

next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001).1015625 is 0 00111101 110100000000000000000000
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2.5 0 × 2 = 1.25 0.5 × 2 = 1.32-BIT FLOATING POINT PROCESSOR 0. the next eleven bits are the exponent bits.3. The value V represented by the word may be determined as follows:
•
If E=2047 and F is nonzero.5. left to right. which may be represented as numbered from 0 to 63.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023
1 [63] 11 [62-52] 52 [51-00]
The IEEE double precision floating point standard representation requires a 64 bit word. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251
For example: 0101000101010100001010111000010111001111000010111110011100010 01
Where 1st bit represents sign bit (0).25 1 × 2 = 0. then V=NaN ("Not a number") PAGE NO.101562510 = 0.5. The first bit is the sign bit. S. DEPARTMENT OF ECE
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. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values. 'E'.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0.00011012 = 1.625 0. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.0 1 0.

using a fixed number of digits.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2. 15 exponent bits and 112 significand bits. while maintaining good precision.F) These are "unnormalized" values.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383
1 [127] 15 [126-112]
2. . floating-point notation allows calculations over a wide range of magnitudes. then V=(-1)**S * 2 ** (-1022) * (0.32-BIT FLOATING POINT PROCESSOR
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• • •
If E=2047 and F is zero and S is 1.25
The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). If E=0 and F is zero and S is 1. then V=-Infinity If E=2047 and F is zero and S is 0. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent.5. then V=-0 If E=0 and F is zero and S is 0. DEPARTMENT OF ECE PAGE NO. then V=0
Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit .6.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038.53 ~ 10308.-14
. Table 2. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision. If E=0 and F is nonzero.F) where "1.

3
Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126
Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52)
2-1074 to (1-2-52 )2-1022
Since the sign of floating point numbers is given by a special leading bit. the range for negative numbers is given by the negation of the above values.85 to ~1038. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent. Approximate Decimal 2127 21023 ~10-44. and the smallest possible value for the exponent. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1). P. P is the precision of the system to P numbers. U) (where B is the base of the system.32-BIT FLOATING POINT PROCESSOR
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Table 2. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand.53 ~10-323. There is a smallest positive normalized floating-point number.6. Negative numbers greater than -2-149 (negative underflow) 3. L.3 to ~10308. DEPARTMENT OF ECE PAGE NO. Zero 4. L is the smallest exponent represent able in the system. Positive numbers less than 2-149 (positive underflow) .2: Effective Range of IEEE Floating Point Number with Denormalized. The number of normalized floating point numbers in a system F(B. Negative numbers less than -(2-2-23) 2127 (negative overflow)
2. There is a largest floating point number. Normalized And Approximate Decimal Values.-15
.

When this occurs. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . the most negative value which is defined in bias-127 exponent representation.infinity. Underflow occurs when the sum of the exponents is more negative than -126. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit
. the number is exactly zero.-16
. Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. the largest value which is defined in bias-127 exponent representation. the exponent is set to -127 (E = 0). there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs.
2. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications. DEPARTMENT OF ECE PAGE NO. If M = 0. When this occurs. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations.32-BIT FLOATING POINT PROCESSOR 5. Recently. However the CPU will have to perform extra arithmetic to read the number when stored in this format.
2. Positive numbers greater than (2-2-23) 2127 (positive overflow)
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Overflow occurs when the sum of the exponents exceeds 127.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic:
Image and digital signal processing applications require high floating-point calculations throughput.

Add the numbers with decimal points aligned.-17
.25x and b= 1.1.. They are: 1.. For example. both the numbers are added. But by using floating point addition this can be avoided to a little extent.e.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal. Now as both the exponent values are same.0225x .8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points. . Subtraction 3.8.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. i. Multiplication 4.32-BIT FLOATING POINT PROCESSOR
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Fig 2. Floating point addition is analogous to addition using scientific notation. Division 2.
Normalize the result. DEPARTMENT OF ECE PAGE NO. Hence the value of number ‘a’ becomes 0. Addition 2. as the smaller number here is a=2. let us consider two numbers a= 2. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded.

Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value.e.8.1.
2. The mantissa of both numbers A and B are added.00000009876543 x c= 1.e. ExpA as exponent of number A .234567x b= 0. 2..1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A . Consider a example in which a =1.32-BIT FLOATING POINT PROCESSOR
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The normalised result may contain the required number of digits discarding the unwanted part. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i. ManA as mantissa of number A.876543x after shifting becomes b= 0. b= 9. then sign of greater number is considered.2345670 x in which the remaining part (9876543) which is discarded also carries the result. then the following result may occur: 1.234567x and b= 9.1. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows:
.876543x and if the addition has to be performed. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB
Out
Fig 2.-18
.1. But the normalised result may sometimes carry the required result. Thus this case can said to be having rounding errors. a =1. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number.8.2.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1. then bit 1 is represented for sign. Now both the numbers are added. If the numbers are represented with both positive and negative sign.1. DEPARTMENT OF ECE PAGE NO. signB as sign of number B.8. ExpB as exponent of number B and ManB as mantissa of number B.. i.00000009876543 x
2.

The exponents of these two numbers are compared and the smaller number is shifted
right until the exponents of both the numbers are same. 1.2: Flow Chart for Floating Point Adder. .
2. If there is an underflow or overflow.-19
. DEPARTMENT OF ECE PAGE NO. Addition of significands is done. the exponent sum would have doubled the bias. the bias value must be subtracted from the sum 3. the numbers are represented in IEEE floating point format. Firstly. 6.1. the significand is rounded to the appropriate number of bits required and again normalization is checked.32-BIT FLOATING POINT PROCESSOR
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Normalized result Fig 2. Thus. 4.8. exception is made. If not. 5. If the exponents are stored in biased form. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent.

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7. DEPARTMENT OF ECE PAGE NO. If the sum overflows the position of the hidden bit. the result is converted back to signmagnitude form. Consider addition of the numbers 2.0625 in IEEE Floating Point Standard is:
To align the binary points. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. The mantissa is always less than 2. then the mantissa must be shifted one bit to the right and the exponent incremented. resulting in a sum which is arbitrarily small.2. Subtraction . cancellation may occur. so the hidden bits can sum to no more than 3 (11).25 becomes:
The mantissas are added using integer addition:
The result is already in normal form.-20
. After the addition is performed.340625x . Thus.
The number 2.
2. resulting in a large loss of accuracy. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. or even zero if the numbers are equal in magnitude. When adding numbers of opposite sign. Normalization in this case may require shifting by the total number of bits in the mantissa.8. 2.25 in IEEE Floating Point Standard is:
The number 134.25x and 1. Negative mantissas are handled by first converting to 2's complement and then performing the addition.

if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if
.8.1.. Now as both the exponent values are same.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .
Normalize the result.e.
2.-21
.0225x . ExpB as exponent of number B and ManB as mantissa of number B.340625x numbers the following steps are performed:
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Shift the decimal point of the smaller number to the right until the exponents are equal. The mantissa of both numbers A and B are subtracted.32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2.2. Hence the value of number ‘a’ becomes 0.2. ManA as mantissa of number A.1. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative..25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal..8. Subtract the numbers with decimal points aligned. DEPARTMENT OF ECE PAGE NO. signB as sign of number B. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. i. as the smaller number here is a=2.e. ExpA as exponent of number A . both the numbers are added. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB
Out
Fig 2. The normalised result may contain the required number of digits discarding the unwanted part.25x and b= 1. then sign is represented according to the number i.

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smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign.0625 in IEEE Floating Point Standard is:
To align the binary points. Thus. 5. If there is an underflow or overflow. the bias value must be subtracted from the sum 3. the significand is rounded to the appropriate number of bits required and again normalization is checked.2. 6.25 become:
The mantissas are subtracted using integer subtraction:
. Subtraction of significands is done. 4.
2.25 in IEEE Floating Point Standard is:
The number 134. 2. DEPARTMENT OF ECE PAGE NO. The numbers are represented in IEEE floating point format. Consider subtraction of the numbers 2.2.
The number 2. If the exponents are stored in biased form.340625x .25x and 1. the exponent sum would have doubled the bias.8. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. exception is made.-22
. The exponents of these two numbers are compared and the smaller number is shifted
right until the exponents of both the numbers are same. If not. Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. 2. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. Thus.

3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked.32-BIT FLOATING POINT PROCESSOR
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The result is already in normal form.2. If number X is not ‘0’. If overflow occurs. Flow chart for floating point subtraction:
Subtract significand si
Fig 2. If it is ‘0’ then the resultant solution Z would be Y i.. At this point. DEPARTMENT OF ECE PAGE NO. If the sum overflows the position of the hidden bit. then the significands of numbers X and Y are subtracted. Z=Y.8.8. If the exponents are same. If both the numbers X and Y are non zeros. then number Y is checked. If it is ‘0’.3. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent . consider two numbers X and Y and the resultant be Z.
2.2. If not then the result is normalized. then the following steps can be followed: Exponents of both the numbers are checked. In the first step. then the result would be Z=X. then the mantissa must be shifted one bit to the right and the exponent incremented. If overflow occurred then overflow is reported and returned.e. number X is checked. If the significand is zero then it is returned if not significand overflow is checked.-23
.

8 x 9. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly. 1.5x : Perform unsigned integer multiplication of the mantissas.8. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z. The number 18.32-BIT FLOATING POINT PROCESSOR
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and shifting the significand towards left side and exponent underflow is checked.8.8x times 9. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.1. If underflow occurred then it is reported if not the normalized result is given out. if the significand is not zero then subtraction and further process is carried out.5 ----17.5 in IEEE FPS format is:
.-24
. to multiply 1. DEPARTMENT OF ECE PAGE NO.3. 2. 2. For example. If the exponents are not same. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers.3.10 Add the exponents: 1 +0 --1 Normalize the result:
Set the sign of the result.0 in IEEE FPS format is:
The number 9.

When the fields are assembled in IEEE FPS format. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since:
The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110
(4) (3)
(-127) (+7)
The mantissa is already in normal form. If the position of the hidden bit overflows.2. the mantissa is:
The biased-127 exponents are added.8. the result is:
2. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR
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The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point:
Truncated to 24 bits with the hidden bit in (). Block diagram of floating point multiplication:
.3. The sign of the result is the xor of the sign bits of the two numbers.-25
. the mantissa must be shifted right and the exponent incremented.

number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero. then the exponents are added and a bias of 127 is subtracted from the result. Resultant mantissa is truncated and normalized to fit for the IEEE format.2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1
2. Thus. If the exponents are stored in biased form. the exponent sum would have doubled the bias.8.8. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. signB as sign of number B. DEPARTMENT OF ECE PAGE NO. If both the numbers X and Y are not zero. .3.-26
. The exponents of both the numbers are added and subtracted from the bias 127. The mantissa of both numbers A and B are multiplied. XOR operation for sign bit can be given as follows:
Table 2.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . manA as mantissa of number A. At the first step. expA as exponent of number A .3. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. expB as exponent of number B and manB as mantissa of number B.3.32-BIT FLOATING POINT PROCESSOR
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Fig 2.3.8. Sign of the result is given by performing xor operation of signA and signB.

Division Consider an example of dividing a=0.
Fig 2. So resultant exponent would be 2-3=-1.2 =1..e.3 and b= 0.3: Flow Chart For Floating Point Multiplication.2 .-27
.5.5. in general floating point division the exponents of both the numbers are subtracted and the significands are divided. 0.32-BIT FLOATING POINT PROCESSOR
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If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned.4.8.3 0. 2. Exponent of a is 2 and exponent of b is 3. When the division of both significands are done then the quotient would be 1. The resultant sign bit would be the xor operation of sign bits of X and Y. Hence the result can be given as 1.5 .
.3. DEPARTMENT OF ECE PAGE NO. i.8.

2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. Subtract the exponent of the divisor from the exponent of the dividend. Special . The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend. If both the numbers are either positive or negative. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement. In the first step. signB as sign of number B.8. Block diagram for floating point division:
Fig 2. When divided by a 24 bit divisor. ExpB as exponent of number B and ManB as mantissa of number B. The exponents are subtracted and biased using the bias value.8.1.4.32-BIT FLOATING POINT PROCESSOR
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2. ManA as mantissa of number A. DEPARTMENT OF ECE PAGE NO. overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation. If anyone number of the two are negative.-28
. then the resultant sign is also positive and is represented by bit ‘0’. ExpA as exponent of number A . 2.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .4.8. Normalize the result. As in floating point multiplication. a 24 bit quotient is produced. The mantissa of both numbers A and B are divided. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. Set the sign of the result.4. then the result is also negative is represented by bit ‘1’.

For this. Considering a=0. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked. or NaN.32-BIT FLOATING POINT PROCESSOR
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representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. . DEPARTMENT OF ECE PAGE NO.4. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity .3 S E and b= 0.
2. in this case as larger number has to be subtracted from smaller number.3 0.2
can be represented as M
010000001(0)11000000000000000000000 0. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero.3.2 S E can be represented as M
01000001100101100100000000000000 Exponents are to be subtracted. Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . Number X and Y are checked.Then the steps that occur are: 1.-29
. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2.8. This value is called Not A Number.

If not the mantissas are divided and truncated and normalized result is given out..-30
. digits may flow off the right end of the significand.32-BIT FLOATING POINT PROCESSOR
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3. If they are present.
Fig 2. some form of rounding is required.8. and it may be reported as 0.g. 2.4. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. then those conditions are reported.200 is less than .3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value. • Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit.127). DEPARTMENT OF ECE PAGE NO. In some systems. rounding errors occur as a result of the limited precision of the mantissa
. As we shall discuss. .This means that the number is too small to be represented.9. Rounding Error In floating point arithmetic. • Significand underflow: In the process of aligning significands. this may be designated as +∞ or -∞.

DEPARTMENT OF ECE PAGE NO. the absolute error of a denormalized number is less than since the truncation error in a denormalized number is
2. Same as truncation in 2's complement.32-BIT FLOATING POINT PROCESSOR
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Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits.
. To efficiently use the bits available for the significand. relative errors increase as the magnitude of the number decreases toward zero. For normalized floating point numbers. Break ties by choosing the least significant bit = 0. RZ: Round toward Zero. it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). RN is generally preferred and introduces less systematic error than the other rules. the relative error is approximately since
For denormalized numbers (E = 0). The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. The least significant 24 bits are discarded. RP: Round toward Positive infinity. highest precision can be achieved. The size of the absolute error is proportional to the magnitude of the number. Normalization By normalization. However. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. For numbers in IEEE FPS format.10. Same as truncation in sign-magnitude. RM: Round toward minus infinity.-31
. The value can be kept unchanged by adjusting the exponent accordingly. the absolute error is less than
The largest absolute rounding error occurs when the exponent is 127 and is approximately since
The relative error is the absolute error divided by the magnitude of the number which is approximated.

a 4-bit exponent field and a 9-bit significand field):
2. as the MSB of the significand is always 1. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR
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Moreover. The actual value represented is
However.g.11. If we assume number. resulting
1. it does not need to be shown explicitly. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. to avoid possible confusion. in the following the default normalization does not assume this implicit 1 unless otherwise specified. By the end of the operation. all extra bits during operation (called guard bits) are kept (e. Truncation To retain maximum accuracy. the bits need to be truncated to guard bit
Chopping: simply drop all
. multiplication). Zero is represented by all 0's and is not (and cannot be) normalized..
extra guard bits are kept during operation. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit.
bits are used in final representation of a bits by one of the three methods.-32
. The first bit 1 before the decimal point is implicit.

the Von Neumann rounding error is unbiased.
is always greater than 0. set whether it is originally 0 or 1).
3. DEPARTMENT OF ECE PAGE NO. add 1 to LSB . . otherwise do nothing.
..32-BIT FLOATING POINT PROCESSOR We define the truncation error as:
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We see that the truncation error of chopping is
As
2.e. (no matter
Von Neumann Rounding: If at least one of the guard bits is 1. we say this truncation error is biased. Interpretation: Value represented by guard bits is greater than 0.5 round up.-33
.
Rounding:
a)
If the highest guard bit is 1 and the rest guard bits are not all 0. Two worst cases
Both two cases can be summarized as
i.

round down:
or if
.
Interpretation: Value represented by guard bits is smaller than 0. DEPARTMENT OF ECE PAGE NO. round up:
Interpretation: Value represented by guard bits is 0. The rounding error of these cases can summarized as
.-34
. it is randomly rounded
.
c)
If the highest guard bit is 1 and the rest guard bits are all 0.5 either up or down with equal probability (50%).32-BIT FLOATING POINT PROCESSOR
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b)
If the highest guard bit
is 0. drop all guard bits.5 round down. the rounding depends on the LSB : if . .

DEPARTMENT OF ECE PAGE NO.e. 1111 and negative numbers are represented by binary values less than it.-35
. The numbers in contention have to be first converted into the standard IEEE 784. Therefore zero is represented by 0111.
. The logic for floating point addition.3 Floating Point Functions
A floating-point number is the one. 1111. the exponent obtained by balancing operations is added to 0111. which is capable of representing real and decimal numbers. The exponent in this IEEE standard is represented in excess-127 format. The logic for these is different from the ordinary arithmetic functions. I. Positive numbers are represented by binary values greater than 0111. subtraction. 1111.32-BIT FLOATING POINT PROCESSOR
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CHAPTER .e. the sign of the floating point number. 1985 floating point standard representation before any sort of operations are conducted on them. multiplication and division is presented in the following pages. The floating-point operations are incorporated into the design as functions. The floating-point representation for a standard single precision number is…
S
E7-E0
Ma23-Ma0
A single precision number is a 32-bit number that is segmented to represent the floating-point number. The next eight bits are that of the exponent. The MSB is the sign-bit i. The above representation is the IEEE-784 1985 standard representation.

So to add their mantissa’s. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. This is done till the lower exponent becomes equal to the higher one. Once the exponents are normalized. namely Accumulator and the Temp register that loads the value appearing on the data bus. we have to first normalize their exponents.
• •
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3. These numbers are stored into the memory from which they are read and processed. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. So. These numbers are distinct. DEPARTMENT OF ECE PAGE NO. The mantissas are then added to each other and the result is then stored in a temporary register. Now the numbers from the memory are loaded into two registers.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation.-36
.

So to add their mantissa’s.-37
. This is done till the lower exponent becomes equal to the higher one. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. we have to first normalize their exponents. Now the numbers from the memory are loaded into two registers. Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. namely Accumulator and the Temp register that loads the value appearing on the data bus. So. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately.
. DEPARTMENT OF ECE PAGE NO. The mantissas are then subtracted and the result is stored in a temporary register. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. These numbers are stored into the memory from which they are read and processed. These numbers are distinct. Once the exponents are normalized.32-BIT FLOATING POINT PROCESSOR 3.2 Floating Point Subtraction • • • • •
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• • • •
The real number is first represented in the IEEE-784 standard floating point representation.

So each input should not exceed 12-bits in length. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. The final output is obtained by concatenating the product of the mantissas. DEPARTMENT OF ECE PAGE NO. There is however a limitation to this operation. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. the resulting exponent and the sign of the result that is calculated separately. so that the result is restricted to not more than 24-bits.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized.
• •
•
.-38
. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs.32-BIT FLOATING POINT PROCESSOR
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3.

till the quotient is full. The logic for floating point division is as follows. Now since the greater of the two numbers is decided. The result is stored in Temp.-39
. This is to ensure that whatever comes as the result is after the decimal point. Once the quotient is full. The convention here is that the Numerator should be always less than the denominator. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. Now both the numbers in the IEEE-784 standard format are compared. We initiate a counter and carry this process for 24 times. First the exponents are directly added or subtracted depending on which is bigger.32-BIT FLOATING POINT PROCESSOR
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3. Apart from that the final sign of the division is calculated separately. DEPARTMENT OF ECE PAGE NO. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. And if it is zero. we put a zero in the quotient.
•
• • • •
. Now the first 24-bits from the MSB are compared with the divisor. we append it with the exponent value and the Sign of the division that are calculated separately.4 Floating Point Division • • • • This is more complicated then Multiplication. if the MSB or the 49th bit is one than we add a one in the quotient. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor. The decimal is assumed to be before the MSB of the resulting quotient.

4. Consider another example of how a document is printed from a word processor. There are technical tradeoffs in the hardware design. With each clock peak. When the processor executes instructions. These devices have seen tremendous growth in the last decade. For instance. There are marketing issues involved: development and manufacturing cost. MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. the processor performs an action that corresponds to an instruction or a part thereof. The basic task is to store the information. local memory locations of 8. finding use in everything from cellular telephones to advanced scientific instruments. and so on. however it is difficult or expensive to make a device that is optimized for both. The clock speed (also called cycle). Computers are extremely capable in two broad areas 1. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing. Mathematical calculation used in science. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. These tasks are accomplished by moving data from one location to another. 32 or 64 bits called registers. Data manipulation such as word processing and database management 2. engineering and digital signal processing. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. written in Hertz (Hz). corresponds to the number of pulses per second. 16. product life time. DEPARTMENT OF ECE PAGE NO. and testing for inequalities (A=B. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. the program moves the data from
. Clock frequency is generally a multiple of the system frequency. Depending on the type of processor. such as the size of the instruction set and how it interrupts are handled. All microprocessors can perform both tasks.32-BIT FLOATING POINT PROCESSOR
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CHAPTER 4 DSP PROCESSORS 4. DSPs can perform the mathematical calculations needed in digital signal processing. A<B . the overall number of registers can vary from about ten to many hundreds. When this code is detected. consider a word processing program. data is temporarily stored in small.1 Processor:
The processor is an electronic circuit that operates at the speed of an internal clock. etc).2 Digital Signal Processing
Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. competitive position.-40
. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). Data manipulations involve storing and sorting information. meaning a multiple of the motherboard frequency.

DEPARTMENT OF ECE PAGE NO.. such as to keep track of the intermediate results and control the loops. Using standard notation... i... while the output signal is denoted by y [ ]. While mathematics is occasionally used in this type of application.. This is simply saying that the input signal has been convolved with a filter kernel consisting of: .. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. The task is to calculate the sample at location n in the output signal. For example. the math operations dominate the execution time. the most common DSP technique. While there is some data transfer and inequality evaluation in this algorithm. the input signal is referred to by x [ ]. y[n]. it is infrequent and does not significantly affect the overall execution speed.
... there may only be a few coefficients in the filter kernel.. depending on the application. In comparison.-41
.. consider the implementation of an FIR digital filter.e.. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: .32-BIT FLOATING POINT PROCESSOR
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computer’s memory to the printer.

The key point in off-line processing is that all of the information is simultaneously available to the processing program.y[n]. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds..000 samples per second. There are a few reasons for why to not to make it faster than necessary because as speed increases. not having a defined start or end. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path. design difficulty and so on. If the digital signal is being received at 20. You simply wait for the action to be completed before you give the computer its next assignment In comparison.x[n-2]. . Off-line processing is a realm of personal computers and mainframes. say. a geophysicist might use a seismometer to record the ground movement during the earthquake. as well as the algorithms that can be applied.x[n-1]. In these cases a 16-bit processor may suffice. whereas 32-bit processors are naturally suited to the size of the data elements.32-BIT FLOATING POINT PROCESSOR
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Fig4. converting a word processing document from one form to another. In addition to performing mathematical calculations very rapidly.2. Floating point calculations also require a 32-bit processor for good efficiency. 4.by the filter kernel coefficients. most DSPs are used in applications where the processing is continuous. and to support code written in high level languages. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors. The disadvantages of 32-bit processors are cost and system complexity. each sample in the output signal .1: Graphical representation of FIR digital filter design. In FIR filtering . the traditional speed advantage of integer operations over floating point operations is decreasing. Hence execution time is critical for selecting the proper device. However.. the DSP must be able to maintain a sustained throughput of 20. x[n].. power consumption.-42
. floating point math must often be used to reduce the cost of programming a project. consider a designing of an audio signal in DSP system such as a hearing aid. There is less room on-chip for extra features such as hardware multipliers.. After shaking is over.000 samples per second. DSPs must also have a predictable execution time. . For instance. and summing the products. For example. If suppose you are launching your desktop computer on some task . This is common in scientific research and engineering. the information may be read into a computer and analysed in some way. but these items will appear as chip fabrication technology gets denser.. Digital signal processors are designed to quickly carry out FIR filters and similar techniques. so as the cost . the entire input signal resides in the computer at the same time. is found by multiplying samples from the input signal. Also. Difference between off-line processing and real time processing: In off-line processing. DEPARTMENT OF ECE PAGE NO. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips.3. with the advent of very fast floating point processing hardware.

To improve upon this situation. there are two serial ports that operate at 40 Mbits/second each. improving the speed over the single bus design. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. For instance. the output signal is produced at the same time that the input signal is acquired. and an I/O controller. we start by relocating part of the "data" to program memory. Harvard architecture has separate memories for data and program instructions. Super Harvard Architecture (SHARC). Likewise. The SHARC DSPs provides both serial and parallel communications ports. For instance. this is needed in telephone communication. Harvard Architecture. with separate buses for each. we might place the filter coefficients in program memory. The basis of Harvard design is that the data memory bus is busier than the program memory bus. DEPARTMENT OF ECE PAGE NO. perform the algorithm and output a sample. Since the buses operate independently. the binary codes that go into the program sequencer. over and over. Most of the computers are using this architecture today. Real time applications input a sample. at a 40 MHz clock speed. For example. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. such as samples from the input signal and filter coefficients as well as program instructions. program instructions and data can be fetched at the same time. while six parallel ports each provide a 40 Mbytes/second data transfer. 4. When all six parallel ports are used together. while keeping the input signal in data memory. they may input a group of samples perform the algorithm and output a group of samples. When two numbers are multiplied.-43
.4. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. Most present day DSPs use this dual bus architecture.
. These are extremely high speed connections. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). two areas are important enough to be included are an instruction cache. This is the world of digital signal processors. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. the data transfer rate is an incredible 240Mbytes/second. while only one binary value (the program instruction) is passed over the program memory bus. While the SHARC DSPs are optimized in dozens of ways. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. This includes data. two binary values (the numbers) must be passed over the data memory bus. Alternatively. For example. hearing aids and radar. Different architectures available are: Von Neumann Architecture.32-BIT FLOATING POINT PROCESSOR
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In real-time processing.

However. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. the program instructions must be passed over the program memory bus. In the jargon of the field. providing higher speed. DSP algorithms generally spend most of their execution time in loops. The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. The first time through a loop. the Harvard architecture uses separate memories for data and instructions. a feature called mixed signal.32-BIT FLOATING POINT PROCESSOR
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Figure 4. However. This is a small memory that contains about 32 of the most recent program instructions. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. all DSPs can interface with external converters through serial or parallel ports. This means that the same set of program instructions will continually pass from program memory to the CPU.-44
. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. providing an additional interface to off-chip memory and peripherals. such as instructions. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path.4. this efficient transfer of data is called a high memory-access bandwidth. the program instructions can be pulled from the instruction cache. In comparison. Some DSPs have on-board analog-to-digital and digital-toanalog converters. on additional executions of the loop. This allows . the coefficient comes over the program memory bus. and the program instruction comes from the instruction cache. DEPARTMENT OF ECE PAGE NO.

Compare this architecture with the tasks needed to implement an FIR filter. The ALU performs addition. data from registers 8-15 can be passed to the ALU. conversion between fixed and floating point formats. and the two results returned to any of the 16 registers. and is quite transparent to the programmer.-45
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the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. absolute value. DEPARTMENT OF ECE PAGE NO. and places the result into another register. NOT). rotating. These control the addresses sent to the program and data memories. multiplies them. XOR.2: Typical DSP architecture. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. In simpler microprocessors this task is handled as an inherent part of the program sequencer. one for each of the two memories. This simplified diagram is of the Analog Devices SHARC DSP.
Fig 4. logical operations (AND. At the top of the diagram are two blocks labelled Data Address Generator (DAG). an arithmetic logic unit (ALU). All of the steps within the loop can be executed in a single clock cycle. In a single clock cycle. and so on. such as shifting. accessible at 40Mwords/second (160 Mbytes/second).4. The math processing is broken into three sections.
. The multiplier takes the values from two registers. and a barrel shifter. data from registers 0-7 can be passed to the multiplier. for 32 bit data. OR. and similar functions. a multiplier. Digital Signal Processors are designed to implement tasks in parallel. specifying where the information is to be read from or written to. Elementary binary operations are carried out by the barrel shifter. subtraction. extracting and depositing segments.

TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel.or floating-point decision in the past. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application. and an 8-bit exponent. a result of the hardware being highly optimized for math operations. For this reason. The internal architecture of a floating point device is more complicated than for a fixed point device. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. In addition. are based on single16-bit data paths. Comparison between Fixed Point and Floating Point System:
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Both fixed. Today. and executes them with equal efficiency. with architectures designed for handheld and control applications." fixed point arithmetic is much faster than floating point in general purpose computers.and floating-point indicate. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). TMS320C64x™ DSPs. though." rather than just “Floating Point.For instance. Tradeoffs of cost and ease of use often heavily influenced the fixed. Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. a necessity to implement counters. Double-width precision achieves much greater precision and dynamic range at the expense of speed. floating-point DSPs support either integer or real arithmetic. it depends on the internal architecture . the latter normalized in the form of scientific notation. DEPARTMENT OF ECE PAGE NO. By contrast. the multiplier and ALU must be able to quickly perform floating point arithmetic. underflow and round-off. since it requires multiple cycles for each operation.5. floating point programs often have a shorter development cycle. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. respectively. However. All the registers and data buses must be 32 bits wide instead of only 16. the instruction set must be larger and so on. TMS320C5x™ and TMS320C2x™ DSPs. As the terms fixed. However. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. loops. the SHARC devices are often referred to as "32-bit DSPs. While fixed-point DSP hardware performs strictly integer arithmetic. with DSPs the speed is about the same. the SHARC DSPs are optimized for both floating point and fixed point operations. since the programmer doesn’t generally need to worry about issues such as overflow.32-BIT FLOATING POINT PROCESSOR 4. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. All floating point DSPs can also handle fixed point numbers.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. including a 53-bit mantissa and an 11-bit exponent). the fundamental difference between the two types of DSPs is in their respective numeric representations of data.
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. thus supporting a vastly greater dynamic range than is available with the fixedpoint format. and signals coming from the ADC and going to the DAC. Fixed point DSPs are cheaper than floating point devices.

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Figure 4. This strategy works very well. To store the number..000 times less quantisation noise than fixed point. In the worst case.5. higher dynamic range. and will correspondingly add quantization noise on each step. In traditional microprocessors. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. For instance. it illustrates the main point when many operations are carried out on each sample. the noise on each output sample may be 500 times the noise on each input sample. although it does limit how some algorithms must be carried out. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. floating point has such low quantization noise that these techniques are usually not necessary. greatly lowering the signal-to-noise ratio of the system. . multiply it by the appropriate sample from the input signal. DEPARTMENT OF ECE PAGE NO.1: Fixed versus floating point. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. and add the product to an accumulator. DSPs handle this problem by using an extended precision accumulator. suppose we store the number 10. each time we store a number in floating point notation. except that the added noise is much worse. we add noise to the signal. It can be rated in the form of signal to noise ratio and quantisation noise. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. To do this. In comparison. it's bad.e. The same thing happens when a number is stored as a 16-bit fixed point value. Standard deviation of this quantisation noise is about one-third of the gap size. we loop through each coefficient. This is because the gaps between adjacent numbers are much larger. while floating point devices have better precision. in a 500 coefficient FIR filter. Noise is signal is usually represented by its standard deviation.000 as a signed integer. really bad. it must be round up or down by a maximum of one-half the gap size i. and a shorter development cycle. this quantization noise will simply add. Although this is an extreme case. we need to scale the values being added. Here's the problem. while in the SHARC DSPs it contains 80 bits for fixed point use. floating point has roughly 3. This extended range virtually eliminates round-off noise while the accumulation is in progress. The gap between numbers is one ten-thousandth of the value of the number we are storing. To avoid overflow. Suppose we implement an FIR filter in fixed point. This is a special register that has 2-3 times as many bits as the other memory locations. For instance. For example. this accumulator is just another 16 bit fixed point variable. Fixed point DSPs are generally cheaper. In other words. in a 16 bit DSP it may have 32 to 40 bits. while for a fixed point number it is only about ten-thousand to one.-47
. Suppose we store in a 32 bit floating point format.

and the precision of fixed point is acceptable. television and other video signals typically use 8 bit ADC and DAC. professional audio applications can sample with as high as 20 or 24 bits. the numbers take care of themselves. In contrast. if it is more complicated. think fixed point. In comparison. In comparison. the possibility of an overflow or underflow needs to be considered after each operation. the development time will be greatly reduced if floating point is used. For instance. FIR filtering and other operations in the time domain only require a few dozen lines of code. these issues do not arise in floating point.
. When fixed point is chosen. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. DEPARTMENT OF ECE PAGE NO. are very detailed and can be much more difficult to program. but the development cost will probably be higher due to the more difficult algorithms.-48
. but a more expensive final product. think floating point. In the reverse manner. the cost of the product will be reduced. frequency domain algorithms. While they can be written in fixed point.32-BIT FLOATING POINT PROCESSOR
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In addition to having lower quantization noise. In many applications. floating point systems are also easier to develop algorithms for. For example. Most DSP techniques are based on repeated multiplications and additions. how the quantization errors are accumulating. making them suitable for fixed point. The next thing to look at is the complexity of the algorithm that will be run .If it is relatively simple. In fixed point. floating point will generally result in a quicker and cheaper development cycle. The programmer needs to continuously understand the amplitude of the numbers. 12-14 bits per sample is the crossover for using fixed versus floating point. such as spectral analysis and FFT convolution. and almost certainly need floating point to capture the large dynamic range. and what scaling needs to take place.

look at all the possible commands for fixed point multiplication. This table also shows that the numbers may be either signed or unsigned (S or U). many options are needed for fixed point. Rn. and format. or into one of the extended precision accumulators. Fn = Fx * Fy.
. These are the many options needed to efficiently handle the problems of round-off. and Ry refer to any of the 16 data registers. DEPARTMENT OF ECE PAGE NO. These are the multiplication instructions used in the SHARC DSPs.-49
. In comparison. Rx. This describes the ways that multiplication can be carried out for both fixed and floating point formats. and MRB = Rx * Ry. the value of any two registers can be multiplied and placed into another register. The RND and SAT options are ways of controlling rounding and register overflow. and MRF and MRB are 80 bit accumulators. MRF = Rx * Ry.2: Fixed versus floating point instructions. In contrast. and Fy are any of the 16 data registers. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. and may be fractional or integer (F or I).32-BIT FLOATING POINT PROCESSOR
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Figure 4. In other words. Fx. scaling. where Fn. the floating point programmer can spend his time concentrating on the algorithm.5. While only a single command is needed for floating point. For instance. The vertical lines indicate options. It could not be any simpler. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication.

32-bit floating point has a higher dynamic range. suppose you are designing a medical imaging system. floating point is the fastest growing segment. over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs . However. such a .6 Trends in DSP:
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Figure 4. such as cellular telephones. This is mainly driven by consumer products that must have low cost electronics. this depends greatly on the application.-50
. In (b). When you are in competition to sell millions of your product. about 38% of embedded designers have already switched from conventional microprocessors to DSPs.1: Major trends in DSPs. meaning there is a greater difference between the largest number and the smallest number that can be represented. The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. As shown in (c). DEPARTMENT OF ECE PAGE NO.6. In comparison. Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low. For instance. about twice as many engineers use fixed point as use floating point DSPs. as shown in (c). However. and another 49% are considering the change. About twice as many engineers currently use fixed point as use floating point DSPs. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. As illustrated in (a). floating point is more common when greater performance is needed and cost is not important. A good example of this is cellular telephones.32-BIT FLOATING POINT PROCESSOR 4. a cost difference of only a few dollars can be the difference between success and failure.

and can be 8. at a price of several hundred-thousand dollars each. Third. this overflow headroom is 8 bits. which would go beyond most application requirements in accuracy. a 32-bit product would be needed. depending whether single or double precision is used. However. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. For a single 16-bit by 16-bit multiplication. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. DEPARTMENT OF ECE PAGE NO. In spite of the larger number of fixed point DSPs being used. 16 bits for fixed-point. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. 4. Second. In fixed. the internal representations of data in floating-point DSPs are more exact than in fixed-point. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). 16. For this application. While fixed-point coefficients are 16 bits. or 32 bits for fixed-point DSPs. Fortunately. First. or a 48-bit product for a single 24-bit by 24-bit multiplication.-51
. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. but the performance is critical. ensuring greater accuracy in end results. in integer as well as real values. Finally. iterated MACs require additional bits for overflow headroom. the cost of the DSP is insignificant.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. The second word width is that of the coefficients used in multiplications. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers. the floating point market is the fastest growing segment. Three data word widths are important to consider in the internal architecture of a DSP.point devices. which is 24 bits for floating-point. Only a few hundred of the model will ever be sold. floating-point coefficients can be 24 bits or 53 bits of precision.
. The first is the I/O signal word width. exponentiation vastly increases the dynamic range available for the application. the same as the signal data in DSPs. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width.32-BIT FLOATING POINT PROCESSOR
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computed tomography scanner.

In this process. and etc. Using design at this level. for design electronics circuits with assistance of software programs. CMOS (Complementary Metal Oxide Semiconductor) process technology. This may be leading to development of sophisticated electronic products for both consumer as well as business. This level is LSI (Large Scale Integration). It became very easy to a designer to verify functionality of design at various levels. I/O peripheral devices and etc. At this point design process started getting very complicated. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale.. Later Integrated Circuits (ICs) were invented.) on an IC. using this scale of integration people succeeded to make digital subsystems (Microprocessor. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. At this point design process still became critical.e.
.e. one can create digital sub blocks (adders.. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration). Using latest CAD tools could solve the problem.-52
. Rapid advances in Software Technology and development of new higher level programming languages taken place. because of manual converting the design from one level to other. DEPARTMENT OF ECE PAGE NO. counters. i. Designers felt need to automate these processes. One can fabricate a chip contains more than Million of gates. i. With advent of new technology. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. multiplexes.) on a chip. This created new challenges to digital designers as well as circuit designers.32-BIT FLOATING POINT PROCESSOR
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CHAPTER: 5
INTRODUCTION
5. Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. registers. This way of designing (using CAD tools) is certainly a revolution in electronic industry.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors.

2 IC DESIGN FLOW:
SPECIFICATION
Behavioral Description
Constraints
Behavioral simulation
RTL Description
Synthesis
r G a t e
S p e c i f i c a t a i v o i n o s r a l
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B e h a v i o r a l
Constraints
L e v Gate level netlist e l Logic Synthesis
Automatic P&R layout
N e t l i s t
Fabrication
F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t
Behavioral simulation
5.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language.32-BIT FLOATING POINT PROCESSOR 5. .-53
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has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. DEPARTMENT OF ECE PAGE NO. The language can be used as a communication medium between different CAD and CAE tools
. According to IEEE rules. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct. It is a hardware description language that can be used to model a digital system at many levels of abstraction. Therefore. Different chip vendors can provide VHDL descriptions of their components to system designers. 5. the syntax of many constructs was made more uniform.-54
. The official language description appears in the IEEE standard VHDL language Reference manual. The language has also been recognized as an American National Standards Institute (ANSI) standard. the language was upgraded with new features. a need for a standardized hardware description language for the design. Consequently.32-BIT FLOATING POINT PROCESSOR
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VHSIC is acronym for very high speed Integrated Circuits. available from IEEE. The IEEE in the December 1987 standardized VHDL language.3. Thus. models written in this language can be verified using a VHDL simulator. and many ambiguities present in the 1987 version of the language were resolved. The language can be used as exchange medium between chip vendors and CAD tool users. and verification of the digital systems was generated.1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD).2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. 5. Reprocurement and reuse was also a big issue. This subset is usually sufficient to model most applications . this version of the language is known as the IEEE STD 1076-1987.3.The complete language. however. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. documentation. This new version of the language is known as the IEEE STD 1076-1993. ranging from the algorithmic level to the gate level.

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The language supports hierarchy. Such a model for the HALF_ADDER entity. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity. which contains one external view and one or more internal views. or mixed.3. 5. As a set of concurrent assignment statements (to represent data flow) 3. In VHDL each device model is treated as a distinct representation of a unique device. Begin X1: Xor2portmap (A. SUM) A1: AND2portmap (A. Structural style of modeling: In this one an entity is described as a set of interconnected components. can be modeled as a set of interconnected subcomponents. As a set of interconnected components (to represent structure) 2.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. and behavioral. M: in BIT. that is a digital can be modeled as asset of interconnected components. CARRY). and there are no limitations imposed by the language on the size of the design. Component And2 Port (L. and machine-readable. can be modeled using the language. Z:out BIT). . called an Entity. Various digital modeling techniques. The language supports three basic different styles: Structural. This model specifies the external view of the device and one or more internal views. is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. B. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. DEPARTMENT OF ECE PAGE NO. Y: in BIT. The language is publicly available. bottom-up. Dataflow. in turn. human-readable. End component. End component. B. Arbitrarily large designs can be modeled using the language. The internal view of the device specifies functionality or structure. The language supports flexible design methodologies: top-down. and Boolean equations.-55
. It supports both synchronous and asynchronous timing models. such as finite –state machine descriptions. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. each component. Each Entity is described using one model. N:outBIT). The Entity is thus a hardware abstraction of the actual hardware device. 1.

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5. SIMULATION TOOL 5. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0.1. Verilog. A process statement is a concurrent statement that can appear with in an architecture body. . the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The architecture body is composed of two parts: the declaration part and the statement part.the entity declaration for half adder specifies the interface ports for this architecture body. VHDL'93 compiler. single simulation kernel.32-BIT FLOATING POINT PROCESSOR
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End ha. These sets of sequential statements. The name of the architecture body is ha .4. Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std.In a signal assignment statement.4.4 INTRODUCTION TO HDL TOOLS
5. graphical and textual simulation output viewers. 1076-1993 standard. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. 5.3. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position.1. Two component declarations are present in the declarative part of the architecture body. 5. The data flow model for the half adder is described using two concurrent signal assignment statements . Verilog compiler. and EDIF and mixed VHDL-Verilog-EDIF designs.4. DEPARTMENT OF ECE PAGE NO. The declared components are instantiated in the statement part of the architecture body using component instantiation. and libraries. designs. the symbol <=implies an assignment of a value to a signal.3. 13641995 standard. which are specified inside a process statement. 5.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. several debugging tools. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std.4 DATAFLOW STYLE OF MODELING: In this modeling style. and auxiliary utilities designed for easy management of resource files.2. It comprises three different design entry tools. do not explicitly specify the structure of the entity but merely its functionality.

1. 2. It allows you to graphically edit waveforms so as to create desired test vectors.1/D1. It displays specific syntax categories in different colors (keyword coloring).0. that is: a. The editor is tightly integrated with the simulator to enable debugging source code. the maintenance. The VITAL-compliant models can be annotated with timing data from SDF files. the communication of hardware design and test verification data. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI).3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. . Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. Resource files attached to the design.32-BIT FLOATING POINT PROCESSOR VITAL:
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The simulator provides built-in acceleration for VITAL packages version 3. Design Browser: The Design Browser window displays the contents of the current design. SDF files must comply with OVI Standard Delay Format Specification Version 2.0 May 1997). The editor automatically translates graphically designed diagrams into VHDL or Verilog code. b. The keyword coloring is also available when HDL Editor is used for editing macro files. 4. and Tcl scripts. The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams. 3. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029.4. 5. modification and procurement of hardware system. The contents of the default-working library of the design. HDL Editor: HDL Editor is a text editor designed for HDL source files. DEPARTMENT OF ECE PAGE NO. 5.1.-57
. Perl scripts.

d. macros.
5. or EDIF file containing HDL code (or net list) generated from the diagram. 6. a source file can be on of the following: • VHDL file (.asf) • Block diagram file (. and EDIF. The structure of the design unit selected for simulation.vhd) • Verilog file (.-58
.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. Verilog. transistors or gates) and their interconnection.v) • EDIF net list file (.
. DEPARTMENT OF ECE PAGE NO.EDIF) • State diagram file (. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel.bde) In the case of a block or state diagram file.32-BIT FLOATING POINT PROCESSOR
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c. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled. VHDL. Active-HDL provides three compilers. Cycle-based simulation is significantly faster than event-driven. Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator. In Active-HDL. the compiler analyzes the intermediate VHDL. When you choose a menu command or toolbar button for compilation. • The Active-HDL simulator provides two simulation engines. or EDIF objects declared within a selected region of the current design. Compilation: Compilation is a process of analysis of a source file. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands.4. and scripts. respectively for VHDL. Verilog. A net list is a set of statements that specifies the elements of a circuit (for example. Verilog. All Active-HDL tools output their messages to Console.

4.6 SYNTHESIS TOOL: 5. Verilog HDL. ISE enables you to start your design with any of a number of different source types. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD. including: • HDL (VHDL.6. including ModelSim Xilinx Edition and the HDL Bencher test bench generator.
.1: Simulation
5.The ISE Text Editor is provided in ISE for entering design code and viewing reports.5.2 Design Entry:
•
ISE Text Editor .4. 5. This overview explains the general progression of a design through ISE from start to finish.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.32-BIT FLOATING POINT PROCESSOR
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Fig4. DEPARTMENT OF ECE PAGE NO. and finally produce a bit stream for your device configuration.4. ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.3.6.-59
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The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. and actions in a graphical editor.6. and memories. and pin assignments. and produces output for the bit stream generator.The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. analysis can be performed immediately after mapping. Place and Route (PAR) .State CAD allows you to specify states.The FPGA Editor allows you view and modify the physical implementation. With Timing Analyzer.-60
. DEPARTMENT OF ECE PAGE NO. The state machine will be created in HDL. placing or routing an FPGA design. transitions. CORE Generator . Map .The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O.
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. Global logic.32-BIT FLOATING POINT PROCESSOR
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Schematic Editor . Fit (CPLD only) . and after fitting and routing a CPLD design.The PAR program accepts the mapped design. PACE . Floor planner .The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders. including routing. to system-level building blocks such as filters. view.The Map program maps a logical design to a Xilinx FPGA.The Floor planner allows you to view a graphical representation of the FPGA.The Chip Viewer tool provides a graphical view of the inputs and outputs. transforms. Timing Analyzer .4. State CAD State Machine Editor .3 Implementation:
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Translate .
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5. Chip Viewer (CPLD only) . FIFOs. places and routes the FPGA. equations. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow. macro cell details.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs.The Constraints Editor allows you to create and modify the most commonly used timing constraints. and to view and modify the placed design. FPGA Editor . Constraints Editor .The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. and Area Group constraints.

DEPARTMENT OF ECE PAGE NO.6. iMPACT .The iMPACT tool generates various programming file formats.4 Device Download and Program File Formatting:
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BitGen .The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration. Integration with ChipScope Pro. and subsequently allows you to configure your device.4.-61
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5.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices. XPower .
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This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .32-BIT FLOATING POINT PROCESSOR
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CHAPTER 6
SIMULATION RESULTS
Simulation for floating point addition.1 simulation results for floating point addition
The inputs given are in the form of hexadecimal and converted into binary format.1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows:
Fig 6.-62
. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. DEPARTMENT OF ECE PAGE NO. multiplication and division are done using active HDL tool and the results are as follows: 6. subtraction.
.

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .-63
. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form. DEPARTMENT OF ECE PAGE NO.
.2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows:
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6.2 simulation results for floating point subtraction
The inputs given are in the form of hexadecimal and converted into binary format.

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows:
Fig 6. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR
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6.3 simulation results for floating point multiplication
The inputs given are in the form of hexadecimal and converted into binary format.-64
.
. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form.

Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows:
Fig 6.-65
.
.4 simulation results for floating point division
The inputs given are in the form of hexadecimal and converted into binary format. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR
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6.

-66
.32-BIT FLOATING POINT PROCESSOR
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CHAPTER 7
CONCLUSION AND FUTURE SCOPE
7.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation.
•
7. DEPARTMENT OF ECE PAGE NO. subtraction. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. Basic arithmetic operations such as addition. The Functional-simulation has been successfully carried out with the results matching with the expected ones. • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations. •
•
Procedures for performing basic arithmetic operations are been formed.
.

The wide dynamic range of a floating-point DSP. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. In these cases. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. Since the subset must be determined in real time during system operation. However. The greater precision of signal data. Many levels of signal input from light. Wide dynamic range also plays a part in robotic design. or something might unexpectedly block its range of motion. The radar system may be tracking in a range from 0 to infinity. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. x-rays. For instance.32-BIT FLOATING POINT PROCESSOR
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CHAPTER 8 APPLICATIONS
Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. however. DEPARTMENT OF ECE PAGE NO. unpredictable events can occur on an assembly line.-67
. but need to use only a small subset of the range for target acquisition and identification. the robot might weld itself to an assembly unit. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. together with the device’s more accurate internal representations of data. enable imaging systems to achieve a much higher level of recognition and definition for the user.
. Normally. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. feedback is well out of the ordinary operating range.

org www.. In: 1986 FORML Conf. pp. J.. DEPARTMENT OF ECE PAGE NO.-68
. Computer. 197-210 Jones..ieee. 14(7) 68-78
REFERENCES
www.1109/SNPD.2007. 1975.intel. In: Stone.46 www.org/portal/web/csdl/doi/10. H. Hayes. 28-30 November 1986. M. July 1981. Chicago. T. Prentice-Hall. New York McKeeman. & Zaremba. (1986) A 32 bit processor architecture for direct execution of Forth. (1987) The Implementation of Functional Programming Languages.com
. S. (1975) Stack computers.computer. (1981) A survey of high-level language machines in Japan. Pacific Grove CA.) Introduction to Computer Architecture. 281-317 Yamamoto. pp. (Ed. Proc.ieeexplore. Williams. R.32-BIT FLOATING POINT PROCESSOR
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BIBLIOGRAPHY
Fraeman. P. Science Research Associates. M. W.

all.all. variable Temp :Std_logic_vector(6 downto 0).std_logic_arith.Compute Ea-Eb -2. begin temp:=x.std_logic_1164.all.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE.Shift the that has lesser Exponent by Ea-Eb places to the right * -3. use IEEE. --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . y : out std_logic_vector(31 downto 0) ). use IEEE. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0).std_logic_unsigned. b : in std_logic_vector(31 downto 0).-69
. DEPARTMENT OF ECE PAGE NO. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition *
--***************************************************************** Function float_add(Acc. end Fadd. use IEEE.32-BIT FLOATING POINT PROCESSOR
TEC
APPENDIX
-*************************************************************************** --Entity Name : Fadd
--Entity Description : Floating Point Addition involves three steps -1.

b :=Data(31).Subtraction of Exponents --*2.Final Result begin MaIn:=Acc(22 downto 0). variable X : std_logic_vector(31 downto 0). Eb :=Data(30 downto 23).b : std_logic.Mb : std_logic_vector(22 downto 0).Sign Of Resultant Mantissa variable W. end if. -. DEPARTMENT OF ECE PAGE NO. -. return sum.Number Of Shifts variable Ma. a :=Acc(31). end function.Mangitude Of Two mantissas variable ES : std_logic. -.Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. Ea :=Acc(30 downto 23). -. -.Two Exponents including Sign variable IR : std_logic_vector(22 downto 0).Internal Register variable MbIn : std_logic_vector(22 downto 0).32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).Z : std_logic_vector(1 downto 0).s2 : std_logic. Es:=Eb(7) .Eb : std_logic_vector(7 downto 0). MbIn:=Data(22 downto 0). --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0). --***************************************************************** --*Equalization of Exponents includes two steps --*1. end loop. -. Ma:=MaIn. else
TEC
Sum:=Sum. -. IE:=Eb(6 downto 0).Resultant Mantissa variable IE : std_logic_vector(6 downto 0). -. end loop.-70
.Sign Of Two mantissas variable Sign : std_logic.Sign Of Two exponents variable s1. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). -.Internal Register variable Ea. -. Z :=(a&b).Resultant Exponent variable Ns : integer. -.Sign Of Resulant Exponent variable a. -.

DEPARTMENT OF ECE PAGE NO. IE:=Ea(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). ES:=Ea(7). Ma:=MaIn. when "01" => Mb:=MbIn.-71
. end loop. ES:=Eb(7). IE:=IE. Ma:=MaIn.
when "11" =>
Mb:=MbIn. end loop. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). end if. else NS:=Ns. Ma:=Ma. Ma:=MaIn.32-BIT FLOATING POINT PROCESSOR
TEC
elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). end loop. Mb:=Mb.
. IE:=Ea(6 downto 0). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)).
when "10" =>
Mb:=MbIn. Es:=Ea(7). IE:=Ea(6 downto 0). end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). IE:=Eb(6 downto 0). ES:=Ea(7). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). ES:=Ea(7). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)).

end if. IE:=Eb(6 downto 0). --***********logic for the sign of the mantissa********************** s1:=Acc(31). end if. PAGE NO. Mb:=Mb. end if. end case. if(Ea>Eb) then sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'.32-BIT FLOATING POINT PROCESSOR
TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto
1)). sign:='1'. case W is when "00" => when "11" => when "01" =>
when "10" => . elsif(Ea<Eb) then sign:='1'. W :=(s1&s2). else sign:=sign. ES:=Ea(7). Ma:=Ma. end loop. s2:=Data(31). elsif(Ma=Mb) then sign:='0'. IE:=IE. if(Ea>Eb) then sign:='1'. else NS:=Ns. DEPARTMENT OF ECE
sign:='0'.-72
. elsif(Ma<Mb) then sign:='1'. ES:=Eb(7). else sign:=sign. --******************Addition of Mantissas**************************** IR:=Ma+Mb. when others => Null.

elsif(Ma<Mb) then sign:='0'. elsif(Ma=Mb) then sign:='0'. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)). else sign:=sign. end function. when others => null. end process.b). end if. return X.-73 *
. end case. DEPARTMENT OF ECE PAGE NO. end Fadd. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'.b) begin y<=float_add(a. end if.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'.
TEC
-*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . else sign:=sign. begin process(a.

.std_logic_unsigned.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0.all.-74
.Shift the that has lesser Exponent by Ea-Eb places to the right * 3. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0).std_logic_arith. use IEEE.Compute Ea-Eb 2. DEPARTMENT OF ECE PAGE NO.std_logic_1164.32-BIT FLOATING POINT PROCESSOR ----1. y : out std_logic_vector(31 downto 0)). use ieee. b : in STD_LOGIC_VECTOR (31 downto 0).Subtract with another Mantissa * *
TEC *
-*************************************************************************** library IEEE.all.all. variable Temp : Std_logic_vector(6 downto 0). architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction *
--***************************************************************** Function float_sub(Accout. end Fsub. use ieee. begin temp:=x.

32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i. -.b : std_logic.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).s2 : std_logic. -.Z : std_logic_vector(1 downto 0). end loop. -.Sign Of Two Mantissas variable sign : std_logic. -. b :=Data(30).Sign Of Resulant Exponent variable a. return sum. -. DEPARTMENT OF ECE PAGE NO. a :=Accout(30).Two exponents Including Sign variable IR : std_logic_vector(22 downto 0). Z :=(a&b).Eb : std_logic_vector(7 downto 0). -.Internal Register variable Ea. -. -. --*********************variable Declarations***********************
TEC
variable MaIn. variable X : std_logic_vector(31 downto 0). --***************************************************************** --*Equalization of Exponents includes two steps * * --*1.Sign Of Two Exponents variable s1.Sign Of Resultant Mantissa variable W.Resultant Exponent variable Ns : integer. Ea :=Accout(30 downto 23). MbIn:=Data(22 downto 0). end if. Eb :=Data(30 downto 23).MbIn: std_logic_vector(22 downto 0).Mangitude Of Two Mantissas variable ES : std_logic. -.Final Result begin
MaIn:=Accout(22 downto 0).Subtraction of Exponents * * . end function.Number Of Shifts variable Ma.-75
. else Sum:=Sum. -.Mb : std_logic_vector(22 downto 0). -.

ES:=Ea(7). end loop. else NS:=Ns. . Ma:=MaIn. IE:=IE. Ma:=Ma. ES:=Ea(7). IE:=Ea(6 downto 0).
TEC *
for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). for x in 1 to Ns loop Mb:=('0' & Mb(22
downto 1)). Ma:=MaIn. Mb:=Mb. ES:=Ea(7). end if.Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn. DEPARTMENT OF ECE PAGE NO. end loop.
when "01" =>
Mb:=MbIn. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=Eb(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). ES:=Eb(7).-76
. end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)).32-BIT FLOATING POINT PROCESSOR --*2. NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). IE:=Ea(6 downto 0).

for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end loop. ES:=Eb(7). Ma:=Ma.
when others => null. end loop.
TEC
Ma:=MaIn. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Mb:=Mb. ES:=Ea(7). end if. --******************Subtraction of Mantissas************************ IR:=Ma-Mb.-77
. end loop. . Ma:=MaIn. IE:=Eb(6 downto 0). IE:=Ea(6 downto 0). when "11" => Mb:=MbIn. ES:=Eb(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). else NS:=Ns. ES:=Ea(7). end case. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). IE:=IE. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). IE:=Eb(6 downto 0).

32-BIT FLOATING POINT PROCESSOR
TEC
--***********logic for the sign of the mantissa********************** s1:=Accout(31). when "11"=> sign:='1'. end if. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. when "01"=> if(Ea>Eb)then sign:='0'. else sign:=sign.
when "10"=>
if (Ea>Eb)then sign:='1'. else sign:=sign. elsif (Ma=Mb) then sign:='0'. W:=(s1&s2). else sign:=sign. elsif(Ma<Mb) then sign:='1'.
. end if. elsif (Ma=Mb) then sign:='0'. elsif(Ma<Mb) then sign:='0'. else sign:=sign.-78
. end if. elsif (Ea<Eb) then sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. case W is when "00"=> sign:='0'. s2:=Data(31). end if. elsif(Ea<Eb) then sign:='1'. DEPARTMENT OF ECE PAGE NO.

end f_sub. end process.b). DEPARTMENT OF ECE PAGE NO. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. use IEEE.32-BIT FLOATING POINT PROCESSOR
TEC
when others=> null. .std_logic_1164. return X. b: in STD_LOGIC_VECTOR (31 downto 0).all.Addtion of the Exponents 5. begin process(a. y: out STD_LOGIC_VECTOR (31 downto 0) ). use IEEE. --***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)).std_logic_unsigned.-79
. --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0).b) begin y<=float_sub(a. end case.Multiplication of the Mantissas * *
-************************************************************************** library IEEE. end Fmul. end function.all.

variable x : std_logic_vector(31 downto 0). end case.Magnitude Of Two Exponents variable c : std_logic.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1.Resultant Mantissa variable carry : std_logic. -.s2 : std_logic.Z : std_logic_vector(1 downto 0). -.m2 : std_logic_vector(10 downto 0).Sign Of Resultant Mantissa variable a. -. -. .Magnitude O Two Mantissas variable s : std_logic. s2:=Data(31).32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication *
TEC
--*****************************************************************
Function float_mul(Accout. DEPARTMENT OF ECE PAGE NO.-80
. Z :=(s1&s2).Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0).Sign Two Exponents variable s1. when "11" => s:='0'. -. e1 :=Accout(30 downto 23).Carry variable W. -.Two Exponents Icluding Sign variable m1. -. e2 :=Data(30 downto 23). -.b : std_logic. --************logic for the sign of the Mantissa******************* s1:=Accout(31).e2 : std_logic_vector(7 downto 0).Resultant exponent variable m : std_logic_vector(21 downto 0). -. m2 :=Data(10 downto 0).Eb : std_logic_vector(6 downto 0). -. case Z is when "00" => s:='0'. -. m1 :=Accout(10 downto 0).Final Result begin Carry:='0'.sign Two Mantissas variable Ea. when others=> s:='1'.

--*************logic for multiplication************************* m:=m1*m2. e:=Ea-Eb. e:=Eb-Ea. DEPARTMENT OF ECE PAGE NO. Eb:=e2(6 downto 0). c:='1'.-81
. a :=Accout(30). e:=Ea+Eb.
when "11" =>
when others => null. elsif(Ea<Eb) then c:='1'. e:="0000000". end case. e:="0000000". end if. e:=Ea+Eb. e:=Ea-Eb. else c:='0'. .32-BIT FLOATING POINT PROCESSOR
TEC
--************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). b :=Data(30). else c:='0'. end if. when "01" => if(Ea>Eb) then c:='0'. W :=(a&b). case W is when "00" => c:='0'. e:=Eb-Ea. when "10" => if(Ea>Eb) then c:='1'. elsif(Ea<Eb) then c:='0'.

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

else c:='0'. e:=Ea+Eb. Eb:=e2(6 downto 0). end if. else c:='0'. if(Ea>Eb) then c:='1'. Z :=(a&b). when "10"=> if(Ea>Eb) then c:='1'. e:="0000000". e:=Ea-Eb. . b :=e2(7). case Z is when "00" => if(Ea>Eb) then c:='0'. e:=Ea+Eb. e:="0000000". elsif(Ea<Eb) then c:='1'. DEPARTMENT OF ECE
TEC
when "11" =>
when "01"=>
PAGE NO.-86
. e:=Eb-Ea. else c:='0'. elsif(Ea<Eb) then c:='0'. e:=Eb-Ea. e:=Ea-Eb. elsif(Ea<Eb) then c:='0'. if(Ea>Eb) then c:='0'. elsif(Ea<Eb) then c:='0'. end if. e:="0000000".32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). e:=Eb+Ea. a :=e1(7). end if.

return X.b).-87
. end if.
TEC
. end function.32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea.b) begin Y<=float_div(a. end case. else c:='0'. e:="0000000". end F_div. when others=> null. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). begin process(a. DEPARTMENT OF ECE PAGE NO. end process.