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TEC

Abstract

This project deals with the designing of 32-bit floating point multiplier DSP processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponents. The next seven bits are that of exponent magnitude, and the remaining 24-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format multiplication will be implemented by the processor. The main functional blocks of floating point arithmetic processor design includes arithmetic logic unit (ALU), register organization, control and decoding unit, memory block, 32-bit floating point multiplication. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The over all system architecture will be designed using HDL language and simulation will be done .

. DEPARTMENT OF ECE PAGE NO.-1

32-BIT FLOATING POINT PROCESSOR

TEC

CHAPTER 1

INTRODUCTION

1.1 Objective The main objective of this project is to design a 32 bit floating point basic arithmetic unit that can be used for DSP processor applications. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operation are conducted on them. The floating representation for a standard single precision number format is 32-bit number that is segmented to represent the floating point number.

The IEEE format consists of three fields, the sign of the exponents. The next eight bits are that of exponent magnitude, and the remaining 23-bits represent the mantissa and mantissa sign. The exponent in this IEEE standard is represented in excess-127 format. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The following figure represents basic arithmetic unit for 32 bit floating point computations:

Fig 1.1 Basic Arithmetic Unit For 32 Bit Computations . DEPARTMENT OF ECE PAGE NO.-2

32-BIT FLOATING POINT PROCESSOR

TEC

When the input is given as floating point it is represented in the form of IEEE 32 bit floating point standard. After representing the required operation is selected and the corresponding operation is performed and the result is also represented in the form of 32 bit IEEE floating point standard. 1.2 Methodology

The overall system architecture will be designed using HDL language and simulation, synthesis and implementation(translation,mapping,placing and routing) will be done using various FPGA based EDA tools. Finally in the proposed system architecture performance (speed, area, power and throughput) will be compared with already existing system implementations. VLSI EDA tools used for development of code and simulation of modules are: ACTIVE HDLALDEC: Active HDL is an integrated environment designed for development of VHDL, VERILOG, EDIF and mixed VHDL-VERILOG-EDIF RTL/behavioral/simulation models.

XILINX ISE: Integrated Software Environment (ISE) enables you to quickly verify the functionality of the sources using the integrated simulation capabilities and the HDL bencher test bench generator

1.3 Conceptual Survey Fixed point DSPs are generally cheaper, than the floating point devices. As fixed point format produce less precision and lesser dynamic range, floating point format is much preferred. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. It can be rated in the form of signal to noise ratio and quantisation noise. Instruction set required for fixed point format is more even if a simple operation is to be performed.

. DEPARTMENT OF ECE PAGE NO.-3

32-BIT FLOATING POINT PROCESSOR 1.4 Organisation Thesis

TEC

Chapter 1 includes objective of the project, the methodologies used in designing it and the conceptual survey. Chapter 2 deals with the representation of floating point in IEEE floating point standard representation and how the basic arithmetic operations are been carried out using this representation. Chapter 3 gives a brief outline regarding the DSP processors and why 32 bit floating point format is much preferred for DSP processors rather than using 16 bit fixed format. Chapter 4 gives a brief description of VLSI language and tools used. Chapter 5 shows the simulation results. Chapter 6 includes applications of 32 bit floating point in DSP processor. Chapter 7 gives conclusion and future scope of the project.

. DEPARTMENT OF ECE PAGE NO.-4

As shown at the bottom of Figure 1. .1: Binary Real Number System Because the size and number of registers that any computer can have is limited. The range and precision of this real-number subset is determined by the format that the FPU uses to represent real numbers. the subset of real numbers that a particular FPU supports represents an approximation of the real number system. As shown in Figure 1. only a subset of the real-number continuum can be used in real-number calculations.-5 . the real-number system comprises the continuum of real numbers from minus infinity (.) to plus infinity (+ ). DEPARTMENT OF ECE PAGE NO. Figure 2. Real Number System A number representation specifies some way of storing a number that may be encoded as a string of digits.1. The arithmetic is defined as a set of actions on the representation that simulate classical arithmetic operations.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 2 FUNCTIONAL BLOCKS OF 32 BIT FLOATING POINT ARITHMETIC UNIT 2.

DEPARTMENT OF ECE PAGE NO.535. Balancing these factors together.2. Fixed point DSPs usually represent each number with a minimum of 16 bits. Among the key factors to consider are the computational capabilities required for the application. Digital Signal Processing can be divided into two categories. signed integer uses two's complement to make the range include negative numbers. the digit string can be of any length. and ease of development. 2. performance attributes. In common mathematical notation. These refer to the format used to store and manipulate numbers within the devices.32-BIT FLOATING POINT PROCESSOR TEC There are several mechanisms by which strings of digits can represent numbers. the signed fraction format allows .536 levels are spread uniformly between 0 and 1. Motorola manufactures a family of fixed point DSPs that use 24 bits. but decimal fixed point is common in commercial applications. the stored number can take on any integer value from 0 to 65.768 to 32. performing the high-speed numeric calculations necessary to enable a broad range of applications – from basic consumer electronics to sophisticated industrial instrumentation. the 65. although a different length can be used. Binary fixed point is usually used in special-purpose applications on embedded processors that can only do integer arithmetic. In unsigned integer. With unsigned fraction notation. DSPs enable designers to build innovative features and differentiating value into their products. from -32. some specific assumption is made about where the radix point is located in the string.536 possible bit patterns can represent a number. low-cost development tools.-6 . Similarly. the number is an integer). The basic difference between fixed point DSP hardware and floating point DSP hardware is that in fixed-point DSP hardware performance is strictly integer arithmetic. In fixed-point systems. There are four common ways that these 216 ' 65. processor and system costs. For instance. Fixed-point Vs floating-point in digital signal processing Fig 2. and the location of the radix point is indicated by placing an explicit "point" character (dot or comma) there. Software programmable for maximum flexibility and supported by easy-touse. Lastly.2: Fixed Vs Floating Point System Digital signal processors (DSPs) are essential for real-time processing of real-world digitized data. and get these products to market quickly and costeffectively There are many considerations that system developers weigh when selecting digital signal processors for their applications. while floating-point DSPs support either integer or real arithmetic. designers can identify the DSP that is best suited for an application. If the radix point is omitted then it is implicitly assumed to lie at the right (least significant) end of the string (that is. fixed point and floating point.767.

This is known as the significand. and floating-point representation can thus be thought of as a computer realization of scientific notation. it can be placed anywhere relative to the significant digits of the number. or sometimes the mantissa (see below) or coefficient. For this reason. Floating point A floating-point number is the one." rather than just "Floating Point. The represented values are unequally spaced between these two extremes.-7 . In the most common format (ANSI/IEEE Std. such that the gap between any two numbers is about ten-million times smaller than the value of the numbers. For instance. the largest and smallest numbers are ±3. but is implicitly assumed to always lie in a certain position within the significand often just after or just before the most . it depends on the internal architecture. and executes them with equal efficiency. This position is indicated separately in the internal representation. This results in many more bit patterns than for fixed point. The logic for these is different from the ordinary arithmetic functions. This is important because it places large gaps between large numbers. 2324. but small gaps between small numbers. Floating point describes a system for representing numbers that would be too large or too small to be represented as integers.4 ×1038 and ±1. 2." 2. The speed of floating-point operations is an important measure of performance for computers in many application domains.However.32-BIT FLOATING POINT PROCESSOR TEC negative numbers. A key feature of floating point notation is that the represented numbers are not uniformly spaced. floating point DSPs typically use a minimum of 32 bits to store each value.294. the SHARC DSPs are optimized for both floating point and fixed point operations. which is capable of representing real and decimal numbers.754-1985). General floating point format: A floating-point number consists of: A signed digit string of a given length in a given base (or radix). The term” floating point” refers to the fact that the radix point can "float". It is measured in” FLOPS”. a necessity to implement counters.967. These numbers are in general represented approximately to a fixed number of significant digits and scaled using an exponent. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations.296 to be exact. All floating point DSPs can also handle fixed point numbers. equally spaced between -1 and 1. respectively.3. DEPARTMENT OF ECE PAGE NO. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. The floating-point operations are incorporated into the design as functions. and signals coming from the ADC and going to the DAC. that is.In comparison. the SHARC devices are often referred to as "32-bit DSPs.4. The radix point is not explicitly included.2 ×1038. loops.

These differed in the word sizes. These differing systems implemented different parts of the arithmetic in hardware and software.32-BIT FLOATING POINT PROCESSOR TEC significant digit. with varying accuracy the bit representation of an IEEE binary floating-point number is proportional to its base 2 logarithm. DEPARTMENT OF ECE PAGE NO. A signed integer exponent. with an average error of about 3%. The floating-point format needs slightly more storage (to encode the position of the radix point). and e is the exponent. 10 or 16. b is the base.5. which modifies the magnitude of the number. The length of the significand determines the precision to which numbers can be represented. or to the right of the rightmost digit. The significand is multiplied by the base raised to the power of the exponent. A real-valued number is represented in a floating-point format as: (-1)Sign × Significand × 2Exponent where: • • • Sign is 0 for positive values. the format of the representations. 2. floating-point numbers achieve their greater range at the expense of precision. IEEE format for floating point: The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. (This is because the exponent field is in . Prior to the IEEE-754 standard. and the rounding behaviour of operations.Fraction. this final value is where s is the value of the significand (after taking into account the implied radix point). so when stored in the same space.-8 . composed as integer. The IEEE-754 standard was created in the early 1980s after word sizes of 32 bits (or 16 or 64) had been generally settled upon. equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent to the right if the exponent is positive or to the left if the exponent is negative. computers used many different forms of floating-point. The typical number that can be represented exactly is of the form: significand digits × baseexponent The base for the scaling is normally 2. Exponent is an integer value The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. Significand is a real number. Symbolically. 1 for negative values. also referred to as the characteristic or scale.

This means that at most 232 possible real numbers can be exactly represented. The first bit of the mantissa is typically assumed to be 1. the exponent.) This can be exploited in some applications. 0 denotes a positive number.5 : representations for floating point numbers Sign Exponent Mantissa IEEE floating point numbers have three basic components: the sign. Flipping the value of this bit flips the sign of the number. The Sign Bit: The sign bit is as simple as it gets. The sign bit is 0 for positive. DEPARTMENT OF ECE . to sum up: 1. even though there are infinitely many real numbers (even between 0 and 1).-9 . A few among them are: • 16-bit: Half (binary16) • • • 32-bit: Single (binary32) 64-bit: Double (binary64) 128-bit: Quadruple (binary128) PAGE NO. The Exponent: The exponent field needs to represent both positive and negative exponents. represents the precision bits of the number. where f is the field of fraction bits. IEEE-754 specifies binary representations for floating point numbers: Table 2. or 1023 plus the true exponent for double precision. 1 denotes a negative number. The exponent field contains 127 plus the true exponent for single-precision. 3. 1 for negative. The exponent's base is two. 2. There are many formats that are used for representation of floating point number. A float is represented using 32 bits. and each possible combination of bits represents one real number. It is composed of an implicit leading bit and the fraction bits. also known as the significand.32-BIT FLOATING POINT PROCESSOR TEC the more significant part of the datum. 4.f. and the mantissa. IEEE 754 binary floating point standard is used to represent floating point numbers and define the results of arithmetic operations. such as volume ramping in digital sound processing. The Mantissa: The mantissa. So. a bias is added to the actual exponent in order to get the stored exponent. To do this.

S. exponent bit is of 5 bits of magnitude and the significand bit is of 10 bits in magnitude.5. and the final 23 bits are the fraction 'F': For example: 01000010 01010101 01100110 00101010 where 1st bit represents sign bit (0).32-BIT FLOATING POINT PROCESSOR TEC Half precision format: The following figure shows the layout of half precision (16 bit) floating point format in which Sign bit is of 1 bit of magnitude.1 Single Precision Format: The following figures show the layout for single (32-bit) precision floating-point values. IEEE floating point 32 standard is: V= S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF 31 30 2322 0 The first bit is the sign bit. 'E'.-10 . The value V represented by the word may be determined as follows: • • • If E=255 and F is nonzero. which may be represented as numbered from 0 to 31. the next eight bits are the exponent bits. next 8 bits represent Exponent Bits(1000010 0) and the remaining part represents Mantissa Bits(1010101 01100110 00101010). Table 2. left to right.5. then V=NaN ("Not a number") If E=255 and F is zero and S is 1.1: Half precision floating point format Type Sign Exponent Fraction Total Bits Bits precision Exponent Bias 16 11 15 Half Precision 1 [15] 5 [14-08] 8 [07-00] 2.5.2: Single (32-Bit) Precision Floating-Point Format Type Sign Exponent Fraction Total Bits 32 Bits precision 24 Exponent Bias 127 Single Precision 1 [31] 8 [30-23] 23 [22-00] The IEEE single precision floating point standard representation requires a 32 bit word. then V=Infinity . DEPARTMENT OF ECE PAGE NO. The number of bits for each field are shown (bit ranges are in square brackets): Table 2. then V=-Infinity If E=255 and F is zero and S is 0.

F) These are "unnormalized" values.F) where "1. 0 00000000 00000000000000000000000 = 0 1 00000000 00000000000000000000000 = -0 0 11111111 00000000000000000000000 = Infinity 1 11111111 00000000000000000000000 = -Infinity 0 11111111 00000100000000000000000 = NaN 1 11111111 00100010001001010101010 = NaN 0 10000000 00000000000000000000000 = +1 * 2**(128-127) * 1.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. DEPARTMENT OF ECE PAGE NO. If E=0 and F is zero and S is 1.5 1 10000001 10100000000000000000000 = -1 * 2**(129-127) * 1.0 = 2**(-126) 0 00000000 10000000000000000000000 = +1 * 2**(-126) * 0.1 = 2**(-127) 0 00000000 00000000000000000000001 = +1 * 2**(-126) * 0.32-BIT FLOATING POINT PROCESSOR • TEC • • • If 0<E<255 then V=(-1)**S * 2 ** (E-127) * (1.00000000000000000000001 = 2**(-149) (Smallest positive value) Examples of IEEE 754 single precision format: • -0. then V=0 In particular.0 = 2 0 10000001 10100000000000000000000 = +1 * 2**(129-127) * 1.-11 . then V=-0 If E=0 and F is zero and S is 0.3125 The biased exponent is -2+127=125= (01111101 • 1.101 = -6.5 0 00000001 00000000000000000000000 = +1 * 2**(1-127) * 1.0 The biased exponent is .101 = 6. If E=0 and F is nonzero. then V=(-1)**S * 2 ** (-126) * (0.

• -78.8125 .3125 0. DEPARTMENT OF ECE PAGE NO. 10 + 127 = 137 = 100010012.0 0 1 0 1 1313. So -1313.40625 0. sign bit is 1.5 The based exponent: 127+5= (10000100 .1015625 × 2 = 0.625 × 2 = 1.5 × 2 = 0.25 × 2 = 0.8125 × 2 = 1.5 × 2 = 1.3125 131310 = 101001000012 0.1015625 0.3125 is • 0.010010000101012 × 210.203125 × 2 = 0.625 0 0 0 1 1 1000 1001 10001001010010000101010000000 0. = 1.01012.25 0.40625 × 2 = 0. .203125 0.-12 .312510 = 10100100001.32-BIT FLOATING POINT PROCESSOR TEC • 37.25 The biased exponent: 127+6=133=(10000101 • -1313.625 0.

DEPARTMENT OF ECE .0 1 0.5.1015625 is 0 00111101 110100000000000000000000 TEC 2.-13 . The first bit is the sign bit. Double Precision Format: The following figures show the layout for double (64-bit) precision floating-point values. then V=NaN ("Not a number") PAGE NO.5 × 2 = 1. The number of bits for each field are shown (bit ranges are in square brackets): Table 2.3: Double (64-Bit) Precision Floating-Point Format Type Double Precision Sign Exponent Fraction Total Bits Bits precision Exponent Bias 64 53 1023 1 [63] 11 [62-52] 52 [51-00] The IEEE double precision floating point standard representation requires a 64 bit word.3. left to right.625 0.00011012 = 1.25 0.25 1 × 2 = 0.32-BIT FLOATING POINT PROCESSOR 0. S. next 11 bits represent exponent bits (10100010101) and the remaining part represents mantissa bits (010000101011100001011100111100001011111001110001001). The value V represented by the word may be determined as follows: • If E=2047 and F is nonzero.5. 'E'. which may be represented as numbered from 0 to 63. and the final 52 bits are the fraction 'F': V = S FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 63 62 0 EEEEEEEEEEE 5251 For example: 0101000101010100001010111000010111001111000010111110011100010 01 Where 1st bit represents sign bit (0).101562510 = 0. the next eleven bits are the exponent bits.5 0 × 2 = 1.1012 × 2-4 The biased exponent : -4 + 127 = 123 = 011110112 So 0.

.1: Effective Range of IEEE Floating Point Number Type Single Double Binary (2-2-23) (2-2-52) 2127 21023 Decimal ~ 1038. using a fixed number of digits.5.F" is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. If E=0 and F is zero and S is 1. then V=(-1)**S * 2 ** (-1022) * (0.F) where "1. Table 2.6 Ranges of Floating-Point Numbers By allowing the radix point to be adjustable. then V=-Infinity If E=2047 and F is zero and S is 0. Here's a table of the effective range (excluding infinite values) of IEEE floating-point numbers: Table 2.53 ~ 10308.32-BIT FLOATING POINT PROCESSOR • • • TEC • • • If E=2047 and F is zero and S is 1.25 The range of positive floating point numbers can be split into normalized numbers (which preserve the full precision of the mantissa). while maintaining good precision. floating-point notation allows calculations over a wide range of magnitudes. and denormalized numbers (discussed later) which use only a portion of the fraction’s precision.6.F) These are "unnormalized" values. then V=Infinity If 0<E<2047 then V=(-1)**S * 2 ** (E-1023) * (1. 15 exponent bits and 112 significand bits.4: Quadruple (128-Bit) Precision Floating-Point Format Type Quadruple Precision Sign Exponent Fraction 112 [11100] Total Bits 128 Bits Exponent precision Bias 113 16383 1 [127] 15 [126-112] 2.-14 . DEPARTMENT OF ECE PAGE NO. The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. then V=-0 If E=0 and F is zero and S is 0. then V=0 Quadruple Precision Format: The following table represents the format for 128 bit Qaudruple precision with 1 sign bit . If E=0 and F is nonzero.

Negative numbers less than -(2-2-23) 2127 (negative overflow) 2.-15 .53 ~10-323. P is the precision of the system to P numbers. Normalized And Approximate Decimal Values. There are five distinct numerical ranges that single-precision floating-point numbers are not able to represent: 1. There is a smallest positive normalized floating-point number. There is a largest floating point number. and the smallest possible value for the exponent. U) (where B is the base of the system. The number of normalized floating point numbers in a system F(B. L is the smallest exponent represent able in the system. Underflow level = UFL = BL which has a 1 as the leading digit and 0 for the remaining digits of the significand.32-BIT FLOATING POINT PROCESSOR TEC Table 2. Zero 4.3 to ~10308. Negative numbers greater than -2-149 (negative underflow) 3. Approximate Decimal 2127 21023 ~10-44. the range for negative numbers is given by the negation of the above values.2: Effective Range of IEEE Floating Point Number with Denormalized.85 to ~1038. and U is the largest exponent used in the system) is: 2(B − 1)(BP −1 )(U − L + 1).3 Denormalized Single Precision Double Precision 2-149 to (1-2-23) 2-126 Normalized 2-126 to (2-2-23) 2-1022 to (2-2-52) 2-1074 to (1-2-52 )2-1022 Since the sign of floating point numbers is given by a special leading bit. Overflow level = OFL = (1 − B − P)(BU + 1) which has B − 1 as the value for each digit of the significand and the largest possible value for the exponent. P. DEPARTMENT OF ECE PAGE NO.6. Positive numbers less than 2-149 (positive underflow) . L.

Underflow occurs when the sum of the exponents is more negative than -126. the number is exactly zero. 2. However the CPU will have to perform extra arithmetic to read the number when stored in this format. If M = 0. Floating point operations are hard to implement on FPGAs as their algorithms are quite complex. Fixed point number usually allow only 8 bits (32 bit computing) of binary numbers for the fractional portion of the number which means many decimal numbers are recorded inaccurately. When this occurs. When this occurs.8 Architecture of 32-Bit Floating Point Basic Arithmetic Unit .infinity. the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or . Positive numbers greater than (2-2-23) 2127 (positive overflow) TEC Overflow occurs when the sum of the exponents exceeds 127.7 Benefits Of Using Floating Point Arithmetic Over Fixed Point Arithmetic: Image and digital signal processing applications require high floating-point calculations throughput. It is a well known concept that the single precision floating point operations algorithm is divided into three main parts corresponding to the three parts of the single precision format. These floating point arithmetic operations are one of the performance bottlenecks in high speed and low power image and digital signal processing applications.-16 .32-BIT FLOATING POINT PROCESSOR 5. 2. the exponent is set to -127 (E = 0). Floating Point numbers use exponents to shift the decimal point therefore they can store more accurate fractional values than fixed point numbers. there has been significant work on analysis of high-performance floating-point arithmetic on FPGAs. Recently. the most negative value which is defined in bias-127 exponent representation. and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations. DEPARTMENT OF ECE PAGE NO. the largest value which is defined in bias-127 exponent representation.

For example. Multiplication 4.25x and b= 1. Hence the value of number ‘a’ becomes 0. both the numbers are added.-17 .8 : Architecture of 32-Bit Floating Point Basic Arithmetic Unit There are four basic arithmetic operations performed used floating points.. Subtraction 3.. Floating point addition is analogous to addition using scientific notation. Addition 2. Normalize the result. Division 2. as the smaller number here is a=2.0225x .8.32-BIT FLOATING POINT PROCESSOR TEC Fig 2.340625x : for the addition of these two numbers the following steps are performed: Shift the decimal point of the smaller number to the right until the exponents are equal.e. Addition Whenever addition is performed with two real numbers mostly the numbers after decimal point are discarded. DEPARTMENT OF ECE PAGE NO. They are: 1.1. Add the numbers with decimal points aligned. . i.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. let us consider two numbers a= 2. But by using floating point addition this can be avoided to a little extent. Now as both the exponent values are same.

The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. Thus this case can said to be having rounding errors.8. b= 9. 2.23456709876543 x In this case the normalised result after rounding to seven digits becomes 1.. a =1. ExpB as exponent of number B and ManB as mantissa of number B. But the normalised result may sometimes carry the required result.2.32-BIT FLOATING POINT PROCESSOR TEC The normalised result may contain the required number of digits discarding the unwanted part. Addition of floating points using IEEE 754 format: Addition of two floating point using IEEE 754 format involves the following steps and can be represented in the form of flow chart as follows: . ManA as mantissa of number A. The mantissa of both numbers A and B are added. DEPARTMENT OF ECE PAGE NO.876543x and if the addition has to be performed.00000009876543 x c= 1. i.1. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.e.1.234567x and b= 9.876543x after shifting becomes b= 0. the smaller number is shifted right so as to equalise the exponent of smaller number with the larger number i.234567x b= 0.e. Block diagram representation of floating point adder: ExpA ExpB Exponent calculator ManA Mantissa Adder Normalization Unit ManB SignA Sign Calculator SignB Out Fig 2. then sign of greater number is considered. then the following result may occur: 1.8. ExpA as exponent of number A . Now both the numbers are added.2345670 x in which the remaining part (9876543) which is discarded also carries the result. If the numbers are represented with both positive and negative sign. Consider a example in which a =1. 2.. signB as sign of number B.1: Block Diagram of Floating Point Adder Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .1.00000009876543 x 2.-18 . then bit 1 is represented for sign. Thus rounding errors can occur when the normalized result doesn’t have the required last digits which have been discarded for rounding of the value.8.1.

-19 . If not. the significand is rounded to the appropriate number of bits required and again normalization is checked. If the exponents are stored in biased form. 4.2: Flow Chart for Floating Point Adder. Addition of significands is done. Firstly. If there is an underflow or overflow. the bias value must be subtracted from the sum 3. Thus.32-BIT FLOATING POINT PROCESSOR TEC Normalized result Fig 2.1. the exponent sum would have doubled the bias. .8. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. 6. exception is made. the numbers are represented in IEEE floating point format. 1. 2. 5. DEPARTMENT OF ECE PAGE NO.

then the mantissa must be shifted one bit to the right and the exponent incremented.25x and 1.-20 .340625x . DEPARTMENT OF ECE PAGE NO.25 in IEEE Floating Point Standard is: The number 134. Subtraction . resulting in a sum which is arbitrarily small. so the hidden bits can sum to no more than 3 (11). resulting in a large loss of accuracy. When adding numbers of opposite sign. The number 2.0625 in IEEE Floating Point Standard is: To align the binary points.8. or even zero if the numbers are equal in magnitude. Normalization in this case may require shifting by the total number of bits in the mantissa. If the result is well normalized then it will become the normalized result if not the result is again normalized and converted back to the floating point form. Thus. The mantissa is always less than 2. the result is converted back to signmagnitude form.25 becomes: The mantissas are added using integer addition: The result is already in normal form. cancellation may occur. If the sum overflows the position of the hidden bit. 2.32-BIT FLOATING POINT PROCESSOR TEC 7. Negative mantissas are handled by first converting to 2's complement and then performing the addition.2. Consider addition of the numbers 2. After the addition is performed. 2. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal.

ManA as mantissa of number A. The mantissa of both numbers A and B are subtracted. i. DEPARTMENT OF ECE PAGE NO.8. Subtract the numbers with decimal points aligned.e. if larger number has to be subtracted from a smaller number then the sign bit would be’1’ which indicates negative sign and if .32-BIT FLOATING POINT PROCESSOR Consider two numbers a= 2.0225x . signB as sign of number B..25x and b= 1. ExpB as exponent of number B and ManB as mantissa of number B. Block diagram representation of floating point subtraction: ExpA ExpB Exponent calculator Normalization ManA Mantissa subtraction Unit ManB SignA Sign Calculator SignB Out Fig 2.8. The exponents are made same for both the numbers by right shifting the mantissa of the smaller number. Normalize the result.25x and the larger exponent is 2 the smaller number ‘a’ is shifted to the left until both the exponents become equal. Now as both the exponent values are same. then sign is represented according to the number i.1. The normalised result may contain the required number of digits discarding the unwanted part. both the numbers are added. as the smaller number here is a=2.1: Block Diagram of Floating Point Subtraction Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .. ExpA as exponent of number A ..2.2. Hence the value of number ‘a’ becomes 0.-21 .e. If both the numbers are positive then bit 0 is represented for sign and if both the numbers are negative.1.340625x numbers the following steps are performed: TEC : For the subtraction of these two Shift the decimal point of the smaller number to the right until the exponents are equal. 2.

4.25x and 1.2. Subtraction of significands is done. Thus. If the exponents are stored in biased form. The result is normalised either by shifting the significand to the right side and increasing the exponent or by shifting the exponent left side and decreasing the exponent. Consider subtraction of the numbers 2. 2. the bias value must be subtracted from the sum 3. 2. 5.8.-22 . Subtraction of floating points using IEEE 754 format: Subtraction of floating point using IEEE floating point standard involves the following steps: 1. 2. DEPARTMENT OF ECE PAGE NO.340625x . exception is made.0625 in IEEE Floating Point Standard is: To align the binary points.25 become: The mantissas are subtracted using integer subtraction: .32-BIT FLOATING POINT PROCESSOR TEC smaller number has to be subtracted from larger number then the resultant sign bit would be ‘0’ which represents positive sign. the significand is rounded to the appropriate number of bits required and again normalization is checked. Thus. The exponents of these two numbers are compared and the smaller number is shifted right until the exponents of both the numbers are same. The numbers are represented in IEEE floating point format.2. 6. the smaller exponent is incremented and the mantissa is shifted right until the exponents are equal. If there is an underflow or overflow. If not. the exponent sum would have doubled the bias.25 in IEEE Floating Point Standard is: The number 134. The number 2.

If the significand is zero then it is returned if not significand overflow is checked. consider two numbers X and Y and the resultant be Z. In the first step. If number X is not ‘0’.3.e.3: Flow chart for floating point subtraction The flow chart can be explained as follows: For subtraction. Z=Y.. then the mantissa must be shifted one bit to the right and the exponent incremented. 2.8. At this point. If the sum overflows the position of the hidden bit.-23 . number X is checked.2. then the significand bits are shifted towards right side and exponents are increased and exponent overflow is checked. normalization is checked if it is occurred then the result is returned if not the result is normalized by decreasing the exponent . If not then the result is normalized. If overflow occurs. If both the numbers X and Y are non zeros. If the exponents are same. then the significands of numbers X and Y are subtracted. then the following steps can be followed: Exponents of both the numbers are checked.32-BIT FLOATING POINT PROCESSOR TEC The result is already in normal form. If overflow occurred then overflow is reported and returned. then number Y is checked. If it is ‘0’. then the result would be Z=X. If it is ‘0’ then the resultant solution Z would be Y i. DEPARTMENT OF ECE PAGE NO. Flow chart for floating point subtraction: Subtract significand si Fig 2.8.2.

8x times 9. then the smaller exponent is incremented until the exponents of both numbers X and Y are same and significand is shifted right and checked if it is zero then the other number is kept at the result Z. 2.8.1. 1. For example.0 in IEEE FPS format is: The number 9. If underflow occurred then it is reported if not the normalized result is given out.5 in IEEE FPS format is: .5x : Perform unsigned integer multiplication of the mantissas. The number 18. Multiplication The multiplication of two floating point numbers can be done by multiplying the mantissa part and adding exponent and adjusting the sign.-24 .8. The decimal point in the sum is positioned so that the number of decimal places equals the sum of the number of decimal places in the numbers.3. 2. Multiplication using IEEE floating point standard: The multiplication of two IEEE FPS numbers is performed similarly.8 x 9.3.32-BIT FLOATING POINT PROCESSOR TEC and shifting the significand towards left side and exponent underflow is checked. If the exponents are not same. to multiply 1. DEPARTMENT OF ECE PAGE NO.10 Add the exponents: 1 +0 --1 Normalize the result: Set the sign of the result.5 ----17. if the significand is not zero then subtraction and further process is carried out.

If the position of the hidden bit overflows.3. Block diagram of floating point multiplication: . When the fields are assembled in IEEE FPS format. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC The product of the 24 bit mantissas produces a 48 bit result with 46 bits to the right of the binary point: Truncated to 24 bits with the hidden bit in (). the mantissa must be shifted right and the exponent incremented. the result is: 2. Addition in biased-127 representation can be performed by 2's complement with an additional bias of -127 since: The sum of the exponents is: E 1000 0011 + 1000 0010 ----------0000 0101 + 1000 0001 ----------1000 0110 (4) (3) (-127) (+7) The mantissa is already in normal form. The sign of the result is the xor of the sign bits of the two numbers.2.8. the mantissa is: The biased-127 exponents are added.-25 .

8.8.3. Thus. the bias value must be subtracted from the sum Now exponent overflow and underflow conditions are checked and if they are present then it is reported. . signB as sign of number B. Sign of the result is given by performing xor operation of signA and signB. DEPARTMENT OF ECE PAGE NO. The mantissa of both numbers A and B are multiplied. XOR operation for sign bit can be given as follows: Table 2. the exponent sum would have doubled the bias. If both the numbers X and Y are not zero.32-BIT FLOATING POINT PROCESSOR TEC Fig 2. expA as exponent of number A .2: XOR OPERATION Sign A Sign B Resultant sign 0 0 0 0 1 1 1 0 1 1 1 1 2. Flow chart for floating point multiplication This flow chart can be explained as follows: Let the two numbers which have to be multiplied be X and Y which are represented in IEEE floating point standard and the result be Z which has to be also represented in IEEE floating point standard. At the first step.2: Block Diagram of Floating Point Multiplication Let A and B be two numbers which are represented in IEEE floating point standard with signA as sign of number A . If the exponents are stored in biased form. expB as exponent of number B and manB as mantissa of number B.3.8. manA as mantissa of number A.-26 . then the exponents are added and a bias of 127 is subtracted from the result. number X is checked and if it is zero then the result Z is also zero if not then next number Y is checked and if it is zero then the result would be zero.3. The exponents of both the numbers are added and subtracted from the bias 127. Resultant mantissa is truncated and normalized to fit for the IEEE format.3.

.32-BIT FLOATING POINT PROCESSOR TEC If exponent overflow and underflow is not present then the next step would be multiplication of the significand bits and the result is truncated and normalized and the result is rounded and returned.3 and b= 0.5. Hence the result can be given as 1.3: Flow Chart For Floating Point Multiplication. The resultant sign bit would be the xor operation of sign bits of X and Y. 0. Division Consider an example of dividing a=0.5.3. When the division of both significands are done then the quotient would be 1.. Exponent of a is 2 and exponent of b is 3. 2.5 .e.2 =1. in general floating point division the exponents of both the numbers are subtracted and the significands are divided. So resultant exponent would be 2-3=-1. i. Fig 2.3 0.4. DEPARTMENT OF ECE PAGE NO.8.-27 .8.2 .

Special . Subtract the exponent of the divisor from the exponent of the dividend. signB as sign of number B. As in floating point multiplication. Normalize the result.8. then the resultant sign is also positive and is represented by bit ‘0’. Block diagram for floating point division: Fig 2. The exponent arithmetic is performed by subtracting the exponent of the divisor from the exponent of the dividend. a 24 bit quotient is produced. Set the sign of the result.32-BIT FLOATING POINT PROCESSOR TEC 2.4. When divided by a 24 bit divisor.4. In the first step. ExpA as exponent of number A . ManA as mantissa of number A.8.2 Floating point division using IEEE floating point standard Floating point division using IEEE floating point standard can be performed using the following steps: Perform unsigned integer division of the dividend mantissa by the divisor mantissa. ExpB as exponent of number B and ManB as mantissa of number B.1: Block Diagram of Floating Point Division Let A and B be two numbers which are represented in IEEE floating point standard with SignA as sign of number A .-28 . overflow and underflow occur when the difference of the exponents is outside the range of the bias-127 exponent representation.1. the dividend mantissa is extended to 48 bits by adding 0's to the right of the least significant bit. 2. If both the numbers are either positive or negative.8. The mantissa of both numbers A and B are divided. If anyone number of the two are negative. The exponents are subtracted and biased using the bias value.4. then the result is also negative is represented by bit ‘1’. DEPARTMENT OF ECE PAGE NO. The negative of a bias-127 number is formed by complementing the bits and adding -1 (1111 1111) in 2's complement.

8.2 S E can be represented as M 01000001100101100100000000000000 Exponents are to be subtracted.32-BIT FLOATING POINT PROCESSOR TEC representations are employed for these cases: E = 255 and M = 0 for overflow and E = 0 for underflow. DEPARTMENT OF ECE PAGE NO.-29 . . For this.Then the steps that occur are: 1. 2. If the numbers X and Y are non zero then the exponents are subtracted and bias 127 is added and exponent overflow and underflow conditions are checked. in this case as larger number has to be subtracted from smaller number.2 can be represented as M 010000001(0)11000000000000000000000 0. If number X is zero then the result would be zero ‘0’ and if the number Y is zero ‘0’ then the result would be infinity . Flow chart for floating point division If division of two numbers X and Y and result Z are considered to be represented in IEEE floating point standard . Number X and Y are checked.4. Considering a=0. Floating point division by zero is undefined and has a special representation in which E = 255 and M is nonzero.3 S E and b= 0. This value is called Not A Number. or NaN. 2’s complement of 1000 0011 is 01111101 1000 0010 +0111 1101 1111 1111 2’s complement of 1111 1111 is 0000 0001 and when biased is 1000 0000 When mantissas are divided and result is truncated and normalized and can be given as S E M 01000001101100000000000000000000 2.3 0. 2’s complement of larger number is done and is added to smaller number and then the resultant exponent is again 2’s complemented and negative sign is assigned.3.

• Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit.8. Rounding Error In floating point arithmetic.3: Flow chart for floating point division Problems may arise as the result of these arithmetic operations: • Exponent overflow: A positive exponent exceeds the maximum possible exponent value.g. digits may flow off the right end of the significand.-30 . • Significand underflow: In the process of aligning significands.. then those conditions are reported. If not the mantissas are divided and truncated and normalized result is given out. some form of rounding is required.200 is less than . this may be designated as +∞ or -∞. Fig 2. • Exponent underflow: A negative exponent is less than the minimum possible exponent value (e. . In some systems. rounding errors occur as a result of the limited precision of the mantissa . 2.This means that the number is too small to be represented.127). DEPARTMENT OF ECE PAGE NO. and it may be reported as 0. If they are present.9. As we shall discuss.4.32-BIT FLOATING POINT PROCESSOR TEC 3.

Normalization By normalization. RP: Round toward Positive infinity. The size of the absolute error is proportional to the magnitude of the number. RM: Round toward minus infinity. Break ties by choosing the least significant bit = 0. The value can be kept unchanged by adjusting the exponent accordingly.10. RN is generally preferred and introduces less systematic error than the other rules. DEPARTMENT OF ECE PAGE NO. However. Same as truncation in 2's complement. the absolute error is less than The largest absolute rounding error occurs when the exponent is 127 and is approximately since The relative error is the absolute error divided by the magnitude of the number which is approximated. Same as truncation in sign-magnitude. For normalized floating point numbers. RZ: Round toward Zero. The IEEE FPS defines four rounding rules for choosing the closest floating point when a rounding error occurs: RN: Round to Nearest. the relative error is approximately since For denormalized numbers (E = 0). the absolute error of a denormalized number is less than since the truncation error in a denormalized number is 2.-31 . highest precision can be achieved. . it is shifted to the left until all leading 0's disappear (as they make no contribution to the precision). The least significant 24 bits are discarded.32-BIT FLOATING POINT PROCESSOR TEC Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. To efficiently use the bits available for the significand. relative errors increase as the magnitude of the number decreases toward zero. The absolute error introduced by rounding is the actual difference between the exact value and the floating point representation. For numbers in IEEE FPS format.

all extra bits during operation (called guard bits) are kept (e. extra guard bits are kept during operation. If we assume number. By the end of the operation.32-BIT FLOATING POINT PROCESSOR TEC Moreover.-32 . Truncation To retain maximum accuracy. in the following the default normalization does not assume this implicit 1 unless otherwise specified. the bits need to be truncated to guard bit Chopping: simply drop all .11. a 4-bit exponent field and a 9-bit significand field): 2. resulting 1. as the MSB of the significand is always 1. it does not need to be shown explicitly.g. Example: A binary number can be represented in 14-bit floating-point form in the following ways (1 sign bit. multiplication). The first bit 1 before the decimal point is implicit. bits are used in final representation of a bits by one of the three methods.. to avoid possible confusion. Zero is represented by all 0's and is not (and cannot be) normalized. The significand could be further shifted to the left by 1 bit to gain one more bit for precision. The actual value represented is However. DEPARTMENT OF ECE PAGE NO.

Two worst cases Both two cases can be summarized as i. Rounding: a) If the highest guard bit is 1 and the rest guard bits are not all 0. Interpretation: Value represented by guard bits is greater than 0. set whether it is originally 0 or 1). (no matter Von Neumann Rounding: If at least one of the guard bits is 1. otherwise do nothing.5 round up. .32-BIT FLOATING POINT PROCESSOR We define the truncation error as: TEC We see that the truncation error of chopping is As 2. . add 1 to LSB .e.. the Von Neumann rounding error is unbiased. is always greater than 0. we say this truncation error is biased.-33 . 3. DEPARTMENT OF ECE PAGE NO.

The rounding error of these cases can summarized as . .5 either up or down with equal probability (50%).32-BIT FLOATING POINT PROCESSOR TEC b) If the highest guard bit is 0.5 round down. DEPARTMENT OF ECE PAGE NO.-34 . round down: or if . Interpretation: Value represented by guard bits is smaller than 0. drop all guard bits. c) If the highest guard bit is 1 and the rest guard bits are all 0. the rounding depends on the LSB : if . round up: Interpretation: Value represented by guard bits is 0. it is randomly rounded .

The above representation is the IEEE-784 1985 standard representation. multiplication and division is presented in the following pages. Therefore zero is represented by 0111. the exponent obtained by balancing operations is added to 0111. The floating-point operations are incorporated into the design as functions. The numbers in contention have to be first converted into the standard IEEE 784.3 Floating Point Functions A floating-point number is the one. The next eight bits are that of the exponent. Positive numbers are represented by binary values greater than 0111.-35 . the sign of the floating point number.e. subtraction. 1111 and negative numbers are represented by binary values less than it. 1111. 1111. The logic for these is different from the ordinary arithmetic functions.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER .e. DEPARTMENT OF ECE PAGE NO. The exponent in this IEEE standard is represented in excess-127 format. The logic for floating point addition. The floating-point representation for a standard single precision number is… S E7-E0 Ma23-Ma0 A single precision number is a 32-bit number that is segmented to represent the floating-point number. 1985 floating point standard representation before any sort of operations are conducted on them. which is capable of representing real and decimal numbers. . I. The MSB is the sign-bit i.

we have to first normalize their exponents. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. So. • • . These numbers are stored into the memory from which they are read and processed. Now the numbers from the memory are loaded into two registers. So to add their mantissa’s. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC 3.-36 . This is done till the lower exponent becomes equal to the higher one.1 Floating Point Addition • • • • • The real number is first represented in the IEEE-784 standard floating point representation. Once the exponents are normalized. These numbers are distinct. The mantissas are then added to each other and the result is then stored in a temporary register. The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. namely Accumulator and the Temp register that loads the value appearing on the data bus.

The exponent that is now normalized is concatenated with the resulting mantissa and the sign of the result that is calculated separately. These numbers are distinct. namely Accumulator and the Temp register that loads the value appearing on the data bus. . Apart from that there is no difference in the procedure of normalizing the numbers before the business of Addition or subtraction is carried out.32-BIT FLOATING POINT PROCESSOR 3. This is done till the lower exponent becomes equal to the higher one.-37 . So. we have to first normalize their exponents. Once the exponents are normalized. The major difference between Addition and subtraction is in the sign of the final result that is calculated separately. The mantissas are then subtracted and the result is stored in a temporary register. DEPARTMENT OF ECE PAGE NO. we compare the exponents and increment the exponent of the lower exponent while right shifting its mantissa. Now the numbers from the memory are loaded into two registers.2 Floating Point Subtraction • • • • • TEC • • • • The real number is first represented in the IEEE-784 standard floating point representation. The following things have been possible due to the fact that Binary single-bit addition and subtraction are defined in Verilog-HDL. These numbers are stored into the memory from which they are read and processed. So to add their mantissa’s.

32-BIT FLOATING POINT PROCESSOR TEC 3. the resulting exponent and the sign of the result that is calculated separately. The final output is obtained by concatenating the product of the mantissas. So each input should not exceed 12-bits in length. • • • . DEPARTMENT OF ECE PAGE NO.3 Floating Point Multiplication • • • Here the exponents and mantissas of the numbers in contention don’t have to be normalized. In multiplication the operations are done simultaneously and separately on the mantissa and the exponent. Binary multiplication is defined for single bit numbers in Verilog-HDL so the exponents are just added and the individual bits in the mantissas are multiplied to get the final result. There is however a limitation to this operation. If two numbers of N-bits are multiplied then the resulting no will be of 2N-bits thereby decreasing the numerical scope of the inputs. so that the result is restricted to not more than 24-bits.-38 .

32-BIT FLOATING POINT PROCESSOR TEC 3. The convention here is that the Numerator should be always less than the denominator. Now since the greater of the two numbers is decided. The result is stored in Temp. we append it with the exponent value and the Sign of the division that are calculated separately. DEPARTMENT OF ECE PAGE NO. Now the first 24-bits from the MSB are compared with the divisor. if the MSB or the 49th bit is one than we add a one in the quotient. First the exponents are directly added or subtracted depending on which is bigger. if the numerator is less than the denominator then we proceed to append the value of the numerator to 24 zeros and load it into an internal register say Temp that consists of 49-bits. Apart from that the final sign of the division is calculated separately. This is to ensure that whatever comes as the result is after the decimal point. owing to the fact that apart from taking care of the exponent we have to consider the cases of dealing with the mantissa. • • • • • .-39 . We initiate a counter and carry this process for 24 times. Now both the numbers in the IEEE-784 standard format are compared. If the divisor is more than the dividend then we left shift the dividend by 1 and add it to the two’s complement of the divisor.4 Floating Point Division • • • • This is more complicated then Multiplication. The logic for floating point division is as follows. And if it is zero. Once the quotient is full. The decimal is assumed to be before the MSB of the resulting quotient. we put a zero in the quotient. till the quotient is full.

however it is difficult or expensive to make a device that is optimized for both. DSPs can perform the mathematical calculations needed in digital signal processing. the processor performs an action that corresponds to an instruction or a part thereof. Mathematical calculation used in science. and so on. The clock speed (also called cycle). data is temporarily stored in small. local memory locations of 8. written in Hertz (Hz). A<B . finding use in everything from cellular telephones to advanced scientific instruments. Data manipulation such as word processing and database management 2. The basic task is to store the information. such as the size of the instruction set and how it interrupts are handled. the overall number of registers can vary from about ten to many hundreds. corresponds to the number of pulses per second. Consider another example of how a document is printed from a word processor. Computers are extremely capable in two broad areas 1. the program moves the data from .32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 4 DSP PROCESSORS 4. The computer continually tests the input device (mouse or keyboard) for the binary code that indicates “print the document”. organize the information and then retrieve the information such as saving the document on a floppy disk or printing it with laser printer. The number of bits in an instruction varies according to the type of data (between 1 and 4 8-bit bytes). and testing for inequalities (A=B. For instance. meaning a multiple of the motherboard frequency. etc). DEPARTMENT OF ECE PAGE NO. With each clock peak. DSPs are designed to perform the mathematical calculations needed in Digital Signal Processing. competitive position. Depending on the type of processor. 32 or 64 bits called registers. Data manipulations involve storing and sorting information. There are marketing issues involved: development and manufacturing cost. A microprocessor power can thus be characterized by the number of instructions per second that it is capable of processing.1 Processor: The processor is an electronic circuit that operates at the speed of an internal clock. engineering and digital signal processing. There are technical tradeoffs in the hardware design. 16.-40 . MIPS (millions of instructions per second) are the unit used and correspond to the processor frequency divided by the CPI.2 Digital Signal Processing Digital Signal Processors are microprocessors specifically designed to handle Digital Signal Processing tasks. 4. These tasks are accomplished by moving data from one location to another. These devices have seen tremendous growth in the last decade. All microprocessors can perform both tasks. When the processor executes instructions. consider a word processing program. When this code is detected. product life time. A measure called CPI (Cycles per Instruction) gives a representation of the average number of clock cycles required for a microprocessor to execute an instruction. Clock frequency is generally a multiple of the system frequency.

.32-BIT FLOATING POINT PROCESSOR TEC computer’s memory to the printer. While there is some data transfer and inequality evaluation in this algorithm. the math operations dominate the execution time.. while the output signal is denoted by y [ ]. it is infrequent and does not significantly affect the overall execution speed. DEPARTMENT OF ECE PAGE NO. the execution speed of most DSP algorithms is limited almost completely by the number of multiplications and additions required. While mathematics is occasionally used in this type of application. consider the implementation of an FIR digital filter. ... such as to keep track of the intermediate results and control the loops. i...e... y[n]. Using standard notation. An FIR filter performs this calculation by multiplying appropriate samples from the input signal by a group of coefficients denoted by: ... This is simply saying that the input signal has been convolved with a filter kernel consisting of: . depending on the application. there may only be a few coefficients in the filter kernel. For example. The task is to calculate the sample at location n in the output signal. the input signal is referred to by x [ ].. In comparison..-41 . the most common DSP technique.

-42 . 4.y[n]. The disadvantages of 32-bit processors are cost and system complexity. as well as the algorithms that can be applied..32-BIT FLOATING POINT PROCESSOR TEC Fig4. is found by multiplying samples from the input signal. with the advent of very fast floating point processing hardware. DSPs must also have a predictable execution time. 32-Bit processor chips tend to cost more because they have more transistors and pins than do 16-bit chips. You simply wait for the action to be completed before you give the computer its next assignment In comparison. the DSP must be able to maintain a sustained throughput of 20.. Floating point calculations also require a 32-bit processor for good efficiency. Also. and summing the products. Hence execution time is critical for selecting the proper device. DEPARTMENT OF ECE PAGE NO.1: Graphical representation of FIR digital filter design. design difficulty and so on.3.. The key point in off-line processing is that all of the information is simultaneously available to the processing program. It doesn’t matter if the processing takes 10 milliseconds or 10 seconds. After shaking is over. This is common in scientific research and engineering.2. . a geophysicist might use a seismometer to record the ground movement during the earthquake. In addition to performing mathematical calculations very rapidly. so as the cost . However. say. A 32-bit processor can offer a linear 32-bit address space with accompanying quick address calculations on a 32-bit data path.x[n-2]. converting a word processing document from one form to another. . most DSPs are used in applications where the processing is continuous. the traditional speed advantage of integer operations over floating point operations is decreasing. In these cases a 16-bit processor may suffice. There are many instances in which scaled integer arithmetic is more appropriate than floating point numbers to increase speed on some processors.. 16-Bit processors spend a significant amount of time manipulating stack elements when dealing with floating point numbers.. For example.by the filter kernel coefficients.x[n-1]. consider a designing of an audio signal in DSP system such as a hearing aid. whereas 32-bit processors are naturally suited to the size of the data elements. They also require 32 bit wide program memory and a generally larger printed circuit board than 16-bit processors. not having a defined start or end. floating point math must often be used to reduce the cost of programming a project.000 samples per second. Digital signal processors are designed to quickly carry out FIR filters and similar techniques. the information may be read into a computer and analysed in some way. There is less room on-chip for extra features such as hardware multipliers. x[n]. and to support code written in high level languages.000 samples per second. Difference between off-line processing and real time processing: In off-line processing. but these items will appear as chip fabrication technology gets denser. each sample in the output signal . In FIR filtering . For instance. There are a few reasons for why to not to make it faster than necessary because as speed increases. If suppose you are launching your desktop computer on some task . power consumption. Off-line processing is a realm of personal computers and mainframes. the entire input signal resides in the computer at the same time. If the digital signal is being received at 20.

at a 40 MHz clock speed. there are two serial ports that operate at 40 Mbits/second each. Likewise. This includes data. over and over. This is the world of digital signal processors. The von Neumann design is satisfactory when the contents of the task to be executed must be serial. they may input a group of samples perform the algorithm and output a group of samples. Architecture of digital signal processor: One of the biggest bottlenecks in executing DSP algorithm is transferring information to and from memory. perform the algorithm and output a sample.32-BIT FLOATING POINT PROCESSOR TEC In real-time processing. Most present day DSPs use this dual bus architecture. such as samples from the input signal and filter coefficients as well as program instructions.-43 . the data transfer rate is an incredible 240Mbytes/second. When all six parallel ports are used together. Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU). To improve upon this situation. two binary values (the numbers) must be passed over the data memory bus. Super Harvard Architecture idea is to build upon the Harvard architecture by adding features to improve the throughput. while six parallel ports each provide a 40 Mbytes/second data transfer. the output signal is produced at the same time that the input signal is acquired. While the SHARC DSPs are optimized in dozens of ways. this is needed in telephone communication. For example. Alternatively. program instructions and data can be fetched at the same time. Most of the computers are using this architecture today. Harvard Architecture. the binary codes that go into the program sequencer.4. Harvard architecture has separate memories for data and program instructions. For example. For instance. When two numbers are multiplied. The basis of Harvard design is that the data memory bus is busier than the program memory bus. These are extremely high speed connections. two areas are important enough to be included are an instruction cache. Super Harvard Architecture (SHARC). we might place the filter coefficients in program memory. Real time applications input a sample. it makes no difference if a radar signal is delayed by few seconds before being displayed to the operator. For instance. a 10 millisecond delay in a telephone call cannot be detected by the speaker or listener. while only one binary value (the program instruction) is passed over the program memory bus. Different architectures available are: Von Neumann Architecture. we start by relocating part of the "data" to program memory. Since the buses operate independently. . 4. and an I/O controller. DEPARTMENT OF ECE PAGE NO. The SHARC DSPs provides both serial and parallel communications ports. with separate buses for each. hearing aids and radar. improving the speed over the single bus design. while keeping the input signal in data memory.

-44 . The Super Harvard architecture takes advantage of this situation by including an instruction cache in the CPU. providing an additional interface to off-chip memory and peripherals. The main buses (program memory bus and data memory bus) are also accessible from outside the chip. this efficient transfer of data is called a high memory-access bandwidth.1: different architectures The Von Neumann architecture uses a single memory to hold both data and instructions. DEPARTMENT OF ECE PAGE NO. the Harvard architecture uses separate memories for data and instructions. This allows . providing higher speed.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. This means that all of the memory to CPU information transfers can be accomplished in a single cycle: the sample from the input signal comes over the data memory bus. This results in slower operation because of the conflict with the coefficients that must also be fetched along this path. the program instructions must be passed over the program memory bus. This means that the same set of program instructions will continually pass from program memory to the CPU. However. the program instructions can be pulled from the instruction cache. the coefficient comes over the program memory bus. DSP algorithms generally spend most of their execution time in loops. In comparison. In the jargon of the field. However. such as instructions. all DSPs can interface with external converters through serial or parallel ports. Some DSPs have on-board analog-to-digital and digital-toanalog converters. The Super Harvard Architecture improves upon the Harvard design by adding an instruction cache and a dedicated I/O controller. a feature called mixed signal.4. The first time through a loop. on additional executions of the loop. and the program instruction comes from the instruction cache. This is a small memory that contains about 32 of the most recent program instructions.

and is quite transparent to the programmer. for 32 bit data. Digital Signal Processors are designed to implement tasks in parallel. accessible at 40Mwords/second (160 Mbytes/second). data from registers 8-15 can be passed to the ALU. OR.32-BIT FLOATING POINT PROCESSOR TEC the SHARC DSPs to use a four Gigaword (16 Gbyte) memory. subtraction. extracting and depositing segments. The multiplier takes the values from two registers. NOT). At the top of the diagram are two blocks labelled Data Address Generator (DAG). In a single clock cycle. Compare this architecture with the tasks needed to implement an FIR filter. and similar functions. and the two results returned to any of the 16 registers. and a barrel shifter. data from registers 0-7 can be passed to the multiplier. Fig 4. XOR. The math processing is broken into three sections. an arithmetic logic unit (ALU). specifying where the information is to be read from or written to.-45 . such as shifting. All of the steps within the loop can be executed in a single clock cycle. This simplified diagram is of the Analog Devices SHARC DSP. logical operations (AND.2: Typical DSP architecture. absolute value. These control the addresses sent to the program and data memories. one for each of the two memories. and places the result into another register. In simpler microprocessors this task is handled as an inherent part of the program sequencer. DEPARTMENT OF ECE PAGE NO. conversion between fixed and floating point formats. multiplies them.4. and so on. . Elementary binary operations are carried out by the barrel shifter. The ALU performs addition. rotating. a multiplier. A powerful feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel.

though. since the programmer doesn’t generally need to worry about issues such as overflow. 32 bit floating-point DSPs divide a 32-bit data path into two parts: a 24-bit mantissa that can be used for either for integer values or as the base of a real number. While fixed-point DSP hardware performs strictly integer arithmetic. All floating point DSPs can also handle fixed point numbers. Double-width precision achieves much greater precision and dynamic range at the expense of speed. However. the fundamental difference between the two types of DSPs is in their respective numeric representations of data. double the overall throughput with four 16-bit (or eight 8-bit or two 32-bit) multipliers. underflow and round-off. the SHARC DSPs are optimized for both floating point and fixed point operations. with architectures designed for handheld and control applications. and an 8-bit exponent. the multiplier and ALU must be able to quickly perform floating point arithmetic. selecting either type of DSP depends mainly on whether the added computational capabilities of the floating-point format are required by the application.32-BIT FLOATING POINT PROCESSOR 4." fixed point arithmetic is much faster than floating point in general purpose computers. floating point programs often have a shorter development cycle. with DSPs the speed is about the same. loops.or floating-point decision in the past.For instance. each with a 16-bit word width that provides signed integer values within a range from –2^15 to2^15. The 32 bit DSP can also perform calculations using industry-standard doublewidth precision (64 bits. However. The 16M range of precision offered by 24 bits with the addition of an 8-bit exponent. Floating point (32 bit) has better precision and a higher dynamics range than fixed point (16 bit). Fixed point DSPs are cheaper than floating point devices." rather than just “Floating Point. a necessity to implement counters. and executes them with equal efficiency.-46 . As the terms fixed. Today. the instruction set must be larger and so on. the latter normalized in the form of scientific notation. TMS320C5x™ and TMS320C2x™ DSPs. and signals coming from the ADC and going to the DAC. respectively. since it requires multiple cycles for each operation. By contrast.and floating-point indicate. are based on single16-bit data paths. TMS320C64x™ DSPs. this doesn't mean that fixed point math will be carried out as quickly as the floating point operations. TI’s TMS320C62x™ fixed-point DSPs have two data paths operating in parallel.5. The internal architecture of a floating point device is more complicated than for a fixed point device. All the registers and data buses must be 32 bits wide instead of only 16. the SHARC devices are often referred to as "32-bit DSPs. floating-point DSPs support either integer or real arithmetic. it depends on the internal architecture . Both feature system-on-a-chip (SOC) integration with on-chip memory and a variety of high-speed peripherals to ensure fast throughput and design flexibility. In addition. Tradeoffs of cost and ease of use often heavily influenced the fixed. DEPARTMENT OF ECE PAGE NO. Comparison between Fixed Point and Floating Point System: TEC Both fixed. a result of the hardware being highly optimized for math operations.and floating-point DSPs are designed to perform the high-speed computations that underlie real-time signal processing. For this reason. including a 53-bit mantissa and an 11-bit exponent). . thus supporting a vastly greater dynamic range than is available with the fixedpoint format.

it's bad. this accumulator is just another 16 bit fixed point variable.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. in a 16 bit DSP it may have 32 to 40 bits. The only round-off error suffered is when the accumulator is scaled and stored in the 16 bit memory. Suppose we store in a 32 bit floating point format. DEPARTMENT OF ECE PAGE NO. greatly lowering the signal-to-noise ratio of the system. In traditional microprocessors. higher dynamic range.-47 . really bad.000 as a signed integer. This means that the signal-to –noise ratio for storing a floating point number is about 30 million to one. floating point has such low quantization noise that these techniques are usually not necessary. This is a special register that has 2-3 times as many bits as the other memory locations. except that the added noise is much worse. in a 500 coefficient FIR filter. each time we store a number in floating point notation. and a shorter development cycle. it illustrates the main point when many operations are carried out on each sample. In other words. The same thing happens when a number is stored as a 16-bit fixed point value. Although this is an extreme case.000 times less quantisation noise than fixed point. The gap between numbers is one ten-thousandth of the value of the number we are storing.5. suppose we store the number 10. For example.. while in the SHARC DSPs it contains 80 bits for fixed point use. DSPs handle this problem by using an extended precision accumulator. This is because the gaps between adjacent numbers are much larger. It can be rated in the form of signal to noise ratio and quantisation noise. Fixed point DSPs are generally cheaper. while for a fixed point number it is only about ten-thousand to one. The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly twenty to one. For instance. 32 bit floating system can do better than a 16 bit fixed point system in the rate of performance. In comparison. floating point has roughly 3. we add noise to the signal. Suppose we implement an FIR filter in fixed point. and add the product to an accumulator. Standard deviation of this quantisation noise is about one-third of the gap size. it must be round up or down by a maximum of one-half the gap size i. To do this. the noise on each output sample may be 500 times the noise on each input sample. and will correspondingly add quantization noise on each step. This extended range virtually eliminates round-off noise while the accumulation is in progress. . we need to scale the values being added. This strategy works very well.e. Here's the problem.1: Fixed versus floating point. while floating point devices have better precision. multiply it by the appropriate sample from the input signal. In the worst case. although it does limit how some algorithms must be carried out. we loop through each coefficient. The gap between this number and its adjacent number is about one ten-millionth of the value of the number. this quantization noise will simply add. To avoid overflow. Noise is signal is usually represented by its standard deviation. To store the number. For instance.

the possibility of an overflow or underflow needs to be considered after each operation. making them suitable for fixed point. 12-14 bits per sample is the crossover for using fixed versus floating point. In fixed point. and almost certainly need floating point to capture the large dynamic range. the development time will be greatly reduced if floating point is used. Considering number of bits are used in the ADC and DAC which can be considered as trade off for fixed and floating point. these issues do not arise in floating point. and the precision of fixed point is acceptable. The next thing to look at is the complexity of the algorithm that will be run . For example.32-BIT FLOATING POINT PROCESSOR TEC In addition to having lower quantization noise. In contrast. In comparison. In many applications. frequency domain algorithms. floating point will generally result in a quicker and cheaper development cycle. how the quantization errors are accumulating. floating point systems are also easier to develop algorithms for. the cost of the product will be reduced. The programmer needs to continuously understand the amplitude of the numbers. such as spectral analysis and FFT convolution. television and other video signals typically use 8 bit ADC and DAC. In comparison. FIR filtering and other operations in the time domain only require a few dozen lines of code.If it is relatively simple. Most DSP techniques are based on repeated multiplications and additions. . if it is more complicated. but the development cost will probably be higher due to the more difficult algorithms.-48 . and what scaling needs to take place. are very detailed and can be much more difficult to program. think floating point. but a more expensive final product. When fixed point is chosen. While they can be written in fixed point. the numbers take care of themselves. DEPARTMENT OF ECE PAGE NO. For instance. professional audio applications can sample with as high as 20 or 24 bits. In the reverse manner. think fixed point.

While only a single command is needed for floating point.32-BIT FLOATING POINT PROCESSOR TEC Figure 4. The RND and SAT options are ways of controlling rounding and register overflow. These are the many options needed to efficiently handle the problems of round-off.2: Fixed versus floating point instructions. and Fy are any of the 16 data registers. and MRB = Rx * Ry. In comparison. In other words. where Fn. For instance. Fn = Fx * Fy. This describes the ways that multiplication can be carried out for both fixed and floating point formats. Rx. or into one of the extended precision accumulators. DEPARTMENT OF ECE PAGE NO. scaling. The vertical lines indicate options. These are the multiplication instructions used in the SHARC DSPs. the value of any two registers can be multiplied and placed into another register.5. and may be fractional or integer (F or I). and format. Rn. the top-left entry in this table means that all the following are valid commands: Rn = Rx * Ry. It could not be any simpler.-49 . Fx. and MRF and MRB are 80 bit accumulators. look at all the possible commands for fixed point multiplication. The important idea is that the fixed point programmer must understand dozens of ways to carry out the very basic task of multiplication. MRF = Rx * Ry. . and Ry refer to any of the 16 data registers. This table also shows that the numbers may be either signed or unsigned (S or U). many options are needed for fixed point. In contrast. the floating point programmer can spend his time concentrating on the algorithm.

a cost difference of only a few dollars can be the difference between success and failure.1: Major trends in DSPs. As illustrated in (a). floating point is more common when greater performance is needed and cost is not important. However. 32-bit floating point has a higher dynamic range. As shown in (c). over one-half of engineers currently using 16 bit devices plan to migrate to floating point DSPs .6. The high throughput and computational power of DSPs often makes them an ideal choice for embedded designs. floating point is the fastest growing segment. this depends greatly on the application. such a . as shown in (c). This is mainly driven by consumer products that must have low cost electronics. and another 49% are considering the change.32-BIT FLOATING POINT PROCESSOR 4. In comparison. about twice as many engineers use fixed point as use floating point DSPs. about 38% of embedded designers have already switched from conventional microprocessors to DSPs. suppose you are designing a medical imaging system. such as cellular telephones.6 Trends in DSP: TEC Figure 4. meaning there is a greater difference between the largest number and the smallest number that can be represented. In (b). Fixed point is more popular in competitive consumer products where the cost of the electronics must be kept very low.-50 . A good example of this is cellular telephones. When you are in competition to sell millions of your product. However. DEPARTMENT OF ECE PAGE NO. About twice as many engineers currently use fixed point as use floating point DSPs. over one-half of engineers using 16-bits devices plan to migrate to floating point at some time in the near future. For instance.

the internal representations of data in floating-point DSPs are more exact than in fixed-point. While fixed-point coefficients are 16 bits. which would go beyond most application requirements in accuracy. this overflow headroom is 8 bits. Third. floating-point coefficients can be 24 bits or 53 bits of precision. .point devices. ensuring greater accuracy in end results. which is 24 bits for floating-point. Three data word widths are important to consider in the internal architecture of a DSP. but the performance is critical. In spite of the larger number of fixed point DSPs being used. or a 48-bit product for a single 24-bit by 24-bit multiplication. depending whether single or double precision is used. In fixed. a 32-bit product would be needed. For this application. the cost of the DSP is insignificant. the same as the signal data in DSPs. iterated MACs require additional bits for overflow headroom. there is the word width for holding the intermediate products of iterated multiply accumulate (MAC) operations. exponentiation vastly increases the dynamic range available for the application. Integrating the same proportion of overflow headroom in 32 bit floating-point DSPs would require 64 intermediate product bits (24 signal + 24 coefficient + 16 overflow). 16 bits for fixed-point. Second. 4. 16. in integer as well as real values. The first is the I/O signal word width. Finally. at a price of several hundred-thousand dollars each. For a single 16-bit by 16-bit multiplication. A wide dynamic range is important in dealing with extremely large data sets and with data sets where the range cannot be easily predicted. Fortunately. First. so that the hardware stays manageable while still providing more bits of inter mediate accuracy than the fixed-point format offers.-51 .32-BIT FLOATING POINT PROCESSOR TEC computed tomography scanner. or 32 bits for fixed-point DSPs. and can be 8. Only a few hundred of the model will ever be sold. making the total intermediate product word width 40 bits (16 signal + 16 coefficient + 8 overflow). DEPARTMENT OF ECE PAGE NO.7 Accuracy of Floating Point DSP The greater accuracy of the floating-point format results from three factors. the floating point market is the fastest growing segment. However. The precision can be extended beyond the 24 and 53 bits in some cases when the exponent can represent significant zeroes in the coefficient. through exponentiation the floating-point format enables keeping only the most significant 48 bits for intermediate products. The second word width is that of the coefficients used in multiplications. the 24-bit word width in floating-point DSPs yields greater precision than the 16-bit fixed-point word width.

. manually conversion from schematic level to gate level or gate level to layout level was becoming somewhat lengthy process and verifying the functionality of digital circuits at various levels became critical. Designers felt need to automate these processes. With the advent of new fabrication techniques designer can place more than 100 gates on an IC called MSI (Medium Scale Integration).. i.e. registers. i. multiplexes. This created new challenges to digital designers as well as circuit designers. and etc.-52 . one can create digital sub blocks (adders. Later Integrated Circuits (ICs) were invented. using this scale of integration people succeeded to make digital subsystems (Microprocessor. At this point design process started getting very complicated. In this process. because of manual converting the design from one level to other. where a designer can be able to place digital circuits on a chip consists of less than 10 gates for an IC called SSI (Small Scale Integration) scale.) on a chip. Existence of logic synthesis tools design engineer can easily translate to higher-level design description to lower levels. Rapid advances in Software Technology and development of new higher level programming languages taken place.1 INTRODUCTION TO VLSI: The first digital circuit was designed by using electronic components like vacuum tubes and transistors. This may be leading to development of sophisticated electronic products for both consumer as well as business. This level is LSI (Large Scale Integration). Functional verification and Logic verification of design can be done using CAD simulation tools with greater efficiency. Using latest CAD tools could solve the problem. At this point design process still became critical. DEPARTMENT OF ECE PAGE NO. Using design at this level.e. I/O peripheral devices and etc. One can fabricate a chip contains more than Million of gates. for design electronics circuits with assistance of software programs. People could able to develop CAD/CAE (Computer Aided Design/Computer Aided Engineering) tools. counters.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER: 5 INTRODUCTION 5. With advent of new technology. .) on an IC. It became very easy to a designer to verify functionality of design at various levels. CMOS (Complementary Metal Oxide Semiconductor) process technology. This way of designing (using CAD tools) is certainly a revolution in electronic industry.

DEPARTMENT OF ECE PAGE NO.3 INTRODUCTION TO VHDL: VHDL is acronym for VHSIC hardware Description language. .32-BIT FLOATING POINT PROCESSOR 5.2 IC DESIGN FLOW: SPECIFICATION Behavioral Description Constraints Behavioral simulation RTL Description Synthesis r G a t e S p e c i f i c a t a i v o i n o s r a l TEC B e h a v i o r a l Constraints L e v Gate level netlist e l Logic Synthesis Automatic P&R layout N e t l i s t Fabrication F u S n i c m u t l i a o t i n o a n Functional simulation l S i mL lib ui lb a Logic simulation t i o n L Lay Out a Manageme y nt o u t Behavioral simulation 5.-53 .

the language was upgraded with new features. an IEEE standard has to be reballoted every 5 years so that it may remain a standard so that it may remain a standard. models written in this language can be verified using a VHDL simulator. Different chip vendors can provide VHDL descriptions of their components to system designers. The IEEE in the December 1987 standardized VHDL language. The VHDL language can be regarded as an integrated amalgamation of the following languages: Sequential language Concurrent language Net-list language Timing specifications Waveform generation language VHDL This language not only defines the syntax but also defines very clear simulation semantics for each language construct.3. According to IEEE rules. ranging from the algorithmic level to the gate level. The official language description appears in the IEEE standard VHDL language Reference manual. Thus. 5.1 HISTORY: The requirements for the language were first generated in 1988 under the VHSIC chips for the department of Defense (DOD). documentation. The language has also been recognized as an American National Standards Institute (ANSI) standard. the syntax of many constructs was made more uniform. Consequently. It is a hardware description language that can be used to model a digital system at many levels of abstraction. DEPARTMENT OF ECE PAGE NO. This new version of the language is known as the IEEE STD 1076-1993. The language can be used as exchange medium between chip vendors and CAD tool users. and many ambiguities present in the 1987 version of the language were resolved. Reprocurement and reuse was also a big issue. This subset is usually sufficient to model most applications .32-BIT FLOATING POINT PROCESSOR TEC VHSIC is acronym for very high speed Integrated Circuits. and verification of the digital systems was generated.3. Therefore.-54 . 5.The complete language. The language can be used as a communication medium between different CAD and CAE tools . a need for a standardized hardware description language for the design. however. available from IEEE.2 CAPABILITIES The following are the major capabilities that the language provides along with the features that the language provides along with the features that differentiate it from other hardware languages. has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. this version of the language is known as the IEEE STD 1076-1987.

human-readable. 1. and there are no limitations imposed by the language on the size of the design. As a set of interconnected components (to represent structure) 2. and machine-readable. End component. . The language is publicly available. and Boolean equations. DEPARTMENT OF ECE PAGE NO. The language supports flexible design methodologies: top-down. As a set of concurrent assignment statements (to represent data flow) 3. in turn. This model specifies the external view of the device and one or more internal views. B. The internal view of the device specifies functionality or structure. can be modeled as a set of interconnected subcomponents. In VHDL each device model is treated as a distinct representation of a unique device. called an Entity. Z:out BIT). which contains one external view and one or more internal views. CARRY).3.32-BIT FLOATING POINT PROCESSOR TEC The language supports hierarchy. such as finite –state machine descriptions. The language supports three basic different styles: Structural. Dataflow.3 HARDWARE ABSTRACTION: VHDL is used to describe a model for a digital hardware device. or mixed.-55 . Y: in BIT. can be modeled using the language. Such a model for the HALF_ADDER entity. each component. Begin X1: Xor2portmap (A. M: in BIT. and behavioral. SUM) A1: AND2portmap (A. As a set of sequential assignment statements (to represent behavior) As any combination of the above three. It supports a wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. while the external view specifies the interface of the device through which it communicates with the other modules in the environment. Each Entity is described using one model. End component. Structural style of modeling: In this one an entity is described as a set of interconnected components. B. that is a digital can be modeled as asset of interconnected components. Component And2 Port (L. It supports both synchronous and asynchronous timing models. N:outBIT). is described in a n architecture body Architecture ha of ha is Component Xor2 Port (X. The Entity is thus a hardware abstraction of the actual hardware device. 5. Arbitrarily large designs can be modeled using the language. bottom-up. Various digital modeling techniques. Architecture Body: An architecture body using any of the following modeling styles specifies the internal details of an entity.

5. do not explicitly specify the structure of the entity but merely its functionality. These sets of sequential statements. Both PLI (Programming Language Interface) and VCD (Value Change Dump) are also supported in Active-HDL. SIMULATION TOOL 5. single simulation kernel. A process statement is a concurrent statement that can appear with in an architecture body.1. EDIF: Active-HDL supports Electronic Design Interchange Format version 2 0 0. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by the position.3. DEPARTMENT OF ECE PAGE NO. Verilog. which are specified inside a process statement.1.5 BEHAVIORAL STYLE OF MODELING: The behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specific order. 5. The declared components are instantiated in the statement part of the architecture body using component instantiation.1 Active HDL Overview: Active-HDL is an integrated environment designed for development of VHDL. several debugging tools.3. Verilog compiler.the entity declaration for half adder specifies the interface ports for this architecture body. It comprises three different design entry tools. The name of the architecture body is ha .32-BIT FLOATING POINT PROCESSOR TEC End ha. The data flow model for the half adder is described using two concurrent signal assignment statements .4.2.4. . Standards Supported VHDL: The VHDL simulator implemented in Active-HDL supports the IEEE Std. the symbol <=implies an assignment of a value to a signal. 13641995 standard.4 INTRODUCTION TO HDL TOOLS 5. 1076-1993 standard. Two component declarations are present in the declarative part of the architecture body.In a signal assignment statement. The architecture body is composed of two parts: the declaration part and the statement part. the flow of data through the entity is expressed primarily using concurrent signal assignment statements. designs.4. graphical and textual simulation output viewers. VHDL'93 compiler. and EDIF and mixed VHDL-Verilog-EDIF designs. 5. and libraries. 5.-56 .4 DATAFLOW STYLE OF MODELING: In this modeling style. and auxiliary utilities designed for easy management of resource files. Verilog: The Verilog simulator implemented in Active-HDL supports the IEEE Std.

The editor automatically translates graphically designed diagrams into VHDL or Verilog code.4. the maintenance. The editor is tightly integrated with the simulator to enable debugging source code. 4. the communication of hardware design and test verification data.1/D1. The keyword coloring is also available when HDL Editor is used for editing macro files. 3.32-BIT FLOATING POINT PROCESSOR VITAL: TEC The simulator provides built-in acceleration for VITAL packages version 3. 1. WAVES: Active-HDL supports automatic generation of test benches compliant with the WAVES standard. The basis for this implementation is a draft version of the standard dated to May 1997 (IEEE P1029.0. that is: a. It allows you to graphically edit waveforms so as to create desired test vectors. Design Browser: The Design Browser window displays the contents of the current design. modification and procurement of hardware system. Resource files attached to the design. HDL Editor: HDL Editor is a text editor designed for HDL source files.0 May 1997). and Tcl scripts. Block Diagram Editor: Block Diagram Editor is a graphical tool designed to create block diagrams. The editor automatically translates graphically designed diagrams into VHDL or Verilog code. 5. The contents of the default-working library of the design.-57 . . DEPARTMENT OF ECE PAGE NO. 2. The language has been designed to enable the user to work with Active-HDL without using the graphical user interface (GUI). The VITAL-compliant models can be annotated with timing data from SDF files. Perl scripts. It displays specific syntax categories in different colors (keyword coloring). The WAVES standard (Waveform and Vector Exchange to Support Design and Test Verification) defines a formal notation that supports the verification and testing of hardware designs. b.3 ACTIVE-HDL Macro Language: All operations in Active-HDL can be performed using Active-HDL macro language. Waveform Editor: Waveform Editor displays the results of a simulation run as signal waveforms. 5.1. SDF files must comply with OVI Standard Delay Format Specification Version 2. State Diagram Editor: State Diagram Editor is a graphical tool designed to edit state machine diagrams.

vhd) • Verilog file (. d. The structure of the design unit selected for simulation. When you choose a menu command or toolbar button for compilation. and scripts. Verilog. or EDIF file containing HDL code (or net list) generated from the diagram. A net list is a set of statements that specifies the elements of a circuit (for example. a source file can be on of the following: • VHDL file (. • Event-Driven Simulation • Cycle-Based Simulation The simulator supports hybrid simulation – some portions of a design can be simulated in the event-driven kernel while the others in the cycle-based kernel. All Active-HDL tools output their messages to Console. • The Active-HDL simulator provides two simulation engines. and EDIF. Active-HDL provides three compilers. . the compiler analyzes the intermediate VHDL.4.bde) In the case of a block or state diagram file. respectively for VHDL. 6. Verilog. VHDL.asf) • Block diagram file (. DEPARTMENT OF ECE PAGE NO.4 Simulation: • The purpose of simulation is to verify that the circuit works as desired. or EDIF objects declared within a selected region of the current design. Verilog.-58 . Analyzed design units contained within the file are placed into the working library in a format understandable for the simulator. Console window: The Console window is an interactive input-output text device providing entry for Active-HDL macro language commands. Active-HDL automatically employs the compiler appropriate for the type of the source file being compiled.32-BIT FLOATING POINT PROCESSOR TEC c. transistors or gates) and their interconnection. Cycle-based simulation is significantly faster than event-driven. Compilation: Compilation is a process of analysis of a source file. In Active-HDL. macros. 5.v) • EDIF net list file (.EDIF) • State diagram file (.

32-BIT FLOATING POINT PROCESSOR TEC Fig4.4. including ModelSim Xilinx Edition and the HDL Bencher test bench generator. The Xilinx implementation tools continue the process into a placed and routed FPGA or fitted CPLD.6. ABEL) • Schematic design files • EDIF • NGC/NGO • State Machines • IP Cores From your source files.6 SYNTHESIS TOOL: 5.2 Design Entry: • ISE Text Editor . ISE enables you to quickly verify the functionality of these sources using the integrated simulation capabilities.6. This overview explains the general progression of a design through ISE from start to finish.4. 5. DEPARTMENT OF ECE PAGE NO.The ISE Text Editor is provided in ISE for entering design code and viewing reports. .4. HDL sources may be synthesized using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE.3. including: • HDL (VHDL.1 OVERVIEW OF XILINX ISE: Integrated Software Environment (ISE) is the Xilinx design software suite. Verilog HDL. and finally produce a bit stream for your device configuration.1: Simulation 5. ISE enables you to start your design with any of a number of different source types.-59 .5.

State CAD State Machine Editor . Global logic.The Engineering Capture System (ECS) is a graphical user interface (GUI) that allows you to create. transforms. including routing. DEPARTMENT OF ECE PAGE NO. and to view and modify the placed design.The CPLDFit process maps a net list(s) into specified devices and creates the JEDEC programming file. view. • • • • • • • . placing or routing an FPGA design. and pin assignments. FPGA Editor .The CORE Generator System is a design tool that delivers parameterized cores optimized for Xilinx FPGAs ranging in complexity from simple arithmetic operators such as adders.-60 . and memories. With Timing Analyzer. Map . analysis can be performed immediately after mapping. and actions in a graphical editor.The Timing Analyzer provides a way to perform static timing analysis on FPGA and CPLD designs. and edit schematics and symbols for the Design Entry step of the Xilinx® design flow.6.State CAD allows you to specify states. CORE Generator . FIFOs.The Constraints Editor allows you to create and modify the most commonly used timing constraints.The Pin out and Area Constraints Editor (PACE) allows you to view and edit I/O.3 Implementation: • Translate . to system-level building blocks such as filters. Place and Route (PAR) .The PAR program accepts the mapped design. Timing Analyzer .The Translate process runs NGDBuild to merge all of the input net lists as well as design constraint information into a Xilinx database file. Constraints Editor . Chip Viewer (CPLD only) .The Map program maps a logical design to a Xilinx FPGA.4. places and routes the FPGA. and after fitting and routing a CPLD design. transitions. equations. Floor planner . The state machine will be created in HDL.The Chip Viewer tool provides a graphical view of the inputs and outputs. and Area Group constraints. • • • • 5. PACE . macro cell details.32-BIT FLOATING POINT PROCESSOR • TEC Schematic Editor .The FPGA Editor allows you view and modify the physical implementation. and produces output for the bit stream generator.The Floor planner allows you to view a graphical representation of the FPGA. Fit (CPLD only) .

4 Device Download and Program File Formatting: • BitGen .6. iMPACT . and subsequently allows you to configure your device.32-BIT FLOATING POINT PROCESSOR TEC 5. • • • .The iMPACT tool generates various programming file formats. Integration with ChipScope Pro.4.The BitGen program receives the placed and routed design and produces a bit stream for Xilinx device configuration.XPower enables you to interactively and automatically analyze power consumption for Xilinx FPGA and CPLD devices.-61 . DEPARTMENT OF ECE PAGE NO. XPower .

1 simulation results for floating point addition The inputs given are in the form of hexadecimal and converted into binary format.-62 .32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 6 SIMULATION RESULTS Simulation for floating point addition. Remaining bits are mantissa bits whose addition is performed and the result is converted back into hexadecimal form. This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .1 simulation results of floating point addition Simulation result for 32 bit floating point addition can be explained as follows: Fig 6. multiplication and division are done using active HDL tool and the results are as follows: 6. subtraction. DEPARTMENT OF ECE PAGE NO. .

-63 .2 simulation results for floating point subtraction Simulation result for 32 bit floating point subtraction can be explained as follows: Fig 6. . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .2 simulation results for floating point subtraction The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose subtraction is performed and the result is converted back into hexadecimal form. DEPARTMENT OF ECE PAGE NO.

3 simulation results for floating point multiplication Simulation result for 32 bit floating point multiplication can be explained as follows: Fig 6.32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose multiplication is performed and the result is converted back into hexadecimal form.-64 . This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out . .3 simulation results for floating point multiplication The inputs given are in the form of hexadecimal and converted into binary format. DEPARTMENT OF ECE PAGE NO.

This converted inputs are represented in the form of IEEE 32 bit floating point standard representation and hence the 31st bit which are sign bits of both the inputs are checked and then the exponent bits which are the next eight bits are also checked and the necessary operation is carried out .4 simulation results for floating point division The inputs given are in the form of hexadecimal and converted into binary format.32-BIT FLOATING POINT PROCESSOR TEC 6. Remaining bits are mantissa bits whose division is performed and the result is converted back into hexadecimal form.4 simulation results for floating point division Simulation result for 32 bit floating point can be division explained as follows: Fig 6.-65 . . DEPARTMENT OF ECE PAGE NO.

• 7. Basic arithmetic operations such as addition.1 CONCLUSIONS • Floating point numbers are been converted into required IEEE floating point standard representation.2 FUTURE SCOPE • 32 bit floating point arithmetic operations can be extended to 64 bit floating point arithmetic operations.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 7 CONCLUSION AND FUTURE SCOPE 7. • • Procedures for performing basic arithmetic operations are been formed. multiplication and division are been performed on floating point by representing the numbers in IEEE 32-bit floating point standard. . The Functional-simulation has been successfully carried out with the results matching with the expected ones.-66 . • Advanced booth algorithm can also be implemented for 32 bit floating point multiplication. DEPARTMENT OF ECE PAGE NO. subtraction.

Since the subset must be determined in real time during system operation. However. enables the robot control circuitry to deal with unpredictable circumstances in a predictable manner. feedback is well out of the ordinary operating range.-67 . enable imaging systems to achieve a much higher level of recognition and definition for the user. together with the device’s more accurate internal representations of data. ultrasound and other sources must be defined and processed to create output images that provide useful diagnostic information. The greater precision of signal data. Wide dynamic range also plays a part in robotic design. Image recognition used for medicine is similar to audio in requiring a high degree of accuracy. The wide dynamic range of a floating-point DSP. unpredictable events can occur on an assembly line. The radar system may be tracking in a range from 0 to infinity. or something might unexpectedly block its range of motion. x-rays. a robot functions within a limited range of motion that might well fit within a fixed-point DSP’s dynamic range. For instance.32-BIT FLOATING POINT PROCESSOR TEC CHAPTER 8 APPLICATIONS Floating-point applications are those that require greater computational accuracy and flexibility than fixed-point DSPs. and a system based on a fixed-point DSP might not offer programmers an effective means of dealing with the unusual conditions. Normally. but need to use only a small subset of the range for target acquisition and identification. Many levels of signal input from light. Radar for navigation and guidance is a traditional floating-point application since it requires a wide dynamic range that cannot be defined ahead of time and either uses the divide operator or matrix inversions. it would be all but impossible to base the design on a fixed-point DSP with its narrow dynamic range and quantization effects. the robot might weld itself to an assembly unit. In these cases. DEPARTMENT OF ECE PAGE NO. however. .

14(7) 68-78 REFERENCES www. July 1981. S. Hayes. 281-317 Yamamoto. Proc. W.) Introduction to Computer Architecture. 28-30 November 1986.1109/SNPD. (1975) Stack computers. Pacific Grove CA.2007. M. P. T. Williams.. pp. 197-210 Jones.ieeexplore. Computer. & Zaremba.org/portal/web/csdl/doi/10.computer. In: Stone. J. Prentice-Hall. New York McKeeman. (Ed. (1987) The Implementation of Functional Programming Languages. H. 1975.intel. pp. Chicago.com . R.46 www.. M.-68 . DEPARTMENT OF ECE PAGE NO. Science Research Associates. (1986) A 32 bit processor architecture for direct execution of Forth.32-BIT FLOATING POINT PROCESSOR TEC BIBLIOGRAPHY Fraeman. (1981) A survey of high-level language machines in Japan.org www.ieee. In: 1986 FORML Conf..

DEPARTMENT OF ECE PAGE NO. architecture Fadd of Fadd is --***************************************************************** --* This Function performs Floating Point Addition * --***************************************************************** Function float_add(Acc. b : in std_logic_vector(31 downto 0).std_logic_arith.std_logic_unsigned.-69 .Compute Ea-Eb -2. y : out std_logic_vector(31 downto 0) ).all. variable Temp :Std_logic_vector(6 downto 0). use IEEE. use IEEE.Add with another Mantissa * -*************************************************************************** --**************This Module performs Floating Point Addition***************** library IEEE.all.std_logic_1164. --*********Generating loop to convert 7-bit Binary to integer******* xxx: for i in 0 to 6 loop . begin temp:=x. end Fadd. use IEEE. --***************Input and Output Declarations******************************* entity Fadd is port ( a : in std_logic_vector(31 downto 0).Shift the that has lesser Exponent by Ea-Eb places to the right * -3.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --**************variable Declararions****************************** variable sum :integer:=0.32-BIT FLOATING POINT PROCESSOR TEC APPENDIX -*************************************************************************** --Entity Name : Fadd --Entity Description : Floating Point Addition involves three steps -1.all.

if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).b : std_logic. end loop. end function.Alignement of Mantissas --***************************************************************** case Z is when "00" => Mb:=MbIn. Z :=(a&b). -.Subtraction of Exponents --*2.-70 .s2 : std_logic. variable X : std_logic_vector(31 downto 0).Two Exponents including Sign variable IR : std_logic_vector(22 downto 0). -. return sum.Z : std_logic_vector(1 downto 0). -. Ma:=MaIn.Mb : std_logic_vector(22 downto 0).Sign Of Resultant Mantissa variable W. -. --***************************************************************** --*Equalization of Exponents includes two steps --*1. end loop.Eb : std_logic_vector(7 downto 0). DEPARTMENT OF ECE PAGE NO. end if.Mangitude Of Two mantissas variable ES : std_logic. else TEC Sum:=Sum.Resultant Mantissa variable IE : std_logic_vector(6 downto 0). Ea :=Acc(30 downto 23).Final Result begin MaIn:=Acc(22 downto 0).32-BIT FLOATING POINT PROCESSOR if (temp(i)='1')then sum:=sum+2**i. Es:=Eb(7) . -. -. -.Sign Of Two mantissas variable Sign : std_logic. Eb :=Data(30 downto 23).Resultant Exponent variable Ns : integer. --*********************Variable Declarations************************ variable MaIn : std_logic_vector(22 downto 0).Number Of Shifts variable Ma. b :=Data(31).Sign Of Resulant Exponent variable a. -. MbIn:=Data(22 downto 0). -. -.Internal Register variable Ea. -. for x in 1 to Ns loop Ma := ('0' & Ma(22 downto 1)). a :=Acc(31). -.Sign Of Two exponents variable s1. IE:=Eb(6 downto 0).Internal Register variable MbIn : std_logic_vector(22 downto 0).

Es:=Ea(7). when "10" => Mb:=MbIn. when "01" => Mb:=MbIn. end loop. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). IE:=Eb(6 downto 0). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). Ma:=MaIn. end loop. ES:=Ea(7). NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)). IE:=IE. . if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)).-71 . IE:=Ea(6 downto 0). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Ma:=Ma. DEPARTMENT OF ECE PAGE NO.32-BIT FLOATING POINT PROCESSOR TEC elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). Mb:=Mb. Ma:=MaIn. Ma:=MaIn. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). else NS:=Ns. end if. ES:=Ea(7). when "11" => Mb:=MbIn. ES:=Eb(7). ES:=Ea(7). IE:=Ea(6 downto 0). IE:=Ea(6 downto 0). end loop. end loop. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)).

end if. --***********logic for the sign of the mantissa********************** s1:=Acc(31). when others => Null. elsif(Ea<Eb) then sign:='1'. ES:=Eb(7). s2:=Data(31). else NS:=Ns. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'. --******************Addition of Mantissas**************************** IR:=Ma+Mb. elsif(Ma=Mb) then sign:='0'. Ma:=Ma. if(Ea>Eb) then sign:='0'. sign:='1'. end if. PAGE NO. case W is when "00" => when "11" => when "01" => when "10" => . ES:=Ea(7). Mb:=Mb. end loop. else sign:=sign. end if.-72 . W :=(s1&s2). IE:=Eb(6 downto 0). else sign:=sign. DEPARTMENT OF ECE sign:='0'. end case. IE:=IE.32-BIT FLOATING POINT PROCESSOR TEC for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). elsif(Ma<Mb) then sign:='1'. if(Ea>Eb) then sign:='1'.

else sign:=sign. else sign:=sign. elsif(Ma<Mb) then sign:='0'. --***********Final Result After Addition************************** X:=(sign & ES & IE & IR(22 downto 0)).b). return X. DEPARTMENT OF ECE PAGE NO. when others => null. end Fadd. elsif(Ea=Eb) then if(Ma>Mb) then sign:='1'. end process.-73 * .b) begin y<=float_add(a. begin process(a. end case. elsif(Ma=Mb) then sign:='0'. TEC -*************************************************************************** --Entity Name : Fsub * --Entity Description : Floating Point Addition involves three steps . end if.32-BIT FLOATING POINT PROCESSOR elsif(Ea<Eb) then sign:='0'. end function. end if.

. end Fsub.all.std_logic_arith. begin temp:=x.std_logic_unsigned.Subtract with another Mantissa * * TEC * -*************************************************************************** library IEEE.std_logic_1164. use ieee.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --************Function to convert 7-bit binary to integer********** Function to_integer(x:in std_logic_vector(6 downto 0)) return integer is --*********************Variable Declarations*********************** variable sum : integer:=0. architecture F_sub of Fsub is --***************************************************************** --* This Function performs Floating Point Subtraction * --***************************************************************** Function float_sub(Accout. --***************Input and Output Declarations****************************** entity Fsub is port ( a : in STD_LOGIC_VECTOR (31 downto 0). y : out std_logic_vector(31 downto 0)). DEPARTMENT OF ECE PAGE NO. use IEEE.32-BIT FLOATING POINT PROCESSOR ----1.Shift the that has lesser Exponent by Ea-Eb places to the right * 3. use ieee.-74 .Compute Ea-Eb 2.all. b : in STD_LOGIC_VECTOR (31 downto 0). variable Temp : Std_logic_vector(6 downto 0).all.

variable X : std_logic_vector(31 downto 0).Sign Of Resultant Mantissa variable W. -. b :=Data(30).s2 : std_logic.Sign Of Two Mantissas variable sign : std_logic. -.Subtraction of Exponents * * .Mangitude Of Two Mantissas variable ES : std_logic. -. -. Ea :=Accout(30 downto 23).Resultant Exponent variable Ns : integer. Z :=(a&b).Mb : std_logic_vector(22 downto 0). end function. -. --***************************************************************** --*Equalization of Exponents includes two steps * * --*1. DEPARTMENT OF ECE PAGE NO.Number Of Shifts variable Ma.Resultant Mantissa variable IE : std_logic_vector(6 downto 0).Two exponents Including Sign variable IR : std_logic_vector(22 downto 0).b : std_logic. -. else Sum:=Sum.Internal Register variable Ea. -. -.Final Result begin MaIn:=Accout(22 downto 0). end loop. MbIn:=Data(22 downto 0). Eb :=Data(30 downto 23).Z : std_logic_vector(1 downto 0). -. -.Sign Of Resulant Exponent variable a.32-BIT FLOATING POINT PROCESSOR xxx: for i in 0 to 6 loop if (temp(i)='1')then sum:=sum+2**i. a :=Accout(30). return sum.Eb : std_logic_vector(7 downto 0). end if. -.-75 .MbIn: std_logic_vector(22 downto 0).Sign Of Two Exponents variable s1. --*********************variable Declarations*********************** TEC variable MaIn.

NS:=to_integer(Ea(6 downto 0)+Eb(6 downto 0)).-76 . end loop. ES:=Ea(7). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). ES:=Ea(7). Ma:=MaIn. IE:=Ea(6 downto 0). . when "01" => Mb:=MbIn. end if. TEC * for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). DEPARTMENT OF ECE PAGE NO. IE:=Ea(6 downto 0). elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). else NS:=Ns.Alignement of Mantissas * --***************************************************************** case Z is when "00" => Mb:=MbIn.32-BIT FLOATING POINT PROCESSOR --*2. ES:=Ea(7). end loop. IE:=IE. IE:=Eb(6 downto 0). for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). Mb:=Mb. ES:=Eb(7). end loop. Ma:=MaIn. Ma:=Ma.

ES:=Ea(7). TEC Ma:=MaIn. if((Ea(6 downto 0))<(Eb(6 downto 0))) then NS:=to_integer(Eb(6 downto 0)-Ea(6 downto 0)). Mb:=Mb. . for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). NS:=to_integer(Eb(6 downto 0)+Ea(6 downto 0)). end loop. elsif((Eb(6 downto 0))<(Ea(6 downto 0))) then NS:=to_integer(Ea(6 downto 0)-Eb(6 downto 0)). Ma:=Ma. IE:=Ea(6 downto 0). when others => null. IE:=IE. IE:=Eb(6 downto 0).32-BIT FLOATING POINT PROCESSOR when "10" => Mb:=MbIn. when "11" => Mb:=MbIn. for x in 1 to Ns loop Mb:=('0' & Mb(22 downto 1)). Ma:=MaIn. --******************Subtraction of Mantissas************************ IR:=Ma-Mb. IE:=Eb(6 downto 0). end loop. ES:=Ea(7). end case.-77 . end loop. else NS:=Ns. DEPARTMENT OF ECE PAGE NO. for x in 1 to Ns loop Ma:=('0' & Ma(22 downto 1)). end if. ES:=Eb(7). ES:=Eb(7).

else sign:=sign. when "01"=> if(Ea>Eb)then sign:='0'. elsif(Ma<Mb) then sign:='0'. end if. end if. case W is when "00"=> sign:='0'. elsif(Ea=Eb) then if(Ma>Mb) then sign:='0'.-78 . elsif(Ma<Mb) then sign:='1'. end if. else sign:=sign. elsif (Ea<Eb) then sign:='0'. elsif(Ea<Eb) then sign:='1'. else sign:=sign. s2:=Data(31).32-BIT FLOATING POINT PROCESSOR TEC --***********logic for the sign of the mantissa********************** s1:=Accout(31). else sign:=sign. DEPARTMENT OF ECE PAGE NO. when "10"=> if (Ea>Eb)then sign:='1'. end if. . W:=(s1&s2). elsif (Ma=Mb) then sign:='0'. when "11"=> sign:='1'. elsif (Ea=Eb) then if(Ma>Mb) then sign:='1'. elsif (Ma=Mb) then sign:='0'.

--***********Final Result After Subtraction************************ X:=(sign & ES & IE & IR(22 downto 0)). end Fmul. DEPARTMENT OF ECE PAGE NO.all.b).-79 .Addtion of the Exponents 5.32-BIT FLOATING POINT PROCESSOR TEC when others=> null.b) begin y<=float_sub(a.std_logic_1164. end process. . end function. use IEEE.all. use IEEE. end case. b: in STD_LOGIC_VECTOR (31 downto 0). return X.std_logic_unsigned. -************************************************************************** --Entity Name : Fmul * -* --Entity Description : Floating Point Multiplication Two steps * --1. --***************Input and Output Declarations*********************** entity Fmul is port ( a: in STD_LOGIC_VECTOR (31 downto 0).Multiplication of the Mantissas * * -************************************************************************** library IEEE. end f_sub. y: out STD_LOGIC_VECTOR (31 downto 0) ). begin process(a.

Z :=(s1&s2).Final Result begin Carry:='0'.m2 : std_logic_vector(10 downto 0). m2 :=Data(10 downto 0).Resultant Mantissa variable carry : std_logic. -. when others=> s:='1'.Magnitude Of Two Exponents variable c : std_logic. m1 :=Accout(10 downto 0). -. end case.Carry variable W.Two Exponents Icluding Sign variable m1. -.Eb : std_logic_vector(6 downto 0). -. DEPARTMENT OF ECE PAGE NO.Data:in std_logic_vector(31 downto 0)) return std_logic_vector is --*********************variable Declarations*********************** variable e1. -.e2 : std_logic_vector(7 downto 0). .Sign Two Exponents variable s1.Resultant exponent variable m : std_logic_vector(21 downto 0). e1 :=Accout(30 downto 23).Z : std_logic_vector(1 downto 0). -. e2 :=Data(30 downto 23). when "11" => s:='0'.Sign Of Resultant Mantissa variable a.-80 . --************logic for the sign of the Mantissa******************* s1:=Accout(31). -. variable x : std_logic_vector(31 downto 0). -.Sign Of Resultant Exponent variable e : std_logic_vector(6 downto 0).32-BIT FLOATING POINT PROCESSOR architecture F_mul of Fmul is --***************************************************************** --* This Function performs Floating Point Multiplication * TEC --***************************************************************** Function float_mul(Accout.Magnitude O Two Mantissas variable s : std_logic. -. -.b : std_logic. s2:=Data(31). -. case Z is when "00" => s:='0'.sign Two Mantissas variable Ea.s2 : std_logic.

end if. else c:='0'. elsif(Ea<Eb) then c:='1'. a :=Accout(30). --*************logic for multiplication************************* m:=m1*m2. e:=Ea-Eb. W :=(a&b). Eb:=e2(6 downto 0). elsif(Ea<Eb) then c:='0'. e:=Ea+Eb. when "01" => if(Ea>Eb) then c:='0'. b :=Data(30). end if. c:='1'. . when "11" => when others => null. when "10" => if(Ea>Eb) then c:='1'. e:=Eb-Ea. e:="0000000". case W is when "00" => c:='0'. e:=Ea-Eb. e:=Eb-Ea.32-BIT FLOATING POINT PROCESSOR TEC --************logic for the sign of the exponent******************* Ea:=e1(6 downto 0). DEPARTMENT OF ECE PAGE NO. e:=Ea+Eb. else c:='0'. e:="0000000". end case.-81 .

32-BIT FLOATING POINT PROCESSOR --***********Final Result After Multiplication******************

TEC

x:=(s & c & e(6 downto 0) &Carry & m(21 downto 0)); return x; end function; begin process(a,b) begin y<=float_mul(a,b); end process; end F_mul; *********************************************************************** --Entity Name : Fdiv * --Entity Description : Floating Point Division includes Five steps * -----1.Check for Zeros 2.Evaluate the sign 3.Align the Dividend 4.Subtraction of Exponents 5.Divide the Mantissas * * * * *

-************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --***************Input and Output Declarations****************************** entity Fdiv is port ( a: in STD_LOGIC_VECTOR (31 downto 0); b: in STD_LOGIC_VECTOR (31 downto 0); y: out STD_LOGIC_VECTOR (31 downto 0) ); end Fdiv; architecture F_div of Fdiv is --***************************************************************** --* This Function performs Floating Point Division * . DEPARTMENT OF ECE PAGE NO.-82

32-BIT FLOATING POINT PROCESSOR

TEC

--***************************************************************** Function float_div(Accout,Data:std_logic_vector(31 downto 0)) return std_logic_vector is --*********************Variable Declarations********************** variable m1,m2 :std_logic_vector(22 downto 0); -- Magnitude Two Mantissas variable e1,e2 :std_logic_vector(7 downto 0); -- Two Exponents Including Sign variable s1,S2 :std_logic; -- Sign Of Two Mantissas variable S :std_logic; -- Sign Of Resultant Mantissa variable a,b :std_logic; -- Sign Of Two Exponents variable Ea,Eb :std_logic_vector(6 downto 0); -- Magnitude Of Two Exponents variable c :std_logic; -- Sign Of Resultant Exponent variable e :std_logic_vector(6 downto 0); -- Resultant Exponent variable temp1 :std_logic_vector(22 downto 0); -- Temporary Register variable temp :std_logic_vector(45 downto 0); -- Temporary Register variable Q :std_logic_vector(22 downto 0); -- Quotient variable Remi :std_logic_vector(22 downto 0); -- Remainder variable r1,r2 :std_logic_vector(22 downto 0); variable W,Z :std_logic_vector(1 downto 0); variable X :std_logic_vector(31 downto 0); -- Final Result variable i :integer; begin m1:=Accout(22 downto 0); m2:=Data(22 downto 0); e1:=Accout(30 downto 23); e2:=Data(30 downto 23);

--*********logic for the sign of mantissa************************** s1:=Accout(31); s2:=Data(31); W:=(s1&s2); case W is when "00"=> s:='0'; when "11"=> s:='0'; when others=> s:='1'; end case;

. DEPARTMENT OF ECE PAGE NO.-83

32-BIT FLOATING POINT PROCESSOR --*************************1.Checking for Zeros******************** if((m1="00000000000000000000000") and (m2="00000000000000000000000")) then report "Non Arithmetic Numbers:Please Verify Inputs"; elsif(m2="00000000000000000000000") then report "Non Arithmetic Numbers:Please Verify Inputs"; else m1:=m1; m2:=m2; end if; --***************************************************************** --*Dividend Alignment :* --*If Dividend is greater than or equal to the Divisor,then * --* the Dividend fraction is Shifted to the Right and * --*its Exponent is incremented by '1' * --***************************************************************** r1:=m1; r2:=m2; if (m1>m2) then report "m1 is greater than m2"; r1:=r1(22 downto 1)&'0'; Ea:=Ea+1; Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23);

TEC

--******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* for i in 22 downto 0 loop if(Temp1>r2) then Remi:=Temp1-r2; Remi:=(Remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then . DEPARTMENT OF ECE PAGE NO.-84

32-BIT FLOATING POINT PROCESSOR

TEC

Remi:=Temp1-"00000000000000000000000"; Remi:=Remi(21 downto 0)&'0'; Remi(0):=Temp(i); Q(i):='0'; else Temp1:=Remi; end if; end loop; elsif(m1=r2) then --***Since Both Dividend and Divisor are Equal Quotient is made '1'** Q:="00000000000000000000001"; elsif(m1<m2)then --******************************************************************* --*Generating the loop:* --*1.If Dividend is smaller than the Divisor then left shift until * --* it becomes greater or equal ,keep those many zeros in Quotient.* --*2.Once Dividend became greter then subtract Divisor from the * --* Dividend and keep '1' in Quotient. * --*3.Continue the procedure until number of bits in Quotient become * --* 23,because the Remainder never becomes Zero. * --******************************************************************* Temp:=(r1 & "00000000000000000000000"); Temp1:=Temp(45 downto 23); for i in 22 downto 0 loop if(Temp1>=r2) then Remi:=Temp1-r2; Remi:=(remi(21 downto 0) & '0' ); Remi(0):=Temp(i); Q(i):='1'; elsif(Temp1<r2) then Remi:=Temp1-"00000000000000000000000"; Remi:=(remi(21 downto 0) & '0'); Remi(0):=Temp(i); Q(i):='0'; end if; Temp1:=Remi; end loop; end if; . DEPARTMENT OF ECE PAGE NO.-85

e:=Eb-Ea. elsif(Ea<Eb) then c:='0'. b :=e2(7). Z :=(a&b). a :=e1(7). when "10"=> if(Ea>Eb) then c:='1'. end if. case Z is when "00" => if(Ea>Eb) then c:='0'. end if. else c:='0'. e:=Ea+Eb. e:="0000000". e:=Ea-Eb. elsif(Ea<Eb) then c:='1'. elsif(Ea<Eb) then c:='0'. else c:='0'. e:=Ea+Eb. else c:='0'. e:=Eb+Ea. e:="0000000". if(Ea>Eb) then c:='1'. elsif(Ea<Eb) then c:='0'. Eb:=e2(6 downto 0). e:="0000000". end if. e:=Eb-Ea.32-BIT FLOATING POINT PROCESSOR --**************Logic for the Sign of Exponent**************** Ea:=e1(6 downto 0). . if(Ea>Eb) then c:='0'. e:=Ea-Eb. DEPARTMENT OF ECE TEC when "11" => when "01"=> PAGE NO.-86 .

b). end F_div. else c:='0'. DEPARTMENT OF ECE PAGE NO. end process.-87 . e:="0000000". end case.32-BIT FLOATING POINT PROCESSOR e:=Eb+Ea. begin process(a. end if. when others=> null. return X.b) begin Y<=float_div(a. end function. --***********Final Result After Division*************************** X:=(S & C & e(6 downto 0) &Q(22 downto 0)). TEC .

C Syntax high-level data abstraction have a close relationship with the resulting object code, and yet
provide relatively high-level data abstraction. The development of this syntax was a major milestone in the history of
computer science as it was the first widely successful high-level language for operating-system development.

by Harshit Gupta

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