Three Dimensional CMOS Devices and Integrated Circuits

Meikei Ieong""2', Kathryn W. GuariniC2', Victor Chan'l', Keny Bemstein"', Rajiv Jo~hi'~', Jakub Kedziersk$2', and Wilfiied Haenscd2'
IBM Semiconductor Research and Development Center (SRDC) "'Microelectronic Division, Hopewell Junction, NY, USA I*) T.J Watson Research Center Yorktown Height, NY, USA Phone: + I -845-892-47 19 Fax: +I-845-892-3039 Email: mkieong@us.ibm.com Abstract Three dimensional devices and integrated circuits are attractive options for overcoming barriers in device and interconnect scaling, offering an opportunity to continue the CMOS performance trend. This paper reviews the process technology and associated design issues in three dimensional devices and integrated circuits. This projection is based on historical trends without regard to any physical and material limitations, so this exponential trend surely cannot go on forever. The whole industry is looking for solutions to delay the end of the scaling trend. At present, there are no known manufacturing solutions to meet the scaling requirements at post45 nm technology nodes. Three dimensional (3D) devices and integrated circuits may provide solutions because of better device scalability and improved packing density. In this paper, the design trade offs in 3D devices and integrated circuits, along with technology options, will be discussed. The paper is organized as follows: The limitations of conventional device and interconnect scaling are first discussed. We then review representative technology for 3D devices and integrated circuits. Various design options and associated trade off in performance, power, and density are presented. The paper concludes with a discussion on the challenges of 3D integrated circuits technology.

Technology Scaling In conventional CMOS device scaling, the oxide thickness, junction depth, and depletion width are all scaled down to support gate-length scaling (3). The accelerated scaling has pushed the gate-dielectric and junction technology to near their physical limits. Simple extrapolation of fundamental physical limits has led to pessimistic predictions for,the end of device scaling. .On the other hand, the race to fabricate the smallest transistor continues to show tremendous progress. Silicon-on-insulator (Sol) technology offers higher performance than bulk CMOS because of junction capacitance reduction and lack of body effect (4). Scaling the SO1 layer thickness is effective in reducing the shortchannel effect (SCE) (5). Functional transistors with gate lengths down to 6 nm have been demonstrated using an aggressive halo implant and an ultrathin channel of 4 to 8 nm (6). An ultrathin SO1 layer can effectively reduce the SCE and eliminate'most of the leakage paths. However, rapid degradation of mobility with decreasing channel thickness will limit how far we can scale the SO1 layer thickness (7-8). Strained silicon channels have also been demonstrated to offer mobility enhancement (9). New materials and processes are being introduced for interconnecting wires to meet the metal conductivity and dielectric permittivity requirements.

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This has created tremendous integration and reliability challenges. The use of repeaters and fat wire global interconnects can partially alleviate the problem. However, as the technology is scaled to beyond the 45 nm node, tens of kilometers of wires are squeezed into a chip area of a few square centimeters interconnecting billions of transistors. These wires will deliver power to each transistor and need to provide a low-skew synchronizing clock throughout the chip. The real issue in wire scaling is how to deal with the increasingly complex wiring and devise ways to improve the wire delay to keep up with intrinsic gate delay (IO). Moreover, the total chip power will continue to increase because of higher operating frequencies and the increasing device leakage. 3D devices and integrated circuits offer opportunities to overcome some of the barriers in technology scaling.

current per unit area. If the additional gate can be separately controlled, it can also be used to adjust the threshold voltage of the active device channel (11). This gives designers the opportunity to trade off device performance with power consumption. The use of a separately -controlled gate for analog applications has also been proposed.

Three-Dimensional Device Structures

We define 3D device structures as MOSFET devices having more than one gate. A 3D device can he implemented in different ways. It can be built such that the channel and current carrying direction are parallel to the wafer plane with the silicon channel in between the top- and bottomgates (Fig. 2a). This type of device is generally called planar double- or back-gate MOSFET (11-12). It can also be built such that the channel is in perpendicular to the wafer surface while the current runs parallel to the wafer surface (Fig. 2b). Because the device structure resembles a fin shape, it is also known as FinFET (13-14). In any double-gate structures, the top and bottom gates must be self-aligned to each other in order to reduce the series resistance and overlap capacitance. The fabrication process .to meet this requirement in a planar Structure is extremely difficult. The FinFET structure is intrinsically self-aligned and has been regarded as the easiest to fabricate. Record high double-gate current was reported in (15). Functional inverter chain (16) and SRAM cells (17) have also been demonstrated. The FinFET structure can be extended to a multiple-gate transistor for better gate control. Tri-gate FET (18), Pi-gate FET (19), Omega-FET (20), and Gate-All-Around FET (21) have been reported. It can also be built vertically such that both the channels and current carrying direction are perpendicular to the wafer surface (22-23). A vertical FET could be implemented in double-gate and gate-all-around configurations (Fig. 2c). The vertical FET offers higher density and is especially attractive for memory applications (23). However, its layout is incompatible with planar structures. Migrating existing logic product to the vertical transistor geometry would be difficult. The additional gate in 3D devices provides better gate control to the channel which can turn on and off the devices more effectively. Therefore, the channel thickness requirement for SCE mntrol can be relaxed with 3D device structures (8). More gates can also deliver more drive

(c) Vertical FETs

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Figure 2: Various three-dimensional device structures. The current carrying directions are indicated with dashed line.

Three-Dimensional Integrated Circuits

Three dimensional OD) integrated circuits (ICs) are defined as integrated circuits with more than one active device layer separated by one o r more levels of inter-level dielectrics and conducting layers (Fig. 3).

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Power: The interconnect wires consume a significant portion of the chips total active power. Since the parasitic capacitance and resistance are reduced in 3D ICs because of the reduction in total wiring Icngth, the total active power may be significantly reduced.
Many of the general techniques for building 3D ICs will also facilitate the integration of heterogeneous materials, devices, and signals and enable flexibility in device structure, system design, and routing. For instance, stacking of device layers could be used to fop hybrid photoniclelectronic circuits, to stack memory and logic circuits, or to design digital, analog, and RF circuits on different layers.

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Fabrication Technology Figure 3: Schematic structure for 3D integrated circuit. There are more than one active device layers in 3D ICs. There are two primary fabrication schemes for wafer-scale integration of 3D circuits. The first is a bottomup approach in which devices in each layer are processed sequentially, starting with the bottommost layer. At the outset, devices on the bottom layer are fabricated by conventional means (typically on bulk silicon or Sol), then a second device layer is formed and device processing E completed on that layer, a sequence that can be repeated for subsequent layers. High quality single crystal silicon for the second layer can he obtained by wafer bonding (28), selectively epitaxial silicon growth from the silicon substrate, and re-crystallization of polysilicon or amorphous silicon through special annealing (30-31). Alternatively, the topdown approach begins with multiple completed 2D circuits fabricated by conventional processes, which are then assembled to form a 3D IC (32-33). There are some limitations of each method. Regarding to the first method, the thermal processing needed to fabricate the top level devices may damage the bottom devices, causing dopant diffusion and silicide nucleation. The second method requires tight alignment tolerances between layers. Recently, we have shown that devices in state-of-the-art 130 nm SO1 CMOS technology with copper metallization and lowk inter-level dielectric insulators can withstand wafer-level layer transfer processes, with virtually no change in the intrinsic device characteristics. A schematic 3D IC and cross-section are shown in Fig. 4a and 4b, respectively. After the SO1 circuit is transferred onto glass, the stack is transparent (Fig. 4c).

In a 3D IC, each transistor can access to a greater number of nearest neighbors such that each transistor or Gnctional block will have a higher bandwidth. The benefits of 3D circuits include:
Densify: By adding a third dimension to the conventional two-dimensional (2D) device layout, the transistor packing density is improved, thereby allowing a reduced chip footprint. This is particularly appealing for wireless or portable electronics, where silicon real estate is at a premium. Reduced chip volume and weight are also motivated by military applications.

Performance: 3D ICs promise a reduced average interconnect length as compared to their 2D counterparts, yielding fewer intrinsic delays per cycle, enhanced accessible die area, and reduced noise coupling. Wire latency is beginning to severely restrict performance as feature sizes are scaled down (24), thus the reduced electrical distance in 3D ICs may be a vital attribute (25-27). For communication between memory and microprocessor, 3D integration may provide the ultimate bandwidth, which will result in a significant performance gain for some applications.
Noise: The amounts of silicon spent combating noise increases dramatically with wire length and hence die size. There will be fewer global wires in 3D ICs, which significantly reduce the number of repeaters necessary. It also improves the noise immunity needed in each input gate.
Logical Span: The trend toward increasingly deep pipelines

Design Examples
will require a greater fan-out from a given data source. Since MOSFET fan-out is limited to a fixed amount capacitive gain per cycle, the increased intrinsic bate load imposes a greater constraint on the extrinsic load (such as wiring). The use of 3D ICs could he an elegant solution to this challenge. 3D ICs can be implemented with different granularity. It can be partitioned at the transistor level, gate level, functional level, or the package level. In the finest granularity, any transistor canbe located in any device layers. Devices in each layer can be separately optimized, processed, and

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tested, offering an opportunity for higher performance and yield in each device layer. It is expected that the circuit area can be significantly minimized in 3D ICs. Fig. 5 shows the layout designs of 2D and 3D inverters with fan-in of one.

region. The metal routing and the contacts between layers could occupy a large portion of the total layout area.

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Figure 4: (a) Schematic 3D integrated circuit with inter-level metal. (b) Cross-section of high-performance SO1 circuit after the SO1 wafer was transferred to a glass substrate. (c) A wafer showing the top level device layer after removing the bulk substrate.

Figure 6: Relative layout area conparison for various inverter circuits with 2D and 3D layout.

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Figure 7: Relative area saving f o 3D ICs. rm

Fig. 6 shows the area of the 3D circuit compared to that 2D circuit. The area saving depends on the channel width of the original 2D circuit and the intexonnect regions. In general, more area saving can be achieved if more active layers are built (Fig. 7). However, more active layers may result more inter-layer contact regions. Moreover, the advantages of area savings diminish if the channel width ofthe original 2D circuit is narrow or the area is dominated by the gate contact

The 3D structure can only save the device area hut not the routing area. The total area saving is strongly dependent on the chip architecture and the metal routing design. There is a continuing need for high-density high-speed SRAMs. The standard six-transistor (6T) SRAM cell with PMOS loads(Fig 8) is the most robust and scalable SRAM configuration. With 3D IC technology, the pull-up PMOS devices could be stacked over the NMOS devices Fig. 8). Stacked CMOS SRAM cell technology was reported in the early 1990s (34). 3D SRAM has its limitations: S U M will require extremely

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tight alignment tolerances for inter-layer contacts. Moreover, cell area reduction may not be achieved as much as in other standard cells. From the layout of an example 2D SRAM cell (Fig. 9), metal interconnects and contacts occupy a major portion of the SRAM cell. Since extra contacts and interconnects are necessary to connect the top and bottom layers, designinga 3D SRAM cell is difficult and not much area can be saved.

A 3D chip can also be fabricated at the package level. A thorough review has been provided recently by AI-sarawi (35). A 3D package typically stacks bare dies or multkhip modules (MCM), securing the full chips by epoxy or other glue. The wiring between layers is mostly implemented as peripheral interconnections. A number of 3D packages are in manufacturing today, most notably as high density memory modules (3637). While the intra-cbip connections in a 3D package are shorter than standard chip-to-chip wires (hundreds of pm instead of several mm), they are still quite long compared to on-chip interconnects. To actualize the potential performance gains from a true 3D IC, the device layers must he brought closer together to allow shorter interlevel wiring.

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While the potential advantages of the 3D IC are certainly compelling, the following challenges have curtailed its adoption as a mainstream technology:
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Maintaining Performance: The electrical integrity ofdevices

Figure 8: Circuit schematic of a 6T SRAM cell.

and circuits must be preserved during the 3D IC fabrication process. One critical issue is thermal cycling during 3D IC fabrication, which can degrade device performance. New processes must be established to precisely align and interconnect the multiple device layers. To obtain the optimal circuit benefit the alignment has to he on the order of that in the critical layers; if that cannot he achieved, the resulting trade-offs must be investigated. The best wafer-to-wafer alignment scheme available to date can achieve roughly 1 p m tolerances.
Minimizing Complexity: 3D circuits are inherently complex,

Figure 9: SRAM cell layout. The interconnect wires and contact occupy a major proportion of the SRAM cell. The amount of on-chip memory continues to increase, to the extent that the majority of the chip will soon he occupied by memory. The latency from the logic to this vast amount of memory is becoming harder and harder to reconcile. The relatively low power density of the m a y s is largely unavailable to the excessive power density in the logic. Both issues can be addressed by placing the array of memory on top of the logic using 3D IC technology. Partitioning the 2D chip into functional blocks and stacking them together in a 3D configuration may be attractive for many applications. Moreover, alignment tolerance requirement for inter-level contacts can be significantly relaxed.

from- the standpoint of both design and fabrication. New design tools will be required to optimize interlayer connections for maximized circuit performance, and the process fabrication complexity must be minimized for manufachuahility and yield. A set of 3D specific tools for standard-cell placement, global routing, and layout was reported in (38-39). A reliability tool specifically targeted for 3D IC technology is also available (39).
Testing: Since 3D circuits with multiple active layers are highly complex, it would not be economical to put off functional testing until the full process flow is complete. Instead, functionality in the different layers must be assessed along the way. Product design and test are challenged to provide suitable solutions. Managing Power: The increased circuit density inevitably

leads to increased power denshy, and new schemes may be required to enable power dissipation from multiple device layers in order to minimize thermal gradients and local heating (40). As silicon process technology, driven by improved performance requirements, migrates to SOI, low

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resistivity metals, and low-k dielectrics, the thermal properties of these materials play a significant role in determining the temperature build-up, power, and performance of the chip (41). Clock buffers are highly loaded circuits and need to be big in size to drive the loads. 3D Temperature distribution in a clock buffer using 0.18 pm copper back end technology and a buried oxide thickness of 0.2 pm was analyzed (Fig. IO). The temperature rise underneath the devices is much larger than that near the interconnects because the heat dissipation across the buried dielectric layer is poor. This temperature rise has a direct impact on the performance of the clock buffer. For 3D ICs these issues should be carefully evaluated, as a thick dielectric between device layers can cause the highly loaded devices placed on the top plane to have severe temperature rise. One solution for this is to place the large, highly loaded gates near the lower-most plane next to silicon substrate.

Conclusion
3D devices and integrated circuits are potential solutions for overcoming the challenges in continuing CMOS performance trend. To fully realize the benefits of 3D devices and ICs, close interaction among the technologists, circuit deskners, and system engineers would be important.

Acknowledgment
The authors are indebted to their many collaborators at 1BM for the results described in this paper. In particular, we thank E. Nowak, HS P Wong, A. W.Topol, B. Pogge, and I. J. Welser for their collaborations and useful discussions. Many colleagues kindly provided data and information for this paper, cited individually in the references. The devices and circuits were fabricated at the IBM ASTLiS and ASTC. Finally, we are grateful to J. M. Warlaumont for his management support. Some of the work described in this Chapter was supported in part by DARPA under contracts N6600 l-OO-C8003 and N6600 1-97- 1-8908.

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Manufacturing Cost: A 3D IC will presumably be more costly to manufacture because of added process complexity. Additional cost may be added, for example, because of required redesign of the layout and ground-mle reverification due to top and bottom layer misalignment. Although some implant mask processes can be eliminated and n-well to p-well spacing can be saved ifnFET and pFETs are individually built on two different layers, extra gate and active masks are inevitable and these critical masks are more expensive than implant masks. The potentially higher manufacturing cost can only be justified if the projected performance benefits are achieved. 3D ICs will probably only make economic sense if other more traditional performance enhancement techniques such as device scaling are no longer capable of driving future technologies.

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