ANALOG CMOS FOUR-QUADRANT MULTIPLIER AND DIVIDER

S. Vlassis and S. Siskos

Electronics Laboratory, Department of Physics, Aristotle University of Thessaloniki

Thessaloniki 54006, Greece
e-mail: svlas@skiathos.physics.auth.gr

ABSTRACT the multiplier circuit. Both multiplier and divider have

been fabricated in CMOS 2 p MIETEC technology.
An analog CMOS four-quadrant multiplier and a two- The theory of the circuit operation is presented along
quadrant divider circuit are introduced. The multiplier with simulated and experimental results that verify
operates for a power supply f 1.5 V and its differential theoretical analysis.
input range is & I V with less than 0.2% linearity error.
The THD is less than 0.3% with input range up to
f O . S V . The divider offers the facility of independent 2. CIRCUITS DESCRIPTION AND OPERATION
control of the sensitivity and has acceptable precision
usefil in analog signal processing, fizzy control and 2.1 Multiplier circuit
instrumentation applications. Experimental results verify
the simulation ones demonstrating the feasibility of both The proposed four-quadrant multiplier circuit is shown in
circuits. fig.1. Transistors M1-M4 operate in the saturation region
and Ms-Ms operate in the linear region. The drain current
Id of an MOS in the saturation and in the linear region,
1. INTRODUCTION neglecting the body effect, is given by eqs (1 a) and (lb)
respectively:
Analog multipliers and dividers are between the more Id ' y k1
(vGS -vT)2 (14
important building blocks in analog signal processing,
fuzzy control and instrumentation [l-31. The most
popular technique in bipolar technology is the variable
transconductance technique, which is based on the
andk, = k,,,
Id +[(VGS -VT) v,
= p , c M ( ~ / ~ ) , , ~and
4
-&I 1

k, = k M 5 - 8 =
(Ib)

Gilbert's translinear principle. Recently, MOS low

voltage analog multipliers based on the well-known =p, C, (W/L ) MJ-8 , are the transconductance
square-law model of the MOS transistor operating in the parameters of the transistors M14 and Ms-8, respectively,
saturation region have been presented [4-61. pn is the electron mobility, C, is the gate capacitance and
On the other hand, dividers require more complex w / ~ i sthe aspect ratio of the transistors and VT is the
circuitry. A simple way to perform the quotient operation threshold voltage. All undefined parameters have their
is the use of a multiplier in the feedback path of an usual meaning.
inverting operational amplifier [7]. Another approach is VDD
to subtract two log-amplifier outputs from one another
and apply antilogarithmic operation on their derived
output [SI. Other implementations utilize the voltage
variable resistance of a FET or MOS transistor [9-1 I]. A
recently proposed circuit uses pool circuits to realize the
quotient operation [121. In addition, many sampled-data
quotient circuit realizations have been presented in the
literature [7], but they are limited in low frequency
applications and have increased power consumption and
chip area. 1 I

In this work a new very simple CMOS voltage four- VSS

quadrant multiplier is proposed. The idea is based on the

operation of two stacked MOS transistors that the first Figure 1. The circuit of the four-quadrant multiplier
one operates in the saturation and the second one in the
linear region. The voltage divider is based on a voltage The total circuit consists of four branches, as it is shown
variable resistor (VVR) circuit, which is generated from in Fig.1, formed by the transistor pairs (MI,M5),(M4,Ms)

0-7803-5471-0I99l$10.0001999 IEEE
v-383
(M3,M7) and (M2,Ms). The voltages V,,V3 and V4 are the
inputs signals and the voltage Vc is the common mode
voltage which bias the transistors MS-8 in the linear
region. Solving the system of eqs.( 1a) and (1 b) we obtain
the current drawn each branch. These currents for the
four branches are given by the following equations
where v3=v,+vz,v,=v,-vz ,,,=v,+vT
and k l , kz are the transconductance parameters of
transistors (MI-M4)and (M5-M,) respectively (see eq.( 1).
From eq.(2-5) the currents which draw each branch are
functions of two voltages; the voltages at the gates of
transistors which operate at the saturation and at the
linear region.
Taking into account the first and the second order terms
of the Taylor’s series expansion, for a function of two
variables x, y around zero, the currents of each branch
(eq.(2)-(5)) is expanded as
After routine calculations the total differential output
current I, can be given as
Io =(Il + 1 2 ) - ( I ; + I ; ) = GV,(V, -V,)= GFY,
The-output voltage V, of the multiplier will be
The non-linearity error is limited to be at third order
terms.
2.2 Divider
The proposed divider circuit is shown in Fig.2. It
consists of two parts; the fvst part is the voltage-variable
resistance (the circuit in the dashed line fiame) and the
second part is a second-generation current conveyor
(CCII).
The voltage-variable resistance (VVR) circuit is
generated from the multiplier if V,, V4 voltages are tied
to the corresponding output nodes V,I and V,2.
- -I
Figure 2. The circuit of the two-quadrant divider
It has a differential input voltage Vl-V2and a differential
input current I,-&, while the differential voltage V,, -VOz
is the output of the circuit. Since the gates of transistors
M5,8and M6,, are tied to the drains of transistor and
M2.4 , respectively, the transistor M5.8operate into the
linear region.
The constant current IC is the common mode input
current of the differential input current which establishes
the common mode voltage of the differential output
voltage. The equation that relate the current IC with the
common mode voltage output V,, is :
From equation (7) for V3 -V4= V,, -Vat it is obtained :
(7) v, = v,,- v,, = -(I,
1
2GV,
-I,) (10)
It is obvious from eq.( 10) that the VVR circuit realizes
an equivalent resistance
which is inversely proportional to the differential input
voltage VI.
The differential input currents IIand Zz are given by
where Ia Iw are the two output currents of the CCII. The
CCII performs two follower operations, voltage and
current: VFV, and Zx= &=-Iw, where current Ix is the
current at port X. Thus the two output currents are given
by
where V , is the input voltage at port Y of the CCII.
Combining the eqs(10,12,13) the output voltage of the
two-quadrant divider circuit is given by
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 OSV, 8KH2, while the voltage V, is a sinusoidal signal
of O.SV, 200KHz.The simulated -3dB bandwidth of the
where s= is the sensitivity of the divider . It is multiplier is up to 400MHz while the total harmonic
distortion level of the output voltage of the multiplier
clear from eq.( 14) that the output voltage is proportional circuit was found to be less than 0.3%.
to the quotient of two analogue voltage inputs; the
voltage V 2 , which is the numerator input and the voltage
VI is the denominator input. The proposed circuit, also
features independent control of the sensitivity by the
resistance R.
For easy tunability of the sensitivity the denominator
G . R in the expression of the sensitivity must take
considerably large values. Therefore, in order to use
reasonably small values of the resistance R, the constant 0 1 4- 1x1; '/7! .........

G must take large values. For this purpose the aspect

ratio of the MI-4 and MSe8should be W / L > 1 $ 0 -A.-

3. EXPERIMENTAL AND SIMULATED RESULTS

The CMOS four-quadrant multiplier and divider circuit

was fabricated 2 p MIETEC CMOS technology. The
transistors MI-M4 and M5-M8 had W/L)=100/5 and
(W/L) =20/5 respectively. Fig.3 shows the
microphotograph of the multiplier. The measurements
conditions for the multiplier are JQ=lKR, the common
mode voltage was set Vc=0.9V and the power supply
was k 1SV.

.! .! i fT i . .;....-.....
i...........i ...........+.....".j
i . .;; ........................i;.
:
i .

.
1 .
. T F
. . . I .
i
: . : . .: : . I
j

............i. ............i.....i .... ...........j:...........:............1............4!...........;i...._.....

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i............:........... _I ..... i....!............ i...........!.-.........i...........j......:.....i........... j........... _i

Figure 4 (4a)Experimental DC transfer characteristics

of the multiplier (4b)Transient response, y-axis; CHI:
O.SV/div, CH2: 0.2Vldiv (x-axis: 25ps/div)

Figure 3. The microphotograph of the multiplier
Fig.4a shows the experimental DC transfer
characteristics of the multiplier. It can be seen that the
output voltage V, against the input voltage VI for
changes of VI from -0.75V to 0.75V and V2 from -0.5V
to OSV with 250mV step. The experimental and the
calculated data are displayed together. This multiplier
has a linear differential input range up to k l V with a
nonlinearity error less than 0.2%. To demonstrate its
time-domain response, two signals are applied to the
proposed multiplier. FigAb shows the output voltage V,
and the input voltage VI. VI is a sinusoidal signal of
For the proposed divider circuit, the CCII circuit was
previously designed with only one current output Z [ 131
and fabricated now on the same chip with the VVR
circuit with an additional current output W in order to
implement the proposed quotient circuit. The
measurement conditions are : power supply +/-2.5V,
current Ic=600pA and R=lOKf2.
The curves in Fig.5a show the output voltage V,-J against
VI with V2 taking values from -1.2 to 1.2V with 0.3V
steps. The output voltage range is *1.5V whereas the
voltage VI varies from 0.05V to 1.4V with less than 1mV
offset for V2=0. The experimental and the calculated data
are displayed together. The relative error is less than

V-385
52.5% for -1.2V<V2<1.2V and 0.1V<V1<1.2V
respectively,while the output voltage is -1.5V< V,< 1SV.
Fig.5b shows the experimental waveforms at the output
where the numerator is held constant V2=1 V and V, is a
20KHz triangular wave varying between 0 and 1V. It is
obvious that the output voltage VO is proportional
Figure 5. (5a) The DC transfer characteristics of the
divider (5b) The transient response (axes; O.ZV/div and
20psec/div)
4. CONCLUSION
In this work two circuits were presented; a four-quadrant
CMOS analog multiplier and a two-quadrant analog
divider. The four-quadrant multiplier operates with
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power supply of f 1 . 5 V and for the differential input
range k 1 V has a linearity error less than 0.2%. The
simulated -3dB bandwidth is up of 4OOMHz and the total
harmonic distortion level was computed less than 0.3%.
This multiplier is expected to be useful in many analog
signal-processing applications. The divider offers the
facility of independent control of the sensitivity and has
acceptable precision useful in analog signal processing,
fuzzy control and instrumentation applications.
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