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Microblaze Tutorial H thng nhng l g, n nh th no, hin nay ngi ta thng ni t "embedded" tc l nhng.

T trc n gi mnh bit bao nhiu l nhng, b nhng gim n, bnh trng nhng nc Trng Bng n... cn h thng nhng nh th no? Nhng sn phm lm ra t h thng nhng rt quen thuc trong cuc sng hng ngy, v d nh ci t lnh, my git, my iu ha nhit n c nhng chic in thoi di ng m my em gi thng vi vnh b m mua cho bng c, mi ln chung in thoi reng te te nh dz ku. Nhng tn nng c hiu i khi nh l kt qu x l Midi to ra m thanh t h thng nhng, v l tri tim ca chic in thoi. kamejoko nghe ni nhiu v embedded nhng cng c lc m h v lng bng ci l tai. Trong h thng nhng li chia ra nhiu mng khc nhau, ty theo tng ng dng c th. Mnh mun m tt c, hc lun nguyn mt th "Ti mun m c t, ti mun m c tri, m sao em i, ti khng m ni mt con ngi" hehhe. Th l mi ti kamejoko li lang thang trn mng, tm kim lng sc trn trang google c thm nhiu kin thc. Embedded devices chc c l c chia ra thnh 3 mng chnh, l ARM, DSP, FPGA. Ci m kamejoko mun cp y chnh l b vi x l processor, l tri tim ca h thng nhng. Kamejoko tng th qua h thng ARM ca Phillips, nhng cng ch dng li phn firmware m thi. Sau nhiu ln n o, t hc embedded th cn phi trang b cho mnh nhng device no? nhng kit ARM c sn gi tng i kh cao, nhng hc embedded ch chuyn su vo firmware th cha . C duyn a mnh n vi FPGA, c c mt kit FPGA th cng khng kh, v sn phm ca Xilinx c nhiu mc gi khc nhau, cng nh c nhiu tin th ta c th chn c mn n ngon, cn khng th chn nhng nn n tm tm, nhng vn m bo mnh no bng. V khi tm hiu kamejoko nhn ra mt iu: Xillinx c ngun resource rt ln. mnh ni n l cc application notes, v cc tool design ca Xilinx lun c update nhanh n mc chng mt.V kamejoko ngh rng s la chn FPGA hc embbeded l ng, v khi i su vo thit k i hi designer phi am hiu c hardware ln software. i, lng bng l tai qu ri phi khng!!! Microblaze l ci g??? N l mt processor, l tn mt loi vi x l ging nh VXL Intel vy. Nhng c iu, khi cn mt con VXL Intel, anh c th ra ca hng my tnh, b ra vi chc n

vi trm USD l c th mang n v. i vi Microblaze, anh khng th ra ca hng mua n mang v c, m phi dng tool ca xilinx design thnh mt h thng Microbalze hon chnh. Chi tit hn, con chip FPGA ca "rng". N l mng ca cc cng nhau. Cng vic ca designer l cng li thnh mch in c th ngi thit k t ra. hng Xilinx sn sut l mt khi logic cha c kt ni vi dng tool ca Xilinx kt ni cc v n phi chy theo ca

Cao hn, mt khi c Microblaze l tri tim ca h thng, cn phi c nhng thit b ngoi vi (IO) i theo. Cng nh nhng thit b ngai vi chut, bn phm... Xilinx cung cp cho designer mt danh sch cc ngoi vi c gi l IP core cataloge. Designer ch vic chn tng mn m mnh thch, m nhc n chn mn th phi tnh n tr tin. Tc l trong danh sch IP core c loi c khuyn mi min ph (mn trng ming), v c mn phi tr tin. Th v phi khng, cng vic design ca mt anh k s cng ging cng vic i ch hng ngy ca cc ch em ph n, cng phi n o xem xt xem gi thnh ca h thng gim c bao nhiu trong khi vn m bo tnh nng m yu cu t ra. Cn nu anh ngho nhng c tng th c th t mnh to ra IP, khng chn th no trong IP cataloge c. Ci m kamejoko sp trnh by di y. C ngi bo mnh ti sao khng dm b tin ra mua nhng thc n ngon m li u t vo nhng th v b nh vy, mnh ch c th tr li mnh rt "mu" v lnh vc ny, ngai ra khng c g c. V kamejoko mun chia s cho nhng ngi cng c "mu" nh mnh. ------------------------------------------------------------------Sau y l cc bc thc hin LCD demo cho microblaze. Tool : EDK 8.2 Demo trn board ML403, tuy nhin vn c th thay i cht t cho board Spartan3E Starter Hng dn step by step, hnh hi nhiu, thng cm nh. Ch : Vi bc c thng qua ( mc nh v n nt next) thay v post hnh y . --------------------------------------------------------------------PHAN 1 : Setup hardware --------------------------------------------------------------------1> Start XPS 8.2i

2> To th mc cha project

3> Creat new base system

4> Select Board (ch : mt s board c nhiu revision khc nhau, nn chn revison thch hp)

5> Chn mn n ty vo ti tin

6> Creat Custom hardware (lcd port)

Sau khi hon tt cc bc trn, XPS to ra cc file c cu trc nh sau: Phn hardware cha trong th mc pcores, bao gm tn (lcd_port) gn vi version hardware ch nh (lcd_port_v1_00_a) Phn software cha trong th mc drivers (s c trnh by trong phn sau)

7> Edit custom hardware Sau khi thc hin xong thao tc creat custom peipheral (dng bus OPB), XPS to ra 2 file source vhdl bao gm name.vhd v user_logic.vhd cha trong th mc vhdl 8> Edit user_logic.vhd goto hng (khong 100) add user port theo hnh sau:

XPS to thanh ghi "slv_reg0" cho truy xut vi customer ip core, trong trng hp ny ta gn cho port xut lcd goto hng (khong 208-209) add code nh hnh sau

9> Edit lcd_port.vhd goto hng (khong 119) add user port theo hnh sau:

goto hng (khong 388) map port

Xong bc creat , edit customer OPB port 10> Import custom hardware Trn tool bar : Hardware -> Creat or import peripheral

t tn lcd_port

Chn yes for overwrite

Check radio cho mc file .pao, browse n ng dn th mc hardware cha file ny

11> Add ipcore vo bus OBP Trn tab IP Catalog chn Project Repository, click chut phi vo lcd_port chn add IP

Trn mc system assembly view ta thy custom ip core lcd_port_0 c add vo, lc ny lcd_port_0 cha tht s c gn vo bus OPB, ta thc hin bc connect vo OPB theo hnh sau:

Chn nt radio ca mc port , connection filters chn all hin th tt c cc ng kt ni. OPB_clk -> sys_clk_s : system clock source lcd_port_pin -> Make external

Sau khi kt ni lcd_port_pin vi external port, mc trn cng External Ports xut hin ng kt ni lcd_port_0_lcd_port_pin, rename phn tn kt ni pha bn tri tin cho vic assign pin constrain.

Chn nt radio address, trong mc size (kch thc vng nh cho ngoi vi) trong drop list chn 64K, sau chn Generate Addresses, Xillin t ng tnh ton cc ng a ch v remap li cho ton b ngoi vi.

Cui cng l bc assign constrain pins cho lcd_port, ty theo kt ni ca cc board khc nhau ta c cc khai bo gn pins khc nhau.

Tool -> Hardware -> Generate Bitstream. n bc ny ta c th thong th ngi ung Coca ch i XPS hon tt cho phn hardware.

LCD Firmware Phn trc gii thiu xong phn import customer hadware, phn ny gii thiu v driver cho LCD. Sau khi import lcd_port vo bus h thng, XPS t ng to ra th vin h tr cho vic pht trin phn mm. Ngoi ra cc file h thng cng c cp nht. Driver c to ra trong ng dn : ...drivers/lcd_port_v1_00_a/src/ /lcd_port.c /lcd_port.h /lcd_port_selftest.c /Makefile File lcd_port_selftest.c c to ra vi mc test s hot ng ca thanh ghi reg0 (lcd_port), ta c th tham kho, sa cha ty vo mc ch x dng. Cc prototype cho cc hm truy xut thanh ghi c khai bo trong lcd_port.h Sau y l cc bc to project mi dng cng c pht trin phn mm SDK ca xilinx. 1> Trn tool bar ca XPS: Chn Software -> Lauch Platform Studio SDK

2> Trong hp thoi Application Wizard: Chn Creat a New SDK Application Project -> Next 3> Trong mc New Project t tn project -> Next

Ly thng s mc nh Xilinx MicroBlaze Executable -> Next

Finish thao tc create new project

Sau khi hon tt cc bc trn xilinx t ng to cc th mc v cc file trong th mc c tn project name, v mt danh sch cc th vin c lin quan n microblaze.

4> To Linker Script : Trong mc Navigator, click chut phi lcd_disp -> Gnenerate Linker Script...

Trong crop down list chn DDRAM, dng lm vng nh data , text .... 6> Creat New Source file Click vo biu tng C+ trn tool bar

t tn file lcd.c

vit chng trnh giao tip lcd, tc l dng microblaze xut tn hiu iu khin ln port_lcd, ngoi lcd_port cn c cc ngoi vi khc. Microblaze l processor c cu trc t chc b nh Havard, Vng Intruction v vng IO, memory nm ring bit. Cc IO c truy xut thng qua a ch, mi IO chim mt vng nh c tm t C_BASEADDR - C_HIGHADDR. Cc base add c cp nht trong file system.mhs sau khi thc hin thao tc Generate Address trong mc trnh by trn. Ta c th tham kho C_BASEADDR thng qua bc sau: Trong XPS -> System Essembly View -> chn IO -> click chut phi -> Conigure IP ...

V a ch u tin 0x77400000 c dng cho vic truy xut thanh ghi reg0 (Do phn creat custom hardware ta chn option cho 1 thanh ghi, trong trng hp to nhiu thanh ghi, v d nh reg0, reg1, reg2 th a ch truy xut cc thanh ghi ny s ln lt l C_BASEADDR,C_BASEADDR+0x04,C_BASEADDR +0x08...)

Hm LCD_PORT_mWriteSlaveReg0(LCD_PORT_BASE_ADDR, (value)) c nh ngha sn bi Xilinx, ghi gi tr "value" ra lcd_port. 7> Edit lcd.c Cng vic k tip l son tho code iu khin LCD, hu ht cc board FPGA u thit k cho vic giao tip mode 4 bit. Trong phn thit k ny dng 1 port xut iu khin, lcd_port<6:0> <-> (E, RW,RS,D7,D6,D5,D4)

8> Edit main.c Chng trnh chy th hin th k t trn LCD. CTRL+S : Save file CTRL+B : Build ( Hoc click vo mc Build trn tool bar) __________________ Sau Khi thc hin 2 phn Hardware v Firmware, ta c th load ln board chy th. chy micoblaze cn phi cu hnh thnh

h thng hon chnh, sau load chng trnh. 1> Kt ni cable Jtag vo taget board 2> Trn tool bar SDK n vo Icon "Program Hardware" chng trnh t ng load bitstream xung board. 3> Trong mc Navigator -> chn lcd_port -> click chut phi -> run

Trn hp thoi Run click "New"

Chn tab XMD Target Connection

Sau khi n "Run" SDK load chng trnh v microblaze bt u chy. SDK h tr chc nng deburg chy step by step thng qua ng JTAG. C th iu khin hot ng ca microblaze thng qua ca s console: Ti du nhc XMD% type lnh run -> cho microbalze chy type lnh stop -> cho microblaze dng run XMD% XMD% RUNNING> XMD% RUNNING> stop XMD% XMD% RUNNING> Processor stopped at PC: 0x2800001c

Ta c th dng Terminal hin th message qua ng UART

Dng microblze hin th ch trn LCD phi qua nhiu bc to port, vit chng trnh th tc rm r, nhng khng km phn th v. Vic chn FPGA cho vic nghin cu h thng nhng c mt s li im. Trong lc pht trin phn mm, ngi lp trnh c th ng n c hardware thay v phi c datasheet v lp trnh n thun. V nh th ta c th nm r hn cht t nhng g mnh ang lm. Ngi pht trin c th custom h thng theo ch ca mnh nhm mang li tnh hiu qu v kinh t nhng vn m bo p ng yu cu t ra.