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A General PWM Strategy for Four-Switch Three-Phase Inverters

Maurcio Beltro de Rossiter Corra, Member, IEEE, Cursino Brando Jacobina, Senior Member, IEEE, Edison Roberto Cabral da Silva, Fellow, IEEE, and Antonio Marcus Nogueira Lima, Member, IEEE

AbstractA general pulsewidth modulation (PWM) method for control of four-switch three-phase inverters is presented. The proposed vector PWM offers a simple method to select three or four vectors that effectively synthesize the desired output voltage, even in presence of voltage oscillations across the two dc-link capacitors. The method utilizes the so called space vector modulation, and includes its scalar version. Different vector combinations are compared. The effect of Wye and delta motor winding connections over the pulse width modulator is also considered. The common mode voltage generated by the four-switch three-phase converter is evaluated and compared to that provided by the standard six-switch three-phase inverter. Simulation and experimental results are presented to demonstrate the feasibility of the proposed approach. Index TermsCommon mode voltage, four-switch three-phase inverter, vector and scalar pulsewidth modulation (PWM).

I. INTRODUCTION

STANDARD three-phase voltage source inverter utilizes three legs [six-switch three-phase voltage source inverter (SSTPI)], with a pair of complementary power switches per phase. A reduced switch count voltage source inverter [fourswitch three-phase voltage source inverter (FSTPI)] uses only two legs, with four switches, as shown in Fig. 1(a). Several articles report on FSTPI structure [1][3], [5][9], regarding inverter performance and switch control. The FSTPI structure plane, instead of six, as generates four active vectors in the generated by the SSTPI topology. This paper presents a general method to generate pulsewidth modulated (PWM) signals for control of four-switch, threephase voltage source inverters, even when there are voltage oscillations across the two dc-link capacitors. The method is based on the so called space vector modulation, and includes the scalar version. The proposed method provides a simple way to select either three, or four vectors to synthesize the desired output voltage during the switching period. In the proposed approach, the selection between three or four vectors is parameterized by a single variable. This permits to implement all alternatives, thus allowing for a fair comparison of the different modulation techniques. The inuence of different switching patterns on output voltage symmetry, current waveform, switching frequency and common mode voltage is examined. The paper also discusses, how the use of the Wye and delta connections of the motor

Fig. 1. AC drive system congurations.

windings affects the implementation of the pulsewidth modulator. The utilization of an induction motor, with its windings connected in delta is studied here as an alternative to reduce the dc-link voltage used, in respect to the Wye connection. For the Wye connection it is investigated, how the common-mode voltage can be reduced. The reduction of the common mode voltage permits to mitigate effects of common mode currents, which commonly are responsible for damage of motor bearings and bearing lubrication [10][13]. Simulation and experimental results illustrate the use of the FSTPI to supply a three-phase induction motor. II. SPACE VECTOR ANALYSIS With respect to the circuit shown in Fig. 1(a) it is assumed that the conduction state of the power switches is associated with binary variables to . Therefore, a binary 1 will indicate a closed switch, while 0 will indicate the open state. Pairs and are complementary and, as a consequence, and . Also it will be assumed that a stiff voltage is available across the two dc-link capacitors, and 2 , where corresponds to a stiff dc-link voltage, i.e., the actual value of the dc-link voltage is equal to .

Manuscript received July 27, 2004; revised March 1, 2006. Recommended by Associate Editor J. D. van Wyk. The authors are with the Departamento de Engenharia Eltrica, Universidade Federal de Campina Grande, Campina Grande 58109-970, Brazil (e-mail: mbrcorrea@dee.ufcg.edu.br). Digital Object Identier 10.1109/TPEL.2006.882964

0885-8993/$20.00 2006 IEEE

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TABLE I AVAILABLE VECTORS IN THE  PLANE FOR THE WYE CONNECTION

Pole voltages , and depend on the states of the power switches. They can be expressed in terms of the binary variables and , and the dc-link voltage as follows: (1) (2) (3) Space vector modulation, and the problem of selecting the appropriate switching sequence are better understood, if the threephase quantities are transformed into quantities. The transvariables are given by formed (4) with mation matrix being read as , and the transforFig. 2. Vectors in the  plane for the same dc bus voltage: (a) Wye connection and (b) delta connection.

TABLE II AVAILABLE VECTORS IN THE  PLANE FOR THE DELTA CONNECTION

(5)

A. Wye Connection Fig. 1(b) shows a three-phase induction motor stator, with windings Wye connected. In this case the line-to-neutral volt, ages are and is the voltage between the neutral and the dc bus mid-point (0), as indicated in Fig. 1(a). The induction motor is assumed to be symmetric, with its neutral wire disconnected. voltage components are given by The (6) (7) Combination of switch states, as given in Table I, results in plane. Using the above vector four different vectors in the plane into four sectors, i.e., denitions one may split the , and , as indicated in Fig. 2(a). Vectors and , named as even vectors, are opposite in direction and their amplitude is a factor times higher than the ampliand . Also, vectors and , named as tude of the pair odd vectors, are opposite in direction . B. Delta Connection Fig. 1(c) shows the three-phase induction motor stator windings delta connected. In this case, and and, consequently, the voltage components are given by (8) (9) The combination of the states of the switches as given in plane. Their Table II account for four different vectors in the amplitude is a factor times higher, than the vectors of the Wye connection [see Fig. 2(b)]. Also, these vectors are rotated of 3 rad, counterclockwise from the vectors of the Wye connection. In the following sections, the analytical formulation of the space vector modulation will be derived for the case of Wye connected load. Furthermore, in, Section VII it will be demonstrated, how these results convert for the case of a delta connected load.

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III. SPACE VECTOR PWM represent the reference voltage being synthesized by Let the FSTPI within a switching period of length . According to the space vector technique, this implies that (10) with the time weights , and restricted to (11) The problem is, how to nd out the values of the time weights given and . Note that the absence of null vectors does not permit to use only two active vectors (as usual for a SSTPI) to synthesize the reference . To simplify the algebraic manipulation and have been and by and , reintroduced. Replacing vectors spectively, into (10) results in (12) with and . From (12) it is possible to conclude that to synthesize , the vector must be applied during and the sign during . In 1, if 0 or these expressions, the operator is sign 1 if 0. sign Rewriting (12) in terms of the components gives (13) (14) Considering the Wye connection 4 4 and and are given by that 12 4, it can be shown

TABLE III USE OF ONE SMALL AND TWO LARGE VECTORS

TABLE IV USE OF ONE LARGE AND TWO SMALL VECTORS

1 for vectors and . The use of the distribution factor to solve the previously under-determined problem can be done as described below Sector I and

(18) Sector II and

(15) (19) (16) As is evident from the above equations, the computation of the time weights is an under-determined problem, i.e., there are four unknowns variables, but only three different equations. It can be shown that there exist two alternatives to solve this problem. The rst one is to use all four vectors, while the second one is used to select only three out of the four available vectors. The present paper proposes a method for selecting different patterns, as it is shown next. and correspond to the minimum efObserving that fective time intervals required to synthesize , the remaining time given by (17) corresponds to the time interval in which a null resultant vector must be provided (17) Therefore, the proposed solution takes into account the sign of and , as well its value, and how the time interval is added to , and . The addition of is based on a distribution factor 0 1 for vectors and and Sector III and

(20) Sector IV and

(21) Note that (11) is always satised, and that the chosen value for the distribution factor indicates how many vectors, with 0 only three vectors their respective weights, are used. If , and or (see Table III). If 0 1, are used, that is, 1, only three vectors, , and all four vectors are used. If or , are used (see Table IV). plane are dened as As an alternative, the sectors in the being centered on each vector as shown in Fig. 3, instead of , and being dened by two active adjacent vectors ( ). It is possible to use the three vectors, which are the closest

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Fig. 3. Sectors A; B; C; and D in the  plane.

TABLE V GROUPED SECTORS AROUND THE VOLTAGE VECTOR

to by changing the value of . This avoids the use of the farthest vector for a given . Table V reveals how to select in order to always use only the three closest vectors for a given . The row labelled Condition in Table V indicates when the and ). To reference vector enters in a given sector ( use the set of equations given by (18)(21), the identication test and must be substituted by the test that for sector identies sectors , and , respectively. For all cases the choice of denes how to provide a null resultant vector, i.e., (22) The use of the switching patterns given in Table V has already been proposed in Blaabjerg et al. [7]. Also, the switching patterns given in Tables III and IV have already been proposed in Jacobina et al. [4]. However, the generic analytical development describing how all these switching patterns can be parameterized in terms of a single quantity has not been previously presented. The above analysis has demonstrated, how the selection of a specic switching pattern is decided by a single variable, that is, the distribution factor . Note that for the Wye connected motor it also denes the common mode voltage prole. This inuence will be explained in detail in Section VIII. IV. SCALAR PWM The use of the space vector approach provides a simple analytical way, to explain the FSTPI operation. However, to implement the modulator with a timer based hardware it is in general more appropriate to dene a scalar and equivalent version of the proposed technique. Besides, this development provides a good insight about how the pulsewidth modulator can be implemented in software. The basic modication to adapt the scalar PWM technique dened for a SSTPI to control a FSTPI relies on the reference

Fig. 4. Command signal waveforms: (a) t

< 0 and (b) t > 0.

waveform generation. In this case the reference pole voltage and supplied to the modulator must obey waveforms specic phase shift relationships, depending whether the motor windings are connected in delta or in Wye. Fig. 4 shows the typical waveforms of the command signals for the switches and when 0 Fig. 4(a) and 0 Fig. 4(b) both for 1. Assuming that 2, with , 0 the time intervals and , during which and must be switched-on in order to synthesize the desired reference voltage at the output of the FSTPI, are determined by [14] (23) 1,2. From Fig. 4 it can be noted that where and . These relationships demonstrate that both the space vector and the scalar techniques give equivalent results in terms of the average voltage. From Fig. 1(a) and (b) it can be seen that voltages . Consequently, if the line-to-neutral reference voltages , and are written in terms of and , the reference pole voltages are given by (24) (25) This result is also valid when the motor windings are connected in delta. The generation of the command signals for switches and can be provided by using programmable timers. Fig. 4 shows that for the general case in which all four vectors are

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employed, pulse widths and can be split into two parts: and and and . In this case, timers are programmed twice at each time period . Note that if one chooses to use only three vectors, timers are programmed once at each time period . V. DC-LINK UNBALANCE COMPENSATION Low frequency current circulating through the dc-link capacitor is an inherent characteristic of the FSTPI, due to the midpoint connection. Indeed, additional low frequency harmonics current belonging to the grid will also ow through the capacitors in case of using a single-phase half bridge rectier. Note that even when there is no mid-point connection the dc-link voltage oscillates due to the uncontrolled rectier, which means that the actual dc-link voltage is different from the desired stiff voltage . Voltage unbalance at dc-link capacitors can be repwhere 2 and 2 , resented by . Despite of such oscillations at the dc-link with voltages the proposed PWM techniques can still be valid if some compensation is provided. A. Compensated Vector PWM In terms of the vector formulation, it can be shown that the effective available vector components for a Wye connected motor can be computed from (6) and (7) by using the actual dc-link voltage and adding characteristic unbalance terms. The resulting expressions are shown in (26) (27) where and are characteristic unbalance terms. Similar expressions can be obtained if the pole voltage as well as and . The phase voltages are computed as a function of impact of such unbalance over the proposed vector PWM techand , meaning that (12) is nique results in: correctly, it no longer valid. As a consequence, to synthesize is necessary to compensate capacitor voltage unbalance, as well as the dc-link voltage oscillation, introduced by the uncontrolled rectier [9]. Use of large capacitors can minimize both effects but it is a drawback for low cost reduced size topology. Generation of an output voltage vector that matches with can be achieved in a two step procedure. Initially, it is assumed 0. This makes all equations presented in Section III that , and . It is worth to note that and valid to compute are computed by assuming that 0 is valid, even when 0, since 0 only introduces variations along and directions. Then, and computed by assuming that 0 are still valid, even when 0, because 0 and directions. Then, only introduces variations along and are computed by considering that 0 are still valid, to ensure that a reference vector component perpendicular to and directions will be correctly synthesized. Finally, after computing and , the correct values of and are obtained by using (28) and (29). It is also important to note that vectors in
Fig. 5. Overview of unbalance effects.

(28) must include the actual value must obey

. Mathematically

and (28) (29)

and are collinear, which means that the Observing that equation for the axis is a linear combination of the equation for the axis, only one of then can be used to compute and . Thus, the previous solution is still valid, but (22) is not true. In fact, is valid to dene contributions of and to synthesize , but the contribution of and depends on . However, if 0 an additional step must be executed to update and 0, or and 0, when or is not used, respectively. Fig. 5 provides an overview of the unbalancing effects. This gure shows: 1) the synthesized vector overlapped by , and its plane (inner circle); 2) the maximum allowed vector path on amplitude path (intermediate circle); 3) vector loci when dc-link voltage unbalance is veried, and; 4) the maximum ideal vector amplitude path, computed by using the average dc-link voltage 0 (outside circle). and assuming that Fig. 5 also helps to describe a modulation index restriction 0. In other words, a reference vector whose imposed by modulation index is slight smaller than 1, and has been computed by considering the average dc-bus voltage, may not be correctly synthesized due to the capacitor voltage unbalance and dc-link voltage oscillations. Thus, the shadowed region in Fig. 5 corresponds to a not allowed modulation index operation area. In general the shadowed region depends on the capacitor size, load power and rectier type. It can be geometrically shown that the maximum reference vector amplitude yields in . B. Compensated Scalar PWM The generation of an output voltage that matches with the reference voltage can be obtained, if the actual values of the and are available. In other words, the expression given by (23) needs to be re-written in terms of actual values of and . It can be easily shown that in this case the pulse width is computed by (30) with 1,2, and . Note that and are still valid to correctly synthesize the output

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Fig. 6. Reference and synthesized vector locus (a) with a non compensated PWM, (b) with compensated vector PWM, and (c) with reference compensated PWM.

voltage when values of and

and .

are computed, by considering the

C. Compensated Reference It was shown before that for generating an output voltage that matches the reference, it is necessary to take into account actual . An alternative for maintaining expressions values of and derived in Section III for a constant and 0, can be achieved if both capacitors voltage unbalance and full dc-link voltage variation are assumed as part of the reference voltage. Since the use of (30) ensure that pulse widths will be correctly 1,2 is computed, then a modied reference voltage needed to ensure that pulse widths computed by (23) are equal to those computed by (30). Therefore, from (23) and (30) it is possible to conclude that the modied reference voltage is given by (31) which guarantees that (32) Note that an equality similar to (31) can be derived for any other and can be computed by the folreference voltage, e.g., lowing equations: (33) (34) In conclusion, it can be stated that if the original reference and are replaced by and it is possible to use the whole set of equations and procedures that have been developed by 2, even when measurement considering that shows that 2, and . D. Unbalance Effects Unbalancing effects, as well as its compensation, can be explained with the help of a case study simulation. The conguration consisting of a single-phase half bridge input rectier, load has been used in the case and a FSTPI supplying a study. Fig. 6(a) shows the reference vector loci (dashed line)
Fig. 7. DC-link voltage, capacitor voltage, and phase currents for (a) non compensated and (b) compensated PWM.

and synthesized vector loci (solid line). For time weight com2, and a non putation, it was assumed that compensated vector PWM was used. In Fig. 6(b) the synthesized voltage vector overlaps the reference. In this case, for time 2 , weight computation it was considered that 2 , and a compensated vector PWM was and used. Fig. 6(c) shows the reference vector loci (dashed line) and synthesized vector loci (solid line) when the compensated reference method is used. In this case, for time weight computation 2, and (31). As it can it was assumed that be seen, both compensation techniques allow to synthesize balanced output vectors. Fig. 7(a) shows, from top to bottom, the , and capacitor voltage and phase curdc-link voltage rents, when a non compensated vector PWM technique is used. , Fig. 7(b) shows, from top to bottom, the dc-link voltage and capacitor voltages and phase currents, when a compensated vector PWM technique is used. The current unbalance is veried only if a non compensated PWM technique has been used.

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VI. PWM IMPLEMENTATION Based on the set of equations, presented in the previous sections it is possible to derive an algorithm that can be included in the ac drive software. This algorithm is adequate for balanced and unbalanced dc-link voltage, and can be described by the following steps: using (15) and (16); i) compute , and using (17); ii) compute iii) for a previously chosen and voltage unbalance compen, and ; sation algorithm compute , program timers count as follows: timer is iv) if and after with ; rst loaded with timer is rst loaded with and after with ; , program timers count as follows: timer v) if and after with is rst loaded with timer is rst loaded with and after . with , and are indicated in Fig. 4. The time intervals Observing Fig. 4(a) and (b) it can be noted that the number of commutations of the FSTPI switches is not equally distributed. Tests included in steps iv) and v) have been added in order to obtain the same number of average commutation for all FSTPI switches.

VIII. COMMON MODE VOLTAGE for the Wye conguration The common-mode voltage with the motor fed by a four-switch three-phase voltage source inverter is dened by (39) However, 0 and consequently (40) (41) which means that may be equal to 3 or 0 or 2 case of capacitor voltage unbalance ( 2 ) (41) will be changed to 3. In , and

(42) and then may be equal to 3 or 2 3 or 3. Evaluation of a FSTPI and a SSTPI in terms of commonmode voltage requires to consider that for generating the same phase voltage, a FSTPI dc-link voltage needs to be twice that of a SSTPI. Despite of that the maximum common-mode voltage generated by a FSTPI corresponds to two-thirds of maximum common-mode voltage generated by a SSTPI. Besides, FSTPI may generate a null common mode voltage output, different from a SSTPI. IX. SIMULATION RESULTS Digital computer simulation model has been developed to test the proposed PWM techniques. The simulations were perload at different operating formed for a FSTPI supplying a conditions. Stiff dc-link and unbalanced dc-link operation have been considered. Weighted total harmonic distortion (THD) and common-mode voltage have been used to evaluate the perforload system. mance of the FSTPI A. Stiff DC-Link Voltage Operation Fig. 8 presents the total harmonic distortion of the FSTPI as a function of the modulation index . The THD presented in Fig. 8 has been calculated by (43) where and are the total harmonic distortion of voltage components. They have been calculated by

VII. DELTA CONNECTION PWM In case of delta connection, 0 , and 0; then, from (13) and (14), one may nd are given by out that , and

(35) (36) Given (35) and (36), it is possible to use the same procedure, as presented in Section VI. However, it is possible to determine , and for the Wye connection (named from now on as , ) in terms of , and ( voltages for the delta and , and connection). Using matrix it can be shown that are given by

(37)

(38) (44) Then pulse widths for the delta connection can be determined by using the same expressions presented in Sections III and IV. Voltage unbalance compensation can be achieved by using one can also of the method proposed in Section V. Note that be used for a SSTPI, when the load is delta connected. or ), is the amplitude where indicate the axis ( is the amplitude of of the fundamental voltage component, the th harmonic, and is the highest harmonic taken into concomponents in (43) has sideration. Use of the square root of

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TABLE VI THD AS A FUNCTION OF LOAD FREQUENCY

Fig. 8. Output voltage THD.

common-mode voltage waveforms for different PWM patterns 0.7. Also, in Fig. 9, the harmonic spectrum is with shown. For waveforms of Fig. 9, four different PWM patterns had been used. Cases 0 1, and 0.5 are shown in Fig. 9(a)(c), respectively. Fig. 9(d) shows the case in which commutate from zero to one and vice-versa 0 1 , as dened in Table V . From this gure, it can be recognized that 1, generates harmonics with larger the pattern dened by amplitudes than those obtained with other patterns at the same switching frequency. 1 is the best choice From this analysis is evident that 0 is the best selection for for THD minimization, while common-mode voltage minimization. B. Effect of Voltage Unbalance Capacitor voltage unbalance does not only affect the average value of the synthesized inverter output voltage, but also the inverter performance. Indeed, the inverter performance depends on the amplitude of the low frequency dc-link voltage with respect to the average dc-link voltage. Characteristics of these harmonic components depends on the dc-link capacitor size, and the distortion introduced from load and grid throughout the dc-link mid-point. Note that grid and load frequencies can differ from each other. Table VI allows to compare the THD computed when a FSTPI operates with a stiff dc-link voltage versus the THD computed when a voltage unbalance is present. In case of voltage unbalance, the compensation method presented in this paper was adopted, and THD results can be identied by row in Table VI. Three different load frequencies have been evaluated (15, 30, and 60 Hz). The overall system characteristic can be summarized as follows: 1) grid frequency equal to 60 Hz, 2) a half bridge single-phase input rectier with 500 F, 3) switching frequency equal to 2 kHz, 4) 1, 6) rated average dc-link modulation index equal to 0.7, 5) load with 10 , and voltage equal to 600 V, and 7) 33.3 mH. Several capacitance values have been evaluated. It has been shown that when capacitance is reduced, the modulation index restriction increases. Note that the maximum output voltage depends on the minimum , which, in turns, depends on the capacitance and load power. X. EXPERIMENTAL RESULTS Experimental tests were performed, using a setup based on a microcomputer (PC-Pentium) equipped with appropriate plug-in boards for power switch control, and sensors to measure voltage and currents. Two experimental procedures have been performed. In both, an IGBT based FSTPI that switches at

Fig. 9. Common-mode voltage waveform and harmonic components for different PWM patterns.

been adopted to avoid results inuenced by a particular characteristic of any of the phase voltages. These different characteristics occur because one motor phase is connected to the capacitor mid-point. Fig. 8(a) presents the THD for the case in which only three 0 1 indicates that vectors are used. In this gure the label varies as indicated in Table V. The switching frequency used for this simulation was 2 kHz. Fig. 8(b) presents THD results when four vectors are used. To maintain the same average switching frequency during the fundamental period, the PWM period used to compute THD presented in Fig. 8(b) is 1.5 times the PWM period used for Fig. 8(a). For high , all alternatives reveal similar THD, but for medium and low values of , the 1 displays better performance in PWM pattern dened by terms of THD. Since Wye and delta congurations have vectors with similar characteristics, the THD analysis can also be used to compare both congurations. Besides the total harmonic distortion, the common-mode voltage can be adopted as a gure of merit to characterize the inverter performance. In Fig. 9 it is possible to observe

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Fig. 10. Experimental and simulation determination of the THD.

Fig. 11. Harmonic components of v

2 kHz with PWM pattern selected by choosing 1 were adopted. For the rst procedure, a three-phase rectier and a bulky capacitor has been chosen as part of the system, to drive an 1/3 hp induction motor. Experimental data from several modulation indexes were recorded, in order to compute the FSTPI THD. These results, as well as the equivalent simulated ones, are shown in Fig. 10. Both results are similar. Fig. 11 compares experimental and simulated results for the harmonics 0.7. components of the common-mode voltage in the case These results are also very close to each other, thus validating the proposed method. Fig. 12(a) and (b) show the dc-link voltage, capacitor voltage and phase currents for a non compensated and compensated vector PWM, respectively. From top to bottom, each gure , capacitor voltage, and phase curshows dc-link voltage load operating at 30 Hz, and with rents in a Wye connected 500 F. A single-phase half bridge rectier was adopted to validate the proposed procedure since it presents the worst operational condition in terms of capacitor voltage harmonic disturbance. As can be seen, the compensated vector PWM yields a balanced current, while results from a non compensated PWM introduces distortions at the phase current. In addition, variations at the dc-link voltage introduce modulation index restrictions or demand a higher dc-link voltage.

Fig. 12. DC-link voltage, capacitor voltage, and phase currents for (a) non compensated and (b) compensated PWM.

XI. CONCLUSION This paper presents a method to generate PWM signals for control of four-switch three-phase inverters. With the proposed approach, it was possible to study several PWM schemes using three or four vectors to synthesize the desired output voltage during the switching period. The scalar version of the proposed modulation technique can be implemented by software and may be easily included in drive software with a negligible increase in the computational effort. The effects of capacitor unbalance have been evaluated, and compensation procedures have been proposed. The THD analysis shows that the PWM pattern based on three vectors, in which two are small, presents the lowest harmonic distortion. However, the common-mode voltage analysis points out that use of the two greatest vectors, , is more adequate for common-mode voltage reduction. The paper also presented suitable PWM strategies to be applied when the motor windings are delta connected.

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REFERENCES [1] H. W. van der Broeck and J. D. van Wyk, A comparative investigation of a three-phase induction machine drive with a component minimized voltage-fed inverter under different control options, IEEE Trans. Ind. Appl., vol. IA-20, no. 2, pp. 309320, Mar./Apr. 1984. [2] W. McMurray, Modulation of the chopping frequency in dc choppers and PWM inverters having current-hysteresis controllers, IEEE Trans. Ind. Appl., vol. IA-20, no. 4, pp. 763768, Jul./Aug. 1984. [3] F. Blaabjerg, S. Freysson, H. H. Hansen, and S. Hansen, Comparison of a space-vector modulation strategy for a three phase standard and a component minimized voltage source inverter, in Proc. EPE Conf., 1995, pp. 18061813. [4] C. B. Jacobina, E. R. C. da Silva, A. M. N. Lima, and R. L. A. Ribeiro, Vector and scalar control of a four switch three phase inverter, in Proc. IEEE-IAS Annu. Meeting, 1995, pp. 24222429. [5] G. Kim and T. A. Lipo, VSI-PWM rectier/inverter system with a reduced switch count, in Proc. IEEE-IAS Annu. Meeting, 1995, pp. 23272332. [6] R. L. A. Ribeiro, C. B. Jacobina, E. R. C. da Silva, and A. M. N. Lima, AC/AC converter with four switch three phase structures, in Proc. IEEE PESC, Jun. 1996, pp. 134139. [7] F. Blaabjerg, S. Freysson, H. H. Hansen, and S. Hansen, A new optimized space-vector modulation strategy for a component-minimized voltage source inverter, IEEE Trans. Power Electon., vol. 12, no. 4, pp. 704714, Jul. 1997. [8] D. T. W. Liang and J. Li, Flux vector modulation strategy for a fourswitch three-phase inverter for motor drive applications, in Proc. IEEE PESC, Jun. 1997, pp. 612617. [9] F. Blaabjerg, D. Neacsu, and J. Pedersen, Adaptive SVM to compensate DC-link voltage ripple for four-switch three-phase voltage-source inverters, IEEE Trans. Power Electon., vol. 14, no. 4, pp. 13311337, Jul. 1999. [10] A. L. Julian, G. Oriti, and T. A. Lipo, Elimination of common-mode voltage in three-phase sinusoidal power converters, IEEE Trans. Power Electron., vol. 14, no. 5, pp. 982989, Sep. 1999. [11] M. D. Manjrekar and T. A. Lipo, An auxiliary zero state synthesizer to reduce common mode voltage in three-phase inverters, in Proc. IEEE-IAS Annu. Meeting, 1999, pp. 5459. [12] Y.-S. Lai, P.-S. Chen, H.-K. Lee, and J. Chou, Common-mode voltage reduction PWM technique for wide speed range control of induction motor drives fed by inverter with diode front end, in Proc. IEEE-IAS Annu. Meeting, 2003, pp. 424431. [13] Y.-S. Lai and F.-S. Shyu, Optimal common-mode voltage reduction PWM technique for induction motor drives with considering the deadtime effects for inverter control, in Proc. IEEE-IAS Annu. Meeting, 2003, pp. 152159. [14] J. Holtz, Pulsewidth modulation for electronic power conversion, in Proc. IEEE, Aug. 1994, vol. 82, no. 8, pp. 11941214.

Cursino Brando Jacobina (S78M78SM98) was born in Correntes, Pernambuco, Brazil, in 1955. He received the B.S. degree in electrical engineering from the Federal University of Paraba, Campina Grande, Brazil, in 1978, and the Dipl me dEtudes o Approfondies and Ph.D. degrees from the Institut National Polytechnique de Toulouse, Toulouse, France, in 1980 and 1983, respectively. From 1978 to 2002, he was with the Electrical Engineering Department, Federal University of Paraba. Since April 2002, he has been with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande, Brazil, where he is now Professor of electrical engineering. His research interests include electrical drives, power electronics, and control systems.

Edison Roberto Cabral da Silva (SM95F03) was born in Pelotas, Brazil, on December 2, 1942. He received the B.C.E.E. degree from the Polytechnic School of Pernambuco, Recife, Brazil, in 1965, the M.S.E.E. degree from the University of Rio de Janeiro, Brazil, in 1968, and the D.Eng. degree from the University Paul Sabatier, Toulouse, France, in 1972. From 1967 to 2002, he was with the Electrical Engineering Department, Federal University of Paraba. Since April 2002, he has been with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande, Paraba, Brazil, where he is a Professor of electrical engineering and Director of the Research Laboratory on Industrial Electronics and Machine Drives. In 1990, he was with COPPE, Federal University of Rio de Janeiro, and from 1990 to 1991, he was with WEMPEC, University of Wisconsin, Madison, as a Visiting Professor. His current research work is in the area of power electronics and motor drives. Dr. Da Silva was the General Chairman of the 1984 Joint Brazilian and LatinAmerican Conference on Automatic Control, sponsored by the Automatic Control Brazilian Society and was the General Chairman of The IEEE Power Electronics Specialists Conference, PESC05.

Maurcio Beltro de Rossiter Corra (S97M03) was born in Macei, Alagoas, Brazil, in 1973. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Federal University of Para ba, Campina Grande, Brazil, in 1996, 1997, and 2002, respectively. From 1997 to 2004, he was with the Centro Federal de Educao Tecnolgica de AlagoasUNED/PI, Palmeira dos Indios, Brazil. From 2001 to 2002, he was with WEMPEC, University of Wisconsin, Madison, as a Scholar. Since July 2004, he has been with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande, Brazil, where he is now an Associate Professor of electrical engineering. His research interests include electrical drives, power electronics, and renewable energy.

Antonio Marcus Nogueira Lima (S77M89) was born in Recife, Pernambuco, Brazil, in 1958. He received the B.S. and M.S. degrees in electrical engineering from the Federal University of Paraba, Campina Grande, Brazil, in 1982 and 1985, respectively, and the Ph.D. from the Institut National Polytechnique de Toulouse, Toulouse, France, in 1989. He was with the Escola Tcnica Redentorista, Campina Grande, Paraba, Brazil, from 1977 to 1982 and was a Project Engineer at Sul-Amrica Philips, Recife, Pernambuco, Brazil, from 1982 to 1983. From 1983 to 2002, he was with the Electrical Engineering Department, Federal University of Paraba. Since April 2002, he has been with the Electrical Engineering Department, Federal University of Campina Grande, Campina Grande, Paraba, where he is now Professor of electrical engineering. His research interests are in the elds of electrical machines and drives, power electronics, electronic instrumentation, control systems, and system identication.