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A New Mathematical Model and Control of a Three-Phase ACDC Voltage Source Converter
Vladimir Blasko, Member, IEEE, and Vikram Kaura, Member, IEEE
AbstractA new mathematical model of the power circuit of a three-phase voltage source converter (VSC) was developed in the stationary and synchronous reference frames. The mathematical model was then used to analyze and synthesize the voltage and current control loops for the VSC. Analytical expressions were derived for calculating the gains and time constants of the current and voltage regulators. The mathematical model was used to control a 140-kW regenerative VSC. The synchronous referenceframe model was used to dene feedforward signals in the current regulators to eliminate the cross coupling between the d and q phases. It allowed the reduction of the current control loops to rst-order plants and improved their tracking capability. The bandwidths of the current and voltage-control loops were found to be approximately 20 and 60 times (respectively) smaller than the sampling frequency. All control algorithms were implemented in a digital-signal processor. All results of the analysis were experimentally veried. Index Terms Control, converter, low harmonic distortion, mathematical model, unity power

model are drawn to facilitate the analysis on an intuitive basis. This model is then used to synthesize the voltage and current control loops for the VSC and study the dynamics of these control loops. Analytical expressions are presented for the gains and time constants of the voltage and current regulators. The model allows for a straightforward algorithm for decoupling control of the active and reactive current components. Complete control of the VSC based on this model is implemented in a digital signal processor (DSP) running at a clock speed of 40 MHz with a sampling rate of 10 kHz. II. THE MATHEMATICAL MODEL A three-phase mathematical model for the VSC was derived in [4][5]. The power unit used was similar to the one shown in Fig. 1. Assuming a balanced three-phase system without the neutral connection and neglecting the resistance of the power switches, the VSC can be modeled as (1)

I. INTRODUCTION HREE-PHASE voltage source converters (VSCs) can provide constant dc bus voltage, low harmonic distortion of the utility currents, bidirectional power ow, and controllable power factor. Because of these features, they are becoming increasingly popular in high-power or highperformance drive applications requiring frequent acceleration and deceleration. In these applications, the cost of the energy wasted during braking becomes too high and can justify the additional cost of a VSC as an integral part of the drive or as a stand-alone unit. The three-phase regenerative VSC is a relatively new apparatus and has attracted much development effort in recent times. References [1][4] present the control principles of a VSC with three-phase stationary reference-frame current regulators and analyze the associated voltage, current, and power conditions. An exhaustive analysis of the VSC is given in [5] for a steady-state dc model, a low-frequency small-signal ac model, and a high-frequency model. These models, while complete in their analysis, are difcult to apply for control purposes because of their complexity. In this paper a new mathematical model of a VSC is presented from the control point of view. The new model, based on the representation, is derived in the stationary and synchronous frames of reference. Block diagrams of the
Manuscript received June 5, 1995; revised June 5, 1996. The authors are with the Rockwell AutomationAllen Bradley Company, Standard Drives Division, Mequon, WI 53092 USA. Publisher Item Identier S 0885-8993(97)00620-0. 08858993/97$10.00 1997 IEEE

(2)

(3) where index for the three-phases ; switching functions; line currents; phase voltages; bus voltage; bus current; resistance of the line reactor; inductance of the line reactor. This three-phase model is represented as a block diagram in Fig. 2. A two-phase coordinate system ( ) is dened in Fig. 3 along with a three-phase system (1, 2, 3). The transformation of variables between these two coordinate systems is given by the following: (4) (5) (6)

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Fig. 1. Circuit diagram of a three-phase VSC.

Fig. 4. Stationary reference-frame dq model of a three-phase VSC.

A two-phase stationary reference-frame model of the VSC is obtained by applying (4) and (5) to (1)(3) (7) (8) (9) A block diagram of this two-phase model in the stationary reference-frame is shown in Fig. 4. Using the complex vector notation of (6), (7)(9) can be written in a more compact form as (10)
Fig. 2. Block diagram for the power circuit of a three-phase VSC.

(11) where denotes the complex conjugate vector. The complex vector representation of the two-phase model in a stationary reference frame [(10) and (11)] can be transformed to a complex vector representation of the two-phase model in the synchronous reference frame using the following transformation (12) where superscript for synchronous reference-frame; utility frequency (constant). Applying (12) to (10) and (11), the following two-phase synchronous reference-frame model in the complex vector notation is obtained (13)

Fig. 3. Orientation of three-phase and dq systems in a complex plane.

where

the two-phase system variables the three-phase system variables Separating (13) and (14) into the following: and

(14) components results in (15)

is a complex vector rotating counterclockwise.

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Fig. 5. Synchronous reference-frame dq model of a three-phase VSC.

(16) (17) A block diagram of this two-phase model (15)(17) in the synchronous reference frame is shown in Fig. 5. Note that the synchronous reference-frame model in Fig. 5 can be transformed into the stationary reference-frame model in Fig. 4 by inserting . This new model in Fig. 5 forms the basis for the analysis which follows. III. CONTROL
OF THE Fig. 6. Control diagram of the VSC.

only work which is performed by the regulators during normal operation is to correct for the errors in the parameters used for the above compensations. The current regulators become more active during operation of the VSC at an increased utility voltage when the PWM transitions toward a six-step mode of operation [8]. IV. DIGITAL CURRENT REGULATORS A. Synthesis and Analysis and axes reduces the synchronous Decoupling the reference-frame current control plant to a rst-order delay and improves the tracking capability of the current regulators. It simplies the analysis and enables the derivation of analytical expressions for the parameters of current regulators. A block diagram for such a simplied current control loop in the synchronous reference-frame is shown in Fig. 7. Because the same diagram applies to both the and axis regulators, the subscripts and are omitted. Variables and are used for the command and feedback currents, respectively. The gains and time constants associated with the various elements of the block diagram are as follows: sampling time; disturbance voltage; gain of PI regulator; time constant of PI regulator; gain of the PWM block; time constant of the PWM block ; gain of the - load ; time constant of the - load. The power unit, approximated with a rst-order element, has a time constant equal to one half of the sampling period and gain . Variations in the utility voltage and the uncompensated effects of blanking time are modeled by the disturbance signal . To further simplify the block diagram

VSC

A functional control diagram of the VSC is presented in Fig. 6. Complete control with the current and voltage-feedback loops was implemented in a DSP. The reference angle generator synchronizes reference angle with the line voltages. Transformation block 3 /2 transforms the three-phase ) from the stationary frame of reference currents ( to the synchronous frame of reference ( ). Synchronous reference-frame proportional integral (PI) current regulators ( reg, reg) regulate the and current components. for reg is generated by PI voltage The command regulator which regulates dc bus voltage . For unity power factor, command for reg is set to zero. The output signals and from the current regulators are inputted to the compensation/transformation/pulse width modulation (PWM) block. To better utilize the dc bus voltage in the presence of utility voltage uctuations and reduce the commutation losses of power devices, two-phase modulation was implemented [8]. The effect of blanking time [9] was compensated for in the software. The cross coupling between the and axes due to inductance was compensated using feedforward signals. The derivation of the algorithm for crosscoupling compensation and compensation of utility voltage is straightforward from the synchronous reference-frame model of the VSC in Fig. 5. Under normal operating conditons and with the proper compensation for inductive cross-coupling, utility voltage uctuation, blanking time effect, and the outputs ( ) of the current regulators are very close to zero. In other words, the

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Fig. 7. Block diagram of the current control loop.

in Fig. 7, the two blocks with the smallest time constants (sample, hold, and the PWM) are grouped together to form a single block with gain and equivalent time constant (18) The dominant pole in the load can be canceled by setting the integral time constant of the PI regulator equal to that of the load (19) With the simplication of (18) and the time constant selection of (19), the closed-loop transfer function of the system in Fig. 7 becomes (20) From (20) the damping factor is given as (21) . Thus, the proFor the technical optimum [6], portional gain of the PI regulator can be calculated from (21) as (22) The closed-loop transfer function (20) can be further simplied by neglecting the term (because of the very small ). After introducing from (21) into product term simplied (20), the following rst-order approximation is obtained [6] (23) ; for a critically damped system, and . The term often used to roughly specify the quality of a control loop is bandwidth: a frequency at which gain of the closed loop is reduced to 3 dB, and the phase delay becomes larger than 45 (assuming that closed-loop behavior can be approximated by a rst-order delay element). In reality, a closed-loop transfer function is seldom a rst-order element, and reduction of the gain to 3 dB and phase to 45 does not happen at the same frequency. The conservative approach is to where

Fig. 8. Simulated response of the current control loop to step change in reference ie and disturbance udis . c

specify the lowest of the frequencies corresponding to these conditions as the bandwidth. In a system with the sampling delay approximated with a rst-order element and all of the small time constants being lumped together into an equivalent time constant, the phase becomes 45 at frequency lower than the frequency at which the gain reduces to 3 dB. With the current loop adjusted to be critically damped, the bandwidth is obtained from (23) as (24) From (24) it follows that the bandwidth of the current regulator is approximately 20 times smaller than the sampling frequency. However, due to the approximations made in the derivation of (23), (24) gives an estimate of the bandwidth which is accurate enough for practical purposes. The adjustment of the current regulator according to (19) and (22) provides good response with about a 4% overshoot to a step change of reference. The time constant of the input choke is usually large ( 100 ms for units of 10 kW or more). According to (19), this would result in a large time constant, , of the PI regulator and hence, poor rejection capability for disturbance . To improve the disturbancerejection capability, the time constant of the PI regulator can be selected to be ten times higher than the smallest equivalent time constant in the system (25) Such an adjustment would increase an overshoot to the step change of the reference; it would not reduce the bandwith of the system with a conservative prediction according to (24). A 140-kW 460-V system with s, mH, and m was simulated and tested. The simulation was done with current control with: 1) a reduced order model according to Fig. 7 and 2) a complete nonlinear model based on Figs. 5 and 6 with the PWM modeled as an amplier. The results of the simulation with the reduced model in Fig. 7 with the proportional gain selected according to (22) and the time constant selected according to (25) are presented in Fig. 8. Note the overshoot of approximately 20% and the fast

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Fig. 9. Simulated step response of d and coupling for integral time constants Ti =

q current regulators without cross TLR and Ti = 10Tei .

Fig. 10. Measured response of the current to a step change of reference current.

response to disturbance voltage . With the time constant selected according to (19), the system is critically damped with an overshoot of 4%. The results of the simulation with a complete nonlinear model with the proportional gains selected according to (22) and the time constants selected according to (19) and (25) are presented in Fig. 9. The cross coupling due to inductance was not compensated for in this simulation to investigate its inuence on the dynamics of current control loops. The response to load disturbance is slow when is selected according to (19). The current component generated without cross-coupling compensation slowly approaches zero. With a much smaller selected according to (25), the overshoot to the step change in command increased from 4% (typical for the technical optimum) to an acceptable level of 20%. Under this condition, a fast rejection of load disturbance is observed, and the cross-coupled current component decays rapidly. With the cross-coupling compensation enabled, the developed due to a change of becomes negligibly small whether (19) or (25) are used to set . Cross-coupling compensation substantially improves the tracking capability of current regulators, particularly if the integral time constant is large. With the cross-coupling compensation enabled, the complete nonlinear model of the VSC and the reduced model in Fig. 7 provide very similar results. B. Experimental Results Experimental verication was done on a 140-kW 460-V VSC. The complete control was implemented in a DSP with a clock speed of 40 MHz and a sampling rate of 10 kHz. Because of the decoupling control of the current regulators, the and axis regulators produce identical results. To be comprehensive, experimental results are shown for only one of the axes. Actual waveforms from one of the current regulators, reg, are shown in Fig. 10. The gain was selected according to (22) and the time constant according to (25). As expected from the simulation results (Fig. 8), an overshoot

Fig. 11. Measured amplitude and phase response of the closed loop of the synchronous reference-frame current regulator.

of approximately 20% is obtained with the feedback current reaching the commanded value in approximately four sampling intervals. The bode plot with the amplitude and phase responses of the current loop were measured on the same unit. The results are show in Fig. 11. Note the at amplitude response with 3 dB at approximately 1.2 kHz and a phase delay higher than 45 after approximately 400 Hz. The theoretical prediction of the bandwidth using (24) was 500 Hz. V. DC BUS VOLTAGE REGULATOR A. Synthesis and Analysis The dc bus-voltage control loop can be modeled with the block diagram of Fig. 12. The gains and time constants associated with the various elements of the block diagram are as follows: feedback-loop delay due to sampling, processing time, and feedback lter; gain of the PI regulator; time constant of the PI regulator.

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Fig. 12.

Block diagram of the dc bus-voltage control loop.

The inner current control loop is modeled with the rstorder transfer function (23). Combining the two smallest time constants in Fig. 12 ( and 2 of ), equivalent time constant is obtained (26) The open-loop transfer function is thus given by (27) The method of symmetrical optimum [6], [7] is used to synthesize the control system using the open-loop transfer function . According to this method, the amplitude and phase plot of are symmetrical about the crossover frequency . The crossover frequency and phase margin are related as the following: (28) (29) where (30) of the PI regulator at the crossover frequency Gain given as is

Fig. 13. Response of dc bus-voltage udc c and disturbance idis .

udc

to the step change of reference

Simulation results for the VSC, tuned according to the above method, are shown in Fig. 13. Substantial overshoot in response due to a step change in command , typical for the technical optimum, is noticeable. This overshoot is not of concern because typically the bus-voltage command of a VSC is kept constant. At power-up conditions, this overshoot can be easily reduced by limiting the rate of change of the bus-voltage reference. The simulation also shows a strong (load-current) disturbance-rejection capability. Adjustment of the bus-voltage regulator according to the method of technical optimum provides high proportional gain and a small integral time constant. This results in a fast response of command and a strong rejection of disturbance. On the other hand, a negligibly small ripple in the dc bus voltage (caused by nonsymmetrical/sinusoidal currents or voltages) appears as a noticeable distortion of and results in the distortion of the utility current. To counter this effect, additional ltering of the bus voltage is needed which results in reduction of the bus-voltage regulator gain and smaller bandwidth than that predicted by (33). B. Experimental Results Experimental results obtained on a 140-kW VSC are shown in Fig. 14 for and with ms selected according to (31) and (30). Fig. 14 shows the open-loop gain and phase response of the bus-voltage control loop. The amplitude and phase plots are symmetrical at about a frequency of 140 Hz. This is bandwidth frequency introduced earlier, and it is satisfactorily close to the predicted value of 166 Hz. Fig. 15 demonstrates the disturbance-rejection capabilities of the bus-voltage control loop under the different settings of the voltage regulator. To reduce the ripple in the bus voltage, a lter was introduced in the voltage feedback increasing to 1 ms. Factor was selected to be four. A resistive load of 4.5 was connected across the dc bus to cause a sudden disturbance in the load current. Forced by the bus-voltage regulator, the current regulators quickly met the demand for additional load current, and the dc bus recovered to the original value of 750 V after a small dip. An increase in the factor

(31) and gain Given phase margin or factor , time constant of the PI regulator can be calculated using (30) and (31). The closed-loop transfer function is given as (32) result in a damping factor; The pair of complex poles of for [6], [7]. If only the sampling delay ), the equivalent is present in the voltage feedback ( time constant becomes . Under the above conditions, transfer function will have a gain of at or the bandwidth frequency (33)

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Fig. 14.

Measured amplitude and phase response of the open-loop bus-voltage regulator.

Fig. 15. Response of dc bus voltage udc to step change in load current from 0 to 170 A; e1 and i1 are the phase voltage and current, respectively.

provided improved load-disturbance rejection capability with an acceptable overshoot of 20% to a step change in the reference. The bandwidth of the current loops was predicted and veried to be approximately 20 times smaller than the sampling frequency. Analytical expressions for the gain and time constant of the bus-voltage PI regulator were derived using the method of symmetrical optimum. Fast response of the dc bus voltage to the reference and strong rejection to the load-current change were obtained. The achievable bandwidth of the voltage control loop was predicted and veried to be as high as 1/60 of the sampling frequency. A small ripple in the dc bus voltage causes a ripple to appear in the current reference and consequently, increases the total harmonic distortion (THD) of the input-line currents. To reduce this effect, it might be necessary to introduce additional ltering in the voltage-feedback loop in exchange for the bandwidth of the dc bus-voltage regulator. REFERENCES

form 2.4 to 4 and additional delay in dc-voltage feedback reduced the proportional gain to and increased the integral time constant of the voltage regulator to ms. The consequence was an increased (but still very fast and satisfactory) response time in dc bus voltage feedback to load disturbance. VI. CONCLUSION A new mathematical model of a three-phase VSC was developed in the stationary and synchronous frames of reference. The model was then used to synthesize the voltage and current control loops of the VSC. Current regulators with a sampling rate of 10 kHz were implemented in a synchronous reference-frame. The method of technical optimum was used to derive expressions for gains and time constants of PI current regulators. Use of (25) rather than (19) to calculate the integral time constant

[1] B.-T. Ooi, J. C. Salmon, J. W. Dixon, and A. B. Kulkarni, A threephase controlled-current PWM converter with leading power factor, IEEE Trans. Ind. Applicat., vol. IA-23, no. 1, pp. 7884, Jan./Feb. 1987. [2] J. W. Dixon and B.-T. Ooi, Indirect current control of a unity power factor sinusoidal current boost type three-phase rectier, IEEE Trans. Ind. Electron., vol. 35, no. 4, pp. 508515, Nov. 1988. [3] S. B. Dewan and R. Wu, A microprocessor-based dual PWM converter fed four quadrant ac drive system, in Conf. Rec. 1987 IEEE-IAS Ann. Meeting, pp. 755759. [4] R. Wu, S. B. Dewan, and G. R. Slemon, A PWM ac to dc converter with xed switching frequency, in Conf. Rec. 1988 IEEE-IAS Ann. Meeting, pp. 706711. [5] R. Wu, S. B. Dewan, and G. R. Slemon, Analysis of an ac-to-dc voltage source converter using PWM with phase and amplitude control, IEEE Trans. Ind. Applicat., vol. 27, no. 2, pp. 355364, Mar./Apr. 1991. [6] W. Leonhard, Introduction to Control Engineering and Linear Control Systems. New Delhi: Allied, 1976. , Control of Electrical Drives. Berlin: Springer-Verlag, 1985. [7] [8] V. Kaura and V. Blasko, Operation of a voltage source converter at increased utility voltage, in Conf. Rec. PESC-95 Ann. Meeting, Atlanta, GA, 1995, pp. 523528. [9] N. Mohan, T. M. Undeland, and W. F. Robbins, Power Electronics: Converters, Applications and Design. New York: Wiley, 1989.

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Vladimir Blasko (M89) was born in Klenovnik, Croatia, in 1953. He received the B.Sc., M.S., and Ph.D. degrees in electrical engineering from the University of Zagreb, Croatia, in 1976, 1982, and 1986, respectively. From 1976 to 1988, he worked at the Electrotechnical Institute Rade Koncar, Zagreb, in the Power Electronics and Automatic Control Department. From 1989 to 1992, he was with the Research and Development Center of the Otis Elevator Company, Farmington, CT. Since 1992, he has been with the Standard Drives Division of the Rockwell AutomationAllen Bradley Company, Mequon, WI. He has been working on the research, development, and design of high-power transistor choppers, drives for electrical vehicles, high-performance ac elevator drives, and low-harmonic regenerative threephase VSCs. His primary areas of interest are ac drives, intelligent power management, power electronics, applied modern control theory, and technology. Dr. Blasko was with the University of Wisconsin during the 198889 academic year as a recipient of the IREX Scholarship.

Vikram Kaura (S86M89) received the B.E. degree in electrical engineering from Punjab Engineering College, Chandigarh, India, in 1987 and the M.S. degree in electrical engineering from the University of Wisconsin, Madison, in 1989. He is also currently a student at the University of Chicago Graduate School of Business, IL. From 1989 to 1991, he worked as a Design Engineer with the Drive Systems Division of the General Electric Company. Since then, he has been with the Standard Drives Division of the Rockwell AutomationAllen Bradley Company, Mequon, WI, where he is currently a Project Engineer involved with the design and development of highperformance ac drives and low-harmonic regenerative converters. His areas of interest include real time control and applied mathematics.