Breaking Through The BIOS Barrier - The Definitive BIOS Optimization Guide For PCs

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Adrian has done the tech community a great service by making this guide. It has personally
saved me time on both repairs and evaluations. With BIOS options as numerous as they are
today, it`s vondertul to have a one-stop-source to decipher them all.
Nathan Warava, GamingIn3D.com
You knov, I couldn`t count the amount ot times I`ve reterred people to your BIOS
Guide.it`s very intormative, and saves me the time ot explaining vhy people should disable
Video BIOS Shadoving, vhy las t Writes isn`t such a big deal tor today`s games, and much
more.
ust vanted to say thanks tor saving me time and also helping me out. (I learned a lot trom it,
too', Keep up the most excellent vork.
Matt Burris, 3DGPL.com
...this isn`t so much a Knovledge base but a labor ot love. Not only has this guide had a place
in both 1itch`s and My lavorites tor many years, but I`m really excited to see it still going atter
many, many years.Well done, Adrian. Keep up the excellent vork.
)ohnL, 1he Modlathers.com
Adrian Wong ot Adrian`s Pojak Pot has been building up his BIOS guide since late 1999.
1oday, he hit version 6.0, and the guide is nov comprehensive in its scope. It comes highly
recommended trom me due to the tact that BIOS optimizations can yield positive results in
pertormance and compatibility tor everyone. Adrian als o goes into tar greater detail than even
your best motherboard manual and even debunks some myths that some manutacturers still
propagate.
Ryu Connor,1ech-Peport.com
1his is one ot the most comprehensive and user-triendly guides I have tound to date. I vas
able to do various tveaks vith my memcpu that increased my overall system pertormance by
about 13.
Many ot the BIOS tveaks vill depend on your mobo and vhether certain options are even
available in your BIOS menu. Hovever, I do recommend that even ppl that aren`t tamiliar
vith vorking vith the BIOS give it a go vith this guide... Peally helps to ansver all your
questions.
)anes, 1imSott.com
Some bookmarks occupy space in my lavorites tolder just in case I need such a resource in
the tuture, but others are trequent visits. I can easily see this one being a resource to vhich I
reter otten.1his site contains very good explanations ot the numerous contguration options you
see in the BIOS.
...this truly is a link you`ll vant to keep around.1his one is already syncèd to my iPaq'
LockerGnone.con
1his is the mos t comprehensive BIOS Guide available. ust about every option in a modern
BIOS is explained.1he best pertormance setting is usually pointed out, and the explanations are
easy to tollov. A must tor any overclocker vanna-be.
1in B., OCWorkbench.com
I`d like to congratulate the author ot the BIOS Optimization Guide.1his is absolutely mar-
velous. I vas looking specitcally tor advanced intormation on the AGP Aperture Size setting,
and you guys have got 1LN paragraphs on it.
Shernan, Microsott Support Services
Breaking 1hrough
the BIOS Barrier
Breaking 1hrough
the BIOS Barrier
1he Detnitive BIOS Optimization
Guide tor PCs
Arian ong
An Imprint ot PLAPSON LDLCA1ION
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Contents
Ioreuoro | Leuis Keiier, Mushkin xxi
Introduction 1
Chapter 1 What Is 1he Bios S
Hov Does 1he BIOS Work 3
1he Motherboard BIOS 6
1he BIOS Chip 6
What Does It Do 7
Why Optimize the BIOS 7
Hov Do I Optimize the BIOS 8
BIOS Lpdates 8
Hov Do I Lpdate the BIOS 9
Determining the BIOS Ver sion 9
Obtaining the BIOS Lpdate 10
Preparing a BIOS ll ash Disk 12
llashing the Motherboard BIOS 12
Accessing the BIOS Setup Ltility 14
1he BIOS Setup Ltil ity 14
Optimizing the BIOS 14
Chapter 2 Special 1opics 17
BIOS Lmergencies 17
Lnbootable System 17
Pover Ott-Pover On 17
Keyboard Peset 18
CMOS Discharge umper 18
CMOS Battery Pemoval 19
Corr upted BIOS 20
Hot llashing 21
What Do I Need 1o Hot llash a BIOS Chip 22
Step 1 : Create a DOS Boot Disk 22
Step 2 : Prepare a Hot-llash Capable Computer 23
Step 3 : Booting Lp vith the Boot Disk 24
Step 4 : Svap the BIOS Chips 24
Step 3 : llash the Cor rupted BIOS Chip 24
Step 6 : Svap the BIOS Chips Again 23
What It You Don`t Have a Similar Motherboard 26
llashing With a Ditterent Motherboard 26
1he Lniversal BIOS ll ash Ltil ity 27
Summary 27
Chapter 3 Quick Revievs 29
Introduction 29
4 30
8-bit IO Pecover y 1ime 30
16-bit IO Pecovery 1ime 30
32-bit Disk Access 30
32-bit 1ranster Mode 30
A 32
Act Bank A to B CMD Delay 32
AGP 2X Mode 32
AGP 4X Drive Strength 32
AGP 4X Mode 33
AGP 8X Mode 33
AGP Alvays Compensate 33
AGP Aperture Size 34
AGP Capability 34
AGP Cl ock CPL lSB Clock 33
AGP Drive Strength 33
AGP Drive Strength N Ctrl 36
AGP Drive Strength P Ctrl 36
AGP Driving Control 36
AGP Driving Value 37
AGP last Wr ite 33
AGP ISA Aliasing 37
AGP Master 1WS Pead 38
AGP Master 1WS Wr ite 38
AGP Pretetch 38
AGP Secondary Iat 1imer 39
AGP Spread Spectrum 39
AGP to DPAM Pretetch 40
AGPCIK CPLCIK 40
Anti-Virus Protection 40
APIC lunction 41
Assign IPQ lor LSB 41
Assign IPQ lor VGA 41
A1 Bus Cl ock 41
A1A100PAID IDL Controller 42
Athlon 4 SSLD Instr uction 42
Auto Detect DIMMPCI Cl k 43
Auto 1urn Ott PCI Clock Pin 43
B 44
Boot Other Device 44
Boot Sequence 44
Boot Sequence LX1 Means 43
Boot 1o OS2 43
Boot Lp lloppy Seek 43
Boot Lp NumIock Status 43
Byte Merge 46
viii LonIcnIs
LonIcnIs ix
C 47
Clock 1hrottle 47
Compatibl e lPL OPCODL 47
CPLDPAM CIK Synch C1I 48
CPL Dr ive Strength 48
CPL last String 48
CPL Hyper-1hreading 49
CPL I2 Cache LCC Checking 49
CPL Iatency 1imer 30
CPL Ievel 1 Cache 30
CPL 1hermal-1hrottling 31
CPL to PCI Post Write 31
CPL to PCI Wr ite Butter 32
CPL VCore Voltage 32
D 33
DBI Output tor AGP 1rans. 33
Delay DPAM Pead Iatch 33
Delay IDL Initial 34
Delay Prior 1o 1hermal 34
Delayed 1ransaction 33
Ditterential Current 36
Disable Lnused PCI Clock 36
DOS llat Mode 37
DPAM Act to PreChrg CMD 37
DPAM Burst Iength 8QW 37
DPAM Data Integrity Mode 38
DPAM Idl e 1imer 38
DPAM Interleave 1ime 39
DPAM Page-Mode 39
DPAM PreChrg to Act CMD 60
DPAM Patio (CPL:DPAM, 60
DPAM Patio HW Strap 61
DPAM Pead Iatch Delay 61
DPAM Petresh Pate 62
Duplex Sel ect 62
L 63
LCP Mode Lse DMA 63
LPP Mode Sel ect 63
l 64
last P-W 1ur n Around 64
last Write to Pead 1urnaround 64
lirst Boot Device 64
llash BIOS Protection 63
lloppy 3 Mode Support 63
lloppy Disk Access Control 66
lorce 4-Way Interleave 66
lorce Lpdate LSCD 66
lPL OPCODL Compatible Mode 67
lrame Butter Size 67
lSB Spread Spectrum 68
lull Screen Iogo 68
G 69
Gate A20 Option 69
Graphic Win Size 69
Graphic Windov WP Combin 70
Graphics Aperture Size 70
H 72
Hardvare Peset Protect 72
HDD S.M.A.P.1. Capabil ity 72
Host Bus In-Order Queue Depth 73
Hyper-1hreading 1echnology 73
I 73
IDL Bus Master Support 73
IDL HDD Block Mode 73
Init Display lirst 76
In-Order Queue Depth 76
Interr upt Mode 77
IOQD 77
ISA 14.318MHz Clock 78
ISA Lnable Bit 78
K 79
K7 CIK_C1I Select 79
KBC Input Clock Select 80
Keyboard Auto-Pepeat Delay 80
Keyboard Auto-Pepeat Pate 80
I 81
I3 Cache 81
ID-Ott Dram PDWP Cycles 81
Ievel 2 Cache Iatency 81
M 83
Master Dr ive PIO Mode 83
Master Dr ive LltraDMA 83
Master Priority Potation 84
MD Dr iving Strength 84
Memory Hole At 13M-16M 83
MP Capabl e Bit Identity 83
MPS Control Version lor OS 86
MPS Pevision 86
Multi-Sector 1ransters 87
N 88
NB Strap CPL As 88
No Mask ot SBA lL 88
O 90
Onboard lDC Svap A 8 B 90
Onboard lDD Controller 90
x LonIcnIs
Onboard IDL-1 Control ler 91
Onboard IP lunction 92
Onboard Parallel Port 92
Onboard Serial Por t 1 92
Onboard LSB Controller 93
OnChip VGA Mode Select 93
OS2 Onboard Memory ~ 64M 94
OS Select lor DPAM ~ 64MB 94
P 93
P2CC2P Concurrency 93
Parallel Port Mode 93
Passive Pelease 96
PCI42 Access 41 Petry 96
PCI 2.1 Compliance 97
PCI Chaining 97
PCI Clock CPL lSB Clock 98
PCI Delay 1ransaction 98
PCI Dynamic Bursting 99
PCI IDL Busmaster 100
PCI IPQ Activated By 100
PCI Iatency 1imer 100
PCI Master 0 WS Pead 101
PCI Master 0 WS Write 101
PCI Master Pead Caching 102
PCI Pipelining 102
PCI Pretetch 102
PCI 1arget Iatency 103
PCI to DPAM Pretetch 103
PCIVGA Palette Snoop 103
PIO Mode 104
PIPQ x Lse IPQ No. 104
PNP OS Installed 103
Post Write Combine 106
Pover On lunction 107
Primary Graphics Adapter 107
Primary VGA BIOS 108
Processor Number leature 108
PS2 Mouse lunction Control 108
Q 110
Quick Boot 110
Quick Pover On Sel t 1est 110
P 111
Pank Interleave 111
Pead-Around-Wr ite 111
Pead Wait State 111
Petresh Inter val 112
Petresh Mode Select 112
Peport No lDD lor Win93 112
Peset Contguration Data 113
LonIcnIs xi
Pesource Controll ed By 113
PxD,1xD Active 114
S 113
S2K Bus Dr iving Strength 113
S2K Strobe N Control 113
S2K Strobe P Control 116
SDPAM 11 Command 116
SDPAM 11 Command Control 117
SDPAM Active to Precharge Delay 117
SDPAM Bank Interleave 117
SDPAM Bank-to-Bank Delay 118
SDPAM Burst Ien 119
SDPAM Burst Iength 119
SDPAM CAS Iatency 1ime 119
SDPAM Command Ieadott 1ime 120
SDPAM Command Pate 120
SDPAM Cycle Iength 120
SDPAM Cycle 1ime 1ras1rc 121
SDPAM LCC Setting 121
SDPAM Idle Iimit 122
SDPAM Ieadott Command 122
SDPAM Page Closing Policy 123
SDPAM Page Hit Iimit 123
SDPAM PH Iimit 124
SDPAM Precharge Control 124
SDPAM PAS Precharge Del ay 124
SDPAM PAS Precharge 1ime 123
SDPAM PAS Pul se Width 123
SDPAM PAS-to-CAS Delay 126
SDPAM Pov Active 1ime 126
SDPAM Pov Cycle 1ime 126
SDPAM 1ras 1iming Value 127
SDPAM 1rc 1iming Value 127
SDPAM 1rcd 1iming Value 128
SDPAM 1r p 1iming Val ue 128
SDPAM 1r rd 1iming Value 129
SDPAM Wr ite Pecover y 1ime 129
SDPAM Wr ite to Pead Command Delay 129
Second Boot Device 130
Security Setup 130
Shadoving Address Panges 130
Share Memory Size 131
Slave Drive PIO Mode 131
Slave Drive Ll traDMA 132
Speed Lrror Hol d 132
Split Iock Operations 133
Spread Spectrum 133
Super Bypass Mode 134
Super Bypass Wait State 134
SuperStability Mode 134
Svap lloppy Drive 133
xii LonIcnIs
Synchronous Mode Select 136
System BIOS Cacheable 136
1 137
1hird Boot Device 137
1X, PX Inverting Lnabl e 137
1ypematic Pate 137
1ypematic Pate Delay 138
1ypematic Pate Setting 138
L 139
Lltra DMA Mode 139
LltraDMA-100 IDL Controller 139
LltraDMA-66 IDL Control ler 140
LSB Controller 141
LSB Keyboard Suppor t 141
LSB Mouse Support 141
LSWC Wr ite Posting 142
V 143
Video BIOS Cacheable 143
Video BIOS Shadoving 143
Video Memory Cache Mode 144
Video PAM Cacheable 143
Virus Warning 143
VIink 8X Support 146
W 147
Watchdog 1imer 147
Write Data In to Pead Delay 147
Write Pecovery 1ime 148
Chapter 4 Detailed Descriptions 149
Introduction 149
4 130
8-bit IO Pecover y 1ime 130
16-bit IO Pecovery 1ime 130
32-bit Disk Access 131
32-bit 1ranster Mode 131
A 133
Act Bank A to B CMD Delay 133
AGP 2X Mode 133
AGP 4X Drive Strength 134
AGP 4X Mode 133
AGP 8X Mode 136
AGP Alvays Compensate 137
AGP Aperture Size 137
AGP Capability 139
AGP Cl ock CPL lSB Clock 139
AGP Drive Strength 160
AGP Drive Strength N Ctrl 161
AGP Drive Strength P Ctrl 162
AGP Driving Control 162
LonIcnIs xii i
AGP Driving Value 163
AGP last Wr ite 164
AGP ISA Aliasing 164
AGP Master 1WS Pead 163
AGP Master 1WS Wr ite 166
AGP Pretetch 166
AGP Secondary Iat 1imer 167
AGP Spread Spectrum 168
AGP to DPAM Pretetch 169
AGPCIK CPLCIK 169
Anti-Virus Protection 170
APIC lunction 170
Assign IPQ lor LSB 171
Assign IPQ lor VGA 171
A1 Bus Cl ock 172
A1A100PAID IDL Controller 173
Athlon 4 SSLD Instr uction 174
Auto Detect DIMMPCI Cl k 173
Auto 1urn Ott PCI Clock Pin 173
B 176
Boot Other Device 176
Boot Sequence 176
Boot Sequence LX1 Means 177
Boot 1o OS2 177
Boot Lp lloppy Seek 178
Boot Lp NumIock Status 178
Byte Merge 178
C 180
Clock 1hrottle 180
Compatibl e lPL OPCODL 181
CPL Dr ive Strength 181
CPL last String 182
CPL Hyper-1hreading 182
CPL I2 Cache LCC Checking 184
CPL 1hermal-1hrottling 187
CPL to PCI Post Write 188
CPL to PCI Wr ite Butter 189
CPL VCore Voltage 189
D 191
DBI Output tor AGP 1rans. 191
Delay DPAM Pead Iatch 191
Delay IDL Initial 192
Delay Prior 1o 1hermal 193
Delayed 1ransaction 194
Disable Lnused PCI Clock 193
DPAM Act to PreChrg CMD 193
DPAM Burst Iength 8QW 196
DPAM Data Integrity Mode 197
xiv LonIcnIs
DPAM Idl e 1imer 198
DPAM Interleave 1ime 200
DPAM PreChrg to Act CMD 200
DPAM Patio (CPL:DPAM, 201
DPAM Patio HW Strap 202
DPAM Pead Iatch Delay 202
DPAM Petresh Pate 203
Duplex Sel ect 204
L 203
LCP Mode Lse DMA 203
LPP Mode Sel ect 203
l 207
last P-W 1ur n Around 207
last Write to Pead 1urnaround 207
lirst Boot Device 208
llash BIOS Protection 208
lloppy 3 Mode Support 209
lloppy Disk Access Control 209
lorce 4-Way Interleave 210
lorce Lpdate LSCD 210
lPL OPCODL Compatible Mode 211
lSB Spread Spectrum 212
lull Screen Iogo 212
G 213
Gate A20 Option 213
Graphic Win Size 213
Graphic Windov WP Combin 214
Graphics Aperture Size 214
H 216
Hardvare Peset Protect 216
HDD S.M.A.P.1. Capabil ity 216
Host Bus In-Order Queue Depth 217
Hyper-1hreading 1echnology 218
I 220
IDL Bus Master Support 220
IDL HDD Block Mode 220
Init Display lirst 221
In-Order Queue Depth 222
Interr upt Mode 223
IOQD 224
ISA 14.318MHz Clock 223
ISA Lnable Bit 223
K 228
K7 CIK_C1I Select 228
KBC Input Clock Select 229
Keyboard Auto-Pepeat Delay 230
Keyboard Auto-Pepeat Pate 230
I 231
I3 Cache 231
Ievel 2 Cache Iatency 232
LonIcnIs xv
M 233
Master Dr ive PIO Mode 233
Master Dr ive LltraDMA 234
Master Priority Potation 233
MD Dr iving Strength 236
Memory Hole At 13M-16M 236
MP Capabl e Bit Identity 237
MPS Control Version lor OS 239
MPS Pevision 239
Multi-Sector 1ransters 240
N 241
NB Strap CPL As 241
No Mask ot SBA lL 241
O 243
Onboard lDC Svap A 8 B 243
Onboard lDD Controller 243
Onboard IP lunction 243
Onboard Parallel Port 243
Onboard LSB Controller 246
OS2 Onboard Memory ~ 64M 247
OS Select lor DPAM ~ 64MB 248
P 249
P2CC2P Concurrency 249
Parallel Port Mode 249
Passive Pelease 230
PCI42 Access 41 Petry 231
PCI 2.1 Compliance 231
PCI Chaining 232
PCI Clock CPL lSB Clock 233
PCI Delay 1ransaction 234
PCI Dynamic Bursting 233
PCI IDL Busmaster 236
PCI IPQ Activated By 237
PCI Iatency 1imer 237
PCI Master 0 WS Pead 238
PCI Master 0 WS Write 238
PCI Master Pead Caching 239
PCI Pipelining 239
PCI Pretetch 260
PCI 1arget Iatency 260
PCI to DPAM Pretetch 261
PCIVGA Palette Snoop 261
PIO Mode 262
PIPQ x Lse IPQ No. 262
PNP OS Installed 264
Post Write Combine 266
xvi LonIcnIs
Pover On lunction 267
Primary Graphics Adapter 267
Primary VGA BIOS 268
Processor Number leature 269
PS2 Mouse lunction Control 269
Q 270
Quick Boot 270
Quick Pover On Sel t 1est 270
P 271
Pank Interleave 271
Pead-Around-Wr ite 271
Pead Wait State 272
Petresh Inter val 272
Petresh Mode Select 273
Peport No lDD lor Win93 274
Peset Contguration Data 273
Pesource Controll ed By 273
PxD,1xD Active 276
S 277
S2K Bus Dr iving Strength 277
S2K Strobe N Control 277
S2K Strobe P Control 278
SDPAM 11 Command 278
SDPAM 11 Command Control 279
SDPAM Active to Precharge Delay 280
SDPAM Bank Interleave 281
SDPAM Burst Ien 283
SDPAM Burst Iength 284
SDPAM CAS Iatency 1ime 283
SDPAM Command Ieadott 1ime 283
SDPAM Command Pate 286
SDPAM Cycle Iength 287
SDPAM Cycle 1ime 1ras1rc 288
SDPAM LCC Setting 288
SDPAM Idle Iimit 289
SDPAM Ieadott Command 291
SDPAM Page Closing Policy 291
SDPAM Page Hit Iimit 292
SDPAM PH Iimit 293
SDPAM Precharge Control 293
SDPAM PAS Precharge Del ay 294
SDPAM PAS Precharge 1ime 293
SDPAM PAS Pul se Width 293
SDPAM PAS-to-CAS Delay 296
SDPAM Pov Active 1ime 297
SDPAM Pov Cycle 1ime 297
SDPAM 1ras 1iming Value 298
SDPAM 1rc 1iming Value 298
SDPAM 1rcd 1iming Value 299
LonIcnIs xvi i
SDPAM 1r p 1iming Val ue 300
SDPAM 1r rd 1iming Value 300
SDPAM Wr ite Pecover y 1ime 301
SDPAM Wr ite to Pead Command Delay 301
Second Boot Device 302
Security Setup 302
Shadoving Address Panges 303
Share Memory Size 303
Slave Drive PIO Mode 304
Slave Drive Ll traDMA 303
Speed Lrror Hol d 306
Split Iock Operations 306
Spread Spectrum 307
Super Bypass Mode 308
Super Bypass Wait State 308
SuperStability Mode 309
Svap lloppy Drive 310
Synchronous Mode Select 310
System BIOS Cacheable 311
1 312
1hird Boot Device 312
1X, PX Inverting Lnabl e 312
1ypematic Pate 312
1ypematic Pate Delay 313
1ypematic Pate Setting 313
L 314
Lltra DMA Mode 314
LltraDMA-66 IDL Control ler 316
LSB Controller 317
LSB Keyboard Suppor t 317
LSB Mouse Support 318
LSWC Wr ite Posting 318
V 320
Video BIOS Cacheable 320
Video BIOS Shadoving 321
Video Memory Cache Mode 322
Video PAM Cacheable 323
Virus Warning 324
VIink 8X Support 323
W 326
Watchdog 1imer 326
Write Data In to Pead Delay 326
Write Pecovery 1ime 327
Acronyn List 329
Inde 33S
About the Author 347
About Adrian's Rojak Pot 349
About the BIOS Optinization Guide 3S1
xviii LonIcnIs
Acknovledgnents
Iike every nev author, I started this project vith the idea that all I needed to do vas vrite the
guide on BIOS options. It vould be a cakevalkor so I thought. Lntortunately, vriting a
book is really a lot more complex than it seems.
As I vorked vith my editor on the book, I tound myselt adding more and more material.
Lnlike the online version ot the BIOS Optimization Guide, this book covers everything about
the BIOS.1his book is the truly complete BIOS Optimization Guide.
Lntortunately, because ot my busy schedule, the development ot this book has taken almost a
year longer than ve planned tor. A thousand apologies to everyone, including my exasperated
editor'
Nov, I vould like to thank my parents (as e:erone shouio:, and my girltriend, enny, tor believ-
ing in my abilities and supporting me all the vay through. Although they never understood
vhy anyone vould vant to optimize the BIOS, I couldn`t have done all this vithout them'
I vould also like to thank the individuals vho made signitcant contributions to this exhausting
projectmy editor, Bernard Goodvin, Iance Ieventhal and im Markham at Prentice Hall, and
ot course, my pal, Chan o Wee'
Bernard, it you did not persist and guide this nev vriter through the pittalls ot vriting a book,
it vouldn`t have become a reality.1hank you'
A big thank you also goes to both Iance and im tor commenting on my vork.You really
helped me raise the standard ot this book.1hank you'
I vould also like to thank my pal, o Wee, tor helping me handle the mundane aspects ot this
project. He vas invaluable in alloving me to concentrate on vriting the book instead ot getting
bogged dovn in clerical vork.You are a savior, o Wee'
linally, I vould like to thank my buddies and core members ot 1eam APPKen Ng and Chai
Ser Ioon tor helping me vith Adrian`s Pojak Pot vhile I tnished the book.1his book is as
much a tribute to 1eam APP as it is to everyone else vho contributed to the book.1hank you,
guys'
Forevord
Preakin lhrouh the PI: Parrier.lhe Defniti:e PI: ptimi:ation uioe for ICs is absolutely
the best guide ot its kind.
Pecent advances in technology have turned the user-triendly BIOS ot the past into an engi-
neer`s maze ot jargon and techno-babble. Most descriptions ot BIOS settings trom motherboard
manutacturer`s manuals give little more than a list ot the available settings options. A description
ot the settings and an indication ot hov to set timings are virtually nonexistent.
Preakin lhrouh the PI: Parrier solves all that by providing easy-to-understand, layman`s
descriptions tor all ot the latest BIOS settings.
Combining these descriptions vith real-vorld reasons tor choosing certain options makes the
guide an invaluable resource to any computer tveaker or enthusiast. lor the advanced user
and the curious, the book is tull ot technical intormation that delves deeply into the mysterious
and uncharted vaters ot the modern BIOS setup.
Memory timings are an extremely important part ot pertormance and stability in today`s high-
end computers. At Mushkin, Adrian Wong`s online BIOS Optimization Guide
(http:vvv.rojakpot.combog.aspx, has helped us give accurate, bleeding-edge sugges tions to
our customers to increase pertormance and stability. It has been an indispensable tool tor our
technical personnel to use in P8D and troubleshooting.
Kudos to Adrian Wong'
Levis Keller
1echnical Services Manager,
Mushkin Lnhanced Memory Systems, Inc.
http:vvv.mushkin.com
Introduction
What Is the BIOS
Welcome to the tirst edition ot Preakin lhrouh the PI: Parrier.lhe Definiti:e PI:
ptimi:ation uioe for ICs.
Most people never think about vhat actually goes on vhen using a computer.1o many, a com-
puter simply reacts to a series ot keyboard entries and clicks. Whatever the computer is com-
manded to do, it just does. No questions asked.
In reality, it isn`t as simple as that. Behind the tacade ot the user-triendly graphical user intertace,
many things have to be done by the system tor a command to be carried out.
Lnter the BIOS, vhich is short tor Basic Input/Output Systen.
By detinition, it is the intertace betveen sottvare and hardvare that allovs them both to com-
municate and interact vith each other.While you may think that the BIOS only exists in the
torm ot the motherboard BIOS, it is actually the combination ot the motherboard BIOS, the
BIOS ot all add-on cards in the system, as vell as their device drivers.
In the early days ot personal computing, the BIOS vas ott-limits to the user. Access vas restrict-
ed to only a tev basic tunctions , just enough tor the system assembler to get the computer run-
ning. Knovledge about the BIOS at that time vas nothing short ot arcane.
Yet today, the situation is not much better.Yes, motherboard manutacturers are alloving a lot
more access to the various BIOS options. 1his gives us more tlexibility in setting up and opti-
mizing the computer. Hovever, little has been done about educating the user about vhat each
BIOS option actually does.
1ake a look at the BIOS section ot any motherboard manual. It vould be very surprising it you
manage to extract anything usetul out ot the terse, cryptic explanations. Hov is anyone expect-
ed to optimize the BIOS vhen no one knovs vhat each BIOS option does
I started vriting this BIOS guide back in 1999 as a simple online guide on hov to optimize the
BIOS. 1oday, it not only covers BIOS optimization, it has also become a comprehensive guide
on over 230 BIOS options.
1his book not only teaches you hov to optimize each BIOS option, you also learn vhat each
BIOS option does and the reason behind each recommended setting. In the end, you vill be
able to optimize the BIOS like a protessional'
Book Objoctivos
Preakin lhrouh the PI: Parrier vas vritten vith several key objectives in mind.
It vas primarily vritten to help the reader optimize the BIOS. Lntortunately, BIOS optimiza-
tion isn`t a clear-cut problem that can be solved by simply tolloving some tixed guidelines.
Although many simple guidelines and recommendations are covered in this book, hardvare and
sottvare contigurations vary trom computer to computer. 1heretore, it is important that the
reader understands vhat each BIOS option does so that he or she can make the best decision
tor the computer in question.
1o that end, this book not only helps you optimize the BIOS vith many guidelines and recom-
mendations, it also helps you understand vhat each BIOS option does, so you can make the
necessary adjustments tor your sys tem.
1his book aims to dispel the misintormation about many BIOS options that have been propa-
gated by both media and manutacturers alike. lor too many years nov, motherboard manuals
and various computer books have been spreading inaccurate intormation and recommendations
on many BIOS options. It`s time to change that tor good'
1his book also discusses basic topics about the BIOS to provide a solid toundation on the BIOS
and hov to keep it updated as vell as access its setup menu.
When you tinis h reading this book, you vill have all the necessary knovledge you need to tully
optimize the BIOS ot your computer'
Who Is lhis Book Ior?
1his book is tor those (novice or advanced, vho are interested in optimizing the BIOS tor per-
tormance and stability.
You vill learn vhat the BIOS is, the ditterent types ot BIOS, hov to access your BIOS, and
hov to update it.You also vill learn vhat each BIOS option does and vhat you should set tor
optimal pertormance and stability.
1his book also teaches you about BIOS emergencies like an unbootable computer or a cor-
rupted BIOS. What should you do Hov can you correct the problem 1his book covers all
that, including a look at the hot tlash method.
lor the novice, Chapters 1 and 2 are just vhat you need. It you are tamiliar vith computers and
vant to understand vhat each BIOS option really does, turn to Chapters 3 and 4.
Choptor Brookdown
Preakin lhrouh the PI: Parrier is really tvo books in one. Chapters 1 and 2 provide a solid
toundation ot BIOS basics and special topics in a narrative tashion, vhile Chapters 3 and 4 are
presented in a more structured manner tor easy reterence. Here, you not only learn everything
about each BIOS option, you also learn the logic behind each optimization.
InIroducIon WhaI Is Ihc 8I0S? 2
LhapIcr 8rcakdown 8
Choptor 1: BIOS Bosics
Chapter 1 serves as an introduction to the BIOS. It deals vith basic topics on the BIOS. In this
chapter, you learn vhat the BIOS really is, hov it vorks, hov to keep it updated, and hov to
access it.
Choptor 2: Spociol lopics
Chapter 2 deals vith special topics like BIOS emergencies and hot tlashing. It you ever run into
trouble vith the BIOS, head straight tor this chapter. It can help you restore your BIOS.
Choptor 3: Quick Roviows
Chapter 3 otters a simplitied explanation ot each BIOS option as vell as its recommended
settings . llip to this chapter it you need a quick overviev ot a BIOS option and its optimal
settings .1his is targeted at those vith little hardvare knovledge.
Choptor 4: Dotoilod Doscriptions
Chapter 4 deals vith each BIOS option in much greater detail. It you already have a moderate
level ot hardvare knovledge, this section allovs you to achieve a greater understanding ot the
various BIOS options and the logic behind their recommended settings.
Please note that certain BIOS options may appear similar in both the uick Pe:ieus and Detaii eo
Descriptions sections.
Acronyn List
lolloving Chapter 4, you vill tind a complete alphabetical list ot acronyms used throughout the
book. Peter to this list it you vant to quickly see an acronym spelled out.
Cotogory Lookup loblo
Printed on the inside tront and back covers ot this book is the Category Iookup 1able. 1he
BIOS teatures have been arranged according to ditterent sub systems so that you can easily
search tor the BIOS teature ot your choice. It the BIOS teature you are interested is not listed
vithin the book (because it has a ditterent name,, you can try checking the Category Iookup
1able tor a similar BIOS teature.
Chapter 1
What Is the BIOS
1he BIOS is short tor Basic Input/Output Systen. By detinition, it is the intertace betveen
sottvare and hardvare that allovs s ottvare and hardvare to communicate and interact vith
each other.
1he BIOS is made up ot everything that allovs sottvare and hardvare to interact vith each
other. While you may think that the BIOS only exists in the torm ot the motherboard BIOS, it
is actually the combination ot the motherboard BIOS, the BIOS ot all add-on cards in the sys-
tem, as vell as their device drivers.
How Doos tho BIOS Work?
Most people never think about vhat actually goes on vhen they do something on the comput-
er.1o most people, vhenever they command the computer to do something, it just does it. No
questions asked.
It isn`t as simple as that. Behind the tacade ot the user-triendly GUI (Graphical User
Interface,, many things have to be done by the system tor the
command to be carried out.
Iet`s visualize the computer system as three separate layers that
communicate vith each other through ditterent intertaces. 1he
diagram to the right is ot that layered division:
In our layered system, the application is the highest level. It
cannot directly interact vith the hardvare. It can only com-
municate vith the operating system through the API or
Application Progran Interface.
1he API is a set ot common tunctions that the application calls
upon to get the operating system to do vhat it vants. Because
the API is operating system-specitic, it ditters trom operating
system to operating system.
Hovever, irrespective ot the operating system, the API allovs
the application to get the job done vithout knoving hov the
operating system does it. 1he application doesn`t need to knov
anything about the computer`s hardvare.
1he operating system then communicates to the BIOS vhat it
needs to carry out the application`s request.1he operating sys-
tem never communicates directly vith the hardvare.
lhe oifferent i aers ano interfaces.
1he BIOS layer allovs the operating system to support all manners ot hardvare. Lach piece ot
hardvare comes vith its ovn BIOS andor driver, vhich become part ot the system`s BIOS.
1heretore, the BIOS layer is dynamic and changes to match the computer`s hardvare contigura-
tion. It serves to mask the ditterences betveen ditterent hardvare by presenting a common
intertace to the operating system.
1he operating system only needs to knov hov to communicate vith the BIOS layer. It is up to
the BIOS layer to translate the operating system commands into action by the hardvare.
Without the BIOS layer, there`s no vay the operating system can access the hardvare layer.1he
BIOS layer is the operating system`s key to the hardvare layer.1hat`s hov important the BIOS
layer is in the computer system.
lho Mothorboord BIOS
Although, by detinition, the BIOS consists ot the motherboard BIOS, the BIOS ot all add-on
cards in the system, as vell as their drivers , ve vill be concentrating on the motherboard BIOS
in this book.
1he motherboard BIOS is the most important component ot the BIOS layer. 1his is because it
contains all the sottvare needed to get the computer started. It also comes vith basic diagnostics
and contiguration utilities.
lho BIOS Chip
1he motherboard BIOS is stored in a chip on the motherboard.1he BIOS chip normally
comes in the torm ot a rectangular DIP (Dual In-line Package) or a square PLCC (Plastic
Leaded Chip Carrier, package.
1he capacity ot BIOS chips is
measured in Megabits (Mb,.
Most BIOS chips these days are
2Mb (236KB, in size.1hese
higher capacity chips allov the
manutacturer to otter more tea-
tures than is possible vith the
smaller 1Mb chips.
Hovever, please note that the
size ot the BIOS chip has noth-
ing to do vith its pertormance.
1he choice ot type and size ot
the BIOS chip is a matter ot
economics and requirements,
rather than pertormance.
LhapIcr 1 WhaI Is Ihc 8I0S?
ILCCtpe PI: chips.
(Ihoto | author.)
Why 0pImzc Ihc 8I0S? 7
Whot Doos It Do?
Here is a breakdovn ot vhat the motherboard BIOS actually consists ot:
Pover-on diagnostic tests
System contiguration utility
Bootstrap loader
BIOS intertace
When you boot up the computer, it initiates the POS1 (Pover-On Diagnostic 1est).
1he POS1 serves as a quick-and-dirty vay to make sure that all the critical components are
tunctioning.
Atter the POS1 sequence completes, you are given the opportunity to access the system contig-
uration utility. 1his utility allovs you to contigure and modity a range ot teatures.1hese BIOS
teatures shov you just hov important the BIOS is.
1hese BIOS teatures control every aspect ot the computer, trom the speed at vhich the proces-
sor runs to the transter mode ot the hard disk. It goes vithout saying that thes e BIOS teatures
are the reason vhy I`m vriting this book. We go into details later in Chapter 4.
Atter the short delay, the BIOS starts the bootstrap loader routine, vhich scans tor a valid master
boot sector on all available drives. 1his can be anything trom a hard disk to a CD-POM drive.
1he master boot sector is just a predetermined area containing code that initiates the loading ot
the operating system.
When executed, the master boot sector turns over the booting process to the operating system
by loading the operating system`s boot sector.1he operating system then starts loading up its
core tiles.
In most cases, this is vhere the BIOS` role ends because current operating systems employ their
ovn 32-bit or 64-bit drivers, vhich otter tar superior tunctionality and pertormance to the
BIOS` basic drivers. Hovever, the BIOS` core drivers still have some importance.
Lven modern operating systems like Microsott Windovs still need to use the BIOS` basic driv-
ers, albeit only in their troubleshooting or sate modes. 1his is because the core BIOS drivers
have been standardized a long time ago, and every piece ot hardvare made since then is
backvard-compatible vith them.
While these core BIOS drivers may be slov and primitive, they are guaranteed to vork vith
any hardvare designed tor the PC. 1hat`s vhy they are still an integral part ot every PC.
Why Optinizo tho BIOS?
Although the BIOS only tunctions trom the time you press the Pover On button until the
operating system takes over, its ettects last as long as the computer is operational.Whatever you
set in the BIOS greatly determines your computing experience.
It the BIOS is not contigured properly, you may be able to boot up the operating system and
run it tor a vhile. Hovever, the system vill become unstable and eventually crash.1his vill go
on and on, ad nauseum.
You may send it back to your computer dealer and, more likely than not, the technician vill
simply reset the BIOS to its tail-sate settings and send it back to you. Hovever, is that the bes t
solution
Most detinitely not' An unoptimized BIOS means an unoptimized system. Not only vill it take
longer to boot up or initialize devices, it vill also slov dovn the entire computer. It`s like knee-
capping s omeone betore sending him out to do the long jump'
BIOS optimization is critical not only to the optimal pertormance ot the computer, but also to
the proper tunctioning ot the system`s components. Computers these days are made up ot a
hodge-podge ot ditterent components trom ditterent manutacturers. 1his presents a real problem
vhen it comes to getting them all to vork together.
Because ot the variety ot components that make up any one computer, it is impossible tor man-
utacturers to optimize their motherboards tor any particular contiguration. 1hat`s vhy all moth-
erboards come vith contigurable BIOS.
1he BIOS allovs the OLM (Original Lquipment Manutacturer,, as vell as the end-user,
to modity settings and timings to support ditterent contigurations.Without them, manutact-
urers vould be torced to use the most conservative settings, vhich vould greatly degrade
pertormance.
How Do I Optinizo tho BIOS?
1he key to optimizing the BIOS lies in its built-in system contiguration utility. As mentioned
earlier, this is vhere you can contigure or modity a variety ot BIOS teatures and options.
1hese BIOS teatures shov you just hov important the BIOS is.1hey control every aspect ot
the computer, trom the speed at vhich the processor runs to the transter mode ot the hard disk.
1his book teaches you hov to optimize your BIOS tor proper operation and maximum per-
tormance. Iet`s turn that snail into a road hog'
BIOS Updotos
lirst ot all, you should knov that the BIOS that ships vith your motherboard is not necessarily
the latest version or the most stable version. Peputable motherboard manutacturers constantly
improve on their motherboard BIOS and regularly release BIOS updates.
1hese BIOS updates are important because they correct bugs and sometimes provide additional
capabilities.You can think ot them as driver updates or sottvare patches.You should alvays keep
the motherboard BIOS up to date.
In the tolloving tigure, you can see the list ot changes in tvo BIOS updates tor the ABI1 Nl7-S
motherboard.
LhapIcr 1 WhaI Is Ihc 8I0S? 8
How Do I Updoto tho BIOS?
1he process ot updating the BIOS can be summarized in the tolloving steps:
1. Determine your BIOS version.
2. Obtain the appropriate BIOS update.
3. Prepare a BIOS tlash disk.
4. llash the motherboard BIOS.
Nov let`s go through the process step by step.
NoIc
!he lern fl ash or flashng is used lo describe lhe acl of udalinq lhe 8l0S.
Dotornining tho BIOS Vorsion
Betore you update your BIOS, it`s best to tind out vhat version ot BIOS you are currently
using. It you already have the latest version, then there`s no point in going through the process.
1he display ot the BIOS version number or ID varies trom manutacturer to manutacturer.
As you can see, the bug tixes and teature enhancements are both numerous and important. It
really pays to keep your BIOS updated'
8I0S updaIcs 0
Detaiis of PI: upoates for the PIl Î7: mother|oaro.
(Courtes of PIl Computer Corporation. seo uith permission.)
Hovever, it is most commonly the last tvo or tour digits or letters at the end ot the string that
appears vhen you boot up the computer.
Determinin the PI: ID.
Your motherboard manutacturer may use numbers or letters to represent the BIOS version or
ID.1he tolloving is an example ot the BIOS version or ID.
Because this string only appears tor a tev s econds vhen you start up the computer, you might
vant to turn on your monitor a tev seconds betore you start up your computer because some
monitors take some time to initialize.
You can also use the Pause key to treeze the screen so that you can s earch tor and identity the
BIOS ID. Pressing any key atter that vill untreeze the screen and allov the booting process
to continue.
In the preceding example, the BIOS ID is a tvo-digit number (00,. Other motherboards may
use tour digits or even letters instead ot digits. Some even use a mix ot letters and digits.
It the BIOS ID does not appear as it does in the example, please check the manual that came
vith your motherboard.Your motherboard manutacturer may have chosen to shov the BIOS
ID somevhere else.
Obtoining tho BIOS Updoto
Nov that you knov your BIOS ID, it`s time to check vhether your motherboard manutacturer
has a BIOS update tor you.
BIOS updates are best obtained directly trom the manutacturer`s vebsite instead ot other distri-
bution points like hardvare sites and unotticial mirrors.1his ensures that you have the very lat-
est BIOS update available and reduces the risk ot dovnloading a virus-intected copy.
So, head over to your motherboard manutacturer`s vebsite. 1he BIOS updates are usually listed
in the Dovnloads or Support section ot the vebsite.
Please note that vhile ditterent motherboard models may appear to have the same BIOS ID,
you mus t dovnload only the BIOS that vas specitically meant tor your motherboard. llashing
a BIOS update that vas meant tor another motherboard vill likely cause your motherboard
to tail.
Atter you have tound the page
listing the BIOS updates tor your
motherboard, there may be a long
list ot BIOS updates. lor example,
the adjacent tigure shovs a tev ot
the BIOS updates tor the ABI1
K17A-PAID-motherboard.
Although the number ot BIOS
updates may be contusing, don`t
vorry' You don`t have to dovn-
load and tlash all ot them. All you
need to do is dovnload and tlash
the i atest version.
Hovever, you must tirst deter-
mine vhether there is an update
tor your BIOS. Pemember the
BIOS ID Compare it against the
list ot BIOS IDs.
Irrespective ot hov the BIOS ID
appears, motherboard manutactur-
ers alvays progressively label
BIOS updates.
It your BIOS ID is a number,
larger numbers alvays denote
a never BIOS. lor example, a
BIOS vith an ID ot 01 is never
than a BIOS vith an ID ot 00
but older than a BIOS vith an ID
ot 02.
It the BIOS ID is made up ot
letters, letters lover in alphabet-
ical order alvays denote a
never BIOS. lor example, a BIOS vith an ID ot AB is never than a BIOS vith an ID ot AA
but older than a BIOS vith an ID ot AC.
1he same goes even it your BIOS ID is a mix ot letters and numbers, just like in the preceding
K17A-PAID example.
8I0S updaIcs 11
List of PI: upoates f or the PIl Kl7PID mother|oaro.
It your BIOS ID is the latest BIOS ID, then there`s no need to proceed turther vith the BIOS
tlash.You already have the latest version. ust make sure you check back once in a vhile.
It there`s a never BIOS ID than your current BIOS ID, dovnload the nev BIOS image. It usu-
ally comes prepackaged vith the tlash utility in the torm ot a compressed ZIP tile or a selt-
extracting compressed tile.
Proporing o BIOS Ilosh Disk
Nov that you have the compressed tile containing the BIOS update, it`s time to prepare a clean
DOS boot disk.1his is because most tlash utilities require the use ot real mode DOS.Also, to
prevent contlicts, nothing other than the necessary boot tiles
should be loaded into this boot disk.
You can easily create a clean boot disk in Windovs. Lven
Windovs XP, vhich does not support DOS, comes vith a utili-
ty that allovs you to create your ovn DOS boot disk. ust
remember to use a reliable tloppy disk.A detective disk may
cause the BIOS update to be corrupted.
In Windovs XP, all you need to do is bring up the tloppy tor-
mat utility. ust right-click on your tloppy drive in Windovs
Lxplorer and click on Fornat.1he lormat 3
1
2 screen appears.
Among the tormat options, there is an option called Create an
MS-DOS startup disk. Check this option and click Start to
tormat the tloppy disk. Windovs XP vill then tormat your
tloppy disk, make it bootable and copy all the necessary tiles tor
it to boot up into real mode DOS.
Atter you have a clean DOS boot disk, all you need to do is
extract the BIOS update tile and the tlash utility and copy them
into the boot disk.
1he BIOS update tile or image usually has a .|in extension.
Some come vith a .rom extension. Hovever, they are all the
same, they are just BIOS image tiles.Write dovn the name ot the
BIOS image tile. It vill come in handy later.
Iloshing tho Mothorboord BIOS
1here are actually a tev vays you can tlash your BIOS.1he traditional vay is by a DOS boot
disk. Hovever these days, manutacturers are implementing never methods.
lor example, many BIOS nov come vith their ovn tlash utility. Some manutacturers even pro-
vide you vith a utility that allovs you to tlash the BIOS online'
lor simplicity`s sake, ve vill only touch on the common DOS tlashing method using the
Avardllash sottvare.
1he Avardllash sottvare is probably the most common tlas h utility around. It is used to tlash
the BIOS ot motherboards using the AvardBIOS. Please note that the Avardllash utility is
DOS-based. It cannot be used in a Windovs-based environment.You must boot up using a
DOS boot disk betore using this utility.
Creatin a |oot oisk in
1inoous XI.
As you can see, the utility is quite versatile. It provides numerous options. Ot course, most ot
them are not necessary tor our use. 1he manutacturer ot our reterence motherboard, ABI1,
recommends the tolloving parameters:
A:(>aWdfJash b1os.b1n 1cc 1cd 1cp 1py 1sn 1cks 1r
1his essentially tells the Avardllash utility to do the tolloving:
1. Skip back up ot original BIOS image.
2. Shov the bios.bin BIOS image tile`s checksum.
3. Program the llash BIOS vith the bios.bin BIOS image tile.
4. Clear CMOS data atter programming the llash BIOS.
S. Clear DMI data atter programming the llash BIOS.
6. Clear PnP (LSCD, data atter programming the llash BIOS.
7. Automatically reset the computer atter programming is complete.
Please consult your motherboard manutacturer tor its recommended parameters. Ditterent man-
utacturers may recommend ditterent parameters even it they are all using the same Avardllash
utility.
It you run this command atter booting up in DOS, the Avardllash utility automatically updates
the motherboard`s llash BIOS vith the nev BIOS image and clears the CMOS, DMI, and
LSCD data betore resetting the computer tor the changes to take ettect.
Atter the computer is rebooted, the nev BIOS takes ettect. Pemember, because the CMOS
data has been cleared during the tlash process, the BIOS reverts to detault settings.You should
access the BIOS setup utility to set up the various parameters as vell as optimize it.
8I0S updaIcs 18
uaroIiash utiiit commanos..
1he tolloving is a screen capture ot the available commands ot the 8.23K version ot the
Avardllash utility:
Accossing tho BIOS Sotup Utility
1he BIOS setup utility is only available tor a tev short seconds vhen you boot up your com-
puter. It your operating system has already loaded up, you must reboot your computer betore
you can access the BIOS setup utility.
In motherboards using the AvardBIOS, the BIOS tlashes the tolloving message tor a tev sec-
onds during the booting up process:
Press Del 1o Lnter Setup
When you see that message, quickly press the Del (Delete, key.1his halts the booting process
and brings up the BIOS setup menu.
Please note that not all BIOS sottvare use the Del key tor access to the setup menu. Ditterent
BIOS vendors have ditterent trigger keys. Alternatives to the Del key include:
Lsc (Lscape, key
F2 key
Ctrl-Alt-Lsc key combination
Please consult your motherboard manual on the trigger key tor your motherboard`s BIOS setup
utility.
lho BIOS Sotup Utility
1he BIOS setup utility varies trom motherboard to motherboard. Some have a graphical
appearance vhile others have a simple menu system. 1he most common is the basic menu sys-
tem.1he top tigure on the opposite page is an example ot that menu system.
1his is vhat greets you vhen you press the trigger key to access the BIOS setup utility. As you
can see, the screen consists ot nothing more than a list ot available sub-menus on the lett and
some commands on the right.
1he keyboard`s cursor keys are used to navigate this menu system. Pressing the Lnter key per-
torms actions like opening up a sub-menu or activating one ot the commands on the lett menu.
Open up a sub-menu and the bottom tigure on the opposite page is vhat you may see.
1his sub-menu (Advanced Chipset Features, displays a list ot available BIOS options or tea-
tures.You can brovse through the list using the cursor keys.
1he values ot those BIOS options can be moditied using the (plus, or (minus, key in this
BIOS. In other BIOS, you may use the Page Up and Page Dovn keys instead.
Optinizing tho BIOS
1his brings us to the crux ot this book. Optimizing the BIOS is vhat this book is all about.
Chapters 3 and 4 concentrate entirely on the numerous BIOS options you may encounter in
your motherboard`s BIOS setup utility.
0pImzng Ihc 8I0S
lhe PIl :I7 PI: setup utiiit.
su|menu in the PIl :I7 PI: setup utiiit.
Chapters 3 and 4 otter tvo ditterent levels ot detail. Chapter 3 otters a quick guide to the vari-
ous BIOS options and optimization recommendations. Chapter 4, on the other hand, delves
into each BIOS option vith much greater detail.
I hope you enjoy reading about the ditterent BIOS options as much as I enjoyed researching
and vriting about them.
But betore you head over to those chapters, be sure to read Chapter 2, vhich teaches you hov
to get out ot trouble vhen something goes vrong during the optimization process. Pemember
to tlip to Chapter 2 it you ever run into trouble'
Nov, let`s go optimize your BIOS'
Chapter 2
Special 1opics
BIOS Lnorgoncios
Although this book vill help you optimize the BIOS, it cannot tell you just hov tar you should
push your system. 1here are just too many possible permutations ot hardvare contigurations to
cover in this or any other book, tor that matter.
It you are particularly adventurous, you vill become very tamiliar vith system crashes, sponta-
neous reboots, or an unresponsive system. Ot course, rebooting the system and undoing the
changes can correct all that.
Hovever, occasionally, you may come tace to tace vith emergencies like an unbootable com-
puter or, even vorse, a BIOS corruption' With such problems, the system is completely dead
and you cannot access the BIOS.
Iuckily, ve have solutions tor these problems. Iet`s take a look'
Unbootoblo Syston
1his otten happens vhen you set an excessively high clock speed vhile overclocking your
processor or memory. It can also happen vhen you set certain BIOS options incorrectly.
In these cases, your system becomes completely unresponsive.When you pover it up, it retuses
to boot. Because the computer cannot be booted up, you cannot access the BIOS menu and
correct the mistakes you made.
lortunately, all you need to do is reset the BIOS. We cover tour ditterent methods here, in the
order ot simplicity.
Powor OII-Powor On
Certain motherboards have a built-in mechanism that protects the computer trom being ren-
dered unbootable due to incorrect BIOS settings.
In such motherboards, the BIOS automatically boots up using its detault settings atter several
tailures to boot.1his allovs you to access the BIOS and correct the BIOS settings.
You should check your motherboard manual to see vhether your motherboard supports such a
teature. Not all motherboards come vith this teature.
It your motherboard supports this teature, all you need to do is pover ott your computer and
pover it on again. Sometimes, you need to do this tour or tive times betore the mechanism
kicks in.
Atter the motherboard boots up using its detault settings, you should immediately access the
BIOS and change the incorrect BIOS settings you made earlier.
Royboord Rosot
Some motherboards support the resetting ot the BIOS using a keyboard shortcut.1his allovs
you to reset the BIOS vithout opening your computer`s case.
lor specitic instructions on hov to do this, you should consult your motherboard manual.
Ditterent motherboard manutacturers have ditterent implementations. Hovever, no matter vhat
key or key combination is used, they only vork vhen the computer is booting up.
We vill use the ABI1 Nl7-S motherboard as an example. In this motherboard, the Insert key
is used as the BIOS reset key. Ot course, it only vorks vhen the computer is povered up. Atter
that, the Insert key tunctions normally.
1o reset the BIOS, the system must be povered ott tirst.1hen, vith the Insert key kept
depressed, turn on the computer.1his vill torce the motherboard to boot up vith detault
settings .
Atter the motherboard boots up using its detault settings, you should immediately access the
BIOS and change the incorrect BIOS settings you made earlier.
CMOS Dischorgo junpor
Lvery motherboard comes vith a CMOS discharge jumper. 1his jumper allovs you to dis-
charge the CMOS and reset the BIOS to its detault settings.
1he position ot this jumper varies betveen motherboard models. Please consult your mother-
board manual tor the location ot the CMOS discharge jumper.
lor the purpose ot this discussion, ve use the ABI1 SI7 motherboard as an example. In this
motherboard, the position ot the CMOS discharge jumper is clearly shovn in the opposite
diagram (from the PIl :I7 manuai,.
1he diagram should give you a good idea ot vhere to tind the jumper.
1o discharge the CMOS data, you should tirst pover ott the system. Please note that you should
also turn ott the main pover to the computer.1his cuts ott the 3V standby pover that can
prevent the CMOS trom discharging properly.
Atter ensuring the system is completely turned ott, open up your computer case to gain access
to the motherboard. Iook tor the CMOS discharge jumper as shovn in the manual.
Atter you have located the CMOS discharge jumper, you vill note some markings next to the
header. In this example, the pins ot the header are labeled 1, 2, and 3. By detault, the CMOS
discharge jumper shorts pins 1 and 2, thus alloving normal operation ot the motherboard.
1o tlush the CMOS data in the ABI1 SI7 motherboard, you just need to remove the jumper
and use it to short pins 2 and 3. Ieave the jumper there tor 3 to 10 seconds.1his tlushes the
CMOS data and restores the BIOS to its detault settings.
You should then replace the jumper in its detault position over pins 1 and 2. 1his allovs the
motherboard to boot up normally.
Nov you can close up your computer`s case and pover on the system. Because the CMOS data
has been erased, you should access the BIOS immediately and restore vhatever cus tomized set-
tings you preter.
LhapIcr 2 Spcca| Jopcs 18
CMOS Bottory Ronovol
Lvery motherboard comes vith a small battery, usually a 3V CP2032 battery. 1his battery pro-
vides the pover necessary to keep the CMOS data intact vhen the computer is not povered.
It all other methods tail, removing the CMOS battery vill erase the CMOS data.Atter the
CMOS battery is removed, the CMOS vill lose its data, resetting the BIOS to its detault settings.
1he position ot the CMOS battery varies betveen motherboard models. Pleas e consult your
motherboard manual tor the location ot this battery in your motherboard.
lor the purpose ot this discussion, ve vill use the ABI1 SI7 motherboard as an example. In the
diagram on the opposite page, the position ot the CMOS battery is circled.
Att er you have an idea ot vhere to look tor the CMOS battery, you can proceed.
1. Pover ott the computer.
2. Open up the computer case.
3. Iocate the CMOS battery. Note the tensioned latch holding it in place.
4. Press the latch to release the battery and litt it out.
S. Wait tor 3 to 10 seconds to allov the CMOS to discharge.
6. Peplace the CMOS battery.
7. Close the computer case.
8. Pover on the computer.
Because the CMOS data has been erased, you should access the BIOS immediately and restore
vhatever customized settings you preter.
unhooIah|c SysIcm 10
CM: oischare jumper position, PIl :I7 mother|oaro.
Corruptod BIOS
Although the BIOS resides in a llash POM that protects it trom data loss vhen pover is not
supplied, it is still susceptible to corruption.1he BIOS can be corrupted by a variety ot
mechanismsviruses, incomplete or bad BIOS tlashes, tlashing the vrong BIOS image, bugs
in the BIOS itselt, and so torth.
When such a corruption occurs, the BIOS either behaves abnormally or maltunctions, prevent-
ing the computer trom booting up. As you can see, BIOS corruption is a big problem vhen
it happens.
1o prevent this, some manutacturers actually ship their motherboards vith tvo BIOS chips. In
the event that one BIOS chip gets corrupted tor any reason, the user can easily svitch to the
alternate BIOS and repair the corrupted BIOS chip later by simply tlashing it vith a nev
BIOS image. Lxamples include Gigabyte`s DualBIOS teature (shovn in the picture on the
opposite page, and Albatron`s BIOS Mirror teature. In such motherboards, you can see tvo
BIOS chips side by side.
Hovever, most motherboards do not ship vith tvo BIOS chips. lor such motherboards, BIOS
corruption usually means returning the motherboard to the manutacturer tor repair or replace-
ment. lor the user, this means days to veeks ot computer dovntime.
CM: |atter position, PIl :I7 mother|oaro.
CMOS
battery
1he more tech-savvy user can speed things up by requesting a replacement BIOS chip and
replacing it herselt. Hovever, this is subject to the manutacturer`s villingness to send the
replacement chip.You vill still have to vait a tev days tor the replacement chip to arrive.
A much quicker alternative is to hot flash the corrupted BIOS. Hovever, this technique
requires a moderate level ot technical expertise and some experience vorking vith hardvare
and tlashing the BIOS.
1he tolloving is a short step-by-step guide on hot tlashing tor your reterence. Please note that
this is a dangerous procedure tor the inexperienced. Do not attempt it unless you have experi-
ence vorking vith hardvare and tlashing the BIOS.
Hot Iloshing
No, hot tlashing does not require you to heat up your BIOS nor does it have anything to do
vith heat. And no, it is certainly not related to the hot tlashes that menopausal vomen
experience'
Hot tlashing is basically the same as a plain ane BIOS tlashyou use a BIOS tlash utility to
tlash a BIOS image into the llash POM. Hovever, there is a tvist to it. Hot tlashing requires
you to svap BIOS chips vhile the system is running.1hat`s vhat the vord hotin hot tlashing
meansyou svap the BIOS chip vhile your system is hot.
hoI F|ashng 21
lhe ia|te DuaiPI:.
(Courtes of Dono:an Dennis Laoh. seo uith permission.)
Nov, vhy vould anyone ot s ane mind do that Obviously, messing around vith any hardvare
vhile the system is running is an act that is otten considered incredibly brave or incredibly stu-
pid. Pisk ot electrocution aside, messing vith your hardvare vhile it is running can cause per-
manent damage to your hardvare, not to mention the data in your computer.
Hovever, the benetits ot hot tlashing may outveigh the risks. It your motherboard BIOS chip
becomes corrupted, hot tlashing allovs you to revive the chip by replacing the corrupted BIOS
sottvare vith a nev BIOS image. Pemember, vhen your BIOS becomes corrupted, you can-
not boot up your computer.1heretore, the conventional BIOS tlashing method cannot be used.
It you cannot boot up the computer, you cannot load the BIOS tlash utility.
1his is vhere hot tlashing comes in. Hot tlashing circumvents the booting problem by using
another computer to boot up. 1he corrupted BIOS chip is then transplanted into the computer
(vhile it is still running, and updated vith an uncorrupted BIOS image. 1his revives vhat vas,
tor all intents and purposes, a dead BIOS chip. 1he BIOS chip can then be returned to the
original motherboard to allov the computer to tunction once again.
Ot course, you vill need another system vith a motherboard that supports the same BIOS chip.
Hovever, it you have access to such a computer and are not squeamish about svapping BIOS
chips vhile the computer is running, you can save yourselt a lot ot time and money.
It you cannot hot tlash your corrupted motherboard BIOS, you vill have to send it back to the
manutacturer or buy a replacement BIOS chip. Both alternatives are not particularly desirable
because they cost money and you cannot use your computer until you get a replacement board
or BIOS chip.
Whot Do I Nood to Hot Ilosh o BIOS Chip?
It you vant to hot tlash a corrupted BIOS chip, you vill need the tolloving:
A vorking computer vith a motherboard that uses the same BIOS chip
A suitable tool tor removing BIOS chips
1he corrupted BIOS chip, ot course
A DOS boot disk containing the BIOS tlash utility and the BIOS image tor the corrupted
BIOS chip
You also need to be experienced in tlashing normal BIOS chips. Please do not attempt a hot
tlash unless you have prior experience in tlashing the BIOS.
Okay, nov that you have everything in place, let`s proceed'
Stop 1: Crooto o DOS Boot Disk
Because you are messing around vith the system vhile it is still running, it is advisable to
remove or at least disconnect all hard disks in the system and boot up us ing a DOS boot disk.
So, you need to create a DOS boot disk.
Here is a retresher tor those vho have not created DOS boot disks in a vhile. Here are the
steps to create a DOS boot disk in Windovs XP:
1. Insert a blank tloppy disk into the tloppy drive.
2. Open Windovs Lxplorer and right-click on the 3
1
/2 Floppy (A:) drive.
3. Select the Fornat... option.1he lormat lloppy screen vill pop up.
4. 1ick the Create an MS-DOS startup disk checkbox.
S. Click the Start button and Windovs XP vill create a
DOS boot disk.
Next, you need to copy the BIOS image tile tor the corrupted
BIOS chip as vell as the BIOS tlash utility into the DOS boot
disk.You should get the latest BIOS image tile trom your moth-
erboard manutacturer`s vebsite. BIOS image tiles usually have a
.|in or .rom extension. Note the tilename ot the BIOS image
tile tor tuture reterence.You vill need it later.
Manutacturers usually bundle these BIOS image tiles vith the
appropriate BIOS tlash utility in a compressed ZIP tile tor easy
dovnloading. All you need to do is dovnload the zipped tile
and extract its contents into the DOS boot disk.
Stop 2: Proporo o Hot Ilosh-Copoblo
Conputor
Not all computers can be used tor hot tlashing. lor hot tlashing
purposes, the computer must use the same type ot BIOS chip. BIOS chips come in either the
torm ot a rectangular DIP (Dual In-line Package, or the square PLCC (Plastic Leaded
Chip Carrier, package.1he tolloving are examples ot PICC BIOS chips:
Needless to say, you cannot use a
motherboard vith a DIP BIOS
chip to hot tlash a PICC
BIOS chip.
Please note that every BIOS chip
has a notch on one corner.1hat
notch tells you hov to align the
chip tor proper insertion into the
socket. It is very important to
insert the BIOS chip the right
vay. Inserting it the vrong vay
may damage the BIOS chip as
vell as the motherboard.
Atter you have a system that is
compatible vith your corrupted
BIOS chip, it is highly recom-
mended that you remove or dis-
connect all unnecessary
hardvare, especially the hard
disks. 1his prevents any possibility
ot data loss on the computer that
is doing the hot tlashing.
hoI F|ashng
Creatin a |oot oisk.
ILCCtpe PI: chips.
(Ihoto | author)
Stop 3: Booting Up with tho Boot Disk
Nov, let`s boot up the hot tlash system using the DOS boot disk. Here is a retresher tor those
vho have not done this in a long time:
1. Boot up and access the BIOS setup menu.
2. Set the BIOS to boot up using the tloppy drive. Lsually, this just involves setting the lirst
Boot Device as lloppy.
3. Insert the DOS boot disk into the tloppy drive.
4. Peboot the computer and allov it to boot up using the DOS boot disk.
Stop 4: Swop tho BIOS Chips
1his is the time to svap the BIOS chips.You need to do so vith the s ystem still running.
1he tolloving is a picture ot the good BIOS chip ot the ABI1 Nl7-S, the motherboard I us ed
to do the hot tlash.
I only had tveezers to vork vith, so
removing the BIOS chip vith the
system hot vas rather dicey. lirst, I
removed the BIOS chip vith the sys-
tem povered ott.1hen I seated the
BIOS chip in its socket vith just
enough pressure to keep it in place
|ef ore booting up. 1his alloved me to
remove the BIOS chip vith just a
slight tlick ot a tveezer prong.
It you have a proper BIOS chip
removal tool, you do not need to take
the above precautions, you can just
boot up and remove the BIOS chip.
It you are torced to use a metallic tool
like a tveezer, please remember that
you can cause a short circuit it you are
not caretul. 1o reduce the risk, you can cover the tip ot your
metallic tool vith non-conductive tape like cellophane tape.
Atter the good BIOS chip has been removed, take the corrupted BIOS chip and insert it into
the socket. Pemember to align the notch in the BIOS chip`s package vith the notch in the
socket betore you insert the BIOS chip'
With the corrupted BIOS chip in place, all you need to do is tlash it vith a nev BIOS image.
Stop $: Ilosh tho Corruptod BIOS Chip
Nov it`s time to tire up the BIOS tlash utility you have prepared in the DOS boot disk. It you
have torgotten or did not vrite dovn the tilename ot the BIOS image tile, you can check tor it
by running a dir command at the command prompt.
lor the reterence motherboard, the ABI1 Nl7-S, I used the tolloving command (as recom-
mended by ABI1,:
A:(>aWdfJash b1os.b1n 1cc 1cd 1cp 1py 1sn 1cks 1r
LhapIcr 2 Spcca| Jopcs
ooo PI: chip in its socket.
(Ihoto | author)
hoI F|ashng
PI: chip remo:eo.
(Ihoto | author)
Insertin the corrupteo PI: chip.
(Ihoto | author)
Please consult your motherboard manual
tor the proper commands tor your
motherboard.1he commands may vary
betveen motherboards.
Atter the BIOS tlash utility completes
tlashing the BIOS image, it automatically
reboots the computer. At this point in
time, you should turn ott the computer.
Stop : Swop tho BIOS Chips Agoin
With the computer turned ott, it is much easier to remove the revived BIOS chip and insert the
original BIOS chip into the socket.Again, make sure the BIOS chip is aligned correctly betore
you insert it into the socket. Start up the system to make sure it didn`t sutter any damage trom
the procedure.
You can nov take the revived BIOS chip and insert it into its socket in the previously dead
motherboard.1hen press the Pover button and vatch your system boot up'
Whot II You Don`t Hovo o Sinilor Mothorboord?
Although it is advisable to use a similar motherboard to hot tlash your dead BIOS chip, you can
use a completely ditterent motherboard model to do the hot tlash.1here are some things you
need to consider betore you do so, though.
lirst, you should tind a vorking motherboard that supports the same BIOS chip as that ot your
dead motherboard. It your BIOS chip is ot the square PLCC type, look tor a vorking mother-
board that also uses a PICC BIOS chip.You can`t hot tlash a PICC BIOS chip using a
motherboard that uses a DIP BIOS chip'
And even it you tind a motherboard that supports the same type ot BIOS chip, you must make
sure that it supports the same voltage. Older BIOS chips run at 3V vhile nev ones only need
3.3V to run. Naturally, inserting a 3.3V BIOS chip into a 3V socket vill burn up that 3.3V
chip in no time at all.
So, check and make sure both the dead BIOS chip and the BIOS chip ot the hot tlash mother-
board run at the same voltage. Because current motherboards all use 3.3V BIOS chips, this
should only be a problem it you are attempting to use a very old motherboard to hot tlash.
When you have everything ready, tollov the steps ve`ve gone through earlier.1he only change
at this point vill be hov to tlash the dead BIOS chip.
Iloshing with o DiIIoront Mothorboord
Depending on the tlash utility you use, it is possible to torce the tlash utility to tlash the dead
BIOS vith your BIOS image tile even it the tlash utility detects it as the vrong BIOS image.
In this example, ve vill use the 8.23K version ot the Avardllash utility. Iet`s look at the list ot
available options:
LhapIcr 2 Spcca| Jopcs
uaroIiash utiiit commanos.
1he manutacturer ot my reterence motherboard, ABI1, recommends the tolloving command
line parameters:
1o torce the Avardllash utility to tlash the dead BIOS chip, you need to add a /f svitch to the
end ot the command line.1hus, the command line should nov be:
1hat should torce the Avardllash utility to tlash the dead BIOS chip vith the BIOS image you
prepared, even atter booting up on a ditterent motherboard vith an incompatible BIOS.
It you are using a ditterent tlash utility, please consult your motherboard manutacturer tor the
correct torce tlash svitch tor that utility.
lho Univorsol BIOS Ilosh Utility
It the preceding method tails, there is still a recourse. 1here is a BIOS tlash utility that claims to
be the universal BIOS tlash utility' BeholdUniFlash'
Developed by Ondrej Zary, this utility has impressive lists ot supported hardvare and compati-
bility tests. Best ot all, it appears to be updated regularly.
Lnillash is detinitely vorth checking out it you need to torce tlash a dead BIOS chip on a dit-
terent motherboard.You can get the latest version ot Lnillash at http:vvv.unitlash.org.
Sunnory
When it comes to minor emergencies like an unbootable system, I have shovn you a variety ot
vays to tackle the problem and restore the sys tem. I have even listed them in order ot preter-
ence (based on simplicity,:
Pover Ott-Pover On
Keyboard Peset
CMOS Discharge umper
CMOS Battery Pemoval
When it comes to a corrupted BIOS, it is usually the end ot the road tor the motherboard.
You vill have to send the motherboard back to the manutacturer or request a replacement
BIOS chip.
Ot course, I have shovn you an alternative in the torm ot the hot tlashing technique. As you
have seen, the concept ot hot tlashing is pretty simple. It is the proper execution ot the tech-
nique that is tricky.
It you are experienced in vorking vith hardvare and knov hov to tlash the BIOS, then it
should not be a ditticult procedure even vithout the proper BIOS removal tool.You can use
hot tlashing to revive dead BIOS chips, thereby saving you money and keeping your computer`s
dovntime to the absolute minimum.
Hovever, it you have virtually no experience in hardvare or tlashing the BIOS, then hot tlash-
ing can be a rather dangerous endeavor. lailure to restore the dead BIOS chip vould be the
leas t ot your vorries. It you are unlucky or careless, you could damage the computer you are
using to hot tlash the dead BIOS chip.
Summary 27
1heretore, it is highly advisable that you do not attempt this procedure unless you are tamiliar
vith hardvare and knov hov to tlash BIOS.
I hope this section on hot tlashing has helped you learn hov to revive corrupted BIOS chips
vith minimal hassle and risk. It you are interested in more details on hot tlashing, please teel
tree to check out lhe PI Hot Iiashi n uioe (http:vvv.rojakpot.comshovar
ticle.aspxartno=62,.
Chapter 3
Quick Pevievs
Introduction
1his chapter contains simplitied explanations ot each BIOS option as vell as its recommended
settings .1his is the best chapter to consult it you need a quick overviev ot a BIOS option and
its optimal settings.
You should also start vith this chapter it you have only limited knovledge ot computer hard-
vare.1his chapter otters simple explanations ot the BIOS options, so you von`t be contus ed by
technical details.
1he BIOS options are all arranged alphabetically vith lettered tabs, so you can navigate quickly
through the chapter.You can also use the 1able ot Contents and the Category Iook-Lp 1able to
quickly access the BIOS options you are interested in.
ôte. Acronyms are not alvays spelled out, so a detailed list ot acronyms is provided at the end
ot this book tor your reterence.
Atter you complete this chapter, you should head on to Chapter 4 tor more details on the
BIOS options covered in this chapter.
#
8-bit I/O Rocovory lino
Connon Options: NA, 8, 1, 2, 3, 4, 3, 6, 7
1his BIOS teature allovs you to add extra vait cycles betveen consecutive 8-bit PCI cycles to
the ISA bus. 1his is used to correct timing issues betveen the PCI bus and ISA bus.
Please note that there is already a tixed minimum delay ot 3.3 clock cycles. So vhatever you set
using this BIOS teature adds to that delay. Choosing NA sets the number ot delay cycles to the
minimum 3.3 clock cycles.
Most 8-bit ISA cards vork tine vith the minimum 3.3 delay cycles (NA,. Hovever, it your ISA
card does not vork properly, try increasing the number ot additional delay cycles.
Connon Options: NA, 4, 1, 2, 3
1his BIOS teature allovs you to add extra vait cycles betveen consecutive 16-bit PCI cycles to
the ISA bus. 1his is used to correct timing issues betveen the PCI bus and ISA bus.
Please note that there is already a tixed minimum delay ot 3.3 clock cycles. So vhatever you set
using this BIOS teature adds to that delay. Choosing NA sets the number ot delay cycles to the
minimum 3.3 clock cycles.
Most 16-bit ISA cards vork tine vith the minimum 3.3 delay cycles (NA,. Hovever, it your
ISA card does not vork properly, try increasing the number ot additional delay cycles.
32-bit Disk Accoss
Connon Options: Lnabled, Disabled
1his BIOS teature allovs you to command the IDL controller to combine tvo 16-bit hard disk
reads into a single 32-bit data transter to the processor.1his greatly improves the pertormance ot
the IDL controller as vell as the PCI bus.
1heretore, it is highly advisable to enable 32-bit Disk Access. It you dis able it, data transters trom
the IDL controller to the processor vill only occur in 16-bits chunks.
LhapIcr 3 0uck cvcws 80
4
32-bit lronsIor Modo
Connon Options: On, Ott
1his BIOS teature allovs you to command the IDL controller to combine tvo 16-bit hard disk
reads into a single 32-bit data transter to the processor.1his greatly improves the pertormance ot
the IDL controller as vell as the PCI bus.
1heretore, it is highly advisable to enable 32-bit 1ranster Mode. It you disable it, data trans ters
trom the IDL controller to the processor vill only occur in 16-bit chunks.
82-hI Jransfcr Modc 81
4
A
Act Bonk A to B CMD Doloy
Connon Options: 2 Cycles, 3 Cycles
1his BIOS teature specities the minimum amount ot time betveen successive AC1IVA1L
commands to the same DDP device.1he shorter the delay, the taster the next bank can be acti-
vated tor read or vrite operations. Hovever, because rov activation requires a lot ot current,
using a short delay may caus e excessive current surges.
lor desktop PCs, a delay ot 2 cycles is recommended, as current surges aren`t really important.
1he pertormance benetit ot using the shorter 2-cycle delay is ot tar greater interest. 1he shorter
delay means every back-to-back bank activation takes one clock cycle less to pertorm.1his
improves the DDP device`s pertormance.
Svitch to 3 cycles only vhen there are stability problems vith the 2-cycle setting.
AGP 2 Modo
1his BIOS teature is a toggle tor the motherboard`s AGP 2X support.
When enabled, it allovs the AGP bus to make use ot the AGP 2X transter protocol to boost
the AGP bus bandvidth. It it`s disabled, then the AGP bus only uses the standard AGP1X trans-
ter protocol.
1he AGP 2X protocol must be supported by both the motherboard and graphics card tor this
teature to vork. Ot course, this teature only appears in your BIOS it your motherboard supports
the AGP 2X transter protocol'
So, all you need to do is make sure your graphics card s upports AGP 2X transters. It it does,
enable AGP 2X Mode to take advantage ot the taster transter mode. Disable it only it you are
tacing stability issues or it you intend to overclock the AGP bus beyond 73MHz vith side-
banding support enabled.
AGP 4 Drivo Strongth
Connon Options: Auto, Manual
1his BIOS teature allovs you to set the AGP controller to dynamically adjust the AGP driving
strength or allov manual contiguration in the BIOS.
Normally, the recommended setting is Auto.1he AGP Drive Strength values are provided by
the auto-compensation circuitry. Hovever, manual contiguration ot the AGP Drive Strength
may be necessary to get certain AGP 4X cards to vork properly.
A
1o correct such compatibility problems, you should set the AGP 4X Drive Strength to Manual.
1his allovs you to set a hiher AGP Drive Strength value manually through the AGP Drive
Strength P Ctrl and AGP Drive Strength N Ctrl options.
Please note that this teature is a little ditterent trom AGP Driving Control, because it usually
comes vith tvo to tour ditterent drive strength controls .1he AGP Driving Control teature
only comes vith a single drive strength control.
AGP 4 Modo
the AGP bus bandvidth. It it`s disabled, then the AGP bus only uses the AGP 1X or AGP 2X
transter protocol.
enable AGP 4X Mode to take advantage ot the taster transter mode.You must disable it it your
graphics card doesn`t support AGP 4X transters. 1he BIOS then reports that the maximum sup-
ported transter mode is AGP 2X.
AGP 8 Modo
the AGP bus bandvidth. It it`s disabled, then the AGP bus is only alloved to use the AGP 4X
transter protocol.
enable AGP 8X Mode to take advantage ot the taster transter mode.You must disable it it your
graphics card doesn`t support AGP 8X transters. 1he BIOS then reports that the maximum sup-
ported transter mode is AGP 4X.
AGP Alwoys Conponsoto
1his BIOS teature determines vhether the AGP controller should be alloved to dynamically
adjust the AGP driving strength or us e preset drive strength values.
A0P A|ways LompcnsaIc 88
A
By detault, it is set to automatically adjust the AGP drive strength once or at regular intervals.
1he circuitry can also be disabled or bypass ed and a user setting used. Hovever, this BIOS tea-
ture does not allov manual contiguration.
When you enable AGP Alvays Compensate, the auto-compensation circuitry automatically
adjusts the AGP Drive Strength at reuiar inter:ai s. It you disable it, the circuitry only adjusts
the drive strength once at boot-up. 1he drive strength values derived at boot-up remain until
the s ystem is rebooted.
It is recommended that you enable AGP Alvays Compensate, so the AGP controller can
dynamically adjust the AGP driving strength at regular intervals .
AGP Aporturo Sizo
Connon Options: 4, 8, 16, 32, 64, 128, 236
1his BIOS teature does tvo things: It selects the size ot the AGP aperture, and it determines
the s ize ot the GAR1 (Graphics Address Relocation 1able).
1he aperture is a portion ot the PCI memory address range that is dedicated tor use as AGP
memory address space, vhile the GAP1 is a translation table that translates AGP memory
addresses into actual memory addresses that are otten tragmented. 1he GAP1 allovs the
graphics card to s ee the memory region available to it as a contiguous piece ot memory
range.
Host cycles that hit the aperture range are torvarded to the AGP bus vithout need tor trans-
lation.1he aperture size also determines the maximum amount ot syst em memory that can be
allocated to the AGP graphics card tor texture storage.
Please note that the AGP aperture is merely address space, not actual physical memory in use.
Although it is very common to hear people recommending that the AGP aperture size should
be haif the size ot system memory, this is uron'
1he requirement tor AGP memory space shrinks as the graphics card`s local memory increases
in size.1his is because the graphics card has more local memory to dedicate to texture storage.
So, it you upgrade to a graphics card vith more memory, you shouldn`t be deceived into
thinking you need even more AGP memory' On the contrary, a smaller AGP memory space
is required.
It is recommended that you keep the AGP aperture around 64MB to 128MB in size, even it
your graphics card has a lot ot onboard memory.1his allovs tlexibility in the event that you
actually need extra memory tor texture storage. It also keeps the GAP1 vithin a reasonable
size.
AGP Copobility
Connon Options: Auto, 1X Mode, 2X Mode, 4X Mode, 8X Mode
1his BIOS teature is only tound in AGP 8X-capable motherboards.AGP 8X is backvard-
compatible vith earlier AGP standards.1his BIOS teature allovs you to set the motherboard`s
maximum supported AGP transter protocol.
A
It is recommended that you leave this BIOS teature at its detault s etting ot Auto. 1his allovs
the motherboard to set the appropriate AGP transter protocol based on the graphics card`s AGP
support detected during boot up.
Hovever, the other options are usetul it your graphics card has problems using the detected
AGP transter protocol.You can manually select a slover AGP transter protocol to solve the
problem.
AGP Clock / CPU ISB Clock
Connon Options: 11, 23, 12, 23
1his BIOS teature allovs you to set the ratio betveen the AGP clock speed and the CPL bus
(aiso knoun as froni sie lus or F8B, clock speed.1his allovs you to keep the AGP bus speed
vithin specitications ( 66MHz, vhile using a much taster CPL bus speed.
When the ratio is set to 1/1, the AGP bus runs at the same speed as the CPL bus.1his is meant
tor processors that use the 66MHz bus speed, such as the older Intel Celeron processors.
1he 2/3 divider is used vhen you use a processor running vith a bus speed ot 100MHz. 1his
divider cuts the AGP bus speed dovn to 66MHz.
1he 2/S divider is used vhen you use a processor running vith a bus speed ot 166MHz. 1his
Generally, you should set this teature according to the CPL bus speed you are using. 1his means
using the 1/1 divider tor 66MHz bus speed CPLs, the 2/3 divider tor 100MHz bus speed
CPLs, the 1/2 divider tor 133MHz CPLs, and the 2/S divider tor 166MHz CPLs.
AGP Drivo Strongth
strength or the BIOS to manually contigure it.
Normally, the recommended setting is Auto.1he AGP Drive Strength values are provided by
the auto-compensation circuitry. Hovever, manual contiguration ot the AGP Drive Strength
may be necessary to get certain AGP 4X8X cards to vork properly.
1o correct such compatibility problems, you should set the AGP Drive Strength to Manual.
1his allovs you to manually set a hiher AGP Drive Strength value through the AGP Drive
Strength P Ctrl and AGP Drive Strength N Ctrl options.
Please note that this teature is a little ditterent trom AGP Driving Control, because it usually
A0P 0rvc SIrcngIh 86
A
AGP Drivo Strongth N Ctrl
Connon Options: 0 to l (Hex numbers,, 0h to lh
1his BIOS teature only is activated it you set the AGP Drive Strength BIOS teature to
Manual. It determines the N transistor drive strength ot the AGP bus.
1he drive strength is represented by Hex values trom 0 to l (0 to 13 in decimal,. 1he higher
the drive strength, the greater the compensation tor the motherboard`s impedance on the
AGP bus .
In conjunction vith AGP Drive Strength and AGP Drive Strength P Ctrl, this tunction is
used to bypass AGP dynamic compensation in cases vhere the auto-compensation circuitry
cannot provide adequate compensation. Please check vith your graphics card manutacturer it
your card requires the N transistor drive strength to be set manually.
Incidentally, increasing the AGP drive strength does not improve the pertormance ot the AGP
bus. It is not a pertormance-enhancing teature, so you shouldn`t increase the N transistor drive
strength unless you need to.
AGP Drivo Strongth P Ctrl
1his BIOS teature only is activated it you set the AGP Drive Strength BIOS teature to
Manual. It determines the P transistor drive strength ot the AGP bus.
1he drive strength is represented by Hex values trom 0 to l (0 to 13 in decimal,. 1he higher the
drive strength, the greater the compensation tor the motherboard`s impedance on the AGP bus.
In conjunction vith AGP Drive Strength and AGP Drive Strength N Ctrl, this tunction is
cannot provide adequate compensation. Please check vith your graphics card manutacturer it
your card requires the P transistor drive strength to be set manually.
bus. It is not a pertormance-enhancing teature, so you shouldn`t increase the P transistor drive
AGP Driving Control
strength or allov manual contiguration by the BIOS.
Normally, the recommended setting is Auto.1he AGP drive strength values are provided by the
auto-compensation circuitry. Hovever, manual contiguration ot the AGP Drive Strength may be
necessary to get certain AGP 4X8X cards to vork properly.
1o correct such compatibility problems, you should set the AGP Drive Strength to Manual.
1his allovs you to set a hiher AGP Drive Strength value manually through the AGP Driving
Value tunction.
A
Please note that this teature is a little ditterent trom AGP 4 Drive Strength, because it
usually comes vith a single drive strength control.1he AGP 4 Drive Strength teature
comes vith tvo to tour drive strength controls.
AGP Driving Voluo
Connon Options: 00 to ll (Hex numbers, , 00h to llh
1his BIOS teature is only activated it you set the AGP Driving Control BIOS teature to
Manual. It determines the overall drive strength ot the AGP bus.
1he drive strength is represented by Hex values trom 00 to ll (0 to 233 in decimal, .1he high-
er the drive strength, the greater the compensation tor the motherboard`s impedance on the
AGP bus.
cannot provide adequate compensation. It you are using an AGP card built around the NVIDIA
Gelorce 2 line ot GPLs, then you should put AGP Driving Control into Manual mode and
set the AGP Driving Value to LA (234,. lor other cards, please check vith the manutacturer it
your card requires the AGP driving strength to be set manually.
bus. It is not a pertormance-enhancing teature, so you shouldn`t increase the AGP drive strength
unless you need to.
AGP Iost Writo
1his BIOS teature controls the AGP bus last Write capability. last Write is a teature that accel-
erates memory vrite transactions trom the chipset to the AGP device.
last Write allovs the AGP device to act like a PCI device.1his allovs it to bypass the main
memory and directly access the data, vhich improves AGP read pertormance. Hovever, AGP
vrite pertormance is not attected.
It is recommended that you enable AGP last Write tor better AGP read pertormance, but dis-
able it it any ot your PCI cards start acting tunny.
AGP ISA Aliosing
1his BIOS teature allovs you to determine vhether the system controller pertorms ISA
Aliasing to prevent contlicts betveen ISA devices.
1he detault setting ot Lnabled torces the system controller to alias ISA addresses using address
bits [13:10| .1his restricts all 16-bit addressing devices to a maximum contiguous IO space ot
236 bytes.
A0P ISA A|asng 87
A
When disabled, the system controller does not pertorm any ISA aliasing and all 16 address lines
can be used tor IO address space decoding. 1his gives 16-bit addressing devices access to the
tull 64KB IO space.
It is recommended that you disable AGP ISA Aliasing tor optimal AGP (and PCI, pertorm-
ance. It also prevents your AGP or PCI card trom contlicting vith your ISA cards. Lnable it
only it you have ISA devices that are contlicting vith each other.
AGP Mostor 1WS Rood
1his BIOS teature allovs you to reduce the time the AGP bus-mastering device has to vait
betore it can initiate a read command to only one vait state. 1his speeds up all reads that the
AGP bus-master makes trom the system memory.
So, tor better AGP read pertormance, enable this teature. Disable it only it you notice visual
anomalies or it your system hangs on running sottvare that makes use ot AGP texturing.
Curiously, some motherboards come vith a detault AGP master read latency ot 0' Lnabling the
AGP Master 1WS Pead in such cases actually increases the latency by one vait state and reduces
AGP read pertormance.Although it`s quite unlikely that the detault AGP master read latency
vould be zero, that`s vhat their manuals say.
AGP Mostor 1WS Writo
1his BIOS teature allovs you to reduce the time the AGP bus-mastering device has to vait
betore it can initiate a vrite command to only one vait state.1his speeds up all vrites that the
AGP bus-master makes to the system memory.
anomalies or it your system hangs on running sottvare that makes use ot AGP texturing.
Curiously, some motherboards come vith a detault AGP master vrite latency ot 0' Lnabling
the AGP Master 1WS Write in such cases actually increases the latency by one vait state and
reduces AGP vrite pertormance. Although it`s quite unlikely that the detault AGP master vrite
latency vould be zero, that`s vhat their manuals say.
AGP ProIotch
1his teature controls the system controller`s AGP pretetch capability.
When enabled, the system controller pretetches data vhenever the AGP device reads trom the
system memory. 1his speeds up AGP reads becaus e it allovs contiguous memory reads by the
AGP device to proceed vith minimal delay.
1heretore, it is recommended that you enable this teature tor better AGP read pertormance.
A
AGP Socondory Lot linor
Connon Options: 00h, 20h, 40h, 60h, 80h, C0h, llh
1his BIOS teature controls hov long the AGP bus can hold the PCI bus (via the PCI-to-PCI
bridge, betore another PCI device takes over.1he longer the latency, the longer the AGP bus
can retain control ot the PCI bus betore handing it over to another PCI device.
Normally, the AGP Secondary Iatency 1imer is set to 20h (32 clock cycles,. 1his means the
AGP bus PCI-to-PCI bridge has to complete its transactions vithin 32 clock cycles or hand it
over to the next PCI device.
lor better AGP pertormance, a longer latency should be used.1ry increasing it to 40h (64
cycles, or even 80h (128 cycles,. 1he optimal value tor every s ystem is ditterent.You should
benchmark your AGP card`s pertormance atter each change to determine the optimal latency
tor your system.
It you set the AGP Secondary Iatency 1imer to a very large value like 80h (128 cycles, or
C0h (192 cycles,, you should set the PCI Latency 1ine to 32 cycles. 1his provides better
access tor your PCI devices that might be unnecessarily stalled it both the AGP and PCI buses
have very long latencies.
In addition, some time-critical PCI devices may not agree vith a long AGP latency. Such
devices require priority access to the PCI bus, vhich may not be possible it the PCI bus is held
up by the AGP bus tor a long period. In such cases, it is recommended that you keep to the
detault latency ot 20h (32 clock cycles,.
AGP Sprood Spoctrun
Connon Options: 0.23, 0.3, Disabled
1his BIOS teature allovs you to reduce the LMI ot the AGP bus by modulating the signals it
generates so that the spikes are reduced to tlatter curves. It achieves this by varying the trequen-
cy siihti, so the signal does not use any particular trequency tor more than a moment.
1he BIOS usually otters tvo levels ot modulation0.2S or 0.S.1he greater the modula-
tion, the greater the reduction ot LMI.1heretore, it you need to signiticantly reduce the AGP
bus LMI, a modulation ot 0.S is recommended.
In most conditions, trequency modulation using this teature should not cause any problems.
Hovever, system stability may be compromised it you are overclocking the AGP bus. Ot course,
this depends on the amount ot modulation, the extent ot overclocking, and other tactors such as
temperature, and so torth. As such, the problem may not manitest itselt immediately.
1heretore, it is recommended that you disable this teature it you are overclocking the AGP bus.
1he risk ot crashing your system is not vorth the reduction in LMI. Ot course, it LMI reduc-
tion is important to you, enable this teature by all means. Hovever, you should reduce the
clock speed a little to provide a margin ot satety.
It you are not overclocking, the decision to enable or disable this teature is really up to you.
Hovever, unless you have LMI problems or sensitive data that must be sateguarded trom elec-
tronic eavesdropping, it is best to disable this teature to remove the possibility ot instability.
A0P Sprcad SpccIrum 80
A
AGP to DRAM ProIotch
1his teature controls the system controller`s AGP pretetch capability.
When enabled, the system controller pretetches data vhenever the AGP device reads trom the
system memory. 1his speeds up AGP reads becaus e it allovs contiguous memory reads by the
AGP device to proceed vith minimal delay.
AGPCLR / CPUCLR
1his BIOS teature allovs you to set the ratio betveen the AGP clock speed and the CPL bus
(aiso knoun as froni sie lus or F8B, clock speed.1his allovs you to keep the AGP bus speed
vithin specitications ( 66MHz, vhile using a much taster CPL bus speed.
tor processors that use the 66MHz bus speed, such as the older Intel Celeron processors.
1he 2/S divider is used vhen you use a processor running vith a bus speed ot 166MHz. 1his
Anti-Virus Protoction
Connon Options: Lnabled, Disabled, ChipAvay
1his BIOS teature controls the motherboard`s virus protection teatures.
When enabled, the BIOS protects the boot sector and partition table by halting the system and
tlashing a varning message vhenever there is an attempt to vrite to these areas.
1his teature can cause problems vith sottvare that needs to access the boot sector, tor example
the installation routine ot all versions ot Microsott Windovs trom Windovs 93 onvard. When
enabled, this teature causes the installation routine to tail.You s hould disable this teature betore
running such sottvare.
Alternatively, you can select the internal rule-based anti-virus code knovn as ChipAvay.
Lnabling ChipAvay provides better anti-virus protection by scanning tor and detecting boot
viruses betore they have a chance to intect the boot sector ot any hard disk. Note that this tea-
ture is useless tor hard disks that run on external controllers vith their ovn BIOS.
A
APIC Iunction
1his BIOS teature is used to enable or disable the motherboard`s APIC (Advanced
Progrannable Interrupt Controller,.1he APIC provides multiprocessor support, more
IPQs, and taster interrupt handling.
Hovever, it is only supported by never operating systems such as Microsott Windovs N1,
Windovs 2000, and Windovs XP. Older operating systems such as DOS or Windovs 9398 do
not support this teature.
It is recommended that you enable this teature it you are using a never operating system such
as Windovs XP. Disable it only it you are using an older operating system such as DOS or
Windovs 9398.
Assign IRQ Ior USB
1his BIOS teature controls vhether the BIOS should assign an IPQ to the LSB controller.
When enabled, an IPQ is assigned to the LSB controller, and you are able to connect your
LSB devices to it.
When disabled, the LSB controller is not assigned an IPQ.1his disables the LSB controller
but trees up an IPQ.
It is recommended that you enable this teature it you use LSB peripherals.
Assign IRQ Ior VGA
1his BIOS teature controls vhether the BIOS should assign an IPQ to the graphics card.
When enabled, an IPQ is assigned to the graphics card.
When disabled, the graphics card is not assigned an IPQ.
While there are some exceptions, most graphics cards require an IPQ to vork properly.
1heretore, it is recommended that you enable this teature tor proper operation ot your
graphics card.
Al Bus Clock
Connon Options: 7.16MHz, CIK2, CIK3, CIK4, CIK3, CIK6
1his BIOS teature allovs you to select the ISA bus clock speed. 1he chipset actually generates
the ISA bus clock by dividing the PCI clock. Hence, the available settings ot CLK/2, CLK/3,
CLK/4, CLK/S, and CLK/6.
1he tixed speed ot 7.16MHz is derived by dividing the reterence clock generator speed ot
14.318MHz by a tactor ot tvo.
AJ 8us L|ock 41
A
As you can see, the setting ot CLK/4 yields an ISA bus speed ot 8.33MHz, vhich is the maxi-
mum speed alloved by the otticial ISA specitications. Hovever, you can choose to overclock the
ISA by selecting the settings CLK/3 or CLK/2, vhich yield clock speeds ot 11.11MHz and
16.67MHz, respectively.
Overclocking the ISA bus greatly improves its pertormance. 1heretore, it is recommended that
you try to use the taster settings it possible. Hovever, vhile never ISA cards are capable ot run-
ning at this out-ot-spec speed, older ones may not vork properly at this speed.
It your ISA cards tail to vork properly, then you should select the setting ot CLK/4 or
7.16MHz.1his keeps the ISA bus vithin specitications.
Please note that the atorementioned calculations and recommendations vere based on a
33MHz PCI bus clock. It you are overclocking your PCI bus, please take the increased PCI
clock speed into account'
It this is contusing and you vant to play it sate, select the setting ot 7.16MHz. 1his is the tail-
sate setting because it sets the ISA bus to run at a tixed speed ot 7.16MHz, irrespective ot the
PCI bus speed.
AlA100RAID IDL Controllor
1his BIOS teature enables or disables the motherboard`s external LltraDMA100 IDL PAID
controller.
When enabled, the external LltraDMA100 IDL PAID controller is enabled to provide an
additional tvo IDL channels and PAID capabilities.
When disabled, the external LltraDMA100 IDL PAID controller is disabled, treeing up tvo
IPQs and speeding up system initialization.
It is recommended that you enable this teature it you require the use ot the external
LltraDMA100 IDL PAID controller, but disable it it you don`t use it.
Athlon 4 SSLD Instruction
Beginning vith the Palomino core ot the Athlon XP (and MP, tamily ot processors, AMD
started implementing Intel`s SSL instruction set.AMD also added a status bit that tells any
querying sottvare that the Athlon XPMP supports the tull SSL instruction set. Hovever, this
status bit ends up causing some compatibility issues vith the BeOS operating system and some
graphics cards .
1his is vhere the Athlon 4 SSLD Instruction BIOS teature comes in. 1his BIOS teature is a
simple toggle tor the AMD Athlon XPMP`s SSL status bit.
When enabled, the BIOS enables the SSL status bit. Querying sottvare vill recognize the
processor as a SSL-compatible processor.1his allovs the processor to take advantage ot SSL-
optimized sottvare.
When disabled, the BIOS disables the SSL status bit. Querying sottvare vill not recognize the
processor as a SSL-compatible processor.1he processor can only take advantage ot Lnhanced
3DNov'-optimized sottvare.
A
By detault, this BIOS teature is set to Lnabled, vhich allovs tor optimal pertormance vith
SSL-optimized sottvare. It is highly recommended that you leave it at the detault setting ot
Lnabled.
You should disable this BIOS teature only it you are tacing compatibility issues vith the SSL
status bit.
Auto Dotoct DIMM/PCI Clk
1his BIOS teature determines vhether the BIOS should actively reduce LMI
(Llectronagnetic Interference) and reduce pover consumption by turning ott unoccupied
or inactive expansion slots.
When enabled, the BIOS monitors AGP, PCI, and memory slots and turns ott clock signals to
all unoccupied and inactive slots.
When disabled, the BIOS does not monitor AGP, PCI, and memory slots. All clock signals
remain active even to unoccupied or inactive slots.
It is recommended that you enable this teature to save pover and reduce LMI.
Auto lurn OII PCI Clock Pin
1his BIOS teature determines vhether the BIOS should actively reduce LMI and reduce pover
consumption by turning ott unoccupied or inactive PCI slots.
When enabled, the BIOS monitors PCI slots and turns ott clock signals to all unoccupied and
inactive slots .
When disabled, the BIOS does not monitor PCI slots. All clock signals remain active even to
unoccupied or inactive slots.
AuIo Jurn 0ff PLI L|ock Pn 48
A
B
Boot Othor Dovico
1his BIOS teature determines vhether the BIOS attempts to load an operating system trom the
Second Boot Device or 1hird Boot Device it it tails to load one trom the First Boot
Device.
1his teature is enabled by detault, and it is recommended that you leave it as such.
Boot Soquonco
Connon Options: A, C, SCSI
C,A, SCSI
C, CD-POM,A
CD-POM, C,A
D, A, SCSI (only vhen you have at least 2 IDL hard disks,
L, A, SCSI (only vhen you have at least 3 IDL hard disks,
l, A, SCSI (only vhen you have 4 IDL hard disks,
SCSI, A, C
SCSI, C, A
A, SCSI, C
ISZIP, C
1his BIOS teature enables you to set the sequence by vhich the BIOS searches tor an operat-
ing system during the boot-up process.1o ensure the shortest booting time possible, set the hard
disk that contains your operating system as the tirst choice. Normally, this is drive C tor IDL
drives, but it you are using an SCSI hard disk, then select SCSI.
Some motherboards have an external (not part ot the chipset, IDL controller. In such mother-
boards, the SCSI option is replaced vith an L1 option. It you vant to boot trom an IDL
hard disk running ott the internal IDL controller, do not set the Boot Sequence to start vith
L1. Please note that this teature vorks in conjunction vith the Boot Sequence L1
Means teature.
B
Boot Soquonco Ll Moons
Connon Options: IDL, SCSI
1his BIOS teature determines vhether the system boots trom an IDL hard dis k connected to
an externai IDL controller or an SCSI hard disk. Hovever, it only has an ettect it the L1
option had been selected in the Boot Sequence teature.
1o boot trom an IDL hard disk that`s connected to the externai IDL controller, you must set this
teature to IDL.
1o boot trom an SCSI hard disk, you must set this teature to SCSI.
Boot lo OS/2
Connon Options: Yes, No
1his is similar to the OS Select For DRAM > 64M BIOS teature.
1his BIOS teature determines hov systems vith more than 64MB ot memory are managed. A
vrong setting can cause problems like erroneous memory detection.
It you are using an older version ot the IBM OS2 operating system, you should select Yes.
It you are using the IBM OS2 Warp v3.0 or higher operating system, you should select No.
It you are using an older version ot the IBM OS2 operating system but have already installed
all the relevant IBM lixPaks, you should select No.
Lsers ot non-OS2 operating systems (such as Microsott Windovs XP, should select the No
option.
Boot Up Iloppy Sook
1his BIOS teature determines vhether the BIOS checks tor a tloppy drive during boot-up.
It enabled, the BIOS attempts to detect and initialize the tloppy drive. It it cannot detect one, it
tlashes an error message. Hovever, the system is still alloved to continue the boot process.
It this teature is disabled, the BIOS skips the tloppy drive check. 1his speeds up the booting
process by several seconds.
Because a tloppy drive check is really pointless, it is recommended that you disable this teature
tor a taster booting process .
Boot Up NunLock Stotus
1his BIOS teature sets the input mode ot the numeric keypad at boot up.
It you turn this teature on, the BIOS sets the numeric keypad to tunction in the nuneric
node.
8ooI up NumLock SIaIus 46
B
It you set it to Off, the numeric keypad tunctions in the cursor control node instead.
1he numeric keypad`s input mode can be svitched to either numeric or cursor control mode
and back again at any time atter boot up.
1he choice ot initial keypad input mode is entirely up to your preterence.
Byto Morgo
1his BIOS teature is similar to the PCI Dynanic Bursting teature.
When enabled, the PCI vrite butter accumulates and merges 8-bit and 16-bit vrites into 32-
bit vrites. 1his increases the etticiency ot the PCI bus and improves its bandvidth.
When disabled, the PCI vrite butter does not accumulate or merge 8-bit or 16-bit vrites. It
just vrites them to the PCI bus as soon as the bus is tree. As such, there may be a loss ot PCI
bus etticiency vhen 8-bit or 16-bit data is vritten to the PCI bus.
1heretore, it is recommended that you enable Byte Merge tor better pertormance.
Hovever, please note that Byte Merge may be incompatible vith certain PCI netvork inter-
tace cards (also knovn as NICs,. So, it your NIC does not vork properly, try disabling this
teature.
B
C
Clock lhrottlo
Connon Options: 12.3, 23.0, 37.3, 30.0, 62.3, 73.0, 87.3
1his BIOS teature allovs manual contiguration ot the 1hermal Control Circuit. Instead ot
alloving the 1CC to automatically start vith a duty cycle ot 30-S0, you can manually set the
duty cycle.
Available options tor this BIOS teature are set values ot the processor`s duty cycle vhen the
1hermal Control Circuit gets activated.1hey range trom a lov ot 12.S to a high ot 87.S.
Please note that these options retlect the processor`s duty cycle, not its clock speed. 1he clock
speed ot the processor remains unchanged.
It you are looking tor a Disabled option, there is no such option.You cannot turn ott the
1hermal Control Circuit. But it you keep your processor cool enough so that it never exceeds
the maximum sate operating temperature, the 1hermal Control Circuit vill never get activated.
1he detault setting is usually 62.S. 1his means the 1hermal Control Circuit vill insert null
cycles to allov the processor to rest 37.S ot the time.
1he choice ot vhat you should set the 1hermal Control Circuit to run at is really up to you.
1he lover the duty cycle, the slover your processor vill pertorm, but it vill take less time to
cool dovn the processor enough to turn ott the 1CC. Lsing a higher duty cycle vill not
impair pertormance as much but it vill take longer tor your processor to cool dovn enough to
turn ott the 1CC.
Conpotiblo IPU OPCODL
1his BIOS teature determines hov Pentium 4 and Xeon processors handle lOP codes using
the lOP (tinal opcode, register.
When enabled, the Pentium 4 and Xeon engage the lOP code compatibility mode, vhich
stores the lOP ot the last non-transparent instruction in the lOP register.
When disabled, the Pentium 4 and Xeon turn ott the lOP code compatibility mode and store
only the lOP ot the last non-transparent tloating point instruction that hao an unmaskeo excep
tion. 1his allovs tor better lPL pertormance.
1heretore, it is recommended that you disable this teature tor better lPL pertormance unless
your sottvare requires this teature to recover trom lPL exceptions.
LompaIh|c FPu 0PL00L 47
C
CPU/DRAM CLR Synch ClL
Connon Options: Synchronous, Asynchronous, Auto
1his BIOS teature allovs a clear-cut vay ot controlling the memory controller`s operating
mode.
When set to Synchronous, the memory controller vill set the memory clock to the same
speed as the tront side bus.
When set to Asynchronous, the memory controller vill allov the memory clock to run at
any speed.
When set to Auto, the operating mode ot the memory controller vill depend on the memory
clock you set.
It is recommended that you select the Synchronous operating mode. 1his generally provides
the best pertormance, even it your memory modules are capable ot higher clock speeds.
CPU Drivo Strongth
1his BIOS teature allovs you to manually set the drive strength ot the CPL bus.1he higher
the value, the stronger the drive strength.
It you are tacing stability problems vith your processor, you might vant to try boosting the
CPL drive strength to a higher value. It helps correct any possible increase in impedance trom
the motherboard. Due to the nature ot this BIOS teature, it is also possible to use it as an aid in
overclocking the CPL.
Hovever, this is not a suretire vay ot overclocking the CPL. Increasing it to the highest value
does not necessarily mean that you can overclock the CPL more than you already can. In addi-
tion, it is important to note that increas ing the CPL drive strength does not improve its per-
tormance. Contrary to popular opinion, it is not a pertormance-enhancing teature.
CPU Iost String
1his BIOS teature controls the processor`s tast string teature.
When enabled, the processor operates on the string in a cache line vhen the tast string con-
ditions are met.
When disabled, the processor does not operate on the string vhile it is in a cache line.
It is recommended that you enable CPL last String tor better pertormance. 1here is currently
no reason vhy you should disable CPL last String.
C
CPU Hypor-lhrooding
1his BIOS teature controls the tunctionality ot the Intel Hyper-1hreading 1echnology.
Intel Hyper-1hreading 1echnology allovs a single proces sor to execute tuo or more separate
threads concurrently.When hyper-threading is enabled, multi-threaded sottvare applications can
execute their threads in parallel, thereby improving their pertormance.
1he Intel Hyper-1hreading 1echnology is only supported by the Intel Pentium 4 (otticially
only those 3.06GHz and taster, and the Intel Xeon processors. Please note that tor Hyper-
1hreading to vork, you should have the tolloving:
Intel processor that supports Hyper-1hreading
Motherboard vith a chipset and BIOS that support Hyper-1hreading
Operating system that supports Hyper-1hreading (Microsott Windovs XP or Iinux 2.4.x,
Because it behaves like tvo separate processors vith their ovn APICs, you should also enable
APIC Function in the BIOS, vhich is required tor multi-processing.
It is highly recommended that you enable CPL Hyper-1hreading tor improved processor
pertormance.
CPU L2 Cocho LCC Chocking
1his BIOS teature enables or disables the L2 (Level 2 or Secondary, cache`s LCC (Lrror
Checking and Correction, tunction, it available.
Lnabling this teature is recommended, because it detects and corrects single-bit errors in data
stored in the I2 cache. As most data reads are satistied by the I2 cache, the I2 cache`s LCC
tunction should catch and correct almost all single-bit errors in the memory subsystem.
It also detects double-bit errors, although it cannot correct them. Hovever, this isn`t such a big
deal, because double-bit errors are extremei rare. lor all practical purposes, the LCC check
should be able to catch virtually all data errors.1his is especially usetul at overclocked speeds
vhen errors are most likely to creep in.
So, tor most intents and purposes, I recommend that you enable this teature tor greater system
stability and reliability.
Please note that the presence ot this teature in the BIOS does not necessarily mean that your
processor`s I2 cache actually supports LCC checking. Many processors do not ship vith LCC-
capable I2 cache. In such cases, you still can enable this teature in the BIOS, but it vill have
no effect.
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CPU Lotoncy linor
1his BIOS teature allovs you to control hov the processor should handle a deterrable processor
operation vhen there is a nev reques t tor the processor. By detault, it is disabled.
When disabled, the processor vill immeoiatei deter all deterrable operations vhen there is a
nev processor request.
When enabled, the processor vill deter those operations only af ter they have been held in a
Snoop Stall tor 31 clock cycles vhen the nev processor request arrives .
It is recommended that you enable this BIOS teature to ensure that deterrable operations are
given sutticient time to complete.1his improves pertormance by alloving deterrable operations
to be processed vithout excessive delay.
CPU Lovol 1 Cocho
1his BIOS teature controls the tunctionality ot the processor`s Ievel 1 cache.
When enabled, the processor`s Ievel 1 cache is alloved to tunction. 1his allovs the best poss i-
ble pertormance trom the processor.
When disabled, the processor`s Ievel 1 cache is disabled.1he process or bypas ses the Ievel 1
cache and relies only on the Ievel 2 and Ievel 3 (it available, caches.1his reduces the pertorm-
ance ot the processor.
1he recommended setting is obviously Lnabled because disabling it severely attects the proces-
sor`s pertormance. Hovever, the Disabled setting is usetul as a troubleshooting tool, especially
vhen you are overclocking your processor.
CPU Lovol 2 Cocho
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CPU Lovol 3 Cocho
When disabled, the processor`s Ievel 3 cache is disabled.1he processor bypasses the Ievel 3 cache
and relies only on the Ievel 1 and Ievel 2 caches.1his reduces the pertormance ot the processor.
CPU lhornol-lhrottling
Connon Options: 12.3, 23.0, 37.3, 30.0, 62.3, 73.0, 87.3
1his BIOS teature allovs manual contiguration ot the 1hermal Control Circuit. Instead ot alloving
the 1CC to automatically start vith a duty cycle ot 30-S0, you can manually set the duty cycle.
Please note that these options retlect the processor`s duty cycle, not its clock speed.1he clock
turn ott the 1CC.
CPU to PCI Post Writo
1his BIOS teature controls the chipset`s CPL-to-PCI vrite butter. It is used to s tore PCI vrites
trom the processor betore they are vritten to the PCI bus.
When enabled, all PCI vrites trom the processor go directly to the vrite butter.1his allovs
the processor to vork on something else vhile the vrite butter vrites the data to the PCI bus
on the next available PCI cycle.
When disabled, the processor bypasses the butter and vrites directly to the PCI bus.1his ties
up the processor tor the entire length ot the transaction.
It is recommended that you enable this BIOS teature tor better pertormance.
LPu Io LPI PosI WrIc 61
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CPU to PCI Writo BuIIor
When enabled, all PCI vrites trom the processor go directly to the vrite butter.1his allovs
the processor to vork on something else vhile the vrite butter vrites the data to the PCI bus
on the next available PCI cycle.
When disabled, the processor bypasses the butter and vrites directly to the PCI bus.1his ties
up the processor tor the entire length ot the transaction.
It is recommended that you enable this BIOS teature tor better pertormance.
CPU VCoro Voltogo
Connon Options: Std.Vcore, Pais ing
1his is a BIOS teature so tar seen only in the ABI1 NV7-series ot motherboards. It is used to
give a small boost to the processor`s core voltage.
When set to Std.Vcore, the motherboard supplies the processor vith the detault core voltage.
When set to Raising, the motherboard boosts the processor`s core voltage by approximately
3. So, it your processor has a core voltage ot 1.7 volts, using the Paising option raises that
voltage to about 1.7SV.
As you can see, the voltage boost courtes y ot this BIOS teature is not remarkable. Hovever,
because it appears to be the only vay to boost the processor`s core voltage in NVIDIA nlorce-
based motherboards, this 3 boost is better than nothing at all' It may not allov radical over-
clocking, but it should allov a little more overclocking treedom.
It you are an overclocker, it is recommended that you select the Raising option. It should allov
your processor to be a little more overclockable. At the very least, it improves its stability at
overclocked speeds.
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DBI Output Ior AGP lrons.
1he tull name tor this BIOS teature is Dynanic Bus Inversion Output for AGP
1ransnitter. It is an AGP 3.0-specitic BIOS teature that only appears vhen you install an AGP
3.0-compliant graphics card.
When enabled, the AGP controller is alloved to use the Dynamic Bus Inversion scheme to
reduce pover consumption and signal noise.
When disabled, the AGP controller does not use the Dynamic Bus Inversion scheme to reduce
pover consumption and signal noise.
1he AGP bus has 32 data lines divided into tvo sets. Sometimes, a large number ot these data
lines may svitch together to the same polarity (either 1 or 0, and then svitch back to the
opposite polarity. 1his mass svitching to the same polarity is called sinultaneous svitching
outputs and it creates a lot ot unvanted electrical noise at the AGP controller and GPL
intertaces.
1o avoid this, the AGP 3.0 specitications introduced a scheme called Dynanic Bus Inversion
or DBI. It makes use ot tvo nev DBI linesone tor each 16-line set. 1hese DBI lines are only
supported by AGP 3.0-compliant graphics cards.
Dynamic Bus Inversion ensures that the data lines are limited to a maximum ot 8 sinultane-
ous svitchings or transitions per 16-line set. It does so by svitching the DBI line instead ot the
data lines vhen the number ot simultaneous transitions exceeds 8 or S0 ot the data lines. 1his
ensures that electrical noise due to simultaneous svitching outputs is minimized.
In short, DBI improves stability ot the AGP intertace by reducing signal noises that occur as a
result ot sinultaneous svitching outputs. It also reduces the AGP controller`s pover
consumption.
1heretore, it is recommended that you enable DBI Output for AGP 1rans. to save pover as
vell as reduce signal noise trom simultaneous svitching outputs.
Doloy DRAM Rood Lotch
Connon Options: Auto, No Delay, 0.3ns, 1.0ns, 1.3ns
1his teature is similar to the DRAM Read Latch Delay BIOS teature. It tine-tunes the
DPAM timing parameters to adjust tor ditterent DPAM loadings.
1he DPAM load changes vith the number as vell as the type ot memory modules ins talled.
DPAM loading increases as the number ot memory modules increases. It also increases it you
use double-sided modules instead ot single-sided ones. In short, the more DPAM devices you
use, the greater the DPAM loading.
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With heavier DPAM loads, you may need to delay the moment vhen the memory controller
latches onto the DPAM device during reads. Othervise, the memory controller may tail to
latch properly onto the desired DPAM device and read trom it.
1he Auto option allovs the BIOS to select the optimal amount ot delay trom values preset by
the manutacturer.
1he No Delay option torces the memory controller to latch onto the DPAM device vithout
delay, even it the BIOS presets indicate that a delay is required.
1he three timing options (0.Sns, 1.0ns, and 1.Sns, give you manual control ot the read latch
delay.
Normally, you should let the BIOS select the optimal amount ot delay trom values preset by the
manutacturer (using the Auto option,. Hovever, it you notice that your system has become
unstable upon installation ot additional memory modules, you should try setting the DPAM
read latch delay yourselt.
1he amount ot delay should be just enough to allov the memory controller to latch onto the
DPAM device in your particular situation. Don`t unnecessarily increase the delay. Start vith
0.Sns and vork your vay up until your system stabilizes.
It you have a light DPAM load, you can ensure optimal pertormance by manually using the
No Delay option. It your system becomes unstable atter using the No Delay option, simply
revert back to the detault value ot Auto so that the BIOS can adjust the read latch delay to suit
the DPAM load.
Doloy IDL Initiol
Connon Options: 0 to 13
Motherboards are capable ot booting up much taster these days. 1heretore, initialization ot IDL
devices nov takes place much earlier. Lntortunately, this also means that s ome older IDL drives
are not be able to spin up in time to be initialized' When this happens, the BIOS is not able to
detect that IDL drive and the drive is not accessible even though it is actually running just tine.
1his is vhere the Delay IDL Initial BIOS teature comes in. It allovs you to torce the BIOS
to delay the initialization ot IDL devices tor up to 13 seconds. 1he delay allovs your IDL
devices more time to spin up betore the BIOS initializes them.
It you do not us e old IDL drives and the BIOS has no problem initializing your IDL devices, it
is recommended that you leave the delay at the detault value ot 0 tor the shortest possible boot-
ing time. Most IDL devices manutactured in the last tev years have no problem spinning up in
time tor initialization.
Hovever, it one or more ot your IDL devices tail to initialize during the boot up process, start
vith a delay ot 1 second. It that doesn`t help, gradually increase the delay until all your IDL
devices initialize properly during the boot up process.
Doloy Prior lo lhornol
Connon Options: 4 Minutes, 8 Minutes, 16 Minutes, 32 Minutes
1his BIOS teature is only valid tor systems that are povered by 0.13 Intel Pentium 4 proces-
sors vith 312KB I2 cache.1hese processors come vith a 1hernal Monitor that actually
consists ot an on-die thermal sensor and a 1hernal Control Circuit (1CC,.
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When the 1hermal Monitor is in automatic mode and the thermal sensor detects that the
processor has reached its maximum sate operating temperature, it activates the 1CC. 1he 1CC
then modulates the clock cycles by inserting null cycles, typically at a rate ot S0-70 ot the
total number ot clock cycles. 1his results in the processor resting 30-70 ot the time.
As the die temperature drops, the 1CC gradually reduces the number ot null cycles until no
more is required to keep the die temperature belov the sate point.1hen the thermal sensor
turns the 1CC ott .1his mechanism allovs the processor to dynamically adjust its duty cycles to
ensure its die temperature remains vithin sate limits.
1he Delay Prior 1o 1hernal BIOS teature controls the activation ot the 1hermal Monitor`s
automatic mode. It allovs you to determine vhen the Pentium 4`s 1hermal Monitor should be
activated in automatic mode atter the system boots. lor example, vith the detault value ot 16
Minutes, the BIOS activates the 1hermal Monitor in automatic mode 16 minutes atter the sys-
tem starts booting up.
Generally, the 1hermal Monitor should not be activated immediately upon booting because the
processor is under a heavy load during the booting process. 1his causes a sharp rise in die tem-
perature trom its cold state. Because it takes time tor the thermal output to radiate trom the die
to the heat sink, the thermal sensor registers the s udden spike in die temperature and prema-
turely activates the 1CC. 1his unnecessarily reduces the processor`s pertormance during the
booting up process.
1heretore, to ensure optimal booting pertormance, the activation ot the 1hermal Monitor must
be delayed tor a set period ot time.
It is recommended that you set this BIOS teature to the lovest value (in minutes, that exceeds
the time it takes to tully boot up your computer. lor example, it it takes 3 minutes to tully boot
up your system, you s hould select 8 Minutes.
You should not select a delay value that is unnecessarily long.Without the 1hermal Monitor,
your processor may heat up to a critical temperature (approximately 13SC,, at vhich point, the
thermal sensor shuts dovn your process or by removing the core voltage vithin 0.S seconds.
Doloyod lronsoction
1o meet PCI 2.1 compliance, the PCI maximum target latency rule must be observed.
According to this rule, a PCI 2.1-compliant device must service a read request vithin 16 PCI
clock cycles tor the initiai read and 8 PCI clock cycles tor each su|seuent read.
It it cannot do so, the PCI bus terminates the transaction so that other PCI devices can access
the bus. Hovever, instead ot rearbitrating tor access (and tailing to meet the minimum latency
requirement again,, the PCI 2.1-compliant device can make use ot the PCI Delayed
1ransaction teature.
With PCI Delayed 1ransaction enabled, the target device can independently continue the
read transaction. So, vhen the mas ter device successtully gains control ot the bus and reissues
the read command, the target device has the data ready tor immediate delivery.1his ensures that
the retried read transaction can be completed vithin the stipulated latency period.
It the delayed transaction is a vrite, the master device rearbitrates tor bus access vhile the target
device completes vriting the data. When the master device regains control ot the bus, it reissues
the same vrite request.1his time, the target device just sends the completion status to the
master device to complete the transaction.
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One advantage ot using PCI Delayed 1ransaction is that it allovs other PCI masters to use
the bus vhile the transaction is being carried out on the target device. Othervise, the bus is lett
idling vhile the target device completes the transaction.
PCI Delayed 1ransaction also allovs vrite-posted data to remain in the butter vhile the PCI
bus initiates a non-postable transaction and yet still adheres to the PCI ordering rules. Without
PCI Delayed 1ransaction, all vrite-posted data has to be tlushed betore another PCI transac-
tion can occur.
It is highly recommended that you enable Delayed 1ransaction tor better PCI pertormance and
to meet PCI 2.1 specitications. Disable it only it your PCI cards cannot vork properly vith
this teature enabled, or it you are using PCI cards that are not PCI 2.1-compliant.
Please note that vhile many manuals, and even earlier versions ot the BIOS Optimization
Guide, have stated that this is an ISA bus-specitic BIOS teature that enables a 32-bit vrite-
posted butter tor taster PCI-to-ISA vrites, they are incorrect' 1his BIOS teature is not ISA bus-
specitic, and it does not control any vrite-posted butters. It merely allovs vrite-posting to con-
tinue vhile a non-postable PCI transaction is undervay.
DiIIorontiol Curront
Connon Options: 4x Iret, 3x Iret, 6x Iret, 7x Iret
1his BIOS teature allovs you to change the amount ot ditterential current produced by the
clock driver pairs, ettectively changing the voltage sving ot the system clocks.
When set to 4 Iref, the current ditterence is tour times that ot Iref, the reterence current
source.
When set to S Iref, the current ditterence is tive times that ot Iref, the reterence current
source.
When set to 6 Iref, the current ditterence is six times that ot Iref, the reterence current
source.
When set to 7 Iref, the current ditterence is seven times that ot Iref, the reterence current
source.
By detault, this BIOS teature is set to 4 Iref. Lntortunately, it is not knovn vhat that trans-
lates to in voltage. Not even the Iret value is knovn. Hovever, the higher the ditterential cur-
rent, the greater the voltage sving.
As a higher voltage sving improves integrity ot the clock signals and overall sys tem stability, it is
recommended that you set this BIOS teature to 7 Iref tor a higher ditterential current.
Hovever, please note that this vill increase the amount ot LMI (Llectronagnetic
Interference) produced by the motherboard.
Disoblo Unusod PCI Clock
1his BIOS teature determines vhether the BIOS should actively reduce LMI
(Llectronagnetic Interference, and reduce pover consumption by turning ott unoccupied
or inactive PCI slots.
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When enabled, the BIOS monitors PCI slots and turns ott clock signals to all unoccupied and
inactive slots .
When disabled, the BIOS does not monitor PCI slots. All clock signals remain active even to
unoccupied or inactive slots.
DOS Ilot Modo
1his BIOS teature controls the BIOS` built-in extended memory manager.
When enabled, DOS programs can run in protected mode vithout the need ot an extended
memory manager.
When disabled, DOS programs require an extended memory manager to run in protected
mode.
It is recommended that you enable this BIOS teature it you use the MS-DOS operating system
and run protected mode DOS programs.
Hovever, it you use a never operating system that supports protected mode (tor example,
Windovs XP,, disable this BIOS teature.
DRAM Act to ProChrg CMD
Connon Options: 31, 61, 71, 81, 91
Iike SDRAM 1ras 1ining Value, this BIOS teature controls the memory bank`s minimum
rov active time (,. 1his constitutes the time vhen a rov is activated until the time the
same rov can be deactivated. Hence, the name DRAM Act to PreChrg CMD, vhich is short
tor DRAM Activate Connand to Precharge Connand.
It the tPAS period is too long, it can reduce pertormance by unnecessarily delaying the deacti-
vation ot active rovs. Peducing the tPAS period allovs the active rov to be deactivated earlier.
Hovever, it the tPAS period is too short, there may not be enough time to complete a burst
transter. 1his reduces pertormance and data may be lost or corrupted.
lor optimal pertormance, use the lovest value you can. Lsually, this should be CAS latency +
tRCD + 2 clock cycles. lor example, it you set the CAS latency to 2 clock cycles and the
tPCD to 3 clock cycles, the optimum tPAS value vould be 7 clock cycles.
Hovever, it you start getting memory errors or system crashes, increase the tPAS value one
clock cycle at a time until your system becomes stable.
DRAM Burst Longth 8QW
1his BIOS teature allovs you to control the length ot a burst transaction.
When this teature is set to Disabled, a burst transaction can only be comprised ot up to four
quadvord (QW, reads or vrites.
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When this teature is set to Lnabled, a burst transaction can only be comprised ot up to eight
As the initial CAS latency is tixed tor each burst transaction, a longer burst transaction allovs
more data to be read or vritten tor less delay than a shorter burst transaction.1heretore, a burst
length ot 8 is taster than a burst length ot 4.
1heretore, it is recommended that you enable this BIOS teature tor better pertormance.
DRAM Doto Intogrity Modo
Connon Options: LCC, Non-LCC
1his BIOS teature controls the LCC teature ot the memory controller.
LCC, vhich stands tor Lrror Checking and Correction, enables the memory controller to
detect and correct single-bit sott memory errors. 1he memory controller is also able to detect
double-bit errors, although it is not able to correct them.1his provides increased data integrity
and system stability. Hovever, this teature can only be enabled it you are using s pecial LCC
memory modules.
Because present day processors use 64-bit vide data paths, 72-bit (64-bit data 8-bit LCC,
LCC memory modules are required to implement LCC. Please note that the maximum data
transter rate ot the 72-bit LCC memory module is the same as the 64-bit memory module.
1he extra 8-bits are only tor the LCC code and do not carry any data. So, using 72-bit memo-
ry modules does not give you any boost in pertormance.
In tact, because the memory controller has to calculate the LCC code tor e:er data vord that is
read or vritten, there is some pertormance degradation, roughly in the region ot 3-S.1his is
one ot the reasons vhy LCC memory modules are not popular among desktop users .1hrov in
the tact that LCC memory modules are both expensive and hard to come by, and you have the
top three reasons vhy LCC memory modules vill never be mainstream solutions.
It you are using standard 64-bit memory modules, you must select the Non-LCC option.
Hovever, it you have already torked out the money tor 72-bit LCC memory modules, you
should enable the LCC teature, no matter vhat people say about losing some memory per-
tormance. It doesn`t make sense to buy expensive LCC memory modules and then disable
LCC' Pemember, you are not really losing pertormance.You are just trading it tor greater sta-
bility and data integrity.
DRAM Idlo linor
Connon Options: 01, 81, 161, 641, Intinite, Auto
1his BIOS teature sets the number ot idle cycles alloved betore the memory controller torces
such open pages to clos e and precharge.
1he premise behind this BIOS teature is the concept ot tenporal locality.According to this
concept, the longer the open page is lett idle, the less likely it vill be accessed again betore it
needs to be precharged.1heretore, it is better to prematurely close and precharge the page, so it
can be opened quickly vhen a data request comes along.
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It can be set to a variety ot clock cycles trom 01 to 641. 1his sets the number ot clock cycles
the open pages are alloved to idle betore they are closed and precharged. An Infinite option is
available as vell as an Auto option.
It you select 0 Cycle, then the memory controller immediately precharges the open pages as
soon as there`s an idle cycle.
It you select Infinite, the memory controller never precharges the open pages prematurely. 1he
open pages are lett activated until they have to be precharged.
It you select Auto, the memory controller uses the manutacturer`s preset detault setting.
Most manutacturers use a detault value ot 81, vhich allovs the memory controller to
precharge the open pages atter eight idle cycles have passed.
lor general desktop use, it is recommended that you choose the Infinite option, so precharging
can be delayed tor as long as possible.1his reduces the number ot retreshes and increases the
ettective memory bandvidth.
lor applications (tor example, servers, that pertorm a lot ot random accesses, it is advisable that
you select 01 because subsequent data requests most likely vill be tultilled by other pages.
Closing open pages to precharge prepares those pages tor the next data request that hits them.
Increased data integrity is an added benetit ot having more trequent retreshes.
DRAM Intorloovo lino
Connon Options: 0ms, 0.3ms
1his BIOS teature determines the amount ot aooitionai delay betveen successive bank accesses
vhen the SDRAM Bank Interleave teature has been enabled. Naturally, the shorter the
delay, the taster the memory module can svitch betveen banks and, consequently, increases
pertormance.
1heretore, it is recommended that you set the DRAM Interleave 1ine as lov as possible tor
better memory pertormance. In this case, it is 0ns, vhich introduces no additional delay
betveen bank accesses. Increase the DRAM Interleave 1ine to 0.Sns only it you experience
instability vith the 0ms setting.
DRAM Pogo-Modo
1his BIOS teature controls the page mode operation ot the memory subsystem.
When enabled, the activated rov is held open to allov multiple memory accesses to the same
memory rov.
When disabled, the activated rov is closed right atter a single memory access. Subsequent
memory accesses to that rov vill require re-activation ot the rov.
It is highly recommended that you enable this BIOS teature tor much better memory
pertormance.
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DRAM ProChrg to Act CMD
Connon Options: 21, 31, 41
Iike SDRAM 1rp 1ining Value, this BIOS teature controls the RAS precharge tine
(tRP,. 1his constitutes the time it takes tor the Precharge command to complete and the rov to
be available tor activation. Hence, the name DRAM PreChrg to Act CMD, vhich is short
tor DRAM Precharge Connand to Activate Connand.
It the PAS precharge time is too long, it reduces pertormance by delaying all rov activations.
Peducing the precharge time to 21 improves pertormance by alloving a nev rov to be acti-
vated earlier.
Hovever, the short precharge time ot 21 may be insutticient tor some memory modules. In
such cases, the active rov may lose its contents betore they can be returned to the memory
bank and the rov deactivated.1his may cause data loss or corruption vhen the memory con-
troller attempts to read trom or vrite to the active rov.
1heretore, it is recommended that you reduce the PAS precharge time to 21 tor better per-
tormance but increase it to 3T or 4T it you experience system s tability issues atter reducing the
precharge time.
DRAM Rotio (CPU:DRAM)
Connon Options: 1:1, 3:2, 3:4, 4:3, 3:4
1he choice ot options in this BIOS teature depends entirely on the setting ot the DRAM
Ratio H/W Strap or N/B Strap CPU As BIOS teature.
When DRAM Ratio H/W Strap has been set to Lov, the available options are 1:1 and 3:4.
When DRAM Ratio H/W Strap has been set to High, the available options are 1:1 and 4:S.
When N/B Strap CPU As has been set to PSB800, the available options are 1:1, 3.2, and
S:4.
When N/B Strap CPU As has been set to PSBS33, the available options are 1:1 and 4:S.
When N/B Strap CPU As has been set to PSB400, the only available option is 3:4.
1he options ot 1:1, 3:2, 3:4, and 4:S reter to the available CPL-to-DPAM (or CPL:DPAM,
ratios.
Please note that vhile the Pentium 4 processor is said to have a 400MHz, 333MHz, or 800MHz
FSB (front side bus,, the tront side bus (also knovn as CPL bus, is actually only running at
100MHz, 133MHz, or 200MHz, respectively.1his is because the Pentium 4 bus is a Quad
Data Rate or QDR bus, vhich transters tour times as much data as a single data rate bus.
lor marketing reasons, the Pentium 4 bus is labeled as running at 400MHz, 333MHz, or
800MHz vhen it is actually running at only 100MHz, 133MHz, and 200MHz, respectively. It is
important to keep this in mind vhen setting this BIOS teature.
lor example, it you set a 3:2 ratio vith a 200MHz (800MHz QDP, CPL bus , the memory bus
runs at (200MHz 3, x 2 = 133MHz or 266MHz DDR.
By detault, this BIOS teature is set to By SPD. 1his allovs the chipset to query the SPD
(Serial Presence Detect, chip on every memory module and use the appropriate ratio.
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It is recommended that you select the ratio that allovs you to maximize your memory modules`
capabilities. Hovever, bear in mind that a synchronous operation using the 1:1 ratio is also
highly desirable because it allovs a high throughput.
DRAM Rotio H/W Strop
Connon Options: High, Iov, By CPL
1his BIOS teature allovs you to circumvent the CPL-to-DPAM ratio limitation tound in the
never Intel i843-series ot chipsets. In those chipsets, Intel has chosen to limit the choices ot
available CPL-to-DPAM ratios.
When a 400MHz FSB processor is installed, the choices ot CPL-to-DPAM ratio are limited
to 1:1 or 3:4.
When a S33MHz FSB processor is installed, the choices ot CPL-to-DPAM ratio are limited
to 1:1 or 4:S.
lortunately, this BIOS teature allovs you to circumvent that limitation.
1he DRAM Ratio H/W Strap BIOS teature actually controls the setting ot the external
hardvare reset strap assigned to the MCH (Menory Controller Hub, ot the chipset. By set-
ting it High or Lov, you can trick the chipset into thinking that the 400MHz FSB or the
S33MHz FSB is being us ed.
When this BIOS teature is set to High, you are able to access the S33MHz CPL-to-DPAM
ratios ot 1:1 and 4:S.
When this BIOS teature is set to Lov, you are able to access the 400MHz CPL-to-DPAM
ratios ot 1:1 and 3:4.
By detault, this BIOS teature is set to By CPU, vhereby the hardvare strap is set according to
the actual lSB rating ot the processor.
Generally, you do not need to manually adjust the hardvare strap setting. Hovever, it you
require access to the CPL-to-DPAM ratio that vould normally not be available to you, then
this BIOS teature vould be very helptul indeed.
DRAM Rood Lotch Doloy
1his BIOS teature is similar to the Delay DRAM Read Latch BIOS teature. It tine-tunes the
DPAM loading increases as the number ot memory modules increase. It also increases it you
use, the greater the DPAM loading.
the manutacturer.
0AM cad LaIch 0c|ay 1
D
delay.
DPAM device in your particular situation. Don`t unnecessarily increase the delay. Start vith
0.Sns and vork your vay up until your system stabilizes.
No Delay option. It your system becomes unstable atter using the No Delay option, simply
revert back to the detault value ot Auto so that the BIOS can adjust the read latch delay to suit
the DPAM load.
DRAM RoIrosh Roto
Connon Options: 7.8 sec, 13.6 sec, 31.2 sec, 64 s ec, 128 sec,Auto
1his BIOS teature allovs you to set the retresh interval ot the memory chips.1here are three
ditterent settings as vell as an Auto option. It the Auto option is selected, the BIOS queries the
memory modules` SPD chips and uses the lovest setting tound tor maximum compatibility.
lor better pertormance, you should consider increasing the DRAM Refresh Rate trom the
detault values (13.6 s ec tor 128Mbit or smaller memory chips and 7.8 sec tor 236Mbit or
larger memory chips, up to 128 sec. Please note that it you increase the DRAM Refresh
Rate too much, the memory cells may lose their contents.
1heretore, you should start vith small increases in the DRAM Refresh Rate and test your
system atter each hike betore increasing it turther. It you tace stability problems atter increasing
the retresh interval, reduce the retresh interval step by step until the system is stable.
Duplo Soloct
Connon Options: lull-Duplex, Halt-Duplex
1his BIOS teature allovs you to determine the transmission mode ot the IR (Infra-Red, com-
munications port.
Selecting Full-Duple permits simultaneous tvo-vay transmis sion, like a conversation over the
phone.
Selecting Half-Duple, on the other hand, only permits transmission in one direction at any
one time, vhich is more like a conversation over a valkie-talkie.
Naturally, the Full-Duple mode is the taster and more desirable choice.You should use Full-
Duple it possible.
Consult your IP peripheral`s manual to determine vhether it supports Full-Duple transmis-
sion.1he IP peripheral must support Full-Duple tor this option to vork.
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LCP Modo Uso DMA
Connon Options: Channel 1, Channel 3
1his BIOS teature determines vhich DMA channel the parallel port should use vhen it is in
LCP mode.
1he LCP mode uses the DMA protocol to achieve data transter rates ot up to 2.S Mbits/s and
provides symmetric bidirectional communications. lor all this, it requires the use ot a DMA
channel.
By detault, the parallel port uses DMA Channel 3 vhen it is in LCP mode.1his vorks tine in
most situations.
1his teature vas provided just in case one ot your add-on cards requires the use ot DMA
Channel 3. In such a case, you can use this BIOS teature to torce the parallel port to use the
alternate DMA Channel 1.
Please note that there is no pertormance advantage in choosing DMA Channel 3 over DMA
Channel 1 or vice versa. As long as either Channel 3 or Channel 1 is available tor your parallel
port to use, the parallel port is able to tunction properly in LCP mode.
LPP Modo Soloct
Connon Options: LPP 1.7, LPP 1.9
1here are tvo versions ot the LPP transter protocolLPP 1.7 and LPP 1.9. 1his BIOS tea-
ture allovs you to select the version ot LPP that the parallel port should use.
Generally, LPP 1.9 is the preterred setting because it supports the never LPP 1.9 devices and
most LPP 1.7 devices and otters advantages like support tor longer cables. Hovever, because
certain LPP 1.7 devices cannot vork properly vith an LPP 1.9 port, this BIOS teature vas
implemented to allov you to set the LPP mode to LPP 1.7 vhen s uch an issue crops up.
1heretore, it is recommended that you set this BIOS teature to LPP 1.9. Hovever, it you have
trouble connecting to your parallel port device, svitch to LPP 1.7.
LPP Modc Sc|ccI 8
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Iost R-W lurn Around
When the memory controller receives a vrite command immediately atter a read command,
an additional period ot delay is normally introduced betore the vrite command is actually
initiated.
As its name suggests, this BIOS teature allovs you to skip that delay. 1his improves the vrite
pertormance ot the memory subsystem. 1heretore, it is recommended that you enable this tea-
ture tor taster read-to-vrite turnarounds.
Hovever, not all memory modules can vork vith the tighter read-to-vrite turn-around. It
your memory modules cannot handle the taster turn-around, the data that vas vritten to the
memory module may be lost or become corrupted. So, vhen you tace stability issues, disable
this teature to correct the problem.
Iost Writo to Rood lurnoround
1his BIOS teature controls the Write Data In to Read Connand Delay (tW1R, memo-
ry timing.1his constitutes the minimum number ot clock cycles that must occur betveen the
last valid urite operation and the next reao command to the sane internal bank ot the DDP
device.
Lnabling this BIOS teature naturally allovs taster svitching trom vrites to reads and conse-
quently better read pertormance.
Disabling this BIOS teature reduces read pertormance but it vill improve stability, especially at
higher clock speeds. It may also allov the memory chips to run at a higher speed. In other
vords, increasing this delay may allov you to overclock the memory module higher than is
normally possible.
It is recommended that you enable this BIOS teature tor better memory read pertormance it
you are using DDP266 or DDP333 memory modules.You can also try enabling it vith
DDP400 memory modules. But it you tace stability issues, revert to the detault setting ot
Disabled.
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Iirst Boot Dovico
Connon Options: lloppy, ISZIP, HDD-0, SCSI, CDPOM, HDD-1, HDD-2, HDD-3,
IAN, Disabled
1his BIOS teature allovs you to select the first device trom vhich the BIOS attempts to load an
operating system. It the BIOS tinds and loads an operating system trom the device selected
through this teature, it doesn`t load another operating system, even it you have one on a ditter-
ent device.
By detault, Floppy is the tirst boot device in practically all motherboards.Lnless you boot otten
trom the tloppy drive, it is better to set your hard disk (usually HDD-0, as the tirst boot device.
1his shortens the booting process because the BIOS no longer needs to check the tloppy drive
tor a bootable operating system.
1o install operating systems that come on bootable CD-POMs (tor example, Microsott
Windovs XP, in a nev hard dis k, you need to select CDROM as the tirst boot device.1his
enables you to boot directly trom the CD-POM and load the operating system`s installation
routine.
Ilosh BIOS Protoction
1he Flash BIOS Protection teature is a sottvare toggle that controls vrite access to the
BIOS. When it is enabled, the BIOS code is vrite-protected and cannot be changed.1his pro-
tects it trom any attempt to modity it, including BIOS updates and virus attacks. 1heretore, it
you intend to update the BIOS, you`ll need to disable this teature tirst.
It is highly recommended that you enable this teature at all times.You should only disable it
vhen you intend to update the BIOS. Atter updating the BIOS, you should immediately re-
enable it to protect the BIOS against virus es.
Iloppy 3 Modo Support
Connon Options: Disabled, Drive A, Drive B, Both
lor reasons best knovn to the apanese, their computers come vith special 3 mode 3.3 tloppy
drives.While physically similar to the standard 3.3 tloppy drives used by the rest ot the vorld,
these 3 mode tloppy drives ditter in the disk tormats they support.
Lnlike normal tloppy drives, 3 mode tloppy drives support three ditterent tloppy disk tormats
1.44MB, 1.2MB, and 720KB, hence, their name.1hey allov the sys tem to support the apanese
1.2MB tloppy disk tormat as vell as the s tandard 1.44MB and 720KB (obsolete, disk tormats.
It you ovn a 3 mode tloppy drive and need to use the apanese 1.2MB disk tormat, you must
enable this teature by selecting either Drive A, Drive B, or Both (it you have tvo 3 mode
tloppy drives,. Othervise, your 3 mode tloppy drive von`t be able to read the special 1.2MB
tormat properly.
Hovever, it you only have a standard tloppy drive, disable this teature or your tloppy drive may
not tunction properly.
F|oppy 3 Modc SupporI 6
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Iloppy Disk Accoss Control
Connon Options: PW, Pead Only
1his BIOS teature controls vrite access to the tloppy drive.
Setting this BIOS teature to R/W (Read/Write, allovs tull access to the tloppy drive.You vill
be alloved to vrite to tloppy disks as vell as read trom them.
Setting this BIOS teature to Read Only prevents vrite access to the tloppy drive.You vill be
alloved to read trom tloppy disks but you cannot vrite to them.
It is recommended that you set this BIOS teature to R/W, so you have tull access to the tloppy
drive. Set it to Read Only it you do not vish to provide vrite access to the tloppy drive.
Iorco 4-Woy Intorloovo
1his BIOS teature allovs you to torce the memory controller to use the 4-bank SDPAM
interleave mode, vhich provides better pertormance than the 2-bank interleave mode. Hovever,
you must have at least 4 banks ot memory in the system tor this teature to vork properly.
Normally, SDPAM modules that use 16Mbit memory chips (usually 32MB or smaller in size,
have only tvo memory banks. So, it you are using s uch a small capacity DIMM, you should
disable lorce 4-Way Interleave. It you use tvo or more ot such DIMMs, you can still enable
lorce-4-Way Interleave.
SDPAM modules that use 64Mbit or larger memory chips are tour-banked in nature.1hese
modules are at least 64MB in size. It you are using such tour-banked modules, it no longer mat-
ters it you are using just one module or several ot them.You can enable lorce 4-Way Interleave
vithout tear.
1heretore, it is recommended that you enable this BIOS teature it you are using 4MP or i arer
memor moouies or at ieast tuo '2MP or smai ier memor moouies. Othervise, it is best to disable
this BIOS teature.
lor more intormation on memory bank interleaving, you should check out the details ot the
SDRAM Bank Interleave BIOS teature.
Iorco Updoto LSCD
It you install a nev piece ot hardvare or modity your computer`s hardvare contiguration, the
BIOS automatically detects the changes and recontigures the LSCD (Ltended Systen
Configuration Data,. 1heretore, there is usually no need to manually torce the BIOS to
recontigure the LSCD.
Hovever, the occasion may arise vhere the BIOS may not be able to detect the hardvare
changes. A serious resource contlict may occur and the operating system may not even boot
as a result.1his is vhere the Force Update LSCD BIOS teature comes in.
LhapIcr 3 0uck cvcws
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1his BIOS teature allovs you to manually torce the BIOS to clear the previously saved LSCD
data and recontigure the settings. All you need to do is enable this BIOS teature and then
reboot your computer.1he nev LSCD should resolve the contlict and allov the operating sys-
tem to load normally.
Please note that the BIOS automatically resets it to the detault setting ot Disabled atter recon-
tiguring the nev LSCD. So, there is no need tor you to manually disable this teature atter
rebooting.
IPU OPCODL Conpotiblo Modo
1his BIOS teature determines hov Pentium 4 and Xeon processors handle lOP codes using
the FOP (final opcode, register.
When enabled, the Pentium 4 and Xeon engage the lOP code compatibility mode, vhich
stores the lOP ot the last non-transparent instruction in the lOP register.
When disabled, the Pentium 4 and Xeon turn ott the lOP code compatibility mode and store
only the lOP ot the last non-transparent tloating point instruction that hao an unmaskeo excep
tion. 1his allovs tor better lPL pertormance.
1heretore, it is recommended that you disable this teature tor better lPL pertormance unless
your sottvare requires this teature to recover trom lPL exceptions.
Irono BuIIor Sizo
Connon Options: 1MB, 4MB, 8MB, 16MB, 32MB, 64MB
1his BIOS teature controls the amount ot system memory that is allocated to the integrated
GPL.
1he selection ot memory sizes allovs you to select hov much system memory you vant to
allocate to the integrated GPL.1he amount you allocate to the GPL is deducted trom the
amount ot system memory available to your operating system and programs.
Please note that unlike the AGP Aperture Size, once the system memory is allocated to the
GPL, it cannot be used by anything else. Lven it the GPL does not make use ot it, it is not
available to the operating system.
1heretore, it is recommended that you select the absolute minimum amount ot system memory
that the GPL requires tor your monitor.You can calculate it by multiplying the resolution and
color depth that you are using.
lor example, it you use a resolution ot 1600 1200 and a color depth ot 32-bit, the amount ot
memory your GPL requires vill be 1600 1200 32-bits = 61,440,000 bits, or 7.68MB.You
should set this BIOS teature to 8MB in this example.
Framc 8uffcr Szc 7
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ISB Sprood Spoctrun
1his BIOS teature allovs you to reduce the LMI ot the front side bus (also knovn as the
FSB or processor bus, by modulating the signals it generates, so the spikes are reduced to tlatter
curves. It achieves this by varying the trequency slightly, so the signal does not use any particular
trequency tor more than a moment.
1he BIOS usually otters tvo levels ot modulation0.S or 1.0.1he greater the modula-
tion, the greater the reduction ot LMI.1heretore, it you need to signiticantly reduce the tront
side bus LMI, a modulation ot 1.0 is recommended.
In most conditions, trequency modulation through this teature should not cause any problems.
Hovever, system stability may be compromised it you are overclocking the tront side bus. Ot
course, this depends on the amount ot modulation, the extent ot overclocking, and other tactors
like temperature, and so torth. As such, the problem may not manitest itselt immediately.
1heretore, it is recommended that you disable this teature it you are overclocking the tront side
bus.1he risk ot crashing your system is not vorth the reduction in LMI. Ot course, it LMI
reduction is important to you, enable this teature by all means. Hovever, you should reduce the
Lnless you have LMI problems or sensitive data that must be sateguarded trom electronic eaves-
dropping, it is best to disable this teature to remove the possibility ot stability issues.
Iull Scroon Logo
1his BIOS teature determines vhether the motherboard or system manutacturer`s logo appears
instead ot the usual boot-up screen.
When it is enabled, the BIOS displays the tull-screen logo during the boot-up sequence.
When it is disabled, the BIOS dis plays the usual boot-up screen instead ot the tull-screen logo.
Please note that enabling this BIOS teature otten adds 23 seconds ot delay to the booting
sequence. 1his delay ensures that the logo is displayed tor a sutticient amount ot time.
1heretore, it is recommended that you disable this BIOS teature tor a taster boot-up time.
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Goto A20 Option
Connon Options: Normal, last
1his BIOS teature is used to determine the method by vhich Gate A20 is controlled.1he
Nornal option torces the chipset to use the slov keyboard controller to do the svitching.1he
Fast option, on the other hand, allovs the chipset to use its ovn 0x92 port tor taster svitching.
No candy tor guessing vhich is the recommended setting'
Please note this teature is only important tor operating systems that svitch a lot betveen real
mode and protected mode.1hese operating systems include 16-bit operating systems, such as
MS-DOS and 16-bit32-bit hybrid operating systems like Microsott Windovs 98.
1his teature has no ettect it the operating system only runs in real mode (no operating system
currently in use does that, as tar as I knov',, or it the operating system operates entirely in pro-
tected mode (tor example, Microsott Windovs XP,.1his is because it A20 mode svitching is
not required, then it does not matter at all it the svitching vas done by the slov keyboard con-
troller or the taster 0x92 port.
With all that said and done, the recommended setting tor this BIOS teature is still Fast, even
vith operating systems that don`t do much mode svitching.Although using the 0x92 port to
control Gate A20 has been knovn to cause spontaneous reboots in very rare instances, there is
really no reason vhy you should keep using the slov keyboard controller to turn A20 on or ott.
Grophic Win Sizo
Connon Options: 4, 8, 16, 32, 64, 128, 236
1his BIOS teature does tvo things. It selects the size ot the AGP aperture (hence, the name
Graphic Windovs Size,, and it determines the size ot the GAR1 (Graphics Address
Relocation 1able,.
addresses into actual memory addresses, vhich are otten tragmented.1he GAP1 allovs the
graphics card to see the memory region available to it as a contiguous piece ot memory range.
Host cycles that hit the aperture range are torvarded to the AGP bus vithout need tor transla-
tion.1he aperture size also determines the maximum amount ot sys tem memory that can be
be haif the size ot system memory, that is uron'
0raphc Wn Szc 0
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LhapIcr 3 0uck cvcws
1he requirement tor AGP memory space shrinks as the graphics card`s local memory increases in
size.1his is because the graphics card has more local memory to dedicate to texture storage. So,
it you upgrade to a graphics card vith more memory, you shouldn`t be deceived into thinking
that you need even more AGP memory' On the contrary, a smaller AGP memory space is
required.
size.
Grophic Window WR Conbin
1his BIOS teature allovs you to control the USWC (Uncached Speculative Write
Conbining, vrite combine butters. Somehov, they had to give it the badly mangled name ot
Graphic Windov WR Conbin.
It enabled, the vrite combine butters vill accumulate and combine partial or smaller graphics
vrites trom the processor and vrite them to the graphics card as burst vrites.
It disabled, the vrite combine butters vill be disabled. All graphics vrites trom the processor
vill be vritten to the graphics card directly.
It is highly recommended that you enable this teature tor improved graphics and processor
pertormance.
Hovever, it you are using an older graphics card, it may not be compatible vith this teature.
Lnabling this teature vith such graphics cards vill cause a host ot problems, such as graphics
artitacts, system crashes, and even the inability to boot up properly.
It you tace such problems, you should disable this BIOS teature immediately.
Grophics Aporturo Sizo
Connon Options: 4, 8, 16, 32, 64, 128, 236
1his BIOS teature does tvo things: It selects the size ot the AGP aperture, and it determines the
size ot the GAR1 (Graphics Address Relocation 1able,.
memory address space, vhereas the GAP1 is a translation table that translates AGP memory
G
size.1his is because the graphics card vill have more local memory to dedicate to texture stor-
age. So, it you upgrade to a graphics card vith more memory, you shouldn`t be deceived into
thinking that you vill need even more AGP memory' On the contrary, a smaller AGP memory
space vill be required.
actually need extra memory tor texture storage. It vill also keep the GAP1 (Graphics Address
Pelocation 1able, vithin a reas onable size.
0raphcs ApcrIurc Szc 71
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Hordworo Rosot Protoct
1his BIOS teature is very usetul tor tile servers and routers that need to be running 24 hours a
day, 363 days a year. When it is enabled, the hardvare reset button is oisa|ieo.1his prevents the
possibility ot any accidental resets. When disabled, the reset button tunctions as normal.
It you are running a mission-critical server or have kids vho just love to press little red buttons,
it is highly recommended that you enable this teature. Othervise, it is really up to your preter-
ence. Naturally, people using buggy operating s ystems or applications are advised to keep this
teature disabled tor more convenient reboots.
HDD S.M.A.R.l. Copobility
1his BIOS teature controls support tor the hard disk`s S.M.A.R.1. (Self Monitoring
Analysis And Reporting 1echnology, capability.
S.M.A.P.1. is supported by all current hard disks and it allovs the early prediction and varning
ot impending hard disk disasters.You should enable it it you vant to use S.M.A.P.1.-avare
utilities to monitor the hard disk`s condition. Lnabling it also allovs the monitoring ot the hard
disk`s condition over a netvork.
Although S.M.A.P.1. looks like a really great satety teature, it isn`t really that usetul or even
necessary tor most users. lor S.M.A.P.1. to vork, it is not just a matter ot enabling it in the
BIOS.You must also keep a S.M.A.P.1.-avare hardvare monitoring utility running in the
background all the time.
1hat`s quite alright it the hard disk you are us ing has a spotty reputation and you need advanced
varning ot any impending tailure. Hovever, hard disks these days are mostly reliable enough to
make S.M.A.P.1. redundant. Lnless you are running mission-critical applications, it is very
unlikely that S.M.A.P.1. vill be ot any use at all.
With that said, S.M.A.P.1. is still usetul in providing a modicum ot data loss prevention by con-
tinuously monitoring hard disks tor signs ot impending tailure. It you have critical or irreplace-
able data, you should enable this BIOS teature and use a S.M.A.P.1.-avare hardvare
monitoring sottvare. ust don`t rely completely on it' Back up your data on a CD or DVD'
Please note that even it you do not use any S.M.A.P.1.-avare utility, enabling S.M.A.P.1. in
the BIOS uses up some bandvidth because the hard disk continuously sends out data packets.
So, it you do not use S.M.A.P.1.-avare utilities, or it you do not need that level ot real-time
reporting, disable HDD S.M.A.P.1. Capability tor better overall pertormance.
H
Some ot the never BIOSes nov come vith S.M.A.P.1. monitoring support built-in.When
you enable HDD S.M.A.P.1. Capability, these nev BIOSes automatically check the hard disk`s
S.M.A.P.1. status at boot-up. Hovever, such a teature has very limited utility because it can only
tell you the status ot the hard disk at boot-up. 1heretore, it is still advisable tor you to disable
HDD S.M.A.P.1. Capability unless you use a proper S.M.A.P.1.-avare monitoring utility.
Host Bus In-Ordor Quouo Dopth
1his BIOS teature controls the use ot the processor bus command queue. Normally, there are
only tvo options available. Depending on the motherboard chipset, the options could be
(1 and 4,, (1 and 8,, or (1 and 12,.
1he tirst queue depth option is alvays 1, vhich prevents the processor bus pipeline trom queu-
ing any outstanding commands. It selected, each command only is issued atter the processor has
tinished vith the previous one.1heretore, every command incurs the maximum amount ot
latency. 1his varies trom 4 clock cycles tor a 4-stage pipeline to 12 clock cycles tor pipelines
vith 12 stages.
In most cases, it is highly recommended that you enable command queuing by selecting the
option ot 4 8 12 or, in some cases, Lnabled.1his allovs the processor bus pipeline to mask
its latency by queuing outstanding commands.You can expect a signiticant boost in pertorm-
ance vith this teature enabled.
Interestingly, this teature can also be used as an aid in overclocking the processor.Although the
queuing ot commands brings vith it a big boost in pertormance, it may also make the processor
unstable at overclocked speeds. 1o overclock beyond vhat`s normally possible, you can try dis-
abling command queuing.
But please note that the pertormance deticit as sociated vith deeper pipelines (8 or 12 stages,
may not be vorth the increase in processor overclockability.1his is because the deep processor
bus pipelines have very long latencies. It they are not masked by command queuing, the proces-
sor may be stalled so badly that you end up vith poorer pertormance, even it you are able to
turther overclock the process or. So, it is recommended that you enable command queuing tor
deep pipelines, even it it means reduced overclockability.
Hypor-lhrooding lochnology
1his BIOS teature controls the tunctionality ot the Intel Hyper-1hreading 1echnology.
1he Intel Hyper-1hreading 1echnology allovs a single processor to execute tuo or more sep-
arate threads concurrently. When hyper-threading is enabled, multi-threaded sottvare applica-
tions can execute their threads in parallel, thereby improving their pertormance.
An Intel processor that supports Hyper-1hreading
hypcr-Jhrcadng Jcchno|ogy 78
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A motherboard vith a chipset and BIOS that support Hyper-1hreading
An operating system that supports Hyper-1hreading ( Microsott Windovs XP or Iinux
2.4.x,
It is highly recommended that you enable Hyper-1hreading 1echnology tor improved proces-
sor pertormance.
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IDL Bus Mostor Support
1his BIOS teature is a misnomer because it doesn`t actually control the bus mastering ability ot
the onboard IDL controller. It is actually a toggle tor the built-in driver that allovs the onboard
IDL controller to pertorm DMA (Direct Menory Access, transters.
When this BIOS teature is enabled, the BIOS loads up the 16-bit busmastering driver tor the
onboard IDL controller. 1his allovs the IDL controller to transter data through DMA, resulting
in greatly improved transter rates and lover CPL utilization in real-mode DOS and during the
loading ot other operating systems.
When this BIOS teature is disabled, the BIOS vill not load up the 16-bit busmastering driver
tor the onboard IDL controller. 1he IDL controller then transters data through PIO
(Progranned Input/Output).
1heretore, it is recommended that you enable IDL Bus Mas ter Support.1his greatly improves
the IDL transter rate and reduces CPL utilization during the booting process or vhen you are
using real-mode DOS. Lsers ot DOS-based dis k utilities, such as Norton Ghost, can expect to
benetit a lot trom this teature.
IDL HDD Block Modo
1his BIOS teature speeds up hard disk access by transterring multiple sectors ot data per inter-
rupt instead ot using the usual single-sector transter mode. 1his mode ot transterring data is
knovn as block transters.
When you enable this teature, the BIOS automatically detects vhether your hard disk supports
block transters and sets the proper block transter settings tor it. Depending on the IDL con-
troller, up to 64KB ot data can be transterred per interrupt vhen block transters are enabled.
Because all current hard disks support block transters, there is usuaii no reason vhy IDL HDD
Block Mode should be disabled.
Please note that it you disable IDL HDD Block Mode, only S12 bytes ot data can transter per
interrupt. Needless to say, this s igniticantly degrades pertormance.
1heretore, you should disable IDL HDD Block Mode oni it you actually tace the possibility
ot data corruption (vith an unpatched version ot Windovs N1 4.0,. Othervise, it is highly rec-
ommended that you enable this BIOS teature tor signiticantly better hard disk pertormance'
I0L h00 8|ock Modc 76
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Init Disploy Iirst
Connon Options: AGP, PCI
1his BIOS teature allovs you to select vhether to boot the system using the AGP graphics card
or the PCI graphics card.1his is particularly important it you have AGP and PCI graphics cards
but only one monitor.
It you are only using a single graphics card, then the BIOS detects it as such and boots it up,
irrespective ot vhat you set the teature to. Hovever, there may be a slight reduction in the time
taken to detect and initialize the card it you select the proper setting tor this BIOS teature. lor
example, it you only use an AGP graphics card, then setting Init Display First to AGP may
speed up your system`s booting-up process .
1heretore, it you are only using a single graphics card, it is recommended that you set the Init
Display lirst teature to the proper setting tor your system (AGP tor a single AGP card and PCI
tor a single PCI card,.
Hovever, it you are using multiple graphics cards, it is up to you vhich card you vant to use as
your primary display card. It is recommended that you select the tastest graphics card as the pri-
mary display card.
In-Ordor Quouo Dopth
only tvo options available. Depending on the motherboard chipset, the options could be (1 and
4,, (1 and 8,, or (1 and 12,.
vith 12 stages.
Interestingly, this teature also can be used as an aid in overclocking the processor.Although the
Hovever, please note that the pertormance deticit associated vith deeper pipelines (8 or 12
stages, may not be vorth the increase in processor overclockability.1his is because the deep
processor bus pipelines have very long latencies. It they are not masked by command queuing,
the processor may be stalled so badly that you may end up vith poorer pertormance even it you
are able to turther overclock the processor. So, it is recommended that you enable command
queuing tor deep pipelines, even it it means reduced overclockability.
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Intorrupt Modo
Connon Options: PIC, APIC
Progrannable Interrupt Controller,.1he APIC provides multiprocessor support, more
IPQs, and taster interrupt handling.
Hovever, it is only supported by never operating systems like Microsott Windovs N1,
Windovs 2000, and Windovs XP. Older operating systems like DOS or Windovs 9398 do not
support this teature.
It is recommended that you select APIC it you are using a never operating system like
Windovs XP. Select PIC only it you are using an older operating system like DOS or
Windovs 9398.
IOQD
(1 and 4,, (1 and 8,, or (1 and 12,.
vith 12 stages.
I000 77
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ISA 14.318MHz Clock
1his BIOS teature allovs you to overclock the ISA bus using the reterence clock generator
speed ot 14.318MHz. 1his greatly improves the ISA bus speed by running the bus 72 taster
than normal.At this clock speed, 8-bit cards have a bandvidth ot 7.16MB/s vhile 16-bit cards
have a bandvidth ot 14.32MB/s.
In most cases, it is recommended that you enable this teature to give the ISA bus a pertorm-
ance boost. Ot course, this is only usetul it you have ISA devices in your system. Othervise, this
teature is redundant.
Please note that vhile never ISA cards are capable ot running at this out-ot-specspeed, older
ones may not vork properly at this speed. 1heretore, it your ISA card tails to tunction properly,
disable this teature.
ISA Lnoblo Bit
1his BIOS teature allovs you to determine it the system controller vill pertorm ISA aliasing to
prevent contlicts betveen ISA devices.
1he detault setting ot Lnabled torces the system controller to alias ISA addresses using address
bits [13:10| .1his restricts all 16-bit addressing devices to a maximum contiguous IO space ot
236 bytes.
tull 64KB IO space.
It is recommended that you disable ISA Lnable Bit tor optimal AGP (and PCI, pertormance.
It also prevents your AGP or PCI cards trom contlicting vith your ISA cards. Lnable it only it
you have ISA devices that are contlicting vith each other.
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R1 CLR_ClL Soloct
Connon Options: Detault, Optimal
As the name suggests, this is an AMD-specitic BIOS teature. It controls the Clock Control
(CLK_C1L, Model Specific Register (MSR,, vhich is part ot the AMD Athlon`s pover
management control system.
Nov, unlike the Intel Pentium 4 processor, the Athlon processor saves pover by actually reduc-
ing its internai clock speed. 1he Athlon bus clock speed remains constant but by using an inter-
nal clock divider, the Athlon processor can reduce its internal clock speed to 1/64th (Palomino
cores and older, or 1/8th (1horoughbred cores and never, ot its nominal clock speed.
1he older Athlons have a bug (Lrrata No. 11, called ILL :ershoot on 1akep from Disconnect
Causes utoCompensation Circuit to Iaii .What happens is the processor can sometimes overshoot
the nominal clock speed vhen it ramps up atter a pover-saving sess ion.1his causes a reduction
in the Athlon bus IO drive strength levels, vhich the auto-compensation circuitry attempts to
correct. Hovever, because there is not enough time, the proper drive strengths cannot be
attained betore the processor reconnects to the system bus. 1his causes the system bus to tail,
vhich results in a system hang.
1his bug is particularly prominent in the older Athlons that use the 164 internal divider
because they normally require a longer ramp-up time, vhich increases the chance tor the
processor to overshoot the nominal clock speed. Hence, a vorkaround tor this bug vas devised
vhereupon the BIOS manually reprograms the CIK_C1I register to reouce the ramp-up time.
By detault, the BIOS programs the CIK_C1I register vith a value ot 6003_1223h during the
POS1 routine.1o increase the ramp-up speed, the BIOS has to change the value to
2003_1223h.
1his is vhere the K7 CLK_C1L Select BIOS teature comes in.When set to Default, the
BIOS programs the CIK_C1I register vith a value ot 6003_1223h. Setting to Optinal causes
the BIOS to program the CIK_C1I register vith a value ot 2003_1223h.
It you are using an AMD Athlon processor vith a Iaiomino or oioer core, it is recommended that
you set K7 CLK_C1L Select to Optinal.1his prevents Lrrata No. 11 trom manitesting itselt
and may even provide a speed boost by alloving the processor to disconnect and connect to the
system bus taster.
lrom the 1horoughbred-A core (CPLID 680, onvard, AMD started using an internal clock
divider ot only 1/8 vith the CIK_C1I value ot 6003_1223h.1his neatly circumvents the
Lrrata No. 11 problem, although AMD also corrected that bug.With such processors, the
CIK_C1I should be set to the Default value ot 6003_1223h.
Lntortunately, AMD then did an about-tace vith the 1horoughbred-B core (CPLID 681, and
changed the value associated vith the 1/8 divider trom 6003_1223h to 2003_1223h. Lnless the
BIOS vas updated to recognize this ditterence, it probably vould vrite the 6003_1223h value
k1 LLk_LJL Sc|ccI 70
K
used tor the 1horoughbred-A core into the register instead ot the correct 2003_1223h required
by the 1horoughbred-B core.When this happens, the processor may become unstable during
transitions trom sleep mode to active mode.
1heretore, tor 1horoughbred-B cores and above, you should set the K7 CLK_C1L Select
BIOS teature to the Optinal setting to ensure proper setting ot the internal clock divider.
RBC Input Clock Soloct
Connon Options: 8MHz, 12MHz, 16MHz
1he PS2 keyboard communicates vith the keyboard controller on the motherboard through a
serial data link.1he speed ot the data link depends on the clock signal generated by the key-
board controller.1he higher the clock speed, the taster the keyboard intertace.1his translates
into a more responsive keyboard, although not all keyboards can vork vith higher clock speeds.
1his BIOS teature allovs you to adjust the keyboard intertace clock tor a better response or to
tix a keyboard problem. It is recommended that you select the 16MHz option tor a better key-
board response. Hovever, it the keyboard pertorms erratically or tails to initialize, try a lover
clock speed.
Royboord Auto-Ropoot Doloy
Connon Options: 14 Sec, 12 Sec, 34 Sec, 1 Sec
1his BIOS teature determines hov long, in tractions ot a second, the keyboard controller vaits
betore it starts repeating the keystroke that you have pressed continuously.1he longer the delay,
the longer the keyboard controller vaits betore it starts repeating the keys troke.
Generally, using a short delay is usetul tor people vho type quickly and don`t like to vait long
tor a keystroke to be repeated. On the other hand, a long delay is usetul tor us ers vho tend to
press the keys longer vhile typing.1his prevents the keyboard controller trom unnecessarily
repeating keystrokes vith such users.
Royboord Auto-Ropoot Roto
Connon Options: 6Sec, 8Sec, 10Sec, 12Sec, 20Sec, 24Sec, 30Sec
1his BIOS teature determines the rate at vhich the keyboard repeats a keystroke it you press it
continuously.
1he available settings are in characters per second.1heretore, a typematic rate ot 30/Sec
causes the keyboard to repeat the keystroke at a rate ot 30 characters per second it you press a
particular key continuously. 1he higher the typematic rate, the taster the keyboard repeats the
keystroke.
1he choice ot vhat setting to use is entirely up to your personal preterence. Please note that
this typematic rate is only applicable in operating systems that communicate vith the hardvare
through the BIOS, like MS-DOS. 1he typematic rate in operating systems like Windovs XP is
controlled by the keyboard driver`s settings .
K
L
L3 Cocho
cache and relies only on the Ievel 1 and Ievel 2 caches.1his reduces the pertormance ot the
processor.
LD-OII Dron RD/WR Cyclos
Connon Options: Delay 11, Normal
1his BIOS teature controls the lead-ott time tor the memory read and vrite cycles.
When set to Delay 11, the memory controller issues the memory address tirst.1he read or
vrite command is issued only atter a delay ot one clock cycle.
When set to Nornal, the memory controller issues both the memory address and readvrite
command simultaneously.
It is recommended that you select the Nornal option tor better pertormance. Select the Delay
11 option only it you have stability issues vith your memory modules.
Lovol 2 Cocho Lotoncy
Connon Options: Auto, 1 to 13
1his BIOS teature enables you to change the latency ot the processor`s Ievel 2 cache. By
detault, this teature is set to Auto, vhich means that the processor`s Ievel 2 cache is lett to its
detault latency setting. 1his is the satest option.
You can als o manually s elect the latency ot the cache. lor this purpose, this BIOS teature pro-
vides options ranging trom 1 clock cycle to 1S clock cycles . Please note that setting the latency
too lov can cause the Ievel 2 cache to lose data integrity or tail altogether. 1his vill manitest as
a system crash or an inability to boot-up altogether.
Lcvc| 2 Lachc LaIcncy 81
I
1heretore, it is recommended that you start vith a high latency and vork your vay dovn until
you start to encounter stability issues.1his allovs you to tigure out the lovest latency your
processor`s Ievel 2 cache can support. Select that latency tor optimal pertormance vithout sta-
bility issues.
Please note that this is a processor-dependent teature. Not all processors support BIOS manipu-
lation ot the Ievel 2 cache latency. It the processor does not allov any manipulation ot its Ievel
2 cache latency, this BIOS teature vill not have any ettect, irrespective ot vhat vas selected.
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Mostor Drivo PIO Modo
Connon Options: Auto, 0, 1, 2, 3, 4
1his BIOS teature allovs you to set the PIO (Progranned Input/Output, mode tor the
Master IDL drive attached to that particular IDL channel.
Setting this BIOS teature to Auto lets the BIOS auto-detect the IDL drive`s maximum sup-
ported PIO mode at boot-up.
Setting this BIOS teature to 0 torces the BIOS to use PIO Mode 0 tor the IDL drive.
Normally, you should leave it as Auto and let the BIOS auto-detect the IDL drive`s PIO mode.
You should only set it manually tor the tolloving reasons:
It the BIOS cannot detect the correct PIO mode
It you vant to try torcing the IDL device to use a taster PIO mode than it vas designed
tor
It you vant to torce the IDL device to use a slover PIO mode it it cannot vork properly
vith the current PIO mode (tor example, vhen the PCI bus is overclocked,
Please note that torcing an IDL device to use a PIO transter rate that is taster than vhat it is
rated tor can potentially cause data corruption.
Mostor Drivo UltroDMA
Connon Options: Auto, Disabled
1his BIOS teature allovs you to enable or disable DMA (Direct Menory Access, support (it
available, tor the Master IDL device attached to that particular IDL channel.
ported DMA mode at boot-up.
Setting this BIOS teature to Disabled torces the BIOS to disable DMA transters tor the IDL
drive.
Normally, you should leave it as Auto and let the BIOS auto-detect the drive`s DMA support.
It the drive supports DMA transters, the proper DMA transter mode is enabled tor that drive,
alloving it to burst data at anyvhere trom 33MBs to 133MBs (depending on the transter
mode supported,.
MasIcr 0rvc u|Ira 0MA 88
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You should only disable it tor troubleshooting purposes. lor example, certain IDL devices may
not run properly using DMA transters vhen the PCI bus is overclocked. Dis abling DMA sup-
port torces the drive to use the slover PIO transter mode.1his may allov the drive to vork
properly vith the higher PCI bus s peed.
Please note that setting this to Auto does not enable DMA transters tor IDL devices that do not
support DMA transters. It your drive does not support DMA transters, the BIOS automatically
sets the drive to do PIO transters only.
Also note that this BIOS teature merely enables DMA transters during the booting up process
and tor operating systems that do not load their ovn drivers tor IDL tunctions. lor operating
systems that use their ovn IDL drivers (tor example,Windovs 9x2000XP,, you have to
enable DMA support tor the drive vithin the operating system as vell.
Mostor Priority Rototion
Connon Options: 1 PCI, 2 PCI, 3 PCI
1his BIOS teature controls the priority ot the processor`s accesses to the PCI bus.
It you choose 1 PCI, the processor alvays grants access right atter the current PCI bus master
completes its transaction, irrespective ot hov many other PCI bus masters are on the queue.
It you choose 2 PCI, the processor alvays grants access right atter the second PCI bus master
on the queue completes its transaction.
It you choose 3 PCI, the processor alvays grants access right atter the third PCI bus master on
the queue completes its transaction.
No matter vhat you choose, the processor is guaranteed access to the PCI bus atter a certain
number ot PCI bus master grants. It doesn`t matter it there are numerous PCI bus masters on
the queue or vhen the processor requests access to the PCI bus.1he processor is alvays granted
access atter one PCI bus master transaction (1 PCI,, tvo transactions (2 PCI,, or three
transactions (3 PCI,.
lor better overall pertormance, it is recommended that you select the 1 PCI option as this
allovs the processor to access the PCI bus vith minimal delay. Hovever, it you vish to improve
the pertormance ot your PCI devices, you can try the 2 PCI or 3 PCI options.1hey ensure
that your PCI cards receive greater PCI bus priority.
MD Driving Strongth
Connon Options: Hi, Io High, Iov
1his BIOS teature otters simplitied control ot the memory data bus driving strength.
1he detault value is Lo or Lov.With heavy DPAM loads, you might vant to set this teature
to Hi or High.
Due to the nature ot this BIOS teature, it is possible to use it as an aid in overclocking the
memory bus.Your memory module may not overclock as vell as you vant it to. By raising the
driving strength ot the memory bus, it is possible to improve its stability at overclocked speeds.
Hovever, this is not a suretire vay ot overclocking the memory bus. All you may get at the end
ot the day is increased LMI and pover consumption.
M
Please note too that increasing the memory bus drive strength does not improve the pertorm-
ance ot your memory subsystem.
1heretore, it is recommended that you leave the MD Driving Strength at its detault Lo or Lov
setting. Set it to Hi or High only it you have a heavy DPAM load or it you are trying to stabi-
lize an overclocked memory module.
Monory Holo At 1$M-1M
Certain ISA cards require exclusive access to the 1MB block ot memory, trom the 13th to the
16th megabyte, to vork properly. 1his BIOS teature allovs you to reserve that 1MB block ot
memory tor such cards to use.
It you enable this teature, 1MB ot memory (the 13th MB, is reserved exclusively tor the ISA
card`s use.1his ettectively reduces the total amount ot memory available to the operating system
by 1MB.
Please note that in certain motherboards, enabling this teature may actually render all memory
above the 13th MB unavailable to the operating system'
It you disable this teature, the 13th MB ot PAM is not reserved tor the ISA card`s use. 1he tull
range ot memory is theretore available tor the operating system to use. Hovever, it your ISA
card requires the use ot that memory area, it may tail to vork.
Because ISA cards are a thing ot the pas t, it is highly recommended that you disable this tea-
ture. Lven it you have an ISA card that you absolutely have to use, you may not actually need to
enable this teature.
Most ISA cards do not need exclusive access to this memory area. Make sure that your ISA card
requires this memory area betore enabling this teature.You should use this BIOS teature only in
a last-ditch attempt to get a stubborn ISA card to vork.
MP Copoblo Bit IdontiIy
1his BIOS teature determines vhether the BIOS should query the MP Capable bit to correctly
identity an AMD Athlon MP processor.
When set to Lnabled, the BIOS vill query the MP Capable bit at boot-up. It it detects a MP
Capable bit setting ot 1, it vrites the Athlon MP processor string name into the appropriate
registers.
When set to Disabled, the BIOS vill not query the MP Capable bit at boot-up.1he Athlon
MP processor vill be indistinguishable trom the Athlon XP processor, as tar as the processor
identitication is concerned.
It you are using an AMD Athlon MP processor, it is recommended that you enable this BIOS
teature to allov proper identitication ot the processor. It you are using other Athlon processors,
you should disable this BIOS teature as the BIOS does not need to query the MP Capable bit
to detect the processor correctly.
MP Lapah|c 8I IdcnIfy 86
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MPS Control Vorsion Ior OS
Connon Options: 1.1, 1.4
1his teature is only applicable to multiprocessor motherboards as it specities the version ot the
Multi-Processor Specification (MPS, that the motherboard uses. 1he MPS is a specitication
by vhich PC manutacturers design and build Intel architecture systems vith tvo or more
processors.
MPS 1.1 vas the original specitication. MPS version 1.4 adds extended contiguration tables tor
improved support ot multiple PCI bus contigurations and greater expandability in the tuture. In
addition, MPS 1.4 introduces support tor a secondary PCI bus vithout requiring a PCI bridge.
It your operating system comes vith support tor MPS 1.4, you should change the setting trom
the detault ot 1.1 to 1.4.You also need to enable MPS 1.4 support it you need to make use ot
the secondary PCI bus on a motherboard that doesn`t come vith a PCI bridge.
You should only leave it as 1.1 it you are running an older operating system that only supports
MPS 1.1.
As tar as Microsott operating systems are concerned,Windovs N12000XP support
MPS 1.4.
Hovever, users ot the ABI1 BP6 motherboard and Windovs 2000 should take note ot a possi-
ble problem vith the MPS version set to 1.4. It you set the MPS version to 1.4 in the ABI1
BP6 motherboard,Windovs 2000 does not use the second processor. So, it you encounter this
problem, set the MPS Version Control lor OS to 1.1.
MPS Rovision
processors.
the secondary PCI bus on a motherboard that doesn`t come vith a PCI bridge.
MPS 1.1.
MPS 1.4.
problem, set the MPS Pevision to 1.1.
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Multi-Soctor lronsIors
Connon Options: Disabled, 2 Sectors, 4 Sectors, 8 Sectors, 16 Sectors, 32 Sectors, Maximum
1here are a tev available options, ranging trom Disabled to Maximum, vith a tev ditterent
multiple sectors options betveen.
1he Disabled option torces your IDL controller to transter only a single sector (312 bytes, per
interrupt. Needless to say, this vill signiticantly degrade pertormance.
1he selection ot 2 Sectors to 32 Sectors allovs you to manually select the number ot sectors
that the IDL controller is alloved to transter per interrupt.
1he Mainun option allovs your IDL controller to transter as many sectors per interrupt as
the hard disk is able to support.
Since all current hard disks support block transters, there is usuaii no reason vhy IDL HDD
ot data corruption (uith an unpatcheo :ersion of 1inoous ^l 4.0,. Othervise, it is highly recom-
mended that you select the Mainun option tor signiticantly better hard disk pertormance.
1he manual selection ot 2 to 32 sectors is usetul it you notice data corruption vith the
Mainun option. It allovs you to scale back the multi-sector transter teature to correct the
problem vithout losing too much pertormance.
Mu|I-SccIor Jransfcrs 87
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N/B Strop CPU As
Connon Options: By CPL, PSB400, PSB333, PSB800
never Intel i863i873-series ot chipsets. In thos e chipsets, Intel has chosen to limit the choices
ot available CPL-to-DPAM ratios.
When a 400MHz FSB processor is installed, the choice ot CPL-to-DPAM ratio is limited
to 3:4.
to 1:1 or 4:S.
to 1:1, 3:2, or S:4.
lortunately, this BIOS teature allovs you to circumvent that limitation.
1he N/B Strap CPU As BIOS teature actually controls the setting ot the external hardvare
reset strap assigned to the MCH (Menory Controller Hub, ot the chipset. By setting it to
PSB400, PSBS33, or PSB800, you can trick the chipset into thinking that the 400MHz FSB,
S33MHz FSB, or the 800MHz FSB is being used.
When this BIOS teature is set to PSB800, you are able to access the 800MHz CPL-to-
DPAM ratios ot 1:1, 3.2 and S:4.
When this BIOS teature is set to PSBS33, you are able to access the S33MHz CPL-to-
DPAM ratios ot 1:1 and 4:S.
DPAM ratio ot 3:4.
require access to the CPL-to-DPAM ratio that normally vould not be available to you, then
this BIOS teature vill be very helptul indeed.
No Mosk oI SBA IL
1his BIOS teature controls the masking ot the signal used to calibrate the SBA (Sideband
Address, port. It is used to tix compatibility issues vith certain graphics cards.
When enabled, the chipset masks (hioes, the SBA calibration signal, so the graphics chip does
not initiate the SBA calibration cycle. Because the SBA port is never recalibrated, the issue ot
the graphics card hanging due to SBA recalibration is avoided.
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When disabled, the graphics chip is alloved to initiate the SBA calibration cycle right atter the
AGP bus calibration cycle.
Lsers ot A1I P3xx-based graphics cards (tor example, Padeon 9700 Pro, Padeon 9800, are
advised to enable this BIOS teature it the graphic card hangs or crashes during 3D benchmark-
ing or gaming.
Lsers ot other unattected graphics cards are advised to disable this teature, so the chipset can
dynamically calibrate the SBA port.
No Mask of S8A FL 80
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Onboord IDC Swop A & B
Connon Options: No Svap, Svap AB
1his BIOS teature is used to logically svap the mapping ot drives A: and B:.1heretore, it is only
usetul it you have tvo tloppy drives.
Normally, the sequence by vhich you connect the tloppy drives to the cable determines vhich
is drive A: and vhich is drive B:. It you attach the tloppy drives the vrong vay and obtain a
drive mapping that is not to your satistaction, the usual vay ot correcting this is to physically
svap the tloppy cable connectors.
1his teature allovs you to svap the logical arrangement ot the tloppy drives vithout the need
to open up the case and physically svap the connectors.
When this BIOS teature is set to Svap AB, the tloppy drive that originally vas mapped to
drive A: is remapped to drive B: and vice versa tor the drive that vas originally set as drive B:.
When this BIOS teature is set to No Svap, the tloppy drive mapping remains as set by the
drive connector arrangement.
Although this appears to be nothing more than a teature ot convenience, it can be quite impor-
tant it you are using tvo tloppy drives ot ditterent torm tactors (3.3and 3.23, and you need to
boot trom the second drive. Because the BIOS can only boot trom drive A:, you have to physi-
cally svap the drive connections or use this BIOS teature to do it logically.
It your tloppy drive mapping is correct or it you only have a single tloppy drive, there is no
need to set this teature to Svap AB. Ieave it at the detault setting ot No Svap.
Onboord IDD Controllor
1his BIOS teature allovs you to enable or disable the onboard tloppy drive controller.
When enabled, the motherboard`s onboard tloppy drive controller is enabled.
When disabled, the motherboard`s onboard tloppy drive controller is disabled.1his trees up the
IPQ used by the tloppy drive controller.
It you are using a tloppy drive connected to the motherboard`s built-in tloppy drive controller,
select the Lnabled option.
It you are using an add-on tloppy drive controller card or it you are not using any tloppy drive
at all, set it to Disabled to save an IPQ that can be used by other devices.
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Onboord IDL-1 Controllor
1his BIOS teature is actually a misnomer because there is only one IDL controller integrated
into current chipsets.
1his single IDL controller comes vith tvo IDL channels, each ot vhich supports up to tvo
IDL drives.1heretore, the IDL controller supports a total ot tour IDL devices through tvo IDL
channels.
When enabled, the IDL channel is able to provide support tor up to tvo IDL drives.
When disabled, the IDL channel is disabled. Any attached IDL drives is not accessible.
Hovever, this trees up an IPQ, vhich can be used by other devices. Disabling this IDL channel
also speeds up the booting sequence a little as the BIOS does not need to query this channel
tor IDL devices vhen it boots up.
You should leave this enabled it you are using this IDL channel. Disabling it prevents any IDL
devices attached to this channel trom being accessed.
It you are not attaching any IDL devices to this IDL channel (or it you are using a SCSI add-
on IDL card,, you can disable this IDL channel to tree an IPQ and speed up the booting
sequence.
channels.
When disabled, the IDL channel is disabled. Any attached IDL drives are not accessible.
It you are not attaching any IDL devices to this IDL channel (or it you are using a SCSI add-
sequence.
0nhoard I0L-2 LonIro||cr 01
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Onboord IR Iunction
Connon Options: IrDA (HPSIP, mode, ASK IP (Amplitude Shitt Keyed IP, mode,
Disabled
1here are tvo ditterent IR (Infra-Red, modesIrDA and ASK IR.
You should select the IP mode that is supported by your external IP device. Choosing the
vrong IP mode prevents your computer trom communicating vith the external IP device.
Hovever, it there is a choice betveen IrDA and ASK IP, the natural choice is IrDA, ot course'
IrDA is taster and has a longer range.
Please note that such IP communications require an IP beam kit to be plugged into the IP
header on the motherboard. Without the IP beam kit, this teature von`t have any ettect.
You should also note that enabling this IP tunction prevents the second serial port trom being
used by normal serial devices.1heretore, it you do not need to use the onboard IP tunction,
disable this BIOS teature, so the second serial port can be used by normal serial devices.
Onboord Porollol Port
Connon Options: 3BChIPQ7, 278hIPQ3, 378hIPQ7, Disabled
1his BIOS teature allovs you to select the IO address and IPQ tor the onboard parallel port.
1he detault IO address ot 378h and IPQ ot 7 should vork vell in most cases. Lnles s you
have a problem vith the parallel port, you should leave it at the detault settings.
You should only select an alternative IO address or IPQ it the detault settings are causing a
contlict vith other devices.
You can als o disable the onboard parallel port it you do not need to use it. Doing so trees up
the IO port and IPQ used by the parallel port. 1hose resources can then be reallocated tor
other devices to use.
Onboord Soriol Port 1
Connon Options: Auto, 3l8hIPQ4, 2l8hIPQ3, 3L8hIPQ4, 2L8hIPQ3, Disabled
1his BIOS teature allovs you to manually select the IO address and IPQ tor the tirst serial
port.
It is recommended that you leave it as Auto, so the BIOS can select the best settings tor it. It
you need a particular IO port or IPQ that has been taken up by this serial port, you can man-
ually select an alternative IO port or IPQ tor it.
Please note that any IO port or IPQ can be used tor the serial port.1here is no advantage or
disadvantage in any ot the options. As long as you do not select an IO port or IPQ that has
already been allocated to another device, any option vill do.
You can als o disable this serial port it you do not need to use it. Doing so trees up the IO
port and IPQ used by this serial port. 1hose resources then can be reallocated tor other devices
to use.
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port.
It is recommended that you leave it as Auto, so the BIOS can select the best settings tor it. It
you need a particular IO port or IPQ that has been taken up by this serial port, you can man-
ually select an alternative IO port or IPQ tor it.
to use.
Onboord USB Controllor
1his BIOS teature enables or disables the motherboard`s onboard LSB controller.
It is recommended that you enable this teature, so you can use the onboard LSB controller to
communicate vith your LSB devices.
It you disable this teature, the LSB controller is disabled and you are not able to use it to com-
municate vith any LSB device. 1his trees up an IPQ tor other devices to use. 1his is usetul
vhen you have many devices that cannot share IPQs.
Hovever, it is recommended that you do not disable this BIOS teature unless you do not use
any LSB device or it you are using a ditterent LSB controller tor your LSB needs.
OnChip VGA Modo Soloct
GPL.
0nLhp v0A Modc Sc|ccI 08
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memory your GPL requires vill be 1600 1200 32-bits = 61,440,000 bits or 7.68MB.You
OS/2 Onboord Monory > 4M
1his BIOS teature determines hov systems vith more than 64MB ot memory are managed.
A vrong setting can cause problems like erroneous memory detection.
It you are using an older version ot the IBM OS2 operating system, you should select Yes.
It you are using the IBM OS2 Warp v3.0 or higher operating system, you should select No.
all the relevant IBM lixPaks, you should select No.
Lsers ot non-OS2 operating systems (like Microsott Windovs XP, should select the No
option.
OS Soloct Ior DRAM > 4MB
Connon Options: OS2, Non-OS2
1his BIOS teature determines hov systems vith more than 64MB ot memory are managed.
A vrong setting can cause problems like erroneous memory detection.
It you are using an older version ot the IBM OS2 operating system, you should select OS/2.
It you are using the IBM OS2 Warp v3.0 or higher operating system, you should select
Non-OS/2.
all the relevant IBM lixPaks, you should select Non-OS/2.
Lsers ot non-OS2 operating systems (like Microsott Windovs XP, should select the
Non-OS/2 option.
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P2C/C2P Concurroncy
1he BIOS teature allovs PCI-to-CPL and CPL-to-PCI trattic to occur concurrently.1his
means PCI trattic to the CPL and CPL trattic to the PCI bus can occur simultaneously.
1his prevents the CPL trom being locked up during PCI transters. It also allovs PCI trattic
to the processor to occur vithout delay even vhen the processor is vriting to the PCI bus.1his
may prevent pertormance issues vith certain PCI cards.
1heretore, it is recommended that you enable this teature tor better pertormance.
Porollol Port Modo
Connon Options: Normal (SPP,, LCP, LPP, LCPLPP
By detault, the parallel port is usually set to the Nornal (SPP) mode. SPP stands tor
Standard Parallel Port. It is the original transter protocol tor the parallel port. 1heretore, it
vorks vith all parallel port devices.
1he LCP (Ltended Capabilities Port, transter mode uses the DMA protocol to achieve
data transter rates ot up to 2MB/s and provides smmetric bidirectional communication.
On the other hand, LPP (Lnhanced Parallel Port,, nov knovn as ILLL 1284, uses existing
parallel port signals to provide asmmetric bidirectional communication. It vas also designed tor
high-speed communications, ottering transter rates ot up to 2MB/s.
As you can see, SPP is a very slov transter mode. It only should be selected vhen taster transter
modes cannot be used (tor example, vith old printers or scanners,. With modern parallel port
devices, the LCP and LPP modes are the transter modes ot choice.
Generally, because ot its lIlOs and the DMA channel it uses, LCP is good at large data trans-
ters. 1heretore, it is the transter mode that vorks best vith scanners and printers. LPP is better
vith devices that svitch betveen reads and vrites trequently (like ZIP drives and hard disks,.
Hovever, you should check your parallel port device`s documentation betore you set the trans-
ter mode. 1he manutacturer ot your parallel port peripheral may have designated a preterred
transter mode tor the device in question. In that case, it is best to tollov their recommendation.
It the device documentation did not state any preterred transter mode and you still do not
knov vhat mode to s elect, you can select the LCP+LPP mode. It you select this mode, the
BIOS automatically determines the transter mode to use tor your device.
Para||c| PorI Modc 06
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Possivo Rolooso
1his BIOS teature controls the passive release teature ot the CPU to PCI Write Buffer.
1heretore, it the vrite butter is disabled, this BIOS teature does not have any ettect. Hovever,
the reverse is not true. 1he CPU to PCI Write Buffer teature still vorks even it Passive
Release is disabled.
When Passive Pelease is enabled, the vrite butter independently vrites the data to the PCI
bus at the tirst available opportunity. It can do so even vhen the processor is busy doing some-
thing else.
When Passive Pelease is disabled, the vrite butter vaits until the process or reasserts (retries,
the vrite request. Only then does it vrite to the PCI bus.1his still improves pertormance
because the process or does not need to resend the data. Hovever, the vrite butter still loses
some ot its ettectiveness because it has to vait tor the CPL to retry the transaction.
lor best pertormance, it is highly recommended that you enable Passive Pelease. 1his dramati-
cally reduces the ettect ot slov ISA devices hogging the PCI bus. Hovever, some ISA cards may
not vork vell vith Passive Pelease. In such cases, disable Passive Pelease or better yet, throv
the card avay and get a PCI version instead'
It you don`t use any ISA device, this teature should still be enabled because it allovs the vrite
butter to ottload its data to the PCI bus vithout vaiting tor the processor to retry the transac-
tion.1his improves the pertormance ot the processor and PCI bus.
Please note again that this BIOS teature has no ettect it you disable the CPU to PCI Write
Buffer.
PCI#2 Accoss #1 Rotry
1his BIOS teature is linked to CPU to PCI Write Buffer. 1heretore, it the vrite butter is dis-
abled, this BIOS teature does not have any ettect. Hovever, the reverse is not true.1he CPU to
PCI Write Buffer teature still vorks even it PCI2 Access 1 Retry is disabled.
When the butter is enabled, the processor vrites directly to the butter instead ot the PCI bus.
1he butter then attempts to vrite the data to the PCI bus by Passive Release. 1his allovs the
processor to pertorm other tasks vithout vaiting tor its data to be vritten to the PCI bus.
Hovever, the attempted butter vrite to the PCI bus may tail because the PCI bus may still be
occupied by another device. When that happens, this BIOS teature determines it the butter
vrite should be reattempted or sent back tor arbitration.
It this BIOS teature is enabled, the butter attempts to vrite to the PCI bus until it is successtul.
It this BIOS teature is disabled, the butter tlushes its contents and registers the transaction as
tailed.1he processor nov has to vrite again to the vrite butter.
Generally, it is recommended that you enable this teature because it improves the processor`s
pertormance.
Hovever, it you have many PCI devices and their pertormance is more important, you may
vant to disable this teature.1his prevents excessive generation ot retries by the vrite butter,
vhich may severely tax the PCI bus. Disabling this teature improves the PCI bus pertormance,
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especially vith slov PCI devices that hog the bus tor long periods ot time at a stretch.
Buffer.
PCI 2.1 Conplionco
It it cannot do so, the PCI bus terminates the transaction, so other PCI devices can access the
bus. Hovever, ins tead ot rearbitrating tor access (and tailing to meet the minimum latency
It the delayed transaction is a urite, the master device rearbitrates tor bus access vhile the target
the same vrite request.1his time, the target device just sends the completion status to the mas-
ter device to complete the transaction.
PCI Delayed 1ransaction also allovs vrite-posted data to remain in the butter, vhile the PCI
bus initiates a non-postable transaction, and yet still adhere to the PCI ordering rules. Without
tion can occur.
It is highly recommended that you enable PCI 2.1 Compliance tor better PCI pertormance
and to meet PCI 2.1 specitications. Disable it only it your PCI cards cannot vork properly
vith this teature enabled or it you are using PCI cards that are not PCI 2.1-compliant.
Please note that vhile many manuals and even earlier versions ot the BIOS Optimization Guide
have stated that this is an ISA bus-specitic BIOS teature that enables a 32-bit vrite-posted
butter tor taster PCI-to-ISA vrites, they are incorrect' 1his BIOS teature is not ISA bus-specitic,
and it does not control any vrite-posted butters. It merely allovs vrite-posting to continue
vhile a non-postable PCI transaction is undervay.
PCI Choining
1his BIOS teature is designed to speed up vrites trom the processor to the PCI bus by alloving
vrite combining to occur at the PCI intertace.
PLI Lhanng 07
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When PCI chaining is enabled, up to tour quadvords ot processor vrites to contiuous PCI
addresses are chained together and vritten to the PCI bus as a single PCI burst vrite.
When PCI chaining is disabled, each processor vrite to the PCI bus is handled as separate
non-burstable vrites.
Needless to say, vriting tour quadvords ot data in a single PCI vrite is much taster than doing
so in tour separate non-burstable vrites. A single PCI burst vrite also reduces the amount ot
time the processor has to vait vhile vriting to the PCI bus.
1heretore, it is recommended that you enable this teature tor better CPL to PCI vrite
pertormance.
PCI Clock / CPU ISB Clock
Connon Options: 12, 13, 14, 13, 16
1his BIOS teature allovs you to manually select the PCI bus clock divider. Because this divider
determines the speed at vhich the PCI bus runs, manipulation ot this teature allovs you some
control over the PCI bus speed.
It vas meant to keep the PCI bus running vithin specitications vhen you overclock the
processor bus, but you can also use it to overclock the PCI bus. With that said, you should keep
in mind that the recommended sate limit tor an overclocked PCI bus is 37.SMHz.1his is the
speed at vhich practically all nev PCI cards can run vithout breaking a sveat.
Selecting the clock divider ot 1/2 makes the PCI bus run at halt the processor bus speed. As
such, this clock divider is usetul tor processor bus speeds ot 66MHz to 7SMHz.
Selecting the clock divider ot 1/3 makes the PCI bus run at a third ot the processor bus speed.
As such, this clock divider is usetul tor processor bus speeds ot 100MHz to 112.SMHz.
Selecting the clock divider ot 1/4 makes the PCI bus run at a quarter ot the processor bus
speed. As such, this clock divider is usetul tor processor bus speeds ot 133MHz to 1S0MHz.
Selecting the clock divider ot 1/S makes the PCI bus run at a titth ot the processor bus speed.
As such, this clock divider is usetul tor processor bus speeds ot 166MHz to 187.SMHz.
Selecting the clock divider ot 1/6 makes the PCI bus run at a sixth ot the processor bus speed.
As such, this clock divider is usetul tor processor bus speeds ot 200MHz to 22SMHz.
You are probably vondering about the gaps in the processor bus speeds listed above. lor your
convenience, only processor bus speeds that produce PCI clock speeds vithin the range ot opti-
mal PCI clock speeds (33MHz to 37.3MHz, are displayed above. 1he other processor bus speeds
either produce a slov PCI bus or an excessively overclocked one.
1heretore, tor optimal PCI bus pertormance, try to shoot tor one ot the processor bus speed-
divider combinations shovn above.
PCI Doloy lronsoction
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It it cannot do so, the PCI bus terminates the transaction, so other PCI devices can access the
bus. Hovever, ins tead ot rearbitrating tor access (and tailing to meet the minimum latency
It the delayed transaction is a urite, the master device rearbitrates tor bus access vhile the target
the same vrite request.1his time, the target device just sends the completion status to the mas-
ter device to complete the transaction.
bus initiates a non-postable transaction, and yet still adhere to the PCI ordering rules. Without
tion can occur.
It is highly recommended that you enable PCI Delay 1ransaction tor better PCI pertormance
PCI Dynonic Bursting
1his BIOS teature is similar to the Byte Merge teature.
When enabled, the PCI vrite butter accumulates and merges 8-bit and 16-bit vrites into 32-
bit vrites. 1his increases the etticiency ot the PCI bus and improves its bandvidth.
When disabled, the PCI vrite butter does not accumulate or merge 8-bit or 16-bit vrites. It
just vrites them to the PCI bus as soon as the bus is tree. As such, there may be a loss ot PCI
bus etticiency vhen 8-bit or 16-bit data is vritten to the PCI bus.
1heretore, it is recommended that you enable PCI Dynamic Bursting tor better pertormance.
Hovever, please note that PCI Dynanic Bursting may be incompatible vith certain PCI
netvork intertace cards (also knovn as NICs, . So, it your NIC von`t vork properly, try
disabling this teature.
PLI 0ynamc 8ursIng 00
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PCI IDL Busnostor
When this BIOS teature is disabled, the BIOS does not load up the 16-bit busmastering driver
tor the onboard IDL controller. 1he IDL controller then transters data through PIO
(Progranned Input/Output).
1heretore, it is recommended that you enable PCI IDL Busmaster.1his greatly improves the
IDL transter rate and reduces the CPL utilization during the booting process or vhen you are
using real-mode DOS. Lsers ot DOS-based dis k utilities like Norton Ghost can expect to ben-
etit a lot trom this teature.
PCI IRQ Activotod By
Connon Options: Ldge, Ievel
1his BIOS teature allovs you to set the method by vhich the IPQs tor your PCI devices are
activated or triggered.
ISA and old PCI devices are edge-triggered (using a single voltage level, vhile never PCI
and AGP devices are level-triggered (using multiple voltage levels,. 1his is important mainly
because PCI devices must be level-triggered to s hare IPQs.
Because all PCI devices currently in the market are level-triggered, it is recommended that you
set this BIOS teature to Level, so your PCI devices can share IPQs.
Hovever, it you are still using old edge-triggered devices, select Ldge to torce the chipset to
allov only edge-triggering ot PCI devices.1his may cause contiguration problems it there are
IPQ contlicts, but it prevents system lockups that can occur it the chipset erroneously attempts
to level-trigger an edge-triggered PCI device.
PCI Lotoncy linor
Connon Options: 0233
1his BIOS teature controls hov long a PCI device can hold the PCI bus betore another takes
over. 1he longer the latency, the longer the PCI device can retain control ot the bus betore
handing it over to another PCI device.
Normally, the PCI Iatency 1imer is set to 32 cycles. 1his means the active PCI device has to
complete its transactions vithin 32 clock cycles or hand it over to the next PCI device.
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lor better PCI pertormance, a longer latency should be used.1ry increasing it to 64 cycles or
even 128 cycles.1he optimal value tor every system is ditterent.You should benchmark your
PCI cards` pertormance atter each change to determine the optimal PCI latency time tor
your system.
Please note that a longer PCI latency isn`t necessarily better. A long latency can also reduce per-
tormance as the other PCI devices queuing up may be stalled tor too long. 1his is especially
true vith systems vith many PCI devices or PCI devices that continuously vrite short burs ts ot
data to the PCI bus. Such systems vork better vith shorter PCI latencies because they allov
rapid access to the PCI bus.
In addition, some time-critical PCI devices may not agree vith a long latency. Such devices
require priority access to the PCI bus, vhich may not be possible it the PCI bus is held up by
another device tor a long period. In such cases, it is recommended that you keep to the detault
PCI latency ot 32 cycles.
PCI Mostor 0 WS Rood
1his BIOS teature determines vhether the chipset inserts a delay betore any reads trom the
PCI bus.
It PCI Master 0 WS Read is enabled, read requests to the PCI bus are executed immediately
(vith zero vait states,, it the PCI bus is ready to send data.
It PCI Master 0 WS Pead is disabled, every read request to the PCI bus is delayed by one
vait state.
It is recommended that you enable this teature tor better PCI read pertormance.
Hovever, disabling it may be usetul it you are attempting to stabilize an overclocked PCI bus.
1he delay generally improves the overclockability and stability ot the PCI bus.
PCI Mostor 0 WS Writo
1his BIOS teature determines vhether the chipset inserts a delay betore any vrites trom the
PCI bus.
It PCI Master 0 WS Write is enabled, vrite requests to the PCI bus are executed immedi-
ately (vith zero vait states,, it the PCI bus is ready to send data.
It PCI Master 0 WS Write is disabled, every vrite request to the PCI bus is delayed by one
vait state.
It is recommended that you enable this teature tor better PCI vrite pertormance.
PLI MasIcr 0 WS WrIc 101
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PCI Mostor Rood Coching
1his is an AMD-specitic BIOS teature. It determines vhether the processor`s I2 cache is used
to cache PCI bus master reads .
It this teature is enabled, the processor`s I2 cache is used to cache PCI bus master reads. 1his
boosts the pertormance ot PCI bus masters. On the other hand, it reduces the processor`s per-
tormance because it uses up some ot the precious I2 cache.
1his is vhy motherboard manutacturers like ASLS recommend that only systems using AMD
Athlon processors should enable this teature. Duron users should disable this teature because
its small I2 cache is not able to cache the PCI reads vithout causing a massive hit to memory
bandvidth.
Although the tinal vord is still in the air, I recommend disabling this teature.1he use ot
precious I2 cache to cache PCI bus masters is not vorth the potential benetit in PCI bus
pertormance.
PCI Pipolining
1his BIOS teature determines it PCI transactions to the memory subsystem are pipelined.
It the PCI pipeline teature is enabled, the memory controller allovs PCI transactions to be
pipelined. 1his masks the latency ot each PCI transaction and improves the etticiency ot the
PCI bus.
It the PCI pipeline teature is disabled, the memory controller is torced to check tor outstand-
ing transactions trom other devices to the same block address that each PCI transaction is tar-
geting.
lor better PCI pertormance, the PCI pipeline should be enabled. 1his allovs the latency ot the
bus to be masked tor consecutive transactions.
Hovever, it your system constantly locks up tor no apparent reason, try disabling this teature.
Disabling PCI Pipelining reduces pertormance but ensures that data coherency is strictly main-
tained tor maximum reliability.
PCI ProIotch
1his teature controls the system controller`s PCI pretetch capability.
When enabled, the system controller pretetches data vhenever the PCI device reads trom the
system memory. 1his speeds up PCI reads because it allovs contiguous memory reads by the
PCI device to proceed vith minimal delay.
1heretore, it is recommended that you enable this teature tor better PCI read pertormance.
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PCI lorgot Lotoncy
1his BIOS teature determines vhether the system controller s hould contorm to the PCI maxi-
mum target latency rule.
When this teature is enabled, the system controller disconnects the PCI bus master it it cannot
service a read request vithin 32 PCI clock cycles tor the initial read and 8 PCI clock cycles tor
subsequent reads.1he PCI bus master then rearbitrates tor access to the PCI bus.
When this teature is disabled, the PCI bus master is not disconnected it it cannot service a read
request vithin the stipulated 32 PCI clock cycles tor the initial read and 8 PCI clock cycles tor
subsequent reads.1he PCI bus master is alloved to complete its transactions.
It is recommended that you enable this teature to entorce the PCI maximum target latency
rule and prevent potential deadlocks.
PCI to DRAM ProIotch
1his teature controls the system controller`s PCI pretetch capability.
When enabled, the system controller pretetches data vhenever the PCI device reads trom the
system memory. 1his speeds up PCI reads because it allovs contiguous memory reads by the
PCI/VGA Polotto Snoop
1his BIOS teature determines vhether your graphics card should allov VGA palette snooping
by a tixed tunction dis play card. It is only usetul it you use a tixed-tunction display card that
requires a VGA-compatible graphics card to be present ( tor example, MPLG decoder card,.
Such tixed-tunction display cards generally do not have their ovn VGA palette. So, they have to
snoopVGA palette data trom the graphics card to generate the proper colors. Normally, the
graphics card`s leature Connector is used tor this purpose.
When this teature is enabled, the graphics card does not respond to tramebutter vrites. It
torvards them to the tixed-tunction display card through its leature Connector.1he tixed-
tunction display card then snoops the palette data and generates the proper colors.
When this teature is disabled, the graphics card displays all tramebutter vrites.
It is recommended that you disable this teature it you do not use any tixed-tunction display
card like an MPLG decoder card.
Hovever, it you are using a tixed-tunction display card that requires palette snooping, enable this
teature. Othervise, the colors displayed may not be accurate and the monitor vill blank out
once you stop using the tixed-tunction display card.
PLIjv0A Pa|cIIc Snoop 108
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PIO Modo
IDL drive.
It the BIOS cannot detect the correct PIO mode.
tor.
vith the current PIO mode (tor example, vhen the PCI bus is overclocked,.
PIRQ Uso IRQ No.
Connon Options: Auto, 3, 4, 3, 7, 9, 10, 11, 12, 14, 13
1his BIOS teature allovs you to manually set the IPQ tor a particular device installed on the
AGP and PCI buses.
It is especially usetul vhen you are transterring a hard disk trom one computer to another, and
you don`t vant to reinstall your operating system to redetect the IPQ settings. By setting the
IPQs to tit the original settings, you can circumvent a lot ot contiguration problems atter
installing the hard disk in a nev system. Hovever, this is only true tor non-ACPI systems.
Here are some important notes trom the reterence motherboard (may vary betveen mother-
boards,:
It you specity a particular IPQ here, you can`t specity the same IPQ tor the ISA bus. It
you do, you vill cause a hardvare contlict.
Lach PCI slot is capable ot activating up to 4 interrupts: IN1 A, IN1 B, IN1 C and IN1
D.
1he AGP slot is capable ot activating up to 2 interrupts: IN1 A and IN1 B.
Normally, each s lot is allocated IN1 A.1he other interrupts are reserves and used only vhen
the PCIAGP device requires more than one IPQ or it the IPQ requested has been used up.
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1he AGP slot and PCI slot 41 share the same IPQ.
PCI slot 44 and 43 share the same IPQs.
LSB uses PIPQ_4.
1he tolloving table shovs the relationship betveen PIPQ (Programmable Interrupt Pequest,
signals and IN1 in the reterence motherboard:
Signals AGP Slot PCI Slot 2 PCI Slot 3 PCI Slot 4
PCI Slot 1 PCI Slot S
PIPQ_0 IN1 A IN1 D IN1 C IN1 B
PIPQ_1 IN1 B IN1 A IN1 D IN1 C
PIPQ_2 IN1 C IN1 B IN1 A IN1 D
PIPQ_3 IN1 D IN1 C IN1 B IN1 A
You vill notice that the interrupts are staggered, so contlicts do not happen easily.
Lven then, you should try not to use up paired slots that s hare the same set ot IPQs. In such
cases, it is recommended that you use only one ot the tvo slots.
In most cases, you should just leave the setting as Auto.1his allovs the motherboard to assign
the IPQs automatically. Hovever, it you need to assign a particular IPQ to a device on the
AGP or PCI bus, here is hov you can make use ot this BIOS teature.
1. Determine the slot in vhich the device is located.
2. Check your motherboard`s PIRQ table (in the manual, to determine the slot`s primary
PIPQ.
3. You then select the IPQ you vant by as signing the IPQ to the appropriate PIPQ.
ust remember that the BIOS alvays tries to allocate the PIPQ linked to IN1 A tor each
slot. It is just a matter ot linking the IPQ you vant to the correct PIPQ tor that slot.
Please note the table, notes , and IN1 details are only examples provided by the reterence moth-
erboard.1hey may vary betveen motherboards.
PNP OS Instollod
What this BIOS teature actually does is determine vhat devices are contigured by the BIOS
vhen the computer boots up and vhat are lett to the operating system.
Non-ACPI BIOSes are tound in older motherboards that do not support the nev ACPI
(Advanced Configuration and Pover Interface, initiative.With such a BIOS, setting the
PNP OS Installed teature to No allovs the BIOS to contigure all devices under the assumption
that the operating system cannot do so.1heretore, all hardvare settings are tixed by the BIOS at
boot up and are not changed by the operating system.
PNP 0S InsIa||cd 106
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On the other hand, it you set the teature to Yes, the BIOS only contigures critical devices that
are required to boot up the system. 1he other devices are then contigured by the operating sys-
tem.1his allovs the operating system some tlexibility in shuttling system resources like IPQs
and IO ports to avoid contlicts. It also gives you some degree ot treedom vhen you vant to
manually assign system resources.
Ot course, all current motherboards nov ship vith the nev ACPI BIOS. It you are using an
ACPI-compliant operating system (tor example,Windovs 98 and above, vith an ACPI BIOS,
then this PNP OS Installed teature is no longer relevant. 1his is because the operating system
uses the ACPI BIOS intertace to contigure all devices as vell as retrieve system intormation.
Hovever, it your operating sys tem does not support ACPI, then the BIOS talls back to PNP
mode. In this situation, consider the BIOS as you vould a Non-ACPI BIOS. It there is no
need to contigure any hardvare manually, it is again recommended that you s et this teature
to No.
Iinux is not really PnP-compatible, but most distributions use a sottvare called ISAP-
NP1OOIS to set up ISA cards. It PnP OS is set to No, the BIOS vill attempt to contigure the
ISA cards, but that von`t vork vith Iinux. Worse, it ISAPNP1OOIS is used to contigure the
ISA cards as vell, it may lead to contlicts betveen the tvo.
1heretore, it is recommended that you set PnP OS to Yes in Iinux and allov ISAPNP1OOIS
to handle the task instead.
As tar as OS2 is concerned, PnP OS should be set to No, especially in a multi-boot system. In
addition, it you add or change hardvare, you should enable tull hardvare detection during the
initial boot s equence ot OS2.
1o sum it all up, except tor certain cases, it is highly recommended that you set this BIOS tea-
ture to No, irrespective ot the operating system you actually use. Lxceptions to this vould be
the inability ot the BIOS to contigure the devices properly in PnP mode and a specitic need to
manually contigure one or more ot the devices.
Post Writo Conbino
Conbining, vrite combine butters.
It enabled, the vrite combine butters accumulate and combine partial or smaller graphics
It disabled, the vrite combine butters are disabled. All graphics vrites trom the processor are
vritten to the graphics card directly.
pertormance.
Lnabling this teature vith such graphics cards causes a host ot problems like graphics artitacts,
system crashes, and even the inability to boot up properly.
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Powor On Iunction
Connon Options: Button Only, Keyboard 98, Hot Key, Mouse Iett, Mouse Pight
1his BIOS teature allovs you to select the method to turn on your computer.
By detault, this teature is set to Button Only.1his allovs your computer to be started up only
through the use ot the pover button or svitch. Other available options:
A Ke|oaro 98-compatible keyboard (vhich comes vith a vake-up button,
A keyboard hot key (tor non-Keyboard 98 keyboards,
A mouse button (either the right or lett button,
It you select the Mouse Left option, the lett button ot the mouse is used to start up the sys-
tem.1he Mouse Right option selects the right mouse button as the pover on button instead.
Please note that only PS2 mice support the Mouse Left or Mouse Right options. Mice
using serial or LSB connections do not support this pover on tunction.
1he Keyboard 98 option only vorks it you are using Windovs 98 or better and have the
appropriate keyboard. 1hen you can use the keyboard`s vake-up or pover-on button to start up
the computer.
Older keyboards that do not contorm to the Ke|oaro 98 standard, and theretore do not have
the special vake-up button, can use the Hot Key option instead. 1here are 12 hot keys avail-
able: Ctrl-F1 through Ctrl-F12. Select the hot key you vant and you are able to start up the
computer using that hot key.
1here is no pertormance advantage in choosing any ot the options above. So, choose the option
that you are most comtortable vith.
Prinory Grophics Adoptor
example, it you only use an AGP graphics card, then setting Primary Graphics Adapter to AGP
may speed up your system`s booting-up process.
1heretore, it you are only using a single graphics card, it is recommended that you set the
Primary Graphics Adapter teature to the proper setting tor your system (AGP tor a single AGP
card and PCI tor a single PCI card,.
mary display card.
Prmary 0raphcs AdapIcr 107
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Prinory VGA BIOS
Connon Options: AGP VGA Card, PCI VGA Card
example, it you only use an AGP graphics card, then setting Primary VGA BIOS to AGP VGA
Card may speed up your system`s booting-up process .
Primary VGA BIOS teature to the proper setting tor your system (AGP VGA Card tor a single
AGP card and PCI VGA Card tor a single PCI card,.
mary display card.
Procossor Nunbor Iooturo
1his BIOS teature allovs you to control the use ot the processor`s embedded unique identifi-
cation nunber.1heretore, it is only valid it you are using a processor that teatures such a tea-
ture.
1his intamous teature debuted in the Intel Pentium III processor and is mainly tound only in
that processor.1he 1ransmeta Crusoe processor also supports this teature. But most manutactur-
ers have retrained trom integrating such a teature in their processors. Lven Intel has declined to
add this teature to the Intel Pentium 4 processors.
It enabled, the processor`s identitication number can be read by external programs. It used to
be required tor certain secure transactions. Hovever, this is no longer true because the initiative
has long been abandoned.
It disabled, the processor`s identitication number cannot be read by external programs.
It is highly advisable that you disable this teature because it no longer has a use. Lven vorse, it
can actually be misused to track your online activities. Disabling this teature sateguards your pri-
vacy by preventing the identitication ot your computer by the processor`s identitication number.
PS/2 Mouso Iunction Control
Connon Options: Lnabled, Auto
IPQ12 is the interrupt usually reserved tor the PS2 mous e`s use.1his BIOS teature determines
vhether the BIOS should reserve IPQ12 tor the PS2 mouse or allov other devices to make
use ot this IPQ.
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Setting this BIOS teature to Auto allovs the BIOS to allocate IPQ12 to the PS2 mouse it
the mouse is detected at startup. Othervise, IPQ12 is released tor use by other devices in
the system.
Setting this BIOS teature to Lnabled torces the BIOS to reserve IPQ12 even it a PS2 mouse
vas not detected at startup.
your BIOS to release IPQ12 tor other devices to use it it doesn`t detect the presence ot a PS2
mouse during startup.
PSj2 Mousc FuncIon LonIro| 100
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Quick Boot
1his BIOS teature allovs you to decrease the time it takes to boot up the computer by shorten-
ing or skipping certain standard booting procedures.
It enabled, the BIOS shortens the booting process by skipping some tests and shortening oth-
ers. In addition, it also pertorms the tolloving tricks to turther speed up the booting process:
Spin up the hard disks as soon as pover is supplied (or as soon as possible,
Initialize only critical parts ot the chipset
Pead memory size trom the SPD (Serial Presence Detect, chip on the memory
modules
Lliminate logo delays (inserted by many manutacturers,
It disabled, the BIOS runs the vhole gamut ot boot-up tests.
It is recommended that you disable this teature vhen you boot up a nev computer tor the
tirst time or vhenever you install a nev piece ot hardvare.1his allovs the BIOS to run tull
diagnostic tests to detect any problems that may slip past Quick Boot`s abbreviated testing
scheme.
Atter a tev error-tree test runs, you should enable this teature tor much taster booting.
Quick Powor On SolI lost
It enabled, the BIOS shortens the booting process by skipping some tests and shortening
others.
diagnostic tests to detect any problems that may slip past the abbreviated testing scheme.
Q
R
Ronk Intorloovo
1his BIOS teature is similar to SDRAM Bank Interleave. Interleaving allovs banks ot
SDPAM to alternate their retresh and access cycles. One bank undergoes its retresh cycle vhile
another is being accessed.1his improves memory pertormance by masking the retresh cycles ot
each memory bank.1he only ditterence is that Rank Interleave vorks betveen ditterent phys-
ical banks or, as they are called nov, ranks.
Because a minimum ot tvo ranks are required tor interleaving to be supported, double-sided
memory modules are a must it you vish to enable Pank Interleave. Lnabling Pank Interleave
vith single-sided memory modules does not result in any pertormance boost.
It is highly recommended that you enable Pank Interleave tor better memory pertormance.
You can als o enable Pank Interleave it you are using a mixture ot single- and double-sided
memory modules. Hovever, it you are using only single-sided memory modules, it`s advisable to
disable Pank Interleave.
Rood-Around-Writo
1his BIOS teature allovs the processor to execute read commands out ot order as it they are
independent trom the vrite commands. It does this by using a Read-Around-Write butter.
It this BIOS teature is enabled, all processor vrites to memory are tirst accumulated in that
butter.1his allovs the processor to execute read commands vithout vaiting tor the vrite com-
mands to be completed.
1he butter then combines the vrites and vrites them to memory as burst transters.1his reduces
the number ot vrites to memory and boosts the process or`s vrite pertormance.
It this BIOS teature is disabled, the processor vrites directly to the memory controller.1his
reduces the processor`s read pertormance.
1heretore, it is highly recommended that you enable this teature tor better processor read and
vrite pertormance.
Rood Woit Stoto
Connon Options: 0 Cycle, 1 Cycle
1his BIOS teature determines hov long the memory controller should vait betore sending read
data to the data requester (tor example, processor, graphics card,and so torth,.
It this teature is set to 1 Cycle, the memory controller imposes a delay ot one clock cycle
cad WaI SIaIc 111
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betore the data is sent to the requester. 1his reduces memory read pertormance because the
memory controller delays the transter ot each piece ot requested data by one clock cycle.
It this teature is set to 0 Cycle, the memory controller transters read data to the data requester
vithout any delay.
1heretore, it is recommended that you set the Pead Wait State to 0 Cycle tor better memory
read and vrite pertormance.
Please note that this may cause system instabilities in certain contigurations.When that happens,
just reset the value to 1 Cycle.
RoIrosh Intorvol
lor better pertormance, you should consider increasing the Refresh Interval trom the detault
values (13.6 sec tor 128Mbit or smaller memory chips and 7.8 sec tor 236Mbit or larger
memory chips, up to 128 sec. Please note that it you increase the Refresh Interval too
much, the memory cells may lose their contents.
1heretore, you should start vith small increases in the Refresh Interval and test your system
atter each hike betore increasing it turther. It you tace stability problems upon increasing the
retresh interval, reduce the retresh interval step by step until the system is stable.
RoIrosh Modo Soloct
lor better pertormance, you should consider increasing the Refresh Mode Select trom the
larger memory chips, up to 128 sec. Please note that it you increase the Refresh Mode
Select too much, the memory cells may lose their contents.
1heretore, you should start vith small increases in the Refresh Mode Select and test your sys-
tem atter each hike betore increasing it turther. It you tace stability problems upon increasing
Roport No IDD Ior Win9$
1his BIOS teature allovs you to set vhether the BIOS should report the absence ot a tloppy
disk drive to Windovs 93.
lor some reason, the Microsott Windovs 93 operating system requires a tloppy dis k drive to be
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present. Hovever, in an age ot LSB tlash media and CDDVD vriters, not all computers come
vith a tloppy disk drive. Such computers tail to boot up Windovs 93 vithout a tloppy disk
drive.
It this teature is enabled, the BIOS assigns IPQ 6 to another device.1his allovs computers
vith no tloppy disk drives to boot into Windovs 93 normally.
It this teature is disabled,Windovs 93 detects the absence ot the tloppy disk drive and halts the
system vith an error message.
It you are using Windovs 93 uithout a tloppy disk drive, you have to enable this teature to
allov Windovs 93 to boot up normally.
It you are using Windovs 93 uith a tloppy disk drive, you can enable or disable this teature.
Windovs 93 boots up normally either vay.
Please note that this BIOS teature has no relevance in other operating systems. Only Windovs
93 is attected. It does not matter vhat you set this BIOS option to it you are using other oper-
ating systems.
Rosot ConIigurotion Doto
BIOS automatically detects the changes and recontigures the LSCD (Ltended Systen
Configuration Data,. 1heretore, there is usually no need to manually torce the BIOS to
recontigure the LSCD.
changes. A serious resource contlict may occur and the operating system may not even boot as a
result.1his is vhere the Reset Configuration Data BIOS teature comes in.
rebooting.
Rosourco Controllod By
1his BIOS teature determines vhether the BIOS should automatically contigure IPQ and
DMA resources.
1he BIOS is generally capable ot automatically contiguring IPQ and DMA resources tor the
devices in your computer.1heretore, it is advis able that you set this teature to Auto.
Hovever, it the BIOS has problems assigning the resources properly, you can select the Manual
option to reveal the IPQ and DMA assignment tields.You can then assign each IPQ or DMA
channel to either Legacy ISA or PCI/ISA PnP devices.
csourcc LonIro||cd 8y 118
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Legacy ISA devices are compliant vith the original PC A1 bus specitication and require a spe-
citic interrupt or DMA channel to tunction properly. PCI/ISA PnP devices, on the other
hand, adhere to the Plug and Play standard and can use any interrupt or DMA channel.
RD, lD Activo
Connon Options: Hi, Hi or Io, Io or Hi, Io or Io, Hi
1his BIOS teature allovs you to set the intra-red reception (RD, and transmission (1D,
polarity.
It is usually tound under the Onboard Serial Port 2 BIOS teature and is linked to the second
serial port. So, it you disable that port, this teature dis appears trom the screen or appears grayed
out.
1here are tour options available based on combinations ot Hi and Io.You`ll need to consult
your IP peripheral`s documentation to determine the correct polarity. Choosing the vrong
polarity prevents a proper IP connection trom being established vith the IP peripheral.
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S2R Bus Driving Strongth
1his BIOS teature determines vhether the motherboard chipset should automatically adjust the
drive strength ot the Athlon processor bus or allov manual contiguration.
It you set this teature to Auto, the chipset is alloved to dynamically adjust the S2K bus strength
or use values pre-set by the manutacturer.
It you set this teature to Manual, the chipset`s dynamic compensation circuitry tor the S2K bus
is turned ott.You then can manually set the S2K bus strength.
Generally, it is recommended that you set this teature to Auto, so the S2K bus strength can be
dynamically adjusted by the chipset. Hovever, there may be occasions vhen manual contigura-
tion ot the S2K bus driving strength may be desirable.
It is possible to make use ot this teature tor overclocking purposes. Increasing the drive strength
increases the stability ot the S2K bus. Hovever, please be very circumspect vhen you increase
the S2K bus drive strength vith an overclocked processor because you may irreversibly damage
the processor'
It you vish to manually contigure the S2K bus driving strength, you must set the S2K Bus
Driving Strength to Manual. 1his allovs you to manually set the S2K bus driving strength
value through the S2K Strobe P Control and S2K Strobe N Control BIOS teatures.
S2R Strobo N Control
1his BIOS teature determines the N transistor drive strength ot the S2K bus.
1he N transistor drive strength is represented by Hex values trom 0 to F (0 to 1S in decimal,.
1he detault N transistor drive strength ditters betveen motherboards. Hovever, the higher the
drive strength, the greater the compensation tor the motherboard`s impedance on the S2K bus.
Due to the nature ot this BIOS teature, it is possible to use it as an aid in overclocking the S2K
bus. A higher N (and P, transistor drive strength may be just vhat you need to overclock the
S2K bus higher than is normally possible. By raising the drive strength ot the S2K bus, you can
improve its stability at overclocked speeds.
Please be very circumspect vhen you increase the S2K drive strength vith an overclocked
processor because you may irreversibly damage the processor'
Also, contrary to popular opinion, increasing the S2K drive strength does not improve the per-
tormance ot your AMD processor. It is not a pertormance-enhancing teature, so you should not
increase the N transistor drive strength unnecessarily.
S2k SIrohc N LonIro| 116
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S2R Strobo P Control
1his BIOS teature determines the P transistor drive strength ot the S2K bus.
1he P transistor drive strength is represented by Hex values trom 0 to F (0 to 1S in decimal,.
1he detault P transistor drive strength ditters betveen motherboards. Hovever, the higher the
bus. A higher P (and N, transistor drive strength may be just vhat you need to overclock the
increase the P transistor drive s trength unnecessarily.
SDRAM 1l Connond
Connon Options: Lnabled, Disabled,Auto
1his BIOS teature allovs you to select the delay betveen the assertion ot the Chip Select signal
until the time the memory controller starts sending commands to the memory bank. 1he lover
the value, the sooner the memory controller can send commands out to the activated memory
bank.
When this teature is enabled, the memory controller only inserts a command delay ot one
clock cycle or 11.
When this teature is disabled, the memory controller inserts a command delay ot tvo clock
cycles or 21.
1he Auto option allovs the memory controller to use the memory module`s SPD value tor
command delay.
It the SDPAM command delay is too long, it can reduce pertormance by unnecessarily pre-
venting the memory controller trom issuing the commands sooner.
Hovever, it the SDPAM command delay is too short, the memory controller may not be able
to translate the addresses in time and the bad commands that result cause data loss and
corruption.
It is recommended that you enable SDPAM 11 Command tor better memory pertormance.
Hovever, it you tace stability is sues, disable this BIOS teature.
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SDRAM 1l Connond Control
bank.
When this teature is enabled, the memory controller inserts a command delay ot only one
clock cycle or 11.
cycles or 21.
command delay.
to translate the addresses in time and the bad commands that result cause data loss and cor-
ruption.
It is recommended that you enable SDPAM 11 Command Control tor better memory per-
tormance. Hovever, it you tace stability issues, disable this BIOS teature.
SDRAM Activo to Prochorgo Doloy
Connon Options: 4, 3, 6, 7, 8, 9
Iike DRAM Act to PreChrg CMD, this BIOS teature controls the memory bank`s minimum
rov active time (tRAS,.1his constitutes the time vhen a rov is activated until the time the
same rov can be deactivated.
transter. 1his reduces pertormance, and data may be lost or corrupted.
But it you start getting memory errors or system crashes, increase the tPAS value one clock
cycle at a time until your system becomes stable.
SDRAM Bonk Intorloovo
Connon Options: 2-Bank, 4-Bank, Disabled
1his BIOS teature enables you to set the interleave mode ot the SDPAM intertace.
Interleaving allovs banks ot SDPAM to alternate their retresh and access cycles. One bank
S0AM 8ank InIcr|cavc 117
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undergoes its retresh cycle vhile another is being accessed.1his improves memory pertormance
by masking the retresh cycles ot each memory bank. A close examination reveals that, because
the retresh cycles ot all the memory banks are staggered, this produces a kind ot pipelining
ettect.
Hovever, bank interleaving only vorks it the addresses requested consecutively are not in the
same bank. It they are in the same memory bank, then the data transactions behave as it the
banks vere not interleaved.1he processor has to vait until the tirst data transaction clears and
that memory bank retreshes betore it can send another address to that bank.
Lach SDPAM module is internally divided into either tvo or four banks ot memory. Double-
banked SDPAM modules generally use 16Mbit SDPAM chips and are usually 32MB or
smaller in size. Quad-banked SDPAM modules, on the other hand, usually use higher density
(64Mbit-2S6Mbit, SDPAM chips. All SDPAM modules ot at least 64MB in size are quad-
banked in nature.
It you are using a sinie double-banked SDPAM module, set this teature to 2-Bank.1his is the
only option available tor the single double-banked SDPAM module.
It you are using at least tuo double-banked SDPAM modules, you can use the 4-Bank option
as vell as the 2-Bank option. Ot course, it is recommended that you select 4-Bank tor better
interleaving pertormance.
It you are using quad-banked SDPAM modules, you can use either interleave options. Ot
course, it is recommended that you select 4-Bank tor better interleaving pertormance.
Because a 4-bank interleave alvays allovs tor better interleaving pertormance, it is highly rec-
ommended that you select the 4-Bank option it your system supports it. Lse the 2-Bank
option only it you are using a single double-banked SDPAM module.
Please note that Avard (nov part ot Phoeni 1echnologies, recommends that SDPAM bank
interleaving be disabled it 16Mbit SDPAM modules are used.1his is because early 16Mbit
SDPAM modules have stability problems vith bank interleaving.1he good nevs is all current
SDPAM modules support bank interleaving.
SDRAM Bonk-to-Bonk Doloy
Connon Options: 2 cycles, 3 cycles
commands to the sane DDP device.1he shorter the delay, the taster the next bank can be
activated tor read or vrite operations. Hovever, because rov activation requires a lot ot current,
lor desktop PCs, a delay ot 2 cycles is recommended because current surges aren`t really
important.1he pertormance benetit ot using the shorter 2 cycles delay is ot tar greater interest.
1he shorter delay means every back-to-back bank activation take one clock cycle less to per-
torm. 1his improves the DDP device`s read and vrite pertormance.
Svitch to 3 cycles only vhen there are stability problems vith the 2 cycles setting.
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SDRAM Burst Lon
Connon Options: 4, 8
When this teature is set to 4, a burst transaction can only be comprised ot up to four reads or
four vrites.
When this teature is set to 8, a burst transaction can only be comprised ot up to eight reads or
eight vrites.
1heretore, it is recommended that you select the longer burst length ot 8 tor better pertormance.
SDRAM Burst Longth
four vrites.
eight vrites.
SDRAM CAS Lotoncy lino
Connon Options: 2, 3 (SDP memory, or 1.3, 2, 2.3, 3 (DDP memory,
1his BIOS teature controls the delay (in clock cycles, betveen the assertion ot the CAS signal
and the availability ot the data trom the target memory cell. It also determines the number ot
clock cycles required tor the completion ot the tirst part ot a burst transter. In other vords, the
lover the CAS latency, the taster memory reads or vrites can occur.
Please note that some memory modules may not be able to handle the lover latency and may
lose data.1heretore, vhile it is recommended that you reduce the SDRAM CAS Latency
1ine to 2 or 2.S clock cycles tor better memory pertormance, you should increase it it your
system becomes unstable.
Interestingly, increasing the CAS latency time otten allovs the memory module to run at a
higher clock speed. So, it you hit a snag vhile overclocking your SDPAM modules, try increas-
ing the CAS latency time.
S0AM LAS LaIcncy Jmc 110
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SDRAM Connond LoodoII lino
By detinition, the command leadott time is the period betveen the assertion ot the
addresscommand lines and the activation ot the target memory bank.1his BIOS teature allovs
you to adjust the command leadott time to meet timing variances ot the motherboard as vell as
the memory module.
1he shorter the leadott time, the earlier the target bank can be activated. 1his allovs taster
access to the data in the memory module. 1heretore, it is recommended that you set the
SDPAM Command Ieadott 1ime to 3 clock cycles tor better memory pertormance.
Hovever, your motherboard and memory combination may not be able to support the tighter
command leadott time ot 3 clock cycles. It your system becomes unstable vith a command
leadott time ot 3 clock cycles, revert to the slover command leadott time ot 4 clock cycles.
SDRAM Connond Roto
bank.
corruption.
It is recommended that you try the 11 command delay tor better memory pertormance.
Hovever, it you tace stability is sues, increase the command delay to 21.
SDRAM Cyclo Longth
1his BIOS teature is the same as the SDRAM CAS Latency 1ine BIOS teature. It controls
the delay (in clock cycles, betveen the assertion ot the CAS signal and the availability ot the
data trom the target memory cell. It also determines the number ot clock cycles required tor the
completion ot the tirst part ot a burst transter. In other vords , the lover the CAS latency, the
taster memory reads or vrites can occur.
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SDRAM Cyclo lino lros/lrc
1his BIOS teature determines the tRAS and the tRC parameters ot the SDPAM memory
module.
tRAS reters to the SDPAM Rov Active 1ine, vhich is the length ot time the rov remains
open tor data transters.
tRC, on the other hand, reters to the SDPAM Rov Cycle 1ine, vhich determines the mini-
mum number ot clock cycles a memory rov takes to complete a tull cycle, trom rov activation
up to the precharging ot the active rov.
1he detault setting is 6/8, vhich is more stable and slover than S/6.1he S/6 setting cycles
taster, but it may not leave the rov open long enough tor burst transactions to complete. When
this happens, data may be lost and the contents ot the memory cells may be corrupted.
lor better memory pertormance, you should try the S/6 setting. Hovever, increase it to 6/8 it
your system becomes uns table.
SDRAM LCC Sotting
Connon Options: Disabled, Check Only, Correct Lrrors , CorrectScrub
1his BIOS teature is the extended version ot the DRAM Data Integrity Mode BIOS tea-
ture. It is tound in never chipsets that support more than just simple LCC (Lrror Checking
and Correction,.
1he tirst mode is Disabled, vhich disables the memory controller`s LCC capabilities. It you are
not using LCC memory modules, you must select this option.
1he Check Only mode torces the memory controller to only check tor errors. 1he memory
controller detects and reports single- and double-bit errors, but it does not correct them. 1his
mode otters minimal pertormance degradation but doesn`t improve data integrity at all.
It you select the Correct Lrrors mode, the memory controller not only checks tor and detects
single- and double-bit errors, it also corrects single-bit errors. 1his mode has a higher overhead.
1he plus side is it improves data integrity by seamlessly correcting single-bit errors.
1he tinal LCC mode is Correct+Scrub.With this mode enabled, the memory controller not
only detects multiple-bit errors and correct single-bit errors, it also vrites the corrected single-
bit value back into memory' Hovever, the scrubbing operation results in even more overhead.
Generally speaking, the Check Only mode isn`t particularly usetul because it only otters error
checking and reporting. Lsers ot LCC memory modules s hould tocus mainly on the Correct
Lrrors and Correct+Scrub modes because they actually improve data integrity by correcting
single-bit errors. Ot course, it you are using normal, non-LCC memory modules, you must
select the Disabled mode'
lor more intormation on hov LCC vorks, please reter the DRAM Data Integrity Mode
BIOS teature.
S0AM LLL ScIIng 121
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SDRAM Idlo Linit
Connon Options: Disabled, 0 Cycle, 8 Cycles, 12 Cycles, 16 Cycles, 24 Cycles, 32 Cycles,
48 Cycles
1his BIOS teature sets the number ot idle cycles alloved betore the memory controller torces
such open pages to clos e and precharge.
It can be set to a variety ot clock cycles trom 0 Cycle to 48 Cycles.1his sets the number ot
clock cycles the open pages are alloved to idle betore they are closed and precharged.1here`s
also a Disabled option.
It you select Disabled, the memory controller never precharges the open pages prematurely.
1he open pages are lett activated until they have to be precharged.
1he detault value is 8 cycles, vhich allovs the memory controller to precharge the open pages
once eight idle cycles have passed.
lor general desktop use, it is recommended that you disable this teature, so precharging can be
delayed tor as long as possible.1his reduces the number ot retreshes and increases the ettective
memory bandvidth.
you select 0 Cycle as subsequent data requests are most likely tultilled by other pages. Closing
open pages to precharge prepares those pages tor the next data request that hits them.1here`s
also the added benetit ot increased data integrity due to more trequent retreshes.
SDRAM LoodoII Connond
1his BIOS teature is actually a misnomer. It should actually be called the SDRAM Connand
Leadoff 1ine.
By detinition, the connand leadoff tine is the period betveen the assertion ot the
the memory module.
SDPAM Ieadott Command to 3 clock cycles tor better memory pertormance.
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SDRAM Pogo Closing Policy
Connon Options: One Bank, All Banks
1his BIOS teature is similar to SDRAM Precharge Control.
1his BIOS teature determines vhether the chipset should try to leave the pages open (by clos-
ing just one open page, or try to keep them closed (by closing all open pages, vhenever there
is a page miss.
1he One Bank setting torces the memory controller to close only one page vhenever a page
miss occurs.1his allovs the other open pages to be accessed at the cost ot only one clock cycle.
Hovever, vhen a page miss occurs, there is a chance that subsequent data requests result in page
misses as vell. In long memory reads that cannot be satistied by any ot the open pages, this may
cause up to four tull latency reads to occur.
1he All Banks setting, on the other hand, torces the memory controller to send an All Banks
Precharge Connand to the SDPAM intertace vhenever there is a page miss.1his causes all
the open pages to close (precharge,.1heretore, subsequent reads only need to activate the neces-
sary memory bank.1his is usetul in cases vhere subsequent data requests also result in page
misses.
As you can see, both settings have their advantages and disadvantages. Hovever, you should see
better pertormance vith the One Bank setting because the open pages allov very tast accesses.
1he All Banks setting, hovever, has the advantage ot keeping the memory contents retreshed
more otten.1his improves data integrity, although it is only usetul it you have chosen a
SDPAM refresh interval that is longer than the standard 64 msec.
1heretore, it is recommended that you select the One Bank setting tor better memory per-
tormance.1he All Banks setting can improve data integrity, but it you are keeping the
SDPAM retresh interval vithin specitication, then it is ot little use.
SDRAM Pogo Hit Linit
Connon Options: 1 Cycle, 4 Cycles, 8 Cycles, 16 Cycles, 32 Cycles
1his BIOS teature is designed to reduce the data starvation that occurs vhen pending non-page
hit requests are unduly delayed. It does so by limiting the number ot consecutive page hit
requests that are processed by the memory controller betore attending to a non-page hit
request.
Generally, the detault value ot 8 Cycles should provide a balance betveen pertormance and tair
memory access to all devices. Hovever, you can try using a higher value (16 Cycles, tor better
memory pertormance by giving priority to a larger number ot consecutive page hit reques ts.
A lover value is not advisable because this normally results in a higher number ot page
interruptions.
S0AM Pagc hI LmI 128
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SDRAM PH Linit
request.
Generally, the detault value ot 8 Cycles should provide a balance betveen pertormance and tair
memory access to all devices. Hovever, you can try using a higher value (16 Cycles, tor better
memory pertormance by giving priority to a larger number ot consecutive page hit reques ts. A
lover value is not advisable because this normally results in a higher number ot page interruptions.
SDRAM Prochorgo Control
1his BIOS teature is similar to SDRAM Page Closing Policy.
1his BIOS teature determines vhether the chipset should try to leave the pages open (by clos-
ing just one open page, or try to keep them closed (by closing all open pages, vhenever there
is a page miss.
When enabled, the memory controller only closes one page vhenever a page miss occurs.1his
allovs the other open pages to be accessed at the cost ot only one clock cycle.
cause up to four tull latency reads to occur.
When disabled, the memory controller sends an All Banks Precharge Connand to the
SDPAM intertace vhenever there is a page miss. 1his causes all the open pages to close
(precharge,.1heretore, subsequent reads only need to activate the necessary memory bank. 1his
is usetul in cases vhere subsequent data requests also result in page misses.
better pertormance vith this teature enabled because the open pages allov very tast acces ses.
Disabling this teature, hovever, has the advantage ot keeping the memory contents retreshed
1heretore, it is recommended that you enable this teature tor better memory pertormance.
Disabling this teature can improve data integrity, but it you are keeping the SDPAM retresh
interval vithin specitication, then it is ot little use.
SDRAM RAS Prochorgo Doloy
1his BIOS teature sets the number ot cycles required tor the PAS to accumulate its charge
betore another rov can be activated. It the PAS Precharge 1ime is too long, it vill reduce
pertormance by delaying all rov activations. Peducing the precharge time to 2 improves
pertormance by alloving a nev rov to be activated earlier.
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Hovever, the short precharge time ot 2 may be insutticient tor some memory modules. In such
cases, the active rov may lose its contents betore they can be returned to the memory bank and
the rov deactivated. 1his may cause data loss or corruption vhen the memory controller
attempts to read trom the active rov or vrite to it.
1heretore, it is recommended that you reduce the SDPAM PAS Precharge Delay to 2 tor bet-
ter pertormance, but increase it to 3 or 4 it you experience system s tability issues atter reducing
the precharge time.
SDRAM RAS Prochorgo lino
betore another rov can be activated. It the PAS Precharge 1ime is too long, it reduces per-
tormance by delaying all rov activations. Peducing the precharge time to 2 improves pertorm-
ance by alloving a nev rov to be activated earlier.
1heretore, it is recommended that you reduce the SDPAM PAS Precharge 1ime to 2 tor bet-
ter pertormance, but increase it to 3 or 4 it you experience system stability issues atter reducing
the precharge time.
SDRAM RAS Pulso Width
rov active time (tPAS,.1his constitutes the time vhen a rov is activated until the time the
lor optimal pertormance, use the lovest value you can. Lsually, this should be CAS latency
tPCD 2 clock cycles . lor example, it you set the CAS latency to 2 clock cycles and the
Hovever, it you start getting memory errors or system crashes, increase the tPCD value one
S0AM AS Pu|sc WdIh 126
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SDRAM RAS-to-CAS Doloy
1his BIOS teature allovs you to set the delay betveen the PAS and CAS signals.1he appropri-
ate delay tor your memory module is retlected in its rated timings. In LDLC specitications, it is
the secono number in the three or tour number sequence.
Because this delay occurs vhenever the rov is retreshed or a nev rov is activated, reducing the
delay improves pertormance.1heretore, it is recommended that you reduce the delay to 3 or 2
tor better memory pertormance.
Please note that it you use a value that is too lov tor your memory module, this can cause the
system to be unstable. It your system becomes unstable atter you reduce the PAS-to-CAS delay,
you should increase the delay or reset it to the rated delay.
Interestingly, increasing the PAS-to-CAS delay may allov the memory module to run at a
higher clock speed. So, it you hit a snag vhile overclocking your SDPAM modules, you can try
increasing the PAS-to-CAS delay.
SDRAM Row Activo lino
tPCD to 3 clock cycles, the optimum tPAS value is 7 clock cycles.
SDRAM Row Cyclo lino
Connon Options: 7, 8, 9, 10, 11, 12, 13
1his BIOS teature controls the memory module`s Pov Cycle 1ime or tPC.1he rov cycle
time determines the minimum number ot clock cycles a memory rov takes to complete a tull
cycle, trom rov activation up to the precharging ot the active rov.
lormula-vise, the rov cycle time (tRC, = minimum rov active time (tRAS, rov precharge
time (tRP,. 1heretore, it is important to tind out vhat the tPAS and tPP parameters are betore
setting the rov cycle time.
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It the rov cycle time is too long, it can reduce pertormance by unnecessarily delaying the acti-
vation ot a nev rov atter a completed cycle. Peducing the rov cycle time allovs a nev cycle
to begin earlier.
Hovever, it the rov cycle time is too short, a nev cycle may be initiated betore the active rov
is sutticiently precharged.When this happens, there may be data loss or corruption.
lor optimal pertormance, use the lovest value you can, according to the tPC = tPAS tPP
tormula. lor example, it your memory module`s tPAS is 7 clock cycles and its tPP is 4 clock
cycles, then the rov cycle time or tPC should be 11 clock cycles.
SDRAM lros lining Voluo
SDRAM lrc lining Voluo
Connon Options: 7, 8, 9, 10, 11, 12, 13
1his BIOS teature controls the memory module`s Pov Cycle 1ime or tPC.1he rov cycle
to begin earlier.
lor optimal pertormance, use the lovest value you can, according to the tPC = tPAS tPP
S0AM Jrc Jmng va|uc 127
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SDRAM lrcd lining Voluo
1his BIOS teature allovs you to set the delay betveen the PAS and CAS signals.1he appropri-
ate delay tor your memory module is retlected in its rated timings. In LDLC specitications, it is
the secono number in the three- or tour-number sequence.
Because this delay occurs vhenever the rov is retreshed or a nev rov is activated, reducing the
delay improves pertormance.1heretore, it is recommended that you reduce the delay to 3 or 2
tor better memory pertormance.
Please note that it you use a value that is too lov tor your memory module, this can cause the
system to be unstable. It your system becomes unstable atter you reduce the tPCD timing
value, you should increase the delay or reset it to the rated delay.
Interestingly, increasing the tPCD timing value may allov the memory module to run at a
increasing the tPCD timing value.
SDRAM lrp lining Voluo
betore another rov can be activated. It the tPP timing value is too long, it reduces pertormance
by delaying all rov activations. Peducing the precharge time to 2 improves pertormance by
alloving a nev rov to be activated earlier.
1heretore, it is recommended that you reduce the SDPAM tPP timing value to 2 tor better
pertormance, but increase it to 3 or 4 it you experience system stability issues atter reducing the
precharge time.
lor desktop PCs, a delay ot 2 cycles is recommended as current surges aren`t really important.
1he pertormance benetit ot using the shorter 2 cycles delay is ot tar greater interest. 1he shorter
improves the DDP device`s read and vrite pertormance.
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SDRAM lrrd lining Voluo
lor desktop PCs, a delay ot 2 cycles is recommended as current surges aren`t really important.
1he pertormance benetit ot using the shorter 2 cycles delay is ot tar greater interest. 1he shorter
improves the DDP device`s read and vrite pertormance.
SDRAM Writo Rocovory lino
Connon Options: 1 Cycle, 2 Cycles, 3 Cycles
1his BIOS teature controls the Write Recovery 1ine (tWR, ot the memory modules.
It specities the amount ot delay (in clock cycles, that must elapse atter the completion ot a valid
vrite operation betore an active bank can be precharged.1his delay is required to guarantee
that data in the vrite butters can be vritten to the memory cells betore precharge occurs.
1he shorter the delay, the earlier the bank can be precharged tor another readvrite operation.
1his improves pertormance but runs the risk ot corrupting data vritten to the memory cells.
It is recommended that you select 2 Cycles it you are using DDP200 or DDP266 memory
modules and 3 Cycles it you are using DDP333 or DDP 400 memory modules .You can try
using a shorter delay tor better memory pertormance, but it you tace stability issues, revert to
the specitied delay to correct the problem.
SDRAM Writo to Rood Connond Doloy
Connon Options: 1 Cycle, 2 Cycles
last valid urite operation and the next reao command to the same internal bank ot the DDP
device.
1he 1 Cycle option naturally otters taster svitching trom vrites to reads and, consequently,
better read pertormance.
1he 2 Cycles option reduces read pertormance, but it improves stability, especially at higher clock
speeds. It may also allov the memory chips to run at a higher speed. In other vords, increasing
this delay may allov you to overclock the memory module higher than is normally possible.
It is recommended that you select the 1 Cycle option tor better memory read pertormance it
you are using DDP266 or DDP333 memory modules.You can also try using the 1 Cycle
option vith DDP400 memory modules. Hovever, it you tace stability iss ues, revert to the
detault setting ot 2 Cycles.
S0AM WrIc Io cad Lommand 0c|ay 120
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Socond Boot Dovico
IAN, Disabled
1his BIOS teature allovs you to select the second device trom vhich the BIOS attempts to
load an operating system. It the BIOS tinds and loads an operating system trom the device
selected through this teature, it doesn`t load another operating system, even it you have one on a
ditterent device.
By detault, HDD-0 is the second boot device in practically all motherboards. Hovever, unless
you boot otten trom the tloppy drive (vhich is otten the tirst boot device, , it is better to set
your hard disk (HDD-0, as the tirst boot device.1his shortens the boot process because the
BIOS no longer needs to check the tloppy drive tor a bootable operating system.
More importantly, doing so prevents the BIOS trom loading the vrong operating system in case
you torgot to remove the boot disk trom the tloppy drive' 1his also indirectly prevents the load-
ing ot any virus-intected tloppy disk that vas lett in the drive during booting.
Socurity Sotup
Connon Options: System, Setup
1his BIOS teature controls the application ot the BIOS` passvord protection. It only vorks atter
you have created a passvord through the Passvord Setting option in the main BIOS screen.
Selecting the Systen option torces the BIOS to ask tor the passvord every time the system
boots up.
It you choose Setup, then the passvord is only required tor access to the BIOS.1his option is
usetul tor system administrators or computer resellers vho need to keep novice users trom
messing around vith the BIOS.:
Shodowing Addross Rongos
Connon Options: C8000-CBlll, CC000-Cllll, D0000-D3ll, D4000-D7lll, D8000-
DBlll, DC000-Dllll, Disabled
1his BIOS teature allovs you to cordon ott specitic memory blocks (xxxx-xxxx, to shadov the
BIOS ot certain add-on cards. 1his improves the pertormance ot cards that are accessed and
controlled through their BIOS, as opposed to drivers. Currently, this is mostly limited to
bootable netvork cards.
lor most users, there is absolutely no need tor this teature becaus e modern operating systems
directly access hardvare through drivers. Shadoving your device`s BIOS just vastes memory.
1heretore, it is recommended that you disable this teature.
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Shoro Monory Sizo
GPL.
Slovo Drivo PIO Modo
Slave IDL drive attached to that particular IDL channel.
tor.
S|avc 0rvc PI0 Modc 181
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Slovo Drivo UltroDMA
available, tor the Slave IDL device attached to that particular IDL channel.
drive.
mode supported,.
Spood Lrror Hold
1his BIOS teature prevents accidental overclocking by preventing the s ystem trom booting up it
the processor clock speed vas not properly set.
When enabled, the BIOS checks the processor clock speed at boot up and halts the boot
process it the clock speed is ditterent trom that imprinted in the processor ID. It also displays an
error message to varn you that the processor is running at the vrong speed.
It you are thinking ot overclocking the processor, you must disable this teature because it pre-
vents the motherboard trom booting up vith an overclocked processor.When disabled, the
BIOS does not check the processor clock speed at boot up. It allovs the system to boot vith the
clock speed set in the BIOS, even it it does not match the processor`s rated clock speed (as
imprinted in the proces sor ID,.
Although this may seem really obvious, I have seen countless overclocking initiates puzzling
over the error message vhenever they try to overclock their processors. So, betore you start
pulling your hair out and screaming hysterically that Intel or AMD has tinally implemented a
clock speed lock on their proces sors, try disabling this teature.
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Split Lock Oporotions
1his is a debug teature specitic to the Intel Pentium 4 and the Intel Pentium 4 Xeon processors.
It allovs you to prevent the processor trom issuing split lock cycles to the processor bus it such
operations cause problems.
Split lock cycles can potentially cause problems in certain situations. lor example, the Split
Lock Cycles bug in the Intel 82860 MCH.
Lsually, it is recommended that you leave Split Iock Operation at its detault setting ot
Lnabled. 1his allovs the processor to issue split lock cycles to the processor bus. Hovever, it
you are using a motherboard based on the Intel 82860 chipset, you should disable this teature.
1here may be other situations vhere split lock cycles can cause problems. It your system hangs
or crashes tor no apparent reason, you can try disabling this teature and see it it solves the prob-
lem. Othervise, leave it Lnabled.
Sprood Spoctrun
Connon Options: 0.23, 0.3, Smart Clock, Disabled
1his BIOS teature allovs you to reduce the LMI ot your motherboard by modulating the sig-
nals it generates, so the spikes are reduced to tlatter curves. It achieves this by varying the tre-
quency siihti, so the signal does not use any particular trequency tor more than a moment.
1he BIOS usually otters tvo levels ot modulation0.2S or 0.S.1he greater the modula-
tion, the greater the reduction ot LMI.1heretore, it you need to signiticantly reduce your
motherboard`s LMI, a modulation ot 0.S is recommended.
In most conditions, trequency modulation through this teature does not cause any problems.
Hovever, system stability may be slightly compromised in certain situations. lor example, this
BIOS teature may cause improper tunctioning ot timing-critical devices, such as clock-s ensitive
SCSI devices.
Spread Spectrum can also cause problems vith overclocked systems, especially those that have
been taken to extremes. Lven a slight modulation ot trequency may cause the processor or any
other overclocked components ot the system to tail, leading to very predictable consequences.
1heretore, it is recommended that you disable this teature it you are overclocking your system.
Some BIOSes also otter a Snart Clock option. Instead ot modulating the trequency ot signals
over time, Smart Clock turns ott the AGP, PCI, and SDPAM clock signals that are not in use.
1heretore, LMI can be reduced uithout compromising system stability. As a bonus, using Smart
Clock also helps reduce pover consumption. 1he degree ot LMI and pover reduction depend
on the number ot empty AGP, PCI, and SDPAM slots. Hovever, generally, Smart Clock is
unable to reduce LMI as ettectively as simple trequency modulation.
With that said, it is recommended that you enable Snart Clock, instead ot the 0.2S or S
options, it the option is available to you. It allovs you to reduce some LMI vithout any risk ot
compromising your computer`s stability.
Sprcad SpccIrum 188
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Supor Byposs Modo
1his BIOS teature basically allovs the nenory request organizer (MRO, ot the memory
controller to skip certain pipeline stages vhile transterring data to and trom the memory sub-
system.
1his improves memory pertormance by alloving lover latency accesses to the memory subsys-
tem. Hovever, this teature can only be sately enabled it the tolloving conditions are true:
1he system only has a single processor present. Systems using dual-processor mother-
boards can enable this teature it only one processor is present.
1he processor clock speed multiplier must be 4 or greater.1his means the processor must
be running at least tour times taster than its bus speed.
lor better memory pertormance, it is recommended that you enable this teature. Hovever, you
must make sure that you are only using a single processor that is running at least tour times
taster than the processor bus.You should disable this teature it your system does not meet the
tvo requirements stated above.
Supor Byposs Woit Stoto
1his BIOS teature is used to tine-tune the Super Bypass teature to correct tor internal timing
variations.
When set to 0 Cycle, the memory controller initiates all super bypass requests vithout delay.
When set to 1 Cycle, the memory controller torces a vait state delay tor all super bypass
requests.
Otticial documents recommend that a vait state be added tor a 133MHz (266MHz DDP,
memory bus. Systems using a 100MHz (200MHz DDP, memory bus do not need this delay.
lorcing a vait state on all super bypass requests reduces the ettectiveness ot the Super Bypass
teature.1heretore, it is recommended that you try using the 0 Cycle setting tor maximum per-
tormance.
Hovever, it you experience system stability issues atter using this 0 Cycle setting, set this tea-
ture to 1 Cycle. 1his slovs dovn super bypass transactions but allovs your system to use the
Super Bypass teature at higher clock speeds.
SuporStobility Modo
1his is a NVIDIA nForce chipset-specitic BIOS teature. It controls the hitherto hidden tea-
ture ot the nlorce chipset, vhich iocks the memory clock at 200MHz instead ot the rated
266MHz vhen it detects a memory module that is not compatible vith the motherboard.1his
allovs the us e ot substandard or incompatible memory modules, albeit at reduced pertormance.
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1he chipset only allovs the memory clock to be set at 266MHz vhen it is satistied that each
and every memory module installed has met its standard. It even a s ingle module tails to meet
the standard, the chipset locks the memory clock at 200MHz, irrespective ot the clock speed at
vhich it vas set to run.
While NVIDIA claims that this teature allovs nlorce motherboards to vork vith substandard
or incompatible memory modules that vould othervise be unusable, there have been reports
that even compatible memory modules are being locked dovn to 200MHz. Apparently, loading
the second slot (Slot B, ot the second memory controller vith a double-sided DIMM also
causes SuperStability to kick in.
Atter this teature vas discovered by Chris Connolly ot GamePC, the BIOS vas revised to
include this SuperStability Mode teature.1his allovs you to svitch the SuperStability teature
on or ott.
When lett at the detault setting ot Lnabled, the nlorce chipset locks the memory clock at
200MHz it it detects an incompatible memory module or it Slot B ot the second memory con-
troller is tilled vith a double-sided memory module.
When disabled, the nlorce chipset does not check the memory modules tor incompatibility or
Slot B ot the second memory controller tor a double-sided memory module.1he memory
modules are alloved to run at the clock speed you set.
It is highly recommended that you disable SuperStability Mode tor better SDPAM pertorm-
ance, especially it you use all three DIMM slots.1here is really no need to enable it because you
can lover the memory clock speed yourselt or increase their timings in order to use incompati-
ble memory modules.
Swop Iloppy Drivo
When this BIOS teature is enabled, the tloppy drive that originally vas mapped to drive A: is
remapped to drive B: and vice-versa tor the drive that vas originally set as drive B:.
When this BIOS teature is disabled, the tloppy drive mapping remains as that set by the drive
connector arrangement.
tant it you are using tvo tloppy drives ot ditterent torm tactors (3.3 and 3.23, and you need
to boot trom the second drive. Because the BIOS can only boot trom drive A:, you have to
physically svap the drive connections or use this teature to do it logically.
need to enable this teature. Ieave it at the detault setting ot disabled.
Swap F|oppy 0rvc 186
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Synchronous Modo Soloct
Connon Options: Synchronous,Asynchronous
1his BIOS teature controls the signal synchronization ot the DPAM-CPL intertace.
When set to Synchronous, the chipset synchronizes the signals trom the DPAM controller
vith signals trom the CPL bus (or tront side bus,. Please note that tor the signals to be synchro-
nous, the DPAM controller and the CPL bus must run at the same clock speed.
When set to Asynchronous, the chipset decouples the DPAM controller trom the CPL bus.
1his allovs the DPAM controller and the CPL bus to run at ditterent clock speeds.
Generally, it is advisable to use the Synchronous setting because a synchronized intertace
allovs data transters to occur vithout delay.1his results in a much higher throughput betveen
the CPL bus and the DPAM controller.
Syston BIOS Cochooblo
Lnabling this teature allovs the caching ot the motherboard BIOS POM trom F0000h to
FFFFFh by the processor`s Level 2 cache.1his greatly speeds up accesses to the BIOS.
Hovever, this does not translate into better system pertormance because modern operating sys-
tems like Microsott Windovs XP do not need to communicate vith the hardvare through the
BIOS. Current operating systems make use ot drivers to access the hardvare directly.
1heretore, it is a vaste ot the Ievel 2 cache`s bandvidth it the motherboard BIOS vas cached
instead ot data that are more critical to the system`s pertormance.
In addition, it any errant program vrites into this memory area, it results in a system crash.
1heretore, it is highly recommended that you disable this teature tor better system
pertormance.
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l
lhird Boot Dovico
IAN, Disabled
1his BIOS teature allovs you to select the third device trom vhich the BIOS attempts to load
an operating system. It the BIOS tinds and loads an operating system trom the device selected
through this teature, it von`t load another operating system, even it you have one on a ditterent
device.
By detault, LS/ZIP is the third boot device in practically all motherboards. Because the third
boot device is only tried atter no bootable operating system can be tound in the tirst tvo boot
devices, it is ot little consequence vhat you set here.1heretore, the choice ot boot device tor
this BIOS teature is entirely up to your personal preterence.
l, R Invorting Lnoblo
Connon Options: No-No, No-Yes,Yes-No,Yes-Yes
polarity.
out.
1here are tour options available based on combinations ot Yes (read as High, and No (read as
Lov,.You`ll need to consult your IP peripheral`s documentation to determine the correct
polarity. Choosing the vrong polarity prevents a proper IP connection trom being established
vith the IP peripheral.
lyponotic Roto
Connon Options: 6, 8, 10, 12, 13, 20, 24, 30
1his BIOS teature only vorks it the 1ypenatic Rate Setting teature has been enabled.
1his teature determines the rate at vhich the keyboard repeats a keystroke it you press it con-
tinuously.
1he available settings are in characters per second.1heretore, a typematic rate ot 30 causes the
keyboard to repeat the keystroke at a rate ot 30 characters per second it you press a particular
key continuously. 1he higher the typematic rate, the taster the keyboard repeats the keystroke.
JypcmaIc aIc 187
1
1he choice ot vhat setting to use is entirely up to your personal preterence. Hovever, note that
through the BIOS, like MS-DOS. 1he typematic rate in operating systems like Windovs XP
are controlled by the keyboard driver`s settings.
lyponotic Roto Doloy
Connon Options: 230, 300, 730, 1000
1his BIOS setting only vorks it the 1ypenatic Rate Setting teature has been enabled.
1his teature determines hov long, in nilliseconds (thousandths ot a second,, the keyboard
controller vaits betore it starts repeating the keystroke that you have pressed continuously.1he
longer the delay, the longer the keyboard controller vaits betore it starts repeating the keystroke.
lyponotic Roto Sotting
1his BIOS teature allovs you to gain manual control ot the keystroke repeat teature.
When enabled, you are given access to these tvo typematic controls:
1ypematic Pate
1ypematic Pate Delay
1hey allov you to manually adjust the 1ypenatic Rate and the 1ypenatic Rate Delay.
It you disable this teature, the tvo typematic controls are disabled and grayed out.1he key-
board controller thereby uses the detault typematic rate and typematic rate delay.
1
U
Ultro DMA Modo
Connon Options: Disabled, 0, 1, 2, 3, 4, 3, 6, Auto
available, tor the IDL device.
drive.
Setting this BIOS teature to 0 torces the BIOS to use DMA Mode 0 tor DMA transters.
Setting this BIOS teature to 3 torces the BIOS to use UltraDMA 33 tor DMA transters.
Setting this BIOS teature to S torces the BIOS to use UltraDMA 100 tor DMA transters.
alloving it to burst data trom anyvhere betveen 33MBs to 133MBs (depending on the
transter mode supported,.
port torce the drive to use the slover PIO transter mode.1his may allov the drive to vork
UltroDMA-100 IDL Controllor
1his BIOS teature is only tound in certain motherboards that come vith an additional built-in
IDL controller. It allovs you to enable or disable the tunction ot that IDL controller.
It you vant to attach one or more IDL devices to the external LltraDMA100 controller, you
should enable this teature.You should only disable this BIOS teature tor the tolloving reasons:
It you do not have any IDL device attached to the external LltraDMA100 controller
lor troubleshooting purposes
u|Ira0MA-100 I0L LonIro||cr 180
L
Disabling the external IDL controller trees up tvo IPQs, vhich can be used by other devices
in the system. It also speeds up the boot-up sequence because the external IDL controller`s
BIOS no longer needs to be loaded.Your system is also able to skip the external controller`s
long boot-up check and initialization sequence.
1heretore, it you do not use the external IDL controller, it is recommended that you disable it
tor a much taster booting process.
BIOS no longer needs to be loaded.Your system also is able to skip the external controller`s
UltroDMA- IDL Controllor
BIOS no longer needs to be loaded.Your system also is able to skip the external controller`s
L
USB Controllor
1his BIOS teature enables or disables the motherboard`s onboard LSB controller.
It is recommend that you enable this teature, so you can use the onboard LSB controller to
It you disable this teature, the LSB controller is disabled and you are unable to use it to com-
any LSB device or you are using a ditterent LSB controller tor your LSB needs.
USB Royboord Support
Connon Options: OS, BIOS
1his BIOS teature determines vhether support tor the LSB keyboard s hould be provided
by the operating system or the BIOS.1heretore, it only attects those vho are using LSB
keyboards.
It your operating system otters native support tor LSB keyboards, you should select the OS
option.1his provides much greater tunctionality. Hovever, it you are using DOS or operating
systems that do not otter support tor LSB keyboards, then using the OS option essentially dis-
ables the keyboard because these operating systems cannot detect or vork vith LSB keyboards.
1his is vhere the BIOS option comes in.When selected, the BIOS provides support tor the
LSB keyboard.You are able to use the keyboard vith both operating systems that do not sup-
port LSB keyboards and those that do.
Hovever, the BIOS option otters only rudimentary support tor the LSB keyboard, so using it
strips the keyboard ot all except basic tunctions.1heretore, you should not select this option it
you are using an operating system that supports LSB keyboards. It is recommended that you
select the OS option it you are using a current operating system like Windovs XP.
Hovever don`t torget to svitch trom the OS option to the BIOS option vhenever you vant
to boot up using a DOS boot disk. Lven it the boot disk vas created by a LSB-avare operating
system like Windovs XP, it does not support the LSB keyboard.
USB Mouso Support
1his BIOS teature determines vhether support tor the LSB mouse should be provided by the
operating system or the BIOS.1heretore, it only attects those vho are using LSB mice.
It your operating system otters native support tor LSB mice, you should select the OS option.
1his provides much greater tunctionality. Hovever, it you are using DOS or operating systems
that do not otter support tor LSB mice, then using the OS option essentially disables the mouse
because thes e operating systems cannot detect or vork vith LSB mice.
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LSB mouse.You are able to use the mouse vith both operating systems that do not support
LSB mice and those that do.
Hovever, the BIOS option otters only rudimentary support tor the LSB mouse, so using it
strips the mouse ot all except basic tunctions. 1heretore, you should not select this option it you
are us ing an operating system that supports LSB mice. It is recommended that you select the
OS option it you are using a current operating system like Windovs XP.
Hovever don`t torget to svitch trom the OS option to the BIOS option vhenever you vant
system like Windovs XP, it does not support the LSB mouse.
USWC Writo Posting
It is highly recommended that you enable this teature tor improved graphics and processor per-
tormance.
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Vidoo BIOS Cochooblo
1his BIOS teature aims to turther boost the pertormance ot a shadoved video BIOS by
caching it using the processor`s Ievel 2 cache. It vorks in conjunction vith Video BIOS
Shadoving and is only valid vhen the Video BIOS Shadoving teature is enabled.
It this BIOS teature is enabled, a 32KB block ot the video BIOS trom C0000hC7FFFh is
cached by the processor`s Ievel 2 cache.1his greatly speeds up su|seuent consecuti:e accesses to
the video BIOS.
It this BIOS teature is disabled, the video BIOS is not cached. 1he video BIOS is read trom
the system memory (it it has been shadoved, or directly trom the BIOS chip.
Hovever, caching the video BIOS does not necessarily translate into better system pertormance.
lirst ot all, modern operating systems like Microsott Windovs XP do not need to use the video
BIOS. 1hey bypass the BIOS completely and use the graphics card`s driver instead. 1heretore,
absolutely no benetit can be realized by caching the BIOS.
Lnlike system memory, vhich can be a gigabyte or more, the processor`s I2 cache is a limited
resource. Diverting such a large portion ot the I2 cache tor the purpose ot caching the video
BIOS deprives the processor ot I2 cache tor its ovn data. Consequently, there is a signiticant
deterioration in processor pertormance vhenever the video BIOS is cached.
As vith the Video BIOS Shadoving teature, llash POM upgrades should not be attempted
it the video BIOS is cached. It the video BIOS is cached, any attempt at tlashing the video
BIOS vill likely result in a system crash. Worst ot all, because only 32KB ot the video BIOS is
cached, the end result is usually a corrupted video BIOS.
Ot course, caching the video BIOS theoretically provides a signiticant boost in real-mode DOS
games or certain operating systems in tail-sate mode. Hovever, the loss ot the processor`s I2
cache negates any pertormance advantage gained by caching the video BIOS.
1heretore, it is recommended that you disableVideo BIOS Caching, even it you play a lot ot
real-mode DOS games or vork vith operating systems running in tail-sate mode.
Vidoo BIOS Shodowing
1his BIOS teature allovs taster access to the video BIOS by shaoouin or making a copy ot it in
the system memory.1his appears quite an attractive teature because it results in at least a
thousand-told improvement in video BIOS pertormance, and the only price you pay is los ing
the small amount ot system memory us ed to mirror the video BIOS. Lntortunately, the truth is
not so simple.
vdco 8I0S Shadowng 148
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Modern operating sys tems do not even use the video BIOS. 1hey bypass the BIOS completely
and use the graphics card`s driver instead.1heretore, absolutely no benetit can be realized by
shadoving the BIOS.
In addition, shadoving the video BIOS can sometimes cause contlicts to occur. 1here is alvays
a risk ot certain sottvare vriting to the PAM region used to shadov the video BIOS. When
this happens, a contlict occurs and the system crashes.
What could be a bigger issue vould be the shadoving ot just a portion ot the video BIOS.
Never video BIOSes are generally much larger than 32KB in size. Hovever, most mother-
boards shadov only a 32KB block trom C0000 to C7FFF. It only this region ot the video
BIOS is shadoved and the rest lett unshadoved, applications may have trouble accessing the
video BIOS properly.
linally, all graphics cards nov use llash POM, vhich allovs easy upgrading ot the tirmvare by
a simple BIOS tlash. Hovever, it the video BIOS is shadoved, any attempt at tlas hing the video
BIOS vill likely result in a system crash. It could be even vorse it only a portion ot the video
BIOS had been shadoved vhen the video BIOS upgrade vas attempted.
With all that said, there may still be a use or tvo tor this BIOS teature. lor one thing, most
real-mode DOS games use the video BIOS`s VGA tunctions because they cannot directly access
the graphics processor. Such games benetit trom the shadoving ot the video BIOS.
Shadoving ot the video BIOS also provides pertormance benetits vhen it comes to the tail-sate
mode ot certain operating systems (tor example, Sate Mode in Microsott Windovs XP,.1hese
operating systems tall back on the video BIOS because all video BIOSes contain the same, stan-
dardized VGA tunctions.
It this BIOS teature is enabled, the video BIOS is shadoved in system memory.1his improves
graphics rendering pertormance it the VGA tunctions ot the video BIOS are used.
It this BIOS teature is disabled, the video BIOS is no shadoved in system memory. Any access
to the video BIOS must go through the X1 or IPC bus.
Because drivers have replaced the video BIOS as the intertace betveen the graphics hardvare
and the operating system, it is recommended that you disableVideo BIOS Shadoving.1he risk
ot crashes and BIOS corruptions due to this BIOS teature is not vorth the benetits it provides
in certain circumstances.
Hovever, it you do play a lot ot old real-mode DOS games or vork a lot in sate-mode
Windovs, then you should shadov the video BIOS tor improved pertormance.
Vidoo Monory Cocho Modo
Connon Options: LSWC, LC
1his is yet another BIOS teature vith a misleading name. It does not cache the video memory
or even graphics data (such data is uncacheable anyvay,.
It enabled, the vrite combine butters accumulates and combines partial or smaller graphics
vrites trom the processor and vrites them to the graphics card as burst vrites.
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pertormance.
Vidoo RAM Cochooblo
1his BIOS teature aims to boost VGA graphics pertormance by using the processor`s Ievel 2
cache to cache the 64KB VGA graphics memory area trom A0000h to AFFFFh.
It this BIOS teature is enabled, the VGA graphics memory area is cached by the processor`s
Level 2 cache.1his speeds up accesses to the VGA graphics memory area.
It this BIOS teature is disabled, the VGA graphics memory area is not cached by the processor`s
Level 2 cache.
lrom vhat ve have discussed so tar, it sounds like caching the VGA graphics memory area is
logically the vay to go. Caching the VGA graphics memory area detinitely speeds up VGA
graphics pertormance by caching accesses to the graphics memory area.
Hovever, reality is tar less ideal. lor one thing,VGA modes are hardly used at all these days. lor
compatibility reason,VGA is still used in Windovs XP`s Safe Mode. It is also used in real mode
DOS, it you still use that. Other than that, there is no more use tor VGA modes. It VGA graph-
ics modes are not used, no benetit can possibly be realized by enabling this BIOS teature.
Lven it you use DOS modes a lot, is there even a point in caching the VGA graphics memory
area tor better pertormance Lven the slovest computer today is more than capable ot handling
VGA graphics vith ease. In short, caching the VGA graphics memory area does not bring any
noticeable advantage.
On the other hand, caching this memory area costs you some processor pertormance. Because
some ot the processor`s Ievel 2 cache is being diverted to cache the VGA graphics memory area,
there is less to keep the process or supplied vith data. Consequently, the processor`s pertormance
sutters.
1heretore, it is highly recommended that you disable this BIOS teature.1here is no reason to
enable it even it you use real mode DOS a lot or vork a lot in Windovs Sate Mode.
Virus Worning
1his BIOS teature provides rudimentary anti-virus protection by monitoring vrites to the boot
sector and partition table.
It this teature is enabled, the BIOS halts the system and tlashes a varning message vhenever it
detects an attempt to vrite to the boot sector or the partition table.
It this teature is disabled, the BIOS does not monitor vrites to the boot sector and partition
table.
vrus Warnng 146
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1his teature can cause problems vith sottvare that need to access the boot sector. One good
example is the installation routine ot all versions ot Micros ott Windovs trom Windovs 93
onvard. When enabled, this teature causes the installation routine to tail. You should disable
this teature betore running such sottvare.
VLink 8 Support
1he VLink 8 Support BIOS teature is used to toggle the V-Iink bus mode betveen the
original V-Iink and the never and taster 8X V-Iink.
It this teature is enabled, the quad-pumped 8-bit V-Iink bus svitches to the nev 8X V-Iink
mode, vhich runs at 133MHz and delivers a bandvidth ot 333MBs.
It this teature is disabled, the V-Iink bus uses a clock speed ot 66MHz, essentially reverting to
the original V-Iink standard. It then delivers a bandvidth ot 266MBs.
1his BIOS teature vas most likely included tor troubleshooting purposes . It is highly recom-
mended that you enable this BIOS teature tor better pertormance.
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Wotchdog linor
1his BIOS teature controls the operation ot the chipset`s Watchdog 1imer.
When enabled, the Watchdog 1imer monitors the time taken tor each task pertormed by the
operating system. Any timeout vill cause it to initiate corrective actions like generate a non-
maskable interrupt or reboot the computer.
When disabled, the Watchdog 1imer does not monitor the time taken tor each task pertormed
by the operating system. Lven it the system locks up, the Watchdog 1imer does not initiate any
corrective action.
It is recommended that you enable the Watchdog 1imer to automatically detect hardvare and
sottvare errors that lock up the computer.While it may do nothing more than automatically
reboot or shut dovn the computer vhen an irresolvable error occurs, there is a chance it may
allov the correction ot the problem and allov the computer to tunction normally.
Writo Doto In to Rood Doloy
device.
1he 2 Cycles option reduces read pertormance but it improves stability, especially at higher
clock speeds. It may also allov the memory chips to run at a higher speed. In other vords,
increasing this delay may allov you to overclock the memory module higher than is normally
possible.
WrIc 0aIa In Io cad 0c|ay 147
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Writo Rocovory lino
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Chapter 4
Detailed Descriptions
Introduction
1his chapter contains in-depth explanations ot each BIOS option and discusses hov I arrived at
the recommended settings.
It you already have a moderate level ot hardvare knovledge, this is the best chapter to read
because it allovs you to achieve a greater understanding ot the various BIOS options and the
logic behind their recommended settings.
1he BIOS options are all arranged alphabetically on separate pages. Iettered tabs are provided
to help you navigate quickly through the chapter.You can also use the 1able ot Contents and
the Category Iook-Lp 1able to quickly access the BIOS option you are interested in.
You should start vith Chapter 3 betore starting vith this chapter it you have only limited
knovledge ot computer hardvare or it you need a quick reterence on BIOS options.
#
Connon Options: NA, 8, 1, 2, 3, 4, 3, 6, 7
1he PCI bus runs at a much higher clock speed than the ISA bus. So, tor ISA cards to vork
properly vith IO cycles trom the PCI bus, additional bus clock cycles must be inserted
betveen each consecutive PCI-originated IO cycle to the ISA bus.
By detault, the bus recovery mechanism inserts 3.3 clock cycles betveen each consecutive 8-bit
IO cycle to the ISA bus.1his teature enables you to insert even more clock cycles betveen
each consecutive 8-bit IO cycle to the ISA bus. lor example, it you choos e 3 cycles, the bus
recovery mechanism inserts a total ot 3.3 cycles 3 cycles = 6.3 cycles betveen each consecu-
tive 8-bit IO cycle. Choosing NA sets the number ot delay cycles to the minimum 3.3 clock
cycles.
Most 8-bit ISA cards vork tine vith the minimum 3.3 delay cycles. Hovever, some ISA cards
may require additional delay cycles. Keep increasing the number ot additional delay cycles until
the card vorks properly.You might also need to increase the number ot delay cycles it you are
overclocking the PCI bus. It possible, set the 8-bit IO Pecovery 1ime to NA tor optimal ISA
bus pertormance. Increase the IO Pecovery 1ime only it you are having problems vith your
8-bit ISA cards.
Note that this teature is only valid it you are using 8-bit ISA cards. It has no ettect it there are
no 8-bit ISA devices in the system.
Connon Options: NA, 4, 1, 2, 3
1he PCI bus runs at a much higher clock speed than the ISA bus. So, tor ISA cards to vork
properly vith IO cycles trom the PCI bus, additional bus clock cycles must be inserted
betveen each consecutive PCI-originated IO cycle to the ISA bus.
By detault, the bus recovery mechanism inserts 3.3 clock cycles betveen each consecutive 16-
bit IO cycle to the ISA bus. 1his teature enables you to insert even more clock cycles betveen
each consecutive 16-bit IO cycle to the ISA bus. lor example, it you choose 3 cycles, the bus
recovery mechanism inserts a total ot 3.3 cycles 3 cycles = 6.3 cycles betveen each consecu-
tive 16-bit IO cycle. Choosing NA sets the number ot delay cycles to the minimum 3.3 clock
cycles.
Most 16-bit ISA cards vork tine vith the minimum 3.3 delay cycles. Hovever, some ISA cards
may require additional delay cycles. Keep increasing the number ot additional delay cycles until
the card vorks properly.You might also need to increase the number ot delay cycles it you are
overclocking the PCI bus. It possible, set the 16-bit IO Pecovery 1ime to NA tor optimal ISA
bus pertormance. Increase the IO Pecovery 1ime only it you are having problems vith your
16-bit ISA cards .
LhapIcr 4 0cIa|cd 0cscrpIons 160
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Note that this teature is only valid it you are using 16-bit ISA cards. It has no ettect it there are
no 16-bit ISA devices in the system.
32-bit Disk Accoss
1he name 32-bit Disk Access is actually a misnomer because it doesn`t really allov 32-bit
access to the hard disk. 1he IDL intertace is alvays 16-bits in vidth even vhen the IDL con-
troller is on the 32-bit PCI bus.What this teature actually does is command the IDL controller
to combine tvo 16-bit reads trom the hard disk into a single 32-bit double vord transter to the
processor.1his allovs the PCI bus to be used more etticiently as the number ot transactions
required tor a particular amount ot data is ettectively hai:eo'
Hovever, according to a Microsott article (Lnhanceo IDL peration noer 1inoous ^l 4.0,, 32-
bit disk access can cause data corruption under Windovs N1 in some cases. 1heretore,
Microsott recommends that Windovs N1 4.0 users disable 32-bit Disk Acces s.
Microsott took a serious viev ot the issue and corrected it in the Windovs N1 4.0 Service
Pack 2. 1heretore, it is sate to enable 32-bit Disk Access in a Windovs N1 4.0 system, so long
as it has been upgraded vith Service Pack 2.
It is highly advisable to enable 32-bit Disk Access because it realizes the pertormance potential
ot the 32-bit IDL controller and improves the etticiency ot the PCI bus. It you disable it, data
transters trom the IDL controller to the processor only occur in 16-bits chunks. Naturally, this
degrades the pertormance ot the IDL controller as vell as the PCI bus. As such, you should dis-
able this teature oni it you actually tace the possibility ot data corruption (vith an unpatched
version ot Windovs N1 4.0,.
You can als o tind more intormation on the Windovs N1 issue in the details ot the IDL HDD
Block Mode teature.
32-bit lronsIor Modo
1his BIOS teature is similar to the 32-bit Disk Access BIOS teature.
1he name 32-bit 1ransfer Mode is actually a misnomer because it doesn`t really allov 32-bit
transters on the IDL bus.1he IDL intertace is alvays 16-bits in vidth even vhen the IDL con-
troller is on the 32-bit PCI bus.What this teature actually does is command the IDL controller
to combine tvo 16-bit reads trom the hard disk into a single 32-bit double vord transter to the
processor.1his allovs the PCI bus to be used more etticiently as the number ot transactions
required tor a particular amount ot data is ettectively hai:eo'
Hovever, according to a Microsott article (Lnhanceo IDL peration noer 1inoous ^l 4.0,, 32-
bit disk access can cause data corruption under Windovs N1 in some cases. 1heretore,
Microsott recommends that Windovs N1 4.0 users disable 32-bit Disk Acces s.
Pack 2. 1heretore, it is sate to enable 32-bit Disk Access in a Windovs N1 4.0 system, so long
as it has been upgraded vith Service Pack 2.
32-hI Jransfcr Modc 161
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It is highly advisable to enable 32-bit 1ranster Mode because it realizes the pertormance poten-
tial ot the 32-bit IDL controller and improves the etticiency ot the PCI bus. It you disable it,
data transters trom the IDL controller to the processor only occur in 16-bits chunks. Naturally,
this degrades the pertormance ot the IDL controller as vell as the PCI bus. As such, you should
disable this teature oni it you actually tace the possibility ot data corruption (vith an
unpatched version ot Windovs N1 4.0,.
You can als o tind more intormation on the Windovs N1 issue in the details ot the IDL HDD
Block Mode teature.
4
A
Act Bonk A to B CMD Doloy
Connon Options: 2 Cycles, 3 Cycles
Act Bank A to B CMD Delay (short tor Activate Bank A to Activate Bank B
Connand Delay, or tRRD is a DDP timing parameter. It specities the minimum amount ot
time betveen successive AC1IVA1L commands to the same DDP device, even to oifferent inter-
nal banks.1he shorter the delay, the taster the next bank can be activated tor read or vrite
operations. Hovever, because rov activation requires a lot ot current, using a short delay may
cause exces sive current surges.
Because this timing parameter is DDP device-specitic, it may ditter trom one DDP device to
another. DDP DPAM manutacturers typically specity the tPPD parameter based on the rov
AC1IVA1L activity to limit current surges vithin the device. It you let the BIOS automatically
contigure your DPAM parameters, it retrieves the manutacturer-set tPPD value trom the SPD
(Serial Presence Detect, chip. Hovever, you may vant to manually set the tPPD parameter
to suit your requirements.
important.1his is because the desktop PC essentially has an unlimited pover supply, and even
the most basic desktop cooling solution is sutticient to dispel any extra thermal load the current
surges may impose.1he pertormance benetit ot using the shorter 2-cycle delay is ot tar greater
interest. 1he shorter delay means every back-to-back bank activation takes one clock cycle less
to pertorm. 1his improves the DDP device`s pertormance.
Note that the shorter delay ot 2 cycles vorks vith most DDP DIMMs, even at 133MHz
(266MHz DDP,. Hovever, DDP DIMMs running beyond 133MHz (266MHz DDP, may
need to introduce a delay ot 3 cycles betveen each successive bank activation. Select 2 cycles
vhenever possible tor optimal DDP DPAM pertormance. Svitch to 3 cycles only vhen there
are stability problems vith the 2-cycle setting.
In mobile devices like laptops, hovever, it is advisable to use the longer delay ot 3 cycles.
Doing so limits the current surges that accompany rov activations.1his reduces the DDP
device`s pover consumption and thermal output, both ot vhich should be ot great interest to
the road varrior.
AGP 2 Modo
1his BIOS teature is tound on AGP 2X-capable motherboards.When enabled, it allovs the
AGP bus to make use ot the AGP 2X transter protocol to boost the AGP bus bandvidth. It it`s
disabled, then the AGP bus only uses the standard AGP 1X transter protocol.
A0P 2X Modc 168
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1he baseline AGP 1X protocol only makes use ot the rising edge ot the AGP signal tor data
transter. 1his translates into a bandvidth ot 264MBs. Hovever, enabling AGP 2X Mode dou-
bles that bandvidth by transterring data on |oth the rising and talling edges ot the signal.
1hrough this method, the ettective bandvidth ot the AGP bus is doubled, even though the AGP
clock speed remains at the standard 66MHz.1his is the same method by vhich LltraDMA33
derives its pertormance boost.
the AGP 2X transter protocol. So, all you need to do is make sure your graphics card supports
AGP 2X transters. It it does, enable AGP 2X Mode to take advantage ot the taster transter
mode. Disable it only it you are tacing stability issues or it you intend to overclock the AGP
bus beyond 73MHz vith sidebanding support enabled.
Please note that doubling the AGP bus bandvidth through the AGP 2X transter protocol von`t
double the pertormance ot your AGP graphics card.1he pertormance ot the graphics card relies
on tar more than the bandvidth ot the AGP bus.1he pertormance boost is most apparent vhen
the AGP bus is really stressed (tor example, during a texture-intensive game,.
AGP 4 Drivo Strongth
1his BIOS teature is similar to AGP Driving Control. It allovs you to set vhether the AGP
controller should dynamically adjust the AGP driving strength or allov manual contiguration in
the BIOS.
Because ot the tighter tolerances ot the AGP 4X bus, the AGP 4X controller teatures auto-
compensation circuitry that compensates tor the motherboard`s impedance on the AGP bus. It
does this by dynamically adjusting the drive strength ot the IO pads over a range ot tempera-
ture and voltages vhen AGP 4X mode is selected.
1he auto-compensation circuitry has tvo operating modes. By detault, it is set to automatically
compensate tor the impedance once, or at regular intervals, by dynamically adjusting the AGP
Drive Strength.1he circuitry can also be disabled or bypassed. In this case, it is up to the user
(through the BIOS, to vrite the desired drive strength value to the AGP IO pads.
When you set this BIOS teature to Auto, the AGP Drive Strength values are obtained trom the
auto-compensation circuitry. Normally, this is the recommenoeo setting as it allovs the AGP con-
troller to dynamically adjust tor motherboard impedance changes. Hovever, Manual contigura-
tion ot the AGP Drive Strength may be necessary.
Some AGP 4X cards vere not designed according to published AGP 4X signal impedance and
routing guidelines.1heretore, these cards may not vork reliably vith the detault drive strengths
issued by the compensation circuit.1o correct this problem, you can bypass the compensation
circuit and torce the AGP IO pads to use a particular drive strength. Lsually, this is a higher
than normal drive strength.
You can als o make use ot this teature tor overclocking purposes. Increasing the drive strength
increases the stability ot the AGP bus by reducing the impedance trom the motherboard and
boosting the signal strength. Hovever, be very circums pect vhen you increase the AGP Drive
Strength on an overclocked AGP bus because your AGP card may be irreversibly damaged in
the process'
A
lor troubleshooting or overclocking purposes, you should set the AGP 4X Drive Strength to
Manual.1his allovs you to manually set the AGP Drive Strength value through the AGP
Drive Strength P Ctrl and AGP Drive Strength N Ctrl options.
Please note that this teature is a little ditterent trom AGP Driving Control because it usually
AGP 4 Modo
1his BIOS teature is only tound on AGP 4X-capable motherboards.When enabled, it allovs the
AGP bus to make use ot the AGP 4X transter protocol to boost the AGP bus bandvidth. It it`s
disabled, then the AGP bus is only alloved to use the AGP 1X or AGP 2X transter protocol.
transter. 1his translates into a bandvidth ot 264MBs.1he AGP 2X protocol doubles that by
utilizing the talling edge ot the AGP signal tor data transter as vell.
Hovever, the AGP 4X protocol uses tour strobe signals to turther double the bandvidth to just
over 1GBs.1he tour strobes can be used either as tour separate signals (vith data transterred
only on the talling edge, or they can be used as tvo ditterential pairs, transterring data on both
edges ot the signals. Lither vay, the AGP bandvidth is quadrupled over that ot the AGP 1X
transter protocol.
the AGP 4X transter protocol. So, all you need to do is make sure your graphics card supports
mode.You must disable it it your graphics card does n`t support AGP 4X transters.1he BIOS
then reports that the maximum supported transter mode is AGP 2X.
By detault, many motherboards come vith the AGP 4X transter mode disabled. 1his is because
not everyone uses AGP 4X-capable graphic cards. When cards capable ot only AGP 1X or 2X
operation are installed, this teature must be disabled tor the cards to tunction properly. 1o pre-
vent complications vith unintormed users, most manutacturers simply disable AGP 4X mode by
detault.
Hovever, this means that users ot AGP 4X cards unnecessarily lose out on the greater amount
ot bandvidth available through the AGP 4X transter mode. So, it you are using an AGP 4X-
capable graphics card, it`s recommended that you enable this teature tor better AGP bus per-
tormance.
Please note that quadrupling the AGP bus bandvidth t hrough the AGP 4X t ranster protocol
doesn`t really quadruple the pertormance ot your AGP graphics card. 1he pertormance ot
the graphics card relies on tar more than the bandvidth ot the AGP bus. 1he pertormance
boost is most apparent vhen the AGP bus is really stress ed ( tor example, during a texture-
intensive game,.
A0P 4X Modc 166
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AGP 8 Modo
1his BIOS teature is only tound on AGP 8X-capable motherboards. When enabled, it allovs
the AGP bus to make use ot the AGP 8X transter protocol to boost the AGP bus bandvidth. It
it`s disabled, then the AGP bus is only alloved to use the AGP 4X transter protocol.
transter. 1his translates into a bandvidth ot 264MBs.1he AGP 2X protocol doubles that by
utilizing the talling edge ot the AGP signal tor data transter as vell.1he AGP 4X protocol uses
tour strobe signals to turther double the bandvidth to just over 1GBs .
1o double the transter again, the nev AGP 8X protocol nov strobes the source synchronous
signals at 8 times the reterence trequency ot 66MHz.1his allovs AGP 8X to boast a bandvidth
ot 2.1GBs'
1he AGP 8X protocol also boasts the tolloving nev teatures:
Nev terminated signaling scheme vith a lover voltage sving
Dynamic calibration cycle
Isochronous 1ransactions support
Dynamic Bus Inversion support
Support tor multiple AGP ports
Support tor multiple GAP1 page sizes
the AGP 8X transter protocol' So, all you need to do is make sure your graphics card supports
mode.You must disable it it your graphics card does n`t support AGP 8X transters.1he BIOS
then reports that the maximum supported transter mode is AGP 4X.
By detault, many motherboards come vith the AGP 8X transter mode disabled. 1his is because
not everyone uses AGP 8X-capable graphic cards. When cards capable ot only AGP 4X opera-
tion are installed, this teature must be disabled tor the cards to tunction properly.1o prevent
complications vith unintormed users, most manutacturers simply disable AGP 8X mode by
detault.
Hovever, this means that users ot AGP 8X cards unnecessarily lose out on the greater amount
ot bandvidth available through the AGP 8X transter mode. So, it you are using an AGP 8X-
capable graphics card, it`s recommended that you enable this teature tor better AGP bus
pertormance.
Please note that quadrupling the AGP bus bandvidth through the AGP 8X transter protocol
doesn`t quadruple the pertormance ot your AGP graphics card. 1he pertormance ot the graphics
card relies on tar more than the bandvidth ot the AGP bus. 1he pertormance boos t is most
apparent vhen the AGP bus is really stressed ( tor example, during a texture-intensive game,.
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AGP Alwoys Conponsoto
1his teature is somevhat similar to the AGP Drive Strength teature. It determines vhether
the AGP controller should be alloved to dynamically adjust the AGP driving strength or use
preset drive strength values.
Due to the tighter tolerances ot the AGP 4X8X bus, the AGP controller teatures auto-com-
pensation circuitry that compensate tor the motherboard`s impedance on the AGP bus. It does
this by dynamically adjusting the drive strength ot the IO pads over a range ot temperatures
and voltages.
compensate tor the impedance once, or at regular intervals, by dynamically adjusting the AGP
Drive Strength.1he circuitry also can be disabled or bypassed. In this case, it is up to the user
1his is vhere AGP Alvays Conpensate ditters trom the AGP Drive Strength teature.
While AGP Drive Strength allovs you to svitch to manual contiguration by the user, AGP
Alvays Compensate does not. It only allovs you to change the auto-compensation mode.
When you enable AGP Alvays Compensate, the auto-compensation circuitry dynamically
compensates tor changes in the impedance at reuiar inter:ais. It you disable it, the circuitry only
compensates tor the impedance once at boot-up. 1he drive strength values derived at boot-up
remain until the system is rebooted.
It is recommended that you enable AGP Alvays Compensate, so the AGP controller can initiate
dynamic compensation at regular intervals.1his allovs it to compensate tor any changes in the
impedance.
AGP Aporturo Sizo
Connon Options: 4, 8, 16, 32, 64, 128, 236
1his BIOS teature does tvo things. It selects the size ot the AGP aperture and it determines the
1he aperture is a portion ot the PCI memory address range dedicated tor use as AGP memory
address space, vhile the GAP1 is a translation table that translates AGP memory addresses into
actual memory addresses that are otten tragmented.1he GAP1 allovs the graphics card to see
the memory region available to it as a contiguous piece ot memory range.
Host cycles that hit the aperture address range are torvarded to the AGP bus vithout need tor
translation. 1he aperture size also determines the maximum amount ot system memory that can
be allocated to the AGP graphics card tor texture storage.
1he AGP aperture size is calculated using this tormula:
AGP Aperture Size = (Mainun usable AGP nenory size 2) + 12MB
As you can see, the actual available AGP memory s pace is less than halt the AGP aperture size
set in the BIOS.1his is because the AGP controller needs a vrite conbined nenory area
equal in size to the actual AGP memory area (uncached,, plus an additional 12MB tor virtual
addressing.
A0P ApcrIurc Szc 167
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1heretore, it isn`t simply a matter ot determining hov much AGP memory space you need.You
also need to calculate the tinal aperture size by doubling the amount ot AGP memory space
desired and adding 12MB to the total.
Please note that the AGP aperture is merely address space, not actual physical memory in use. It
doesn`t lock up any ot your system memory.1he physical memory is allocated and released as
needed vhenever Direct3D makes a create non-local surtace call.
Windovs 93 (vith VGAP1D.VXD,, and later versions ot Microsott Windovs, use a vatertall
method ot memory allocation. Surtaces are tirst created in the graphics card`s local memory.
When that memory is tull, surtace creation spills over into AGP memory and then system mem-
ory. So, memory usage is automatically optimized tor each application. AGP and system memory
are not used unless absolutely necessary.
Lntortunately, it is very common to hear people recommending that the AGP aperture size
should be halt the size ot system memory. Hovever, this is vrong tor the same reason svaptile
size should not be tixed at 14 ot system memory. Iike the svaptile, the requirement tor AGP
memory space shrinks as the graphics card`s local memory increases in size.1his is because the
graphics card has more local memory to use tor texture storage'
1his reduces the need tor AGP memory.1heretore, vhen you upgrade to a graphics card vith
more memory, you shouldn`t be deceived into thinking that you need even more AGP memory'
On the contrary, a smaller AGP memory space is required.
It your graphics card has very little graphics memory (4MB16MB,, you may need to create a
large AGP aperture, up to halt the size ot the system memory.1he graphics card`s local memory
and the AGP aperture size combined should be roughly around 64MB. Please note that the size
ot the aperture does not correspond to pertormance' Increasing it to gargantuan proportions
does not improve pertormance.
Still, it is recommended that you keep the AGP aperture size around 64MB to 128MB. Nov,
vhy should ve use such a large aperture size vhen most graphics cards come vith large amounts
ot local memory Shouldn`t ve set it to the absolute minimum to save system memory
1. lirst ot all, setting it to a lover memory uon`t save you memory' Don`t torget that all the
AGP aperture size does is limit the amount ot system memory the AGP bus can appropri-
ate vhenever it needs more memory. It is not used unless absolutely necessary. So, setting
the AGP aperture size to 64MB doesn`t mean that 64MB ot your system memory is
appropriated and reserved tor the AGP bus use.What it does is limit the AGP bus to a
maximum ot 64MB ot system memory vhen the need arises.
2. Next, most graphics cards require an AGP aperture ot at least 16MB in size to vork prop-
erly. Many nev graphics cards require even more.1his is probably because the virtual
addressing space is already 12MB in size. So, setting the AGP aperture size to 4MB or
8MB is a big no-no.
3. We should also remember that many sottvare have AGP aperture size and texture s torage
requirements that are mostly unspecitied. Some applications vill not vork vith AGP
apertures that are too small. And some games use so much texture that a large AGP aper-
ture is needed even vith graphics cards vith large memory butters.
4. linally, you should remember that the actual available AGP memory space is less than halt
the size ot the AGP aperture size you set. It you vant just 13MB ot AGP memory tor
texture storage, the AGP aperture has to be at least 42MB in size.1heretore, it makes s ense
to set a large AGP aperture size to cater to all eventualities.
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Nov, vhile increasing the AGP aperture size beyond 128MB doesn`t take up sys tem memory, it
still is best to keep the aperture size in the 64MB128MB range, so the GAP1 von`t become
too big. 1he larger the GAP1 gets, the longer it takes to scan through the GAP1 to tind the
translated address tor each AGP memory address request.
With local memory on graphics cards increasing to incredible sizes and texture compression
commonplace, there`s really not much need tor the AGP aperture size to grov beyond 64MB.
1heretore, it is recommended that you set the AGP Aperture Size to 64MB or at most, 128MB.
AGP Copobility
Connon Options: Auto, 1X Mode, 2X Mode, 4X Mode, 8X Mode
1his BIOS teature is only tound in AGP 8X-capable motherboards.AGP 8X is backvard-
compatible vith earlier AGP standards.1his BIOS teature allovs you to set the motherboard`s
maximum supported AGP transter protocol.
When this BIOS teature is set to Auto, the motherboard automatically selects the appropriate
AGP transter protocol atter detecting the capabilities ot the AGP graphics card.
When this BIOS teature is set to 1 Mode, the motherboard torces the AGP bus to use the
AGP 1X transter protocol. AGP 1X allovs a maximum transter rate ot 266MB/s.
AGP 2X transter protocol. AGP 2X allovs a maximum transter rate ot S33MB/s.
AGP 4X transter protocol. AGP 4X allovs a maximum transter rate ot 1GB/s.
AGP 2X transter protocol. AGP 8X allovs a maximum transter rate ot 2.1GB/s.
the motherboard to set the appropriate AGP transter protocol based on the graphics card`s AGP
support detected during the boot up process.
Hovever, the other options are usetul it your graphics card has problems using the detected
AGP transter protocol.You can manually select a slover AGP transter protocol to solve the
problem.
Please note that manually setting the AGP Capabilities BIOS teature to 8 Mode does not
enable AGP 8X transters it your graphics card supports only AGP 4X.1he AGP bus makes use
ot the tastest AGP transter protocol supported by both motherboard and graphics card.
AGP Clock / CPU ISB Clock
1he AGP bus clock speed is reterenced trom the CPL bus clock speed. Hovever, the AGP bus
vas only designed to run at 66MHz vhile the CPL bus runs anyvhere trom 66MHz to
133MHz.1heretore, a suitable AGP bus to CPL bus clock speed ratio or divider must be select-
ed to ensure that the AGP bus does not run vay beyond 66MHz.
tor processors that use the 66MHz bus speed, like the older Intel Celeron processors.
A0P L|ock j LPu FS8 L|ock 160
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1he 1/2 divider vas introduced vith motherboards that provide 133MHz bus speed support.
Such motherboards need the 1/2 divider to make the AGP bus run at the standard 66MHz.
Without this divider, the AGP bus vould have to run at 89MHz, vhich is more than vhat most
AGP cards can vithstand.
1he 2/S divider vas introduced vith motherboards that provide 166MHz bus speed support.
Such motherboards need the 2/S divider to make the AGP bus run at the standard 66MHz.
It you are overclocking the CPL bus, you are supposed to reduce the divider to ensure that the
AGP bus speed remains vithin specitications. Hovever, most AGP cards can run vith the AGP
bus overclocked to 73MHz. Some even happily run at 83MHz' Hovever, anything above
83MHz is a little itty.
In most cases, you can stick vith the original AGP busCPL bus clock divider vhen you over-
clock the CPL. 1his means that the AGP bus is overclocked as vell. As long as the AGP card
can vork at the higher clock speed, it shouldn`t be a problem. In tact, you can expect a linear
increase in AGP bus pertormance.
Be varned, thoughoverclocking the AGP bus can potentially damage your AGP card. So, be
circumspect vhen you overclock the AGP bus. 73MHz is normally the sate limit tor most
AGP cards .
AGP Drivo Strongth
1his BIOS teature is similar to AGP Driving Control. It allovs you to set vhether to allov
the AGP controller to dynamically adjust the AGP driving strength or to allov manual contigu-
ration by the BIOS.
Due to the tighter tolerances ot the AGP 4X8X bus, the AGP controller teatures auto-
compensation circuitry that compensate tor the motherboard`s impedance on the AGP bus.
It does this by dynamically adjusting the drive strength ot the IO pads over a range ot
temperatures and voltages.
compensate tor the impedance once or at regular intervals by dynamically adjusting the AGP
auto-compensation circuitry. Normally, this is the recommenoeo setting as it allovs the AGP
controller to dynamically adjust tor motherboard impedance changes. Hovever, manual
contiguration ot the AGP Drive Strength may be necessary.
A
Some AGP 4X8X cards vere not designed according to published AGP 4X8X signal imped-
ance and routing guidelines. 1heretore, these cards may not vork reliably vith the detault drive
strengths issued by the compensation circuit.1o correct this problem, you can bypass the com-
pensation circuit and torce the AGP IO pads to use a particular drive strength. Lsually, this vill
be a higher than normal drive s trength.
boosting the signal strength. But be very, very circumspect vhen you increase the AGP Drive
Strength on an overclocked AGP bus as your AGP card may be irrevers ibly damaged in the
process'
1heretore, tor troubleshooting or overclocking purposes, you should set the AGP Drive Strength
to Manual.1his allovs you to manually set the AGP Drive Strength value through the AGP
Drive Strength P Ctrl and AGP Drive Strength N Ctrl options.
Please note that this teature is a little ditterent trom AGP Driving Control because it usually
AGP Drivo Strongth N Ctrl
1his is one ot the tunctions slaved to the AGP Drive Strength teature. It you set the AGP
Drive Strength to Auto, then the value you choose doesn`t have any ettect. lor this tunction to
have any ettect, you need to set the AGP Drive Strength to Manual.
1his tunction determines the N transistor drive strength ot the AGP bus. 1he drive strength is
represented by Hex values trom 0 to l (0 to 13 in decimal,.1he detault N transistor drive
strength ditters trom motherboard to motherboard. But the higher the drive strength, the greater
the compensation tor the motherboard`s impedance on the AGP bus.
cannot provide adequate compensation.1his is mainly seen vhen the AGP graphics card vas
not designed according to the AGP 4X8X impedance and routing guidelines. Please check
vith your graphics card manutacturer it your card requires the N transistor drive strength to be
manually set.
Due to the nature ot this BIOS tunction, it is possible to use it as an aid in overclocking the
AGP bus. 1he AGP bus is s ensitive to overclocking, especially in AGP 4X8X mode, vith side-
band and last Write support enabled. A higher N (and P, transistor drive strength may be just
vhat you need to overclock the AGP bus higher than is normally possible. By raising the drive
strength ot the AGP bus, you can improve its stability at overclocked speeds.
Please be very circumspect vhen you increase the AGP Drive Strength on an overclocked AGP
bus because your AGP card may be irreversibly damaged in the process' Also, contrary to popu-
lar opinion, increasing the AGP Drive Strength does not improve the pertormance ot the AGP
bus. It is not a pertormance-enhancing teature, so you shouldn`t increase the N transistor drive
A0P 0rvc SIrcngIh N LIr| 11
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AGP Drivo Strongth P Ctrl
1his is one ot the tunctions slaved to the AGP Drive Strength teature. It you set the AGP
Drive Strength to Auto, then the value you choose doesn`t have any ettect. lor this tunction to
have any ettect, you need to set the AGP Drive Strength to Manual.
1his tunction determines the P transistor drive strength ot the AGP bus.1he drive strength is
represented by Hex values trom 0 to l (0 to 13 in decimal,.1he detault P transistor drive
strength ditters trom motherboard to motherboard. But the higher the drive strength, the greater
the compensation tor the motherboard`s impedance on the AGP bus.
In conjunction vith AGP Drive Strength and AGP Drive Strength N Ctrl, this tunction is
cannot provide adequate compensation.1his is mainly seen vhen the AGP graphics card vas
not designed according to the AGP 4X8X impedance and routing guidelines. Please check
vith your graphics card manutacturer it your card requires the P transistor drive strength to be
manually set.
band and last Write support enabled. A higher P (and N, transistor drive strength may be just
vhat you need to overclock the AGP bus higher than is normally possible. By raising the drive
strength ot the AGP bus, you can improve its stability at overclocked speeds.
bus. It is not a pertormance-enhancing teature, so you shouldn`t increase the P transistor drive
AGP Driving Control
1his teature is similar to AGP 4 Drive Strength. It allovs you to set vhether the AGP con-
troller should dynamically adjust the AGP driving strength or allov manual contiguration by the
BIOS.
Due to the tighter tolerances ot the AGP 4X8X bus, the AGP controller teatures auto-com-
pensation circuitry that compensates tor the motherboard`s impedance on the AGP bus. It does
this by dynamically adjusting the drive strength ot the IO pads over a range ot temperatures
and voltages vhen AGP 4X8X mode is s elected.
compensate tor the impedance once or at regular intervals by dynamically adjusting the AGP
auto-compensation circuitry. Normally, this is the recommenoeo setting because it allovs the AGP
controller to dynamically adjust tor motherboard impedance changes. Hovever, manual
contiguration ot the AGP Drive Strength may be necessary.
A
Some AGP 4X8X cards vere not designed according to published AGP 4X8X signal imped-
ance and routing guidelines. 1heretore, these cards may not vork reliably vith the detault drive
strengths issued by the compensation circuit.1o correct this problem, you can bypass the com-
pensation circuit and torce the AGP IO pads to use a particular drive strength. Lsually, this is a
higher than normal drive strength.
boosting the signal strength. Hovever, be very circums pect vhen you increase the AGP Drive
Strength on an overclocked AGP bus because your AGP card may be irreversibly damaged in
the process'
1heretore, tor troubleshooting or overclocking purposes, you should set the AGP Driving
Control to Manual.1his allovs you to manually set the AGP Drive Strength value through the
AGP Driving Value tunction.
Please note that this teature is a little ditterent trom AGP 4 Drive Strength because it usual-
ly comes vith a single drive strength control.1he AGP 4 Drive Strength teature comes
vith tvo to tour drive strength controls.
AGP Driving Voluo
Connon Options: 00 to ll (Hex numbers, , 00h to llh
1his tunction is slaved to AGP Driving Control. It you set the AGP Driving Control to
Auto, then the value you set here von`t have any ettect. In order tor this tunction to have any
ettect, you need to set the AGP Driving Control to Manual.
1his tunction determines the overall drive strength ot the AGP bus. 1he drive strength is repre-
sented by Hex values trom 00 to ll (0 to 233 in decimal,.1he detault AGP Drive Strength dit-
ters trom motherboard to motherboard. But the higher the drive strength, the greater the
compensation tor the motherboard`s impedance on the AGP bus. On the reterence mother-
board, the detault drive strength vas C3 (197,.
In conjunction vith AGP Driving Control, this tunction is used to bypass AGP dynamic
compensation in cases vhere the auto-compensation circuitry cannot provide adequate com-
pensation. 1his is mainly seen vhen the AGP graphics card vas not designed according to the
AGP 4X8X impedance and routing guidelines. It you are using an AGP card built around the
NVIDIA Gelorce 2 line ot GPLs, then it is recommended that you put AGP Driving
Control into Manual mode and set the AGP Driving Value to LA (234,. lor other cards,
please check vith the manutacturer it your card requires the AGP driving strength to be set
manually.
band and last Write support enabled. A higher AGP Drive Strength may be just vhat you need
to overclock the AGP bus higher than is normally possible. By raising the drive strength ot the
AGP bus, you can improve its stability at overclocked speeds.
bus. It is not a pertormance-enhancing teature, so you shouldn`t increase the AGP Drive
Strength unless you need to.
A0P 0rvng va|uc 18
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AGP Iost Writo
1his BIOS teature controls the chipset`s AGP Fast Write capability. last Write is a teature that
accelerates memory vrite transactions trom the chipset to the AGP device.
Normally, any data meant tor the AGP device must be vritten to the main memory tor the
AGP device to read. last Write allovs the AGP device to bypass the main memory and directly
access the data.1o do so, the AGP device acts as a PCI device vhenever the chipset attempts to
vrite to it.1his allovs the data to be vritten directly to the AGP device (iike other ICI oe:ices,,
instead ot being vritten to the main memory tirst.
As you can see, bypassing the main memory saves time and improves the AGP read pertorm-
ance. Hovever, AGP vrites (to the chipset, do not benetit trom last Writes because it tollovs
normal AGP protocol and vrites to the main memory.
In addition, vhile PCI signals are used tor last Write transactions, the behavior ot those PCI
signals has been moditied, so they do not tollov PCI specitications.1heretore, this teature may
cause problems vith some PCI cards.
1heretore, it is recommended that you enable AGP last Write tor better AGP read pertorm-
ance, but disable it it any ot your PCI cards start acting tunny.
Please note that tor AGP last Write to vork, both motherboard chipset and graphics card must
support the last Write protocol, and the data transter rate must be AGP2X or taster.
AGP ISA Aliosing
1he origin ot this teature can be traced back all the vay to the original IBM PC. When the
IBM PC vas designed, it only had 10 address lines (10-bits, tor IO space allocation. 1heretore,
the IO space back in those days vas only 1KB, or 1024 bytes in size. Out ot those 1024 avail-
able addresses, the tirst 2S6 addresses vere reserved exclusively tor the motherboard`s use, leav-
ing the last 768 addresses tor use by add-in devices. 1his vould eventually become a critical
tactor.
Iater, motherboards began to utilize 1 address lines tor IO space allocation.1his vas supposed
to create a contiguous IO space ot 64KB in size. Lntortunately, many ISA devices vere only
capable ot doing 10-bit decodes.1his vas because they vere designed tor computers based on
the original IBM design, vhich only supported 10 address lines.
1o circumvent this problem, they tragmented the 64KB IO space into 1KB chunks.
Lntortunately, because the tirst 236 addresses must be reserved exclusively tor the motherboard,
this meant that only the tirst (or iouer, 236 bytes ot each 1KB chunk could be decoded in tull
16-bits. All 10-bits-decoding ISA devices are, theretore, restricted to the last (or top, 768 bytes
ot the 1KB chunk ot IO space.
As a result, such ISA devices only have 768 IO locations to use. Because there vere so many
ISA devices back then, this limitation created a lot ot compatibility problems because the
chances ot tvo ISA cards using the same IO space vere high.When that happened, one or
both ot the cards vould not vork. Although they tried to reduce the chance ot such contlicts
by standardizing the IO locations used by ditterent classes ot ISA devices, it vas still not good
enough.
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Lventually, they came up vith a vorkaround. Instead ot giving each ISA device all the IO
space it vants in the 10-bit range, they gave each ISA device a much smaller number ot IO
locations and made up tor the ditterence by borroving them trom the 16-bit IO space'
Here`s hov they did it.
1he ISA device take up a small number ot IO locations in the 10-bit range. It then extends its
IO space by using 16-bit aliases ot the tev 10-bit IO locations taken up earlier. Because
each IO location in the 10-bit decode area has sity-three 16-bit alias es, the total number ot
IO locations expands trom just 768 locations to a maximum ot 49,132 locations'
More importantly, each ISA card nov requires very tev IO locations in the 10-bit range.1his
drastically reduced the chances ot tvo ISA cards contlicting vith each other in the limited 10-
bit IO space.1his vorkaround became knovn as ISA Aliasing.
Nov, that`s all vell and good tor ISA devices. Lntortunately, the 10-bit limitation ot ISA
devices becomes a liability to devices that require 16-bit addressing, AGP and PCI devices come
to mind.As noted earlier, only the tirst 236 addresses ot the 1KB chunks support 16-bit address-
ing. What that really means is all 16-bit addressing devices are limited to only 236 bytes ot
contiuous IO space.
When a 16-bit addressing device requires a larger contiguous IO space, it has to encroach on
the 10-bit ISA IO space. lor example, it an AGP card requires 8KB ot contiguous IO space, it
takes up eiht ot the 1KB IO chunks (uhich comprise of eiht 1|it areas ano eiht 10|it areas:,.
Because ISA devices are using ISA Aliasing to extend their IO space, there is a high chance ot
IO space contlicts betveen ISA devices and the AGP card.When that happens, the attected
cards generally tail to vork.
1here are tvo vays out ot this mess. Obviously, you can limit the AGP card to a maximum ot
236 bytes ot contiguous IO space. Ot course, this is not an acceptable solution.
1he second, and the preterred method, is to throv avay the restriction and provide the AGP
card vith all the contiguous IO space it vants.
Here`s vhere the AGP ISA Aliasing BIOS teature comes in.1he detault setting ot Lnabled
torces the system controller to alias ISA addresses using address bits [13:10|the last 6-bits.
Only the tirst 10-bits (address bits 0 to 9, are used tor decoding. 1his restricts all 16-bit address-
ing devices to a maximum contiguous IO space ot 236 bytes.
tull 64KB IO space.
It is recommended that you disable AGP ISA Aliasing tor optimal AGP (and PCI, pertorm-
ance. It also prevents your AGP or PCI cards trom contlicting vith your ISA cards. Lnable it
only it you have ISA devices that are contlicting vith each other.
AGP Mostor 1WS Rood
In most motherboards, the AGP bus-mastering device has to vait tor at least tvo vait states
(AGP clock cycles, betore it can initiate a read command.1his BIOS teature allovs you to
reduce that delay to only one vait state.1his speeds up all reads that the AGP bus-master makes
trom the system memory.
A0P MasIcr 1WS cad 16
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anomalies like viretrame ettects and pixel artitacts, or it your system depends on running sott-
vare that makes use ot AGP texturing.
Curiously, some motherboards come vith a detault AGP master read latency ot 0' Lnabling the
AGP Master 1WS Pead in such cases actually increases the latency by one vait state and reduces
AGP read pertormance.Although it`s quite unlikely that the detault AGP master read latency
vould be zero, that`s vhat their manuals say.
So, check your motherboard manual to see it your motherboard`s manutacturer implemented
the tirst (and more common, interpretation ot the AGP Master 1WS Pead teature or the sec-
ond one. Lither vay, the lover the AGP master read latency, the higher the read pertormance ot
the AGP bus.
AGP Mostor 1WS Writo
In most motherboards, the AGP bus-mastering device has to vait tor at least tvo vait states
(AGP clock cycles, betore it can initiate a vrite command. 1his BIOS teature allovs you to
reduce that delay to only one vait state.1his speeds up all vrites that the AGP bus-master
makes to the system memory.
So, tor better AGP vrite pertormance, enable this teature. Disable it only it you notice visual
anomalies like viretrame ettects and pixel artitacts, or it your system depends on running sott-
vare that makes use ot AGP texturing.
Curiously, some motherboards come vith a detault AGP master vrite latency ot 0' Lnabling
the AGP Master 1WS Write in such cases actually increases the latency by one vait state and
reduces AGP vrite pertormance. Although it`s quite unlikely that the detault AGP master vrite
latency vould be zero, that`s vhat their manuals say.
So, check your motherboard manual to see it your motherboard`s manutacturer implemented
the tirst (and more common, interpretation ot the AGP Master 1WS Write teature or the sec-
ond one. Lither vay, the lover the AGP master vrite latency, the higher the vrite pertormance
ot the AGP bus.
AGP ProIotch
1his teature controls the system controller`s AGP pretetch capability.When enabled, the system
controller pretetches data vhenever the AGP device reads trom the system memory. Here`s hov
it vorks.
Whenever the system controller reads AGP-requested data trom the system memory, it also reads
the subsequent chunk ot data. 1his is done on the assumption that the AGP device requests the
subsequent chunk ot data.When the AGP device actually initiates a read command tor that
chunk ot data, the system controller can immediately send it to the AGP device.
1his speeds up AGP reads because the AGP device doesn`t need to vait tor the system con-
troller to read trom the system memory. As such,AGP Pretetch allovs contiguous memory reads
by the AGP device to proceed vith minimal delay.
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Option (He) Actual Latency
00h 0
20h 32
40h 64
60h 96
80h 128
C0h 192
llh 233
Please note that AGP vrites to the system memory do not benetit trom this teature.
AGP Socondory Lot linor
Connon Options: 00h, 20h, 40h, 60h, 80h, C0h, llh
A bridge is a device that connects a primary bus (vhich connects to the host, vith one or
more logical secondary buses.1he AGP bus is theretore a secondary bus connected to the PCI
bus through a PCI-to-PCI bridge.
1his BIOS teature is similar to the PCI Latency 1iner BIOS teature. 1he only ditterence is
this latency timer only applies to the AGP bus, vhich is a secondary bus connected to the PCI
bus through a PCI-to-PCI bridge.
Hovever, it is unknovn vhy they named this BIOS teature AGP Secondary Lat 1iner
instead ot the more appropriate AGP Iatency 1imer, or even PCI Secondary Iatency 1imer.
1he name is both misleading and inaccurate because the AGP bus does not have a secondary
latency timer.
1his BIOS teature controls hov long the AGP bus can hold the PCI bus (through the PCI-to-
PCI bridge, betore another PCI device takes over.1he longer the latency, the longer the AGP
bus can retain control ot the PCI bus betore handing it over to another PCI device.
Because a bridge device introduces an additional delay to every transaction, a short latency tur-
ther reduces the amount ot time the AGP bus has access to the PCI bus. A longer latency allovs
the AGP bus more time to transact on the PCI bus.1his speeds up AGP-to-PCI transactions.
1he available options range is usually stated in terms ot hexadecimal numbers. Here is a transla-
tion ot those numbers into actual latencies:
A0P Sccondary LaI Jmcr 17
A
Normally, the AGP Secondary Iatency 1imer is set to 20h (32 clock cycles,. 1his means the
AGP bus PCI-to-PCI bridge has to complete its transactions vithin 32 clock cycles or hand it
over to the next PCI device.
lor better AGP pertormance, a longer latency should be used.1ry increasing it to 40h (64
cycles, or even 80h (128 cycles,. 1he optimal value tor every s ystem is ditterent.You should
benchmark your AGP card`s pertormance atter each change to determine the optimal latency
tor your system.
Please note that a longer latency isn`t necessarily better.A long latency can reduce pertormance
because the other PCI devices queuing up may be stalled tor too long.1his is especially true
vith systems vith many PCI devices or PCI devices that continuously vrite short bursts ot data
to the PCI bus. Such systems vork better vith shorter latencies because they allov quicker
access to the PCI bus.
1heretore, it you s et the AGP Secondary Iatency 1imer to a very large value like 80h (128
cycles, or C0h (192 cycles,, it is recommended that you set the PCI Latency 1ine to 32
cycles.1his provides better access tor your PCI devices that might be unnecessarily stalled it
both the AGP and PCI buses have very long latencies.
In addition, some time-critical PCI devices may not agree vith a long AGP latency. Such
devices require priority access to the PCI bus, vhich may not be possible it the PCI bus is held
up by the AGP bus tor a long period. In such cases, it is recommended that you keep to the
detault latency ot 20h (32 clock cycles,.
AGP Sprood Spoctrun
When the motherboard`s clock generator pulses, the extreme values (spikes, ot these signals gen-
erated create LMI (Llectronagnetic Interference,.1his LMI interteres vith other electronics
in the area.1here are also claims that it may allov electronic eavesdropping ot the data that is
being transmitted.
1his BIOS teature allovs you to reduce the LMI ot the AGP bus by modulating the signals it
generates, so the spikes are reduced to tlatter curves. It achieves this by varying the trequency
siihti, so the signal does not use any particular trequency tor more than a moment.1his
reduces the amount ot LMI generated by the motherboard.
1he BIOS usually otters tvo levels ot modulation: 0.2S or 0.S.1hey denote the amount ot
modulation or jitter trom the baseline signal. 1he greater the modulation, the greater the reduc-
tion ot LMI. 1heretore, it you need to signiticantly reduce the AGP bus LMI, a modulation ot
0.S is recommended.
Hovever, system stability may be compromised it you are overclocking the AGP bus. Ot course,
this depends on the amount ot modulation, the extent ot overclocking, and other tactors like
temperature, and so torth. As such, the problem may not manitest itselt immediately.
1heretore, it is recommended that you disable this teature it you are overclocking the AGP bus.
tion is important to you, enable this teature by all means. But you should reduce the clock
speed a little to provide a margin ot satety.
It you are not overclocking, the decision to enable or disable this teature is really up to you. But
unless you have LMI problems or sensitive data that must be sateguarded trom electronic eaves-
dropping, it is best to disable this teature to remove the possibility ot instability.
A
AGP to DRAM ProIotch
1his teature controls the system controller`s AGP pretetch capability.When enabled, the system
controller pretetches data vhenever the AGP device reads trom the system memory. Here`s hov
it vorks.
When the system controller reads AGP-requested data trom the s ystem memory, it also reads the
subsequent chunk ot data.1his is done on the ass umption that the AGP device vill request the
subsequent chunk ot data.When the AGP device actually initiates a read command tor that
chunk ot data, the system controller can immediately send it to the AGP device.
1his speeds up AGP reads because the AGP device doesn`t need to vait tor the system con-
troller to read trom the system memory. As such,AGP to DPAM Pretetch allovs contiguous
memory reads by the AGP device to proceed vith minimal delay.
Please note that AGP vrites to the system memory do not benetit trom this teature.
AGPCLR / CPUCLR
1he AGP bus clock speed is reterenced trom the CPL bus clock speed. Hovever, the AGP bus
vas only designed to run at 66MHz vhile the CPL bus runs anyvhere trom 66MHz to
133MHz.1heretore, a suitable AGP bus to CPL bus clock speed ratio or divider must be select-
ed to ensure that the AGP bus doesn`t run vay beyond 66MHz.
tor processors that use the 66MHz bus speed, like the older Intel Celeron processors.
1he 1/2 divider vas introduced vith motherboards that provide 133MHz bus speed support.
Such motherboards need the 1/2 divider to make the AGP bus run at the standard 66MHz.
1he 2/S divider vas introduced vith motherboards that provide 166MHz bus speed support.
Such motherboards need the 2/S divider to make the AGP bus run at the standard 66MHz.
It you are overclocking the CPL bus, you are supposed to reduce the divider to ensure that the
AGP bus speed remains vithin specitications. Hovever, most AGP cards can run vith the AGP
bus overclocked to 73MHz. Some even happily run at 83MHz' Hovever, anything above
83MHz is a little itty.
A0PLLk j LPuLLk 10
A
In most cases, you can still stick vith the original AGP busCPL bus clock divider vhen you
overclock the CPL. 1his means that the AGP bus is overclocked as vell. Hovever, as long as the
AGP card can vork at the higher clock speed, it shouldn`t be a problem. In tact, you can expect
a linear increase in AGP bus pertormance.
Be varned, thoughoverclocking the AGP bus potentially can damage your AGP card. So, be
circumspect vhen you overclock the AGP bus. 73MHz is normally the s ate limit tor most
AGP cards .
Anti-Virus Protoction
Connon Options: Lnabled, Disabled, ChipAvay
1he Anti-Virus Protection teature is actually an enhanced version ot the Virus Warning tea-
ture. Besides the standard boot sector or partition table protection, this BIOS teature also otters
more comprehensive anti-virus protection through built-in, rule-based, anti-virus code such as
ChipAvay.
When you enable this teature, the BIOS halts the system and tlashes a varning message vhen-
ever there`s an attempt to vrite to the boot sector or the partition table. Note that this only
protects the boot sector and the partition table, not the entire hard disk.
1his teature can cause problems vith sottvare that needs to access the boot sector. One good
onvard. When enabled, this teature causes the installation routine to tail.Also, many disk diag-
nostic utilities that access the boot sector can also trigger the system halt and error message as
vell.1heretore, you should disable this teature betore running such sottvare.
Alternatively, you can select the internal rule-based, anti-virus code. 1he sottvare used in the
reterence motherboard is called ChipAvay. Lnabling ChipAvay provides better anti-virus
protection by scanning tor and detecting boot viruses betore they have a chance to intect the
boot sector ot any hard disk.
Note that this teature is useless tor hard disks that run on external controllers vith their ovn
BIOS. Boot sector viruses bypass the system BIOS vith its anti-virus protection teatures and
vrite directly to the hard disks. Such controllers include additional IDL or SCSI controllers that
are either built into the motherboard or available through add-on cards.
APIC Iunction
1he APIC Function BIOS teature is used to enable or disable the motherboard`s APIC
(Advanced Progrannable Interrupt Controller,. 1he APIC is a nev distributed set ot
devices that make up an interrupt controller. In current implementations, it consis ts ot three
parts: a local APIC, an IO APIC, and an APIC bus.
1he local APIC delivers interrupts to a specitic processor, so each processor in a system has to
have its ovn local APIC.1heretore, a dual processor system must have tvo local APICs. Because
a local APIC has been integrated into every proces sor since the debut ot the original Intel
Pentium P34C processor, there`s no need to vorry about the number ot local APICs.
A
1he IO APIC is the replacement tor the old chained 82S9 PIC (Progrannable Interrupt
Controller, still in use in many motherboards. It collects interrupt signals trom IO devices and
sends messages to the local APICs through the APIC bus, vhich connects it to the local APICs.
1here can be up to eight IO APICs in a system, each supporting anyvhere trom 24 (usually,
to 64 interrupt lines. As you can see, this allovs a lot more IPQs than is currently possible vith
the 8239 PIC. Note that vithout at least one IO APIC, the local APIC is useless and the sys-
tem tunctions as it it`s based on the 8239 PIC.
1o sum it up,APIC provides multiprocessor support, more IPQs, and taster interrupt handling,
vhich is not possible vith the old 8239 PIC. Although they can be used in single-processor
boards, you are more likely to tind them in multi-processor motherboards.1his is because APIC
is only supported in Windovs N1, 2000, and XP. It is not supported in operating systems that
are required to support MS-DOS device drivers, tor example Windovs 9398. Hovever, as
users transition to Windovs XP, you can expect more manutacturers to ship single-processor
boards vith IO APICs.
It your single-processor motherboard supports APIC and you are using a Win32 operating sys-
tem (Windovs N1, 2000, and XP,, it`s recommended that you enable this teature to allov
taster and better IPQ handling. It you are using a multiprocessor motherboard, you must
enable this teature because it`s required tor IPQ handling in multiprocessor systems.
Hovever, it you are running Windovs 9398 or a DOS-based operating system on a single-
processor motherboard, you must disable this teature. 1his is because MS-DOS drivers assume
they can vrite directly to the 8239 PIC (APIC did not exist yet in those days, and its associated
ID1 entries. Disabling this teature torces the APIC to revert to the legacy 8239 PIC mode.
Assign IRQ Ior USB
1his BIOS teature is somevhat similar to Onboard USB Controller. It enables or disables the
motherboard`s onboard LSB controller by determining vhether it should be assigned an IPQ.
Lnable this teature it you vant to attach your LSB devices to the onboard LSB controller.
It you disable this teature, the LSB controller is not assigned an IPQ. 1his disables the con-
troller and you aren`t able to connect any LSB devices to it. Hovever, it you don`t use any LSB
devices, this trees up an IPQ tor other devices to use. 1his is particularly usetul vhen you have
many devices that can`t share IPQs.
Disabling this teature may not be necessary vith APIC-capable motherboards because they
come vith more IPQs.
Assign IRQ Ior VGA
Many graphics cards require an IPQ to tunction properly. Disabling an IPQ assignment tor
such cards causes improper operation and poor pertormance.1heretore, it is recommended that
you enable this teature. Doing so allovs the BIOS to assign an IPQ to the graphics card.
Some graphics cards may not need an IPQ to vork. 1hese cards are usually the lov-end cards
that provide basic video tunctions. Check your graphics card`s documentation to contirm
vhether it requires an IPQ to vork.
Assgn I0 For v0A 171
A
Setting Clock Speed Bandvidth
CIK2 16.67 MHz 16.67 MBs
CIK3 11.11 MHz 11.11 MBs
CIK4 8.33 MHz 8.33 MBs
It your graphics card doesn`t require an IPQ, then you can disable this teature to release an
IPQ tor other devices to use.1his is particularly usetul vhen you have many devices that can`t
share IPQs. Disabling this teature may not be necessary vith APIC-capable motherboards
because they come vith more IPQs.
When in doubt, it`s otten best to leave it enabled as graphics cards generally tunction better
vith an IPQ. 1his is true even tor cards that oon`t require IPQs.
Al Bus Clock
Connon Options: 7.16MHz, CIK2, CIK3, CIK4, CIK3, CIK6
1he A1 bus is nothing more than another name tor the ISA bus.1he ISA bus vas originally an
8-bit bus running at just 4.77MHz. It vas then expanded to include a 16-bit bus running ini-
tially at 6MHz and later at 8MHz. Lventually, the ISA bus vas standardized to run at a maxi-
mum speed ot 8.33MHz.
Because each ISA data transter takes anyvhere trom tvo to eight clock cycles to complete, this
yields a maximum bandvidth ot only 4.77MB/s tor 8-bit cards and 8.33MB/s tor 16-bit
cards.
Maximum bandvidth tor the 8-bit ISA bus = 8.33MHz 1 byte (8-bits, 2 clock cycles per
transter = 4.77MBs
Maximum bandvidth tor the 16-bit ISA bus = 8.33MHz 2 bytes (16-bits, 2 clock cycles
per transter = 8.33MBs
1his BIOS teature allovs you to select the ISA bus clock speed. 1he chipset actually generates
the ISA bus clock by dividing the PCI clock. Hence, the available settings ot CLK/2, CLK/3,
CLK/4, CLK/S, and CLK/6. Assuming that the PCI clock is set to 33MHz, these settings
yield the tolloving clock speeds and bandvidth vith a 16-bit ISA bus:
A
1here is also the tixed speed ot 7.16MHz, vhich is derived by dividing the reterence clock
generator speed ot 14.318MHz by a tactor ot tvo.
As you can see, the setting ot CLK/4 yields an ISA bus speed ot 8.33MHz, vhich is the maxi-
mum speed alloved by the otticial ISA specitications. Hovever, you can choose to overclock the
ISA by selecting the settings CLK/3 or CLK/2, vhich yield clock speeds ot 11.11MHz and
16.67MHz, respectively.
Overclocking the ISA bus greatly improves its pertormance. 1heretore, it is recommended that
you try to use the taster settings it possible. Hovever, vhile never ISA cards are capable ot run-
ning at this out-ot-spec speed, older ones may not vork properly at this speed.
Setting Clock Speed Bandvidth
CIK2 18.73 MHz 18.73 MBs
CIK3 12.30 MHz 12.30 MBs
It your ISA cards tail to vork properly, then you should select the setting ot CLK/4 or
7.16MHz.1his keeps the ISA bus vithin specitications.
Please note that the previous calculations and recommendations vere based on a 33MHz PCI
bus clock. It you are overclocking your PCI bus, please take the increased PCI clock speed into
account'
lor example, vith an overclocked PCI bus speed ot 37.3MHz, the available settings ot
CLK/2, CLK/3, CLK/4, CLK/S, and CLK/6 yields the tolloving clock speeds and band-
vidth vith a 16-bit ISA bus:
AJA100AI0 I0L LonIro||cr 178
A
With a 37.3MHz PCI bus, all ISA bus speed dividers yield increased clock speeds. Only the set-
tings ot CLK/S, CLK/6, and 7.16MHz remain vithin ISA specitications. So, it you overclock
your PCI bus, keep that in mind vhen you select the ISA bus speed divider.
It all this is contusing and you vant to play s ate, select the setting ot 7.16MHz. 1hat is the tail-
sate setting because it vill set the ISA bus to run at a tixed speed ot 7.16MHz, irrespective ot
the PCI bus speed.
AlA100RAID IDL Controllor
1his teature is only tound on certain motherboards that come vith an extra LltraDMA100
IDL controller vith PAID support. It allovs you to enable or disable the tunction ot that con-
troller.
Please note that the IDL controller covered by this BIOS teature is ditterent trom the chipset`s
built-in IDL controller. 1his extra LltraDMA100 IDL controller is otten added to provide
LltraDMA100 and PAID support in motherboards vhose chipset does not otter
LltraDMA100 or PAID support. Lven it the chipset`s built-in IDL controller supports
LltraDMA100 as vell as PAID, it is not controlled by this BIOS teature.1his teature is only
used tor the extra IDL controller.
lor the purpose ot avoiding contus ion, I shall hence reter to the built-in IDL controller as an
internal IDL controller vhile the add-on IDL controller vill be knovn as an eternal IDL
controller.
It you vant to attach one or more IDL devices to the external LltraDMA100 PAID con-
troller, you should enable this teature.You should only disable it tor the tolloving reasons :
It you don`t have any IDL device attached to the external LltraDMA100 PAID
controller
Disabling the external IDL controller trees up tvo IPQs and speeds up system booting. 1his is
because the IDL controller`s BIOS doesn`t have to be loaded and the external controller`s otten
long boot-up check and initialization sequence is skipped. So, it you don`t use the external IDL
controller, it is recommended that you disable it.
Athlon 4 SSLD Instruction
1he AMD Athlon originally came vith AMD`s Lnhanced 3DNov! 1echnology, vhich vas a
collection ot 19 nev SIMD instructions. 1hese instructions vere similar to Intel`s SSL
(Streaning SIMD Ltensions) instruction set, vhich debuted in the Intel Pentium III
processor. Intel`s SSL vas, hovever, more complete in the sense that it consisted ot 70 SIMD
instructions.
Lventually, AMD vas torced to concede that the Intel SSL vas tar more popular vith sottvare
developers. So, beginning vith the Palomino core ot the Athlon XP (and MP, tamily ot proces-
sors, AMD started implementing Intel`s SSL instruction set.
Since 18 ot the original Lnhanced 3DNov' instruction sets vere identical to those in Intel`s
SSL, all AMD needed to do vas add another 32 instructions to make a complete implementa-
tion ot Intel`s SSL instruction set. Ot course, that didn`t stop AMD trom calling it the 3DNov!
Professional, even though it vas really just Intel`s SSL instruction set'
AMD also added a status bit that tells any querying sottvare that the Athlon XPMP supports
the tull SSL instruction set.1his vas meant to allov the Athlon XPMP to immediately take
advantage ot SSL-optimized sottvare. Hovever, this status bit ends up causing some compatibil-
ity issues.
1he BeOS operating system vas probably the biggest victim.1he SSL status bit actually fooieo
BeOS` kernel into thinking that the Athlon XPMP processor vas an Intel processor.1his
caused the kernel to send the vrong instructions to the Athlon XPMP processor, causing it to
crash and reboot.
1here vere also compatibility issues vith other sottvare, all due to the SSL status bit. lor
example, some graphics cards ( tor example, Matrox G430, cannot run Quake III under
Windovs N1 4.0 vith the SSL status bit enabled.
1his is vhere the Athlon 4 SSLD Instruction BIOS teature comes in. 1his BIOS teature is a
simple toggle tor the AMD Athlon XPMP`s SSL status bit.
When enabled, the BIOS enables the SSL status bit. Querying sottvare vill recognize the
processor as an SSL-compatible processor.1his allovs the processor to take advantage ot SSL-
optimized sottvare.
When disabled, the BIOS disables the SSL status bit. Querying sottvare vill not recognize the
processor as an SSL-compatible processor.1he processor can only take advantage ot Lnhanced
3DNov'-optimized sottvare.
By detault, this BIOS teature is set to Lnabled, vhich allovs tor optimal pertormance vith
SSL-optimized sottvare. It is highly recommended that you leave it at the detault setting ot
Lnabled.
You should disable this BIOS teature only it you are tacing compatibility issues vith the SSL
status bit.
A
Auto Dotoct DIMM/PCI Clk
When the motherboard`s clock generator pulses, the extreme values (spikes, ot the puls es creates
LMI (Llectronagnetic Interference,. 1his causes interterence vith other electronics in the
area. 1o reduce this problem, the BIOS can either modulate the pulses (to make them tlatter, or
turn ott unused AGP, PCI, or memory clock signals.
1his teature is similar to the Snart Clock option ot the Spread Spectrun teature, vhich
acts by the second method. It you enable it, the BIOS monitors the AGP, PCI, and memory
slots. 1he clock signals ot unoccupied slots are automatically turned ott.1he clock signals to
occupieo AGP, PCI, or memory slots are also turned ott vhenever there`s no activity.
1heoretically, LMI can be reduced this vay vithout compromising system stability.1his also
allovs the computer to reduce pover consumption because only components that are running
use pover, and then only vhen they are actually doing vork.
1he choice ot vhether to enable or disable this teature is really up to your personal preterence.
Hovever, because this teature reduces LMI and pover consumption vithout compromising sys-
tem stability, it is recommended that you enable it.
Auto lurn OII PCI Clock Pin
turn ott the unused clock signals.
1his teature is a subset ot the Auto Detect DIMM/PCI Clk teature. It you enable it, the
BIOS monitors the PCI slots tor activity. 1he clock signals ot unoccupied slots are automatically
turned ott.1he clock signals to occupieo PCI slots are also turned ott vhenever there`s no activity.
use pover, and then only vhen they are actually doing vork.
Hovever, because this teature reduces LMI and pover consumption vithout compromising
system stability, it is recommended that you enable it.
AuIo Jurn 0ff PLI L|ock Pn 176
A
B
Boot Othor Dovico
1his teature determines vhether the BIOS attempts to load an operating system trom the
Second Boot Device or 1hird Boot Device it it tails to load one trom the First Boot
Device. 1his teature is enabled by detault, and it is recommended that you leave it as such.
1his allovs the BIOS to check the second and third boot devices tor operating systems atter
tailing to tind one on the tirst boot device. Othervise, the BIOS simply halts the booting
process vith the error mess age: No Operating Systen Found, even it there is an operating
system on the second or third boot device.
Boot Soquonco
Connon Options: A, C, SCSI
C,A, SCSI
C, CD-POM,A
CD-POM, C,A
D, A, SCSI (only vhen you have at least 2 IDL hard disks,
L, A, SCSI (only vhen you have at least 3 IDL hard disks,
l, A, SCSI (only vhen you have 4 IDL hard disks,
SCSI, A, C
SCSI, C, A
A, SCSI, C
ISZIP, C
1his teature enables you to set the sequence by vhich the BIOS searches tor an operating sys-
tem during the boot-up process.
1o ensure the shortest booting time possible, set the hard disk that contains your operating sys-
tem as the tirst choice. Normally, this vould be drive C tor IDL drives but it you are using a
SCSI hard disk, then select SCSI.
Some motherboards have an external (not part ot the chipset, IDL controller. In such mother-
boards, the SCSI option is replaced vith an L1 option. 1his allovs the computer to either
boot trom an IDL hard disk connected to the external IDL controller or an SCSI hard disk.
It you vant to boot trom an IDL hard disk running ott the internal IDL controller, do not set
the Boot Sequence to start vith L1. Please note that this teature vorks in conjunction
vith the Boot Sequence L1 Means teature.
B
Boot Soquonco Ll Moons
Connon Options: IDL, SCSI
1his BIOS teature determines vhether the system boots trom an IDL hard dis k connected to
the externai IDL controller or an SCSI hard disk. Hovever, it only has an ettect it the L1
option has been selected in the Boot Sequence teature.
1o boot trom an IDL hard disk that`s connected to the externai IDL controller, you must tirst set
the Boot Sequence teature to start vith the L1 option. lor example, the L1, C, A set-
ting. 1hen, you have to set the Boot Sequence L1 Means teature to IDL.
1o boot trom an SCSI hard disk, set the Boot Sequence teature to start vith the L1 option.
lor example, the L1, C, A setting.1hen, you have to set the Boot Sequence L1 Means
teature to SCSI.
Boot lo OS/2
When there is more than 64MB ot memory in a computer, older versions ot IBM`s OS2 oper-
ating system ditter trom other operating systems in the vay it manages memory. It is ditterent
trom the conventional vay ot memory management.1heretore, a BIOS option vas created to
provide compatibility tor such OS2 systems.
It you are running an old, unpatched version ot OS2, you must select the Yes option. Hovever,
please note that this is only true tor older versions ot OS2 that haven`t been upgraded using
IBM`s lixPaks.
Starting vith the OS2 Warp v3.0, IBM changed the memory management system to the more
conventional method. IBM also issued lixPaks to address this issue vith older versions ot OS2.
1heretore, it you are using OS2 Warp v3.0 or higher, you should select No.You should also
select No it you have upgraded an older version ot OS2 vith the lixPaks that IBM has been
releasing over the years.
It you select the Yes option vith a never or updated version (v3.0 or higher, ot OS2, it
causes erroneous memory detection. lor example, it you have 64MB ot memory, it may only
register as 16MB. Or, it you have more than 64MB ot memory, it may register as only 64MB
ot memory.
Lsers ot non-OS2 operating systems (such as Microsott Windovs XP, should select the No
option. Doing othervise causes memory errors it you have more than 64MB ot memory in
your system.
In conclusion:
It you are using an older version ot the IBM OS2 operating system, you should select
Yes.
No.
8ooI Jo 0Sj2 177
B
It you are using an older version ot the IBM OS2 operating system but have already
installed all the relevant IBM lixPaks, you should select No.
Lsers ot non-OS2 operating systems (such as Microsott Windovs XP, should select the
No option.
Boot Up Iloppy Sook
1his BIOS teature determines it the BIOS checks tor a tloppy drive during boot-up.
It enabled, the BIOS attempts to detect and initialize the tloppy drive. It it cannot detect one
(due to improper contiguration or physical unavailability,, it tlashes an error message. Hovever,
the system still is alloved to continue the boot process.
It the tloppy drive is present, the BIOS queries the drive to tind out it it supports 40 tracks or
80 tracks operation. Because all tloppy drives in use today only support 80 tracks operation, this
check is, trankly, redundant.
It this teature is disabled, the BIOS skips the tloppy drive check. 1his speeds up the booting
process by several seconds.
Because a tloppy drive check is really pointless, it is recommended that you disable this teature
tor a taster booting process .
Boot Up NunLock Stotus
1his BIOS teature sets the input mode ot the numeric keypad at boot up.
It you turn this teature on, the BIOS sets the numeric keypad to tunction in the nuneric
node (tor typing out numbers,.
It you set it to Off, the numeric keypad tunctions in the cursor control node (tor control-
ling the cursor, instead.
1he numeric keypad`s input mode can be svitched to either numeric or cursor control mode
and back again at any time atter boot up.1his teature merely sets the initial input mode ot the
keypad at boot up.
1he choice ot initial keypad input mode is entirely up to your preterence.
Byto Morgo
1his BIOS teature is similar to the PCI Dynanic Bursting teature.
It you have already read about the CPU to PCI Write Buffer teature, you should knov that
the chipset has an integrated PCI vrite butter that allovs the CPL to immediately vrite up to
four vords (or 64-bits, ot PCI vrites to it.1his trees up the CPL to vork on other tasks
vhile the PCI vrite butter vrites them to the PCI bus.
B
Nov, the CPL doesn`t alvays vrite 32-bit data to the PCI bus. 8-bit and 16-bit vrites can also
take place. Hovever, vhile the CPL may only vrite 8-bits ot data to the PCI bus, it is still con-
sidered a single PCI transaction.1his makes it equivalent to a 16-bit or 32-bit vrite in terms ot
PCI bandvidth. 1his reduces the ettective PCI bandvidth, especially it there are many 8-bit or
16-bit CPL-to-PCI vrites.
1o solve this problem, the vrite butter can be programmed to accumulate and merge 8-bit and
16-bit vrites into 32-bit vrites.1he butter then vrites the merged data to the PCI bus. As you
can see, merging the smaller 8-bit or 16-bit vrites into a tev large 32-bit vrites reduces the
number ot PCI transactions required. 1his increases the etticiency ot the PCI bus and improves
its bandvidth.
1his is vhere the Byte Merge BIOS teature comes in. It controls the byte merging capability
ot the PCI vrite butter.
It it is enabled, every vrite transaction goes straight to the vrite butter.1hey are accumulated
until there is enough to be vritten to the PCI bus in a single burst.1his improves the PCI bus
pertormance.
It you disable byte merging, all vrites s till go to the PCI vrite butter (it the CPU to PCI
Write Buffer teature has been enabled,. Hovever, the butter does not accumulate and merge
the data. 1he data is vritten to the PCI bus as soon as the bus becomes tree.1his reduces PCI
bus etticiency, particularly vhen 8-bit or 16-bit data is vritten to the PCI bus.
1heretore, it is recommended that you enable Byte Merge tor better pertormance.
Hovever, please note that Byte Merge may be incompatible vith certain PCI netvork intertace
cards (also knovn as NICs,. lor example, 3Com`s 3C903-series ot NICs von`t vork properly
vith Byte Merge enabled.
So, it your NIC (Netvork Intertace Card, von`t vork properly, try disabling Byte Merge.
Othervise, you should enable Byte Merge tor better pertormance.
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Clock lhrottlo
Connon Options: 12.3, 23.0, 37.3, 30.0, 62.3, 73.0, 87.3
sors vith 312KB I2 cache.1hese processors come vith a 1hernal Monitor that actually con-
sists ot an on-die thermal sensor and a 1hernal Control Circuit (1CC,. Because the thermal
sensor is on-die and placed at the hottest part ot the dienear the integer AIL unitsit is able
to closely monitor the processor's die temperature.
processor has reached its maximum sate operating temperature, it vill send a PPOCHO14
(Processor Hot, signal, vhich activates the 1CC.1he 1CC vill then modulate the clock cycles
by inserting null cycles, typically at a rate ot S0-70 ot the total number ot clock cycles. Note
that the operating trequency ot the processor remains unchanged. 1he 1CC only inserts null
cycles that result in the processor resting30-70 ot the time.
As the die temperature drops, the 1CC vill gradually reduce the number ot null cycles until no
stops sending the PPOCHO14 signal, thereby turning ott the 1CC.1his mechanism allovs the
processor to dynamically adjust its duty cycles to ensure its die temperature remains vithin sate
limits.
duty cycle.
Available options tor this BIOS teature are set values ot the processo`s duty cycle vhen the
turn ott the 1CC.
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Conpotiblo IPU OPCODL
In Intel IA-32 (P6 tamily, Pentium 4, and so torth, processors, the x87 lPL stores the opcode
ot the last executed non-control instruction (also knovn as the fopcode or FOP code, in an
11-bit register. 1his is to provide state intormation tor exception handlers .
Because the tirst
3 bits ot the tirst
opcode byte are the
same tor all lPL
opcodes, only the
last 3 bits ot the
tirst opcode byte
are stored in the
register. 1he second
opcode byte pro-
vides the remaining
8-bits ot data.
In previous imple-
mentations, the tinal
opcode (or lOP, stored in the lOP register vas alvays the lOP ot the last non-transparent
tloating point instruction executed betore an lSAVL, lS1LNV, or lXSAVL instruction.
Hovever, to improve lPL pertormance, the Pentium 4 and Xeon processors only store the
lOP ot the last non-transparent tloating point instruction that have an unmasked exception. lor
backvard compatibility, the Pentium 4 and Xeon processors allov programmable control ot the
lOP register. 1his is vhere the Conpatible FPU OPCODL BIOS teature comes in.
When enabled, the processor reverts to the lOP code compatibility mode and stores the last
non-transparent tloating point instruction in the 11-bit lOP register. Intel recommends that this
teature should only be enabled it the sottvare vas designed to use the topcode to analyze pro-
gram pertormance or to res tart the program atter an exception has been handled.
When disabled, the processor turns ott the lOP code compatibility mode and only stores the
lOP ot the last non-transparent tloating point instruction that had an unmasked exception.1his
allovs tor better lPL pertormance.
1heretore, it is recommended that you disable this teature.1his allovs tor better lPL pertorm-
ance, although some older programs may require you to enable this teature to allov recovery
trom lPL exceptions.
CPU Drivo Strongth
1he system controller has auto-compensation circuitry that automatically compensates tor
impedance variations in motherboard designs. Hovever, because the motherboard impedance is
more or less tixed tor each motherboard design, some manutacturers may choose to pre-
calculate the optimal drive strength tor a particular design and use it instead. Lither vay, the
motherboard`s impedance on the processor bus is compensated tor.
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7 2 0 7 0
10 8 7 0
1st nst ruct ion Byte 2nd nstruction Byte
x87 FPU Opcode Register
(Courtes of Intei Corporation)
Hovever, vhen the auto-compensation logic is bypassed and a tixed drive strength is used, the
amount ot impedance compensation may not be sutticient sometimes. Hence the need tor this
BIOS teature.1his BIOS teature allovs you to manually set the processor bus drive strength.
1he higher the value, the stronger the drive strength.
So, it you are tacing stability problems vith your processor, you might vant to try boosting the
CPL drive strength to a higher value. It vill help to correct any possible increase in impedance
trom the motherboard.
Due to the nature ot this BIOS teature, it is also possible to use it as an aid in overclocking the
CPL. By raising the CPU Drive Strength, it is possible to improve its stability at overclocked
speeds . So, try the higher values ot 2 or 3 it your CPL just von`t go the extra mile.
Hovever, this is not a suretire vay ot overclocking the CPL. Increasing it to the highest value
does not necessarily mean that you can overclock the CPL more than you already can. In addi-
tion, it is important to note that increas ing the CPL drive strength does not improve its per-
tormance. Contrary to popular opinion, it is not a pertormance-enhancing teature.
Although little else is knovn about this teature, the dovnside to a high CPL drive strength is
increased LMI (Llectronagnetic Interference,, pover consumption, and thermal output.
1heretore, unless you need to boost the processor bus drive strength (tor troubleshooting or
overclocking purposes,, it is recommended that you leave it at the detault s etting.
CPU Iost String
1he Pentium 4, Xeon, and P6 tamily ot processors can actually modity their operation during
string store operations to maximize pertormance.1his ability is called fast string processing.
It certain tast string conditions are met, the processor can actually operate oirecti on the string
in a cache-line us ing the cache-line mode.1he string data is then vritten back to the cache-
line atter moditication by the processor.
1his BIOS teature controls the processor`s tast string teature.
When enabled, the processor operates on the string in a cache line vhen the tast string con-
ditions are met.
When disabled, the processor does not operate on the string vhile it is in a cache line.
It is recommended that you enable CPL last String tor better pertormance. 1here is currently
no reason vhy you should disable CPL last String.
CPU Hypor-lhrooding
1he Intel Hyper-1hreading 1echnology is an extension to the IA-32 architecture, vhich
allovs a single processor to execute tuo or more separate threads concurrently. When hyper-
threading is enabled, multi-threaded sottvare applications can execute their threads in parallel,
thereby improving the processor`s pertormance.
1he current implementation involves tuo logical processors sharing the processor`s execution
engine and its bus intertace. Lach logical processor, hovever, comes vith its ovn APIC. 1he
other teatures ot the processor are either shared or duplicated in each logical proces sor.
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Here is a list ot the teatures duplicated in each logical processor:
General registers (LAX, LBX, LCX, LDX, LSI, LDI, LSP, and LBP,
Segment registers (CS, DS, SS, LS, lS, and GS,
LlIAGS and LIP registers
x87 lPL regis ters (S10 to S17, status vord, control vord, tag vord, data operand pointer,
and instruction pointer,
MMX registers (MM0 to MM7,
XMM registers (XMM0 to XMM7,
MXCSP register
Control registers (CP0, CP2, CP3, CP4,
System table pointer registers (GD1P, ID1P, ID1P, task register,
Debug registers (DP0, DP1, DP2, DP3, DP6, DP7,
Debug control MSP (IA32_DLBLGC1I,
Machine check global status MSP (IA32_MCG_S1A1LS,
Machine check capability MSP (IA32_MCG_CAP,
1hermal clock modulation and ACPI pover management control MSPs
1ime stamp counter MSPs
Most ot the other MSP registers including Page Attribute 1able (PA1,
Iocal APIC registers
Here are the teatures shared by the tvo logical processors:
IA32_MISC_LNABIL MSP
Memory type range registers (M1PPs,
And the tolloving are teatures that can be duplicated or shared according to requirements:
Machine check architecture (MCA, MSPs
Pertormance monitoring control and counter MSPs
An Intel processor that supports Hyper-1hreading
A motherboard vith a chipset and BIOS that support Hyper-1hreading
An operating system that supports Hyper-1hreading ( Microsott Windovs XP or
Iinux 2.4.x,
It is highly recommended that you enable CPL Hyper-1hreading tor improved processor
pertormance.
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CPU L2 Cocho LCC Chocking
1his BIOS teature enables or disables the L2 (Level 2 or Secondary, cache`s LCC (Lrror
Checking and Correction, tunction, it available.
Lnabling this teature is recommended because it detects and corrects single-bit errors in data
stored in the I2 cache. As most data reads are satistied by the I2 cache, the I2 cache`s LCC
tunction should catch and correct almost all single-bit errors in the memory subsystem.
It also detects double-bit errors, although it cannot correct them. Hovever, this isn`t such a big
deal because double-bit errors are extremei rare. lor all practical purposes, the LCC check
should be able to catch virtually all data errors.1his is especially usetul at overclocked speeds
vhen errors are most likely to creep in.
1here are those vho advocate disabling LCC checking because it reduces pertormance. 1rue,
LCC checking doesn`t come tree.You can expect some pertormance degradation vith LCC
checking enabled. Hovever, unlike LCC checking ot DPAM modules, the pertormance degra-
dation associated vith I2 cache LCC checking is comparatively small.
Balance that against the increased stability and reliability achieved through I2 cache LCC
checking and the minimal reduction in pertormance seems rather cheap, doesn`t it Ot course,
it you don`t do any serious vork vith your system and vant a little speed boost tor your games,
disable CPL I2 Cache LCC Checking by all means.
Hovever, it you are overclocking your processor, LCC checking may enable you to overclock
higher than originally possible.1his is because any single-bit errors that occur as a result ot
overclocking are corrected by the I2 cache`s LCC tunction. So, tor most intents and purposes,
I recommend that you enable this teature tor greater sys tem stability and reliability.
Please note that the presence ot this teature in the BIOS does not necessarily mean that your
processor`s I2 cache actually supports LCC checking. Many processors do not ship vith LCC-
capable I2 cache. In such cases, you still can enable this teature in the BIOS, but it has no eff ect.
CPU Lovol 1 Cocho
1he modern processor is a very tast piece ot silicon. Lntortunately, PAM development has
lagged so tar behind that the processor vould be tatally stalled by slov memory accesses it it has
to rely entirely on current PAM technology.
1o alleviate this problem, processors nov come vith a small amount ot ultra-tast SRAM
(Static RAM, vithin its core. 1his small amount ot SPAM is used to cache instructions and
data, so the processor can access them instantaneously.
Because this is the tirst cache that the processor checks vhen it needs data, it is knovn as the
Level 1 cache or L1 cache. It is also knovn by some as the prinary cache. In current
processor designs, the Ievel 1 cache can range trom 32KB to 128KB in size.
It the processor cannot tind vhat it vants in the Ievel 1 cache, it checks the Level 2 cache
betore proceeding to the Level 3 cache (in some cases,. In the vorst-case scenario, all the
caches are unable to tultill the processor`s request.When this happens, the processor has to access
the PAM itselt.
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Naturally, the processor is severely s talled vhen it has to retrieve intormation trom the much
slover memory. lortunately, the combination ot tast caches is otten able to satisty the processor`s
data requests most ot the time. In tact, the caches are so etticient that they make the entire
memory subsystem appear almost as tast as they are'
1his is vhere the CPU Level 1 Cache BIOS teature comes in. It controls the tunctionality ot
the processor`s Ievel 1 cache.
lor example, it your processor cannot reach 2GHz, you can try to tind out it the cause is the
Ievel 1 cache by disabling this BIOS teature. It this allovs your proces sor to run at 2GHz and
beyond, then the Ievel 1 cache is the cause ot your processor`s tailure to run at 2GHz.
Hovever, it your processor still cannot run at 2GHz even vith the Ievel 1 cache disabled, then
the problem lies elsevhere.
Please note that disabling the Ievel 1 cache in order to increase the overclockability ot the CPL
is a :er |ao idea. It the Ievel 1 cache is disabled, the processor vill stall trequently because the
memory subsystem just isn`t tast enough to continuously teed data to the processor by itselt'
1heretore, except tor troubleshooting purposes, this teature should alvays be lett enabled.
CPU Lovol 2 Cocho
1he modern processor is a very tast piece ot silicon. Lntortunately, PAM development has
lagged so tar behind that the processor vould be tatally stalled by slov memory accesses it it has
to rely entirely on current PAM technology.
1o alleviate this problem, processors nov come vith a small amount ot ultra-tast SRAM
(Static RAM, vithin its core. 1his small amount ot SPAM is used to cache instructions and
data, so the processor can access them instantaneously. 1his is knovn as the Level 1 cache or
L1 cache. In current processor designs, the Ievel 1 cache can range trom 32KB to 128KB
in size.
It the processor cannot tind vhat it vants in the Ievel 1 cache, it checks the Level 2 cache
betore proceeding to the Level 3 cache (in some cases,. In the vorst-case scenario, all the
caches are unable to tultill the processor`s request.When this happens, the processor has to access
the PAM itselt.
Naturally, the processor is severely s talled vhen it has to retrieve intormation trom the much
slover memory. lortunately, the combination ot tast caches is otten able to satisty the processor`s
data requests most ot the time. In tact, the caches are so etticient that they make the entire
memory subsystem appear almost as tast as they are'
As mentioned above, the processor not only has a Ievel 1 cache but, by necessity, a Level 2
cache or L2 cache as vell. 1his cache is also knovn by some as the secondary cache.
LPu Lcvc| 2 Lachc 186
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1his Ievel 2 cache is designed to handle data requests that the Ievel 1 cache tails to satisty.
Although slover than the Ievel 1 cache, the Ievel 2 cache compensates by being much larger in
size.While the largest Ievel 1 cache at this time is only 128KB, Ievel 2 caches can be as large as
1MB'
Irrespective ot the actual numbers, the larger size ot the Ievel 2 cache allovs it to store a lot
more data than the Ievel 1 cache.1his gives it a high probability ot satis tying cache misses trom
the Ievel 1 cache. In tact, the tvo caches vorking together are actually capable ot satistying the
processor`s data request 909 ot the time' 1his greatly reduces the need tor the processor to
access the much slover PAM.
is a :er |ao idea. It the Ievel 2 cache is disabled, the processor vill stall trequently because the
memory subsystem just isn`t tast enough to continuously teed data to the processor by itselt'
CPU Lovol 3 Cocho
In addition to the Ievel 1 and Ievel 2 caches, some processors come vith an additional cache
called Level 3 cache or L3 cache.
1his Ievel 3 cache is designed to handle data requests that the Ievel 1 and Ievel 2 caches tail to
satisty. Although slover than the Ievel 2 cache, the Ievel 3 cache compensates by being much
larger in size.While the largest Ievel 2 cache at this time is only 312KB, Ievel 3 caches can be
as large as 4MB'
more data than the Ievel 2 cache.1his gives it a high probability ot satistying cache misses trom
the Ievel 2 cache.With three caches vorking together, the chance ot the processor stalling due
to the need to access the much slover PAM is very small.
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Currently, this is an Intel Xeon MP-specitic BIOS teature. 1he Intel Xeon MP processor tea-
tures an on-die Ievel 3 cache that can be 312KB, 1MB or 2MB in size. It is an 8-vay set asso-
ciative sectored cache vith 64-byte cache lines.
When enabled, the processor`s Ievel 3 cache is alloved to tunction. 1his allovs the best pos si-
processor.
is a :er |ao idea. It the Ievel 3 cache is disabled, the processor may stall trequently, especially
vhen the system is running memory-intensive applications.
CPU lhornol-lhrottling
Connon Options: 12.3, 23.0, 37.3, 30.0, 62.3, 73.0, 87.3
sors vith 312KB I2 cache.1hese processors come vith a 1hernal Monitor, vhich actually
consists ot an on-die thermal sensor and a 1hernal Control Circuit (1CC,. Because the
thermal sensor is on-die and placed at the hottest part ot the die[md|near the integer AIL
unitsit is able to closely monitor the processor`s die temperature.
processor has reached its maximum sate operating temperature, it vill send a PROCHO1
(Processor Hot, signal, vhich activates the 1CC.1he 1CC vill then modulate the clock cycles
by inserting null cycles, typically at a rate ot S0-70 ot the total number ot clock cycles. Note
cycles that result in the processor resting30-70 ot the time.
As the die temperature drops, the 1CC vill gradually reduce the number ot null cycles until no
stops sending the PPOCHO14 signal, thereby turning ott the 1CC.1his mechanism allovs
the processor to dynamically adjust its duty cycles to ensure its die temperature remains vithin
sate limits.
duty cycle.
LPu Jhcrma|-JhroII|ng 187
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turn ott the 1CC.
CPU to PCI Post Writo
It this butter is disabled, the processor bypasses the butter and vrites directly to the PCI bus.
Although this may seem like the taster and better method, it really isn`t so.
When the processor vants to vrite to the PCI bus, it has to arbitrate tor control ot the PCI
bus.1his takes time, especially vhen there are other devices requesting access to the PCI bus as
vell. During this time, the processor cannot do anything else but vait tor its turn.
Lven vhen it gets control ot the PCI bus, the processor s till has to vait until the PCI bus is
tree. Because the processor bus (vhich can be as tast as 333MHz, is many times taster than the
PCI bus (at only 33MHz,, the processor vastes many clock cycles just vaiting tor the PCI bus.
And it hasn`t even begun vriting to the PCI bus yet' 1he entire transaction, theretore, puts the
processor out ot commission tor many clock cycles.
1his is vhere the CPL-to-PCI vrite butter comes in. It is a small memory butter built into the
chipset. 1he actual size ot the butter varies trom chipset to chipset. But in most cases, it is big
enough tor four vords or 64-bits vorth ot data.
When this vrite butter is enabled, all PCI vrites trom the processor go straight into it, instead
ot the PCI bus.1his is virtually instantaneous because the processor does not have to arbitrate
or vait tor the PCI bus. 1hat task is nov lett to the chipset and its vrite butter.1he processor is
thus tree to vork on something else.
It is important to note that the vrite butter isn`t able to vrite the data to the PCI bus any taster
than the processor can.1his is because the vrite butter still has to arbitrate and vait tor control
ot the PCI bus' Hovever, the ditterence here is that the entire transaction can be carried out
vithout tying up the processor.
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1o sum it all up, enabling the CPL to PCI vrite butter trees up CPL cycles that vould nor-
mally be vasted vaiting tor the PCI bus. 1heretore, it is recommended that you enable this tea-
ture tor better pertormance.
CPU to PCI Writo BuIIor
It this butter is disabled, the processor bypasses the butter and vrites directly to the PCI bus.
Although this may seem like the taster and better method, it really isn`t so.
When the processor vants to vrite to the PCI bus, it has to arbitrate tor control ot the PCI
bus.1his takes time, especially vhen there are other devices requesting access to the PCI bus as
vell. During this time, the processor cannot do anything else but vait tor its turn.
Lven vhen it gets control ot the PCI bus, the processor s till has to vait until the PCI bus is
tree. Because the processor bus (vhich can be as tast as 333MHz, is many times taster than the
PCI bus (at only 33MHz,, the processor vastes many clock cycles just vaiting tor the PCI bus.
And it hasn`t even begun vriting to the PCI bus yet' 1he entire transaction, theretore, puts the
processor out ot commission tor many clock cycles.
1his is vhere the CPL-to-PCI vrite butter comes in. It is a small memory butter built into the
chipset. 1he actual size ot the butter varies trom chipset to chipset. But in most cases, it is big
enough tor four vords or 64-bits vorth ot data.
When this vrite butter is enabled, all PCI vrites trom the processor go straight into it, instead
ot the PCI bus.1his is virtually instantaneous because the processor does not have to arbitrate
or vait tor the PCI bus. 1hat task is nov lett to the chipset and its vrite butter.1he processor is
thus tree to vork on something else.
It is important to note that the vrite butter isn`t able to vrite the data to the PCI bus any taster
than the processor can.1his is because the vrite butter still has to arbitrate and vait tor control
ot the PCI bus' Hovever, the ditterence here is that the entire transaction can be carried out
vithout tying up the processor.
1o sum it all up, enabling the CPL to PCI vrite butter trees up CPL cycles that vould nor-
mally be vasted vaiting tor the PCI bus. 1heretore, it is recommended that you enable this tea-
ture tor better pertormance.
CPU VCoro Voltogo
Connon Options: Std.Vcore, Paising
1his is a BIOS teature so tar seen only in the ABI1 NV7-series ot motherboards. It is used to
give a small boost to the processor`s core voltage.
When set to Std.Vcore, the motherboard supplies the processor vith the detault core voltage.
When set to Raising, the motherboard boosts the processor`s core voltage by approximately
3. So, it your processor has a core voltage ot 1.7 volts, using the Paising option raises that
voltage to about 1.7SV.
LPu vLorc vo|Iagc 180
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As you can see, the voltage boost courtes y ot this BIOS teature is not remarkable. In tact, this
boosted voltage is still vithin the processor`s specitied voltage limits'
Hovever, because it appears to be the only vay to boost the processor`s core voltage in
NVIDIA nlorce-based motherboards, this 3 boost is better than nothing at all' It may not
allov radical overclocking, but it should allov a little more overclocking treedom.
It you are an overclocker, it is recommended that you select the Raising option. It should allov
your processor to be a little more overclockable. At the very least, it improves its stability at
overclocked speeds.
It you are not an overclocker, the choice ot vhether to enable or disable this BIOS teature is
really up to you.You can enable it to ensure a more stable processor or you can disable it to save
pover and reduce the thermal output.
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DBI Output Ior AGP lrons.
1he tull name tor this BIOS teature is Dynanic Bus Inversion Output for AGP
1ransnitter. It is an AGP 3.0-specitic BIOS teature that only appears vhen you install an AGP
3.0-compliant graphics card.
1he AGP bus has 32 data lines divided into tvo sets. In each set, there are 16 data lines that
individually svitch to either a high (1, or lov (0, as it sends out data. Sometimes, a large num-
ber ot these data lines may svitch together to the same polarity (either 1 or 0, and then svitch
back to the opposite polarity. 1his mass svitching to the same polarity is called sinultaneous
svitching outputs and it creates a lot ot unvanted electrical noise at the AGP controller and
GPL intertaces.1his is only signiticant it the number ot lines simultaneously svitching to the
same polarity exceeds S0 ot the data lines.
1o avoid this, the AGP 3.0 specitications introduced a scheme called Dynanic Bus Inversion
or DBI. It makes use ot tvo nev DBI linesone tor each 16-line set. 1hese DBI lines are only
supported by AGP 3.0-compliant graphics cards.
When enabled, it ensures that the data lines are limited to a maximum ot 8 sinultaneous
svitchings or transitions per 16-line set.When the number ot simultaneous transitions exceeds 8
or S0 ot the data lines, the AGP controller svitches the polarity ot the DBI line instead.1he
data lines that vere supposed to svitch en masse to the opposite polarity remain at the same
polarity.
When disabled, there are no restrictions to the number ot simultaneous svitchings that the
data lines can pertorm.
At the receiving end hovever, the data is reproduced exactly as it vas meant to. 1his is because
the DBI line actually serves as a reterence signal tor the AGP data signals. Although the data sig-
nals may have been inverted on the transmitter end, the inverted DBI signal corrects it at the
receiving end.
Hovever, because only one, instead ot 9 or more, data lines svitched to the opposite polarity,
the amount ot electrical noise generated is signiticantly reduced. In short, DBI improves stability
ot the AGP intertace by reducing signal noises that occur as a result ot sinultaneous svitch-
ing outputs. It also reduces the AGP controller`s pover consumption.
1heretore, it is recommended that you enable DBI Output for AGP 1rans. to save pover as
vell as reduce signal noise trom simultaneous svitching outputs.
Doloy DRAM Rood Lotch
Connon Options: Auto, No Delay, 0.3ns, 1.0ns, 1.3ns
1his teature is similar to the DRAM Read Latch Delay BIOS teature. It tine-tunes the
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DPAM loading increases as the number ot memory modules increases. It also increases it you
use, the greater the DPAM loading. As such, a lone single-sided memory module provides the
lovest DPAM load possible.
the manutacturer.
delay.
1he longer the delay, the poorer the read pertormance ot your memory modules. Hovever, the
stability ot your memory modules von`t increase together vith the length ot the delay.
Pemember, the purpose ot the teature is to ensure that the memory controller is able to latch
onto the DPAM device vith all sorts ot DPAM loadings.
DPAM device in your particular situation. Don`t unnecessarily increase the delay. It isn`t going
to increas e stability. In tact, it may just make things vorse' So, start vith 0.Sns and vork your
vay up until your system stabilizes.
No Delay option.1his torces the memory controller to latch onto the DPAM devices uithout
oeia, even it the BIOS presets indicate that a delay is required. Naturally, this can potentially
cause stability problems it you actually have a heavy DPAM load. 1heretore, it your system
becomes unstable atter using the No Delay option, simply revert back to the detault value ot
Auto so that the BIOS can adjust the read latch delay to suit the DPAM load.
Doloy IDL Initiol
Connon Options: 0 to 13
Pegardless ot its shortcomings, the IDL standard is remarkably backvard-compatible. Lvery
upgrade ot the standard vas designed to be tully compatible vith older IDL devices. So, you
can actually use the old 40MB hard disk that came vith your ancient 386 system in your
spanking nev Athlon XP s ystem' Hovever, even backvard compatibility cannot account tor the
slover motors used in the older drives.
Motherboards are capable ot booting up much taster these days. 1heretore, initialization ot IDL
devices nov take place much earlier. Lntortunately, this also means that some older IDL drives
are not be able to spin up in time to be initialized' When this happens, the BIOS is unable to
detect that IDL drive and the drive is not accessible even though it is actually running just tine.
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1his is vhere the Delay IDL Initial BIOS teature comes in. It allovs you to torce the BIOS
to delay the initialization ot IDL devices tor up to 13 seconds. 1he delay allovs your IDL
devices more time to spin up betore the BIOS initializes them.
It you do not us e old IDL drives and the BIOS has no problem initializing your IDL devices, it
is recommended that you leave the delay at the detault value ot 0 tor the shortest possible boot-
ing time. Most IDL devices manutactured in the last tev years have no problem spinning up in
time tor initialization.
Hovever, it one or more ot your IDL devices tail to initialize during the boot up process, start
vith a delay ot 1 second. It that doesn`t help, gradually increase the delay until all your IDL
devices initialize properly during the boot up process.
Doloy Prior lo lhornol
Connon Options: 4 Minutes, 8 Minutes, 16 Minutes, 32 Minutes
sors vith 312KB I2 cache.1hese processors come vith a 1hernal Monitor that actually con-
sists ot an on-die thermal sensor and a 1hernal Control Circuit (1CC,. Because the thermal
sensor is on-die and placed at the hottest part ot the dienear the integer AIL units, it is able
to closely monitor the processor`s die temperature.
processor has reached its maximum sate operating temperature, it sends a PROCHO1
(Processor Hot, signal that activates the 1CC. 1he 1CC then modulates the clock cycles by
inserting null cycles, typically at a rate ot S070 ot the total number ot clock cycles . Note
cycles that result in the processor resting3070 ot the time.
As the die temperature drops, the 1CC gradually reduces the number ot null cycles until no
stops sending the PPOCHO14 signal, thereby turning ott the 1CC.1his mechanism allovs the
processor to dynamically adjust its duty cycles to ensure its die temperature remains vithin sate
limits.
1he Delay Prior 1o 1hernal BIOS teature controls the activation ot the 1hermal Monitor`s
automatic mode. It allovs you to determine vhen the Pentium 4`s 1hermal Monitor should be
activated in automatic mode atter the system boots. lor example, vith the detault value ot
16 Minutes, the BIOS activates the 1hermal Monitor in automatic mode 16 minutes atter the
system starts booting up.
It also allovs the vatchdog timer to generate a Systen Managenent Interrupt (SMI,,
thereby presenting the BIOS vith an opportunity to enable the 1hermal Monitor vhen run-
ning non-ACPI-compliant operating s ystems.
Generally, the 1hermal Monitor should not be activated immediately atter booting because the
processor is under a heavy load during the booting process. 1his causes a sharp rise in die tem-
perature trom its cold state. Because it takes time tor the thermal output to radiate trom the die
to the heat sink, the thermal sensor registers the s udden spike in die temperature and prema-
turely activates the 1CC. 1his unnecessarily reduces the processor`s pertormance during the
booting up process.
0c|ay Pror Jo Jhcrma| 108
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1heretore, to ensure optimal booting pertormance, the activation ot the 1hermal Monitor must
be delayed tor a set period ot time.1his allovs the processor to operate at maximum pertorm-
ance vithout interterence trom the 1hermal Monitor. It also prevents the unnecessary activation
ot the 1CC and the subsequent modulation ot processor cycles by alloving the die to stabilize
to its true temperature betore 1hermal Monitor is activated.
It is recommended that you set this BIOS teature to the lovest value (in minutes, that exceeds
the time it takes to tully boot up your computer. lor example, it it takes 3 minutes to tully boot
up your system, you s hould select 8 Minutes.
You should not select a delay value that is unnecessarily long.Without the 1hermal Monitor,
your processor may heat up to a critical temperature (approximately 13SC,, at vhich point the
1HLRM1RIP signal is asserted. 1his shuts dovn your processor by removing the core volt-
age vithin 0.S seconds.While this measure saves the processor trom permanent damage, you
have to reset the system betore the processor vill start vorking again.
Doloyod lronsoction
On the PCI bus, there are many devices that may not meet the PCI target latency rule. Such
devices include IO controllers and bridges (tor example, PCI-to-PCI and PCI-to-ISA bridges,.
clock cycles (32 clock cycles tor a host bus bridge, tor the initiai read and 8 PCI clock cycles
tor each su|seuent read. It it cannot do so, the PCI bus terminates the transaction, so other PCI
devices can access the bus. Hovever, instead ot rearbitrating tor access ( and tailing to meet the
minimum latency requirement again,, the PCI 2.1-compliant device can make use ot the PCI
Delayed 1ransaction teature.
When a master device reads trom a target device on the PCI bus but tails to meet the latency
requirements, the transaction is terminated vith a Petry command.1he master device then has
to rearbitrate tor bus access. Hovever, it PCI Delayed 1ransaction is enabled, the target
device can independently continue the read transaction. So, vhen the master device successtully
gains control ot the bus and reissues the read command, the target device has the data ready tor
immediate delivery. 1his ensures that the retried read transaction can be completed vithin the
stipulated latency period.
It the delayed transaction is a vrite, the target device latches on the data and terminates the
transaction it it cannot be completed vithin the target latency period.1he mas ter device then
rearbitrates tor bus access vhile the target device completes vriting the data. When the master
device regains control ot the bus, it reissues the same vrite request.1his time, instead ot return-
ing data (in the case ot a read transaction,, the target device sends the completion status to the
PCI Delayed 1ransaction also allovs vrite-posted data to remain in the butter vhile the PCI
bus initiates a non-postable transaction and yet still adheres to the PCI ordering rules. 1he
vrite-posted data is vritten to memory vhile the target device is vorking on the non-postable
transaction and tlushed betore the transaction is completed on the master device. Without PCI
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Delayed 1ransaction, all vrite-posted data has to be tlushed betore another PCI transaction
can occur.
As you can see, the PCI Delayed 1ransaction teature allovs tor more etticient use ot the PCI
bus as vell as better PCI pertormance by alloving vrite-posting to occur concurrently vith
non-postable transactions. In this BIOS, the Delayed 1ransaction option allovs you to enable
or disable the PCI Delayed 1ransaction teature.
It is highly recommended that you enable Delayed 1ransaction tor better PCI pertormance and
to meet PCI 2.1 specitications. Disable it only it your PCI cards cannot vork properly vith
this teature enabled or it you are using PCI cards that are not PCI 2.1-compliant.
Please note that vhile many manuals, and even earlier versions ot the BIOS Optimization
Guide, have stated that this is an ISA bus-specitic BIOS teature that enables a 32-bit vrite-post-
ed butter tor taster PCI-to-ISA vrites, they are incorrect' 1his BIOS teature is not ISA bus-spe-
citic, and it does not control any vrite-posted butters. It merely allovs vrite-posting to
continue vhile a non-postable PCI transaction is undervay.
Disoblo Unusod PCI Clock
turn ott the unused clock signals.
1his teature is a subset ot the Auto Detect DIMM/PCI Clk teature. It you enable it, the
BIOS monitors the PCI slots tor activity. 1he clock signals ot unoccupied slots are automati-
cally turned ott.1he clock signals to occupieo PCI slots are also turned ott vhenever there is
no activity.
use pover and only vhen they are actually doing vork.
Hovever, because this teature reduces LMI and pover consumption vithout compromising sys-
tem stability, it is recommended that you enable it.
DRAM Act to ProChrg CMD
Connon Options: 31, 61, 71, 81, 91
Whenever a read command is issued, a memory rov is activated using the RAS (Row Address
Strobe,.1hen, to read data trom the target memory cell, the appropriate column is activated
using the CAS (Column Address Strobe,. Multiple cells can be read trom the same active rov
by applying the appropriate CAS signals.
Hovever, vhen data has to be read trom a ditterent rov, the active rov has to be
deactivated.1he rov cannot be deactivated until the Minimum Row Active Time or tRAS has
elapsed.
0AM AcI Io PrcLhrg LM0 106
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1he appropriate delay tor your memory module is retlected in its rated timings. In LDLC
specitications, it is the fourth number in the tour number sequence. lor example, it your memo-
ry module has the rated timings ot 2-3-4-7, its rated tPAS delay vould be 7 clock cycles.
Iike SDRAM 1ras 1ining Value, this BIOS teature controls the memory bank`s minimum
same rov can be deactivated. Hence, the name DRAM Act to PreChrg CMD, vhich is short
tor DRAM Activate Connand to Precharge Connand. It is also the length ot time the
rov remains open tor data transters.
DRAM Burst Longth 8QW
Burst transactions improve SDPAM pertormance by alloving the reading or vriting ot vhole
blocks ot contiguous data vith only one column address.
In a burst sequence, only the first read or vrite transter incurs the initial latency ot activating the
column.1he subsequent reads or vrites in that burst sequence can then tollov behind vithout
any turther delay.1his allovs blocks ot data to be read or vritten vith tar less delay than non-
burst transactions.
lor example, a burst transaction ot tour vrites can incur the tolloving latencies: 4-1-1-1. In this
example, the total time it takes to transact the tour vrites is merely 7 clock cycles .
In contrast, it the tour vrites are not vritten by burst transaction, they incur the tolloving
latencies: 4-4-4-4.1he time it takes to transact the tour vrites becomes 16 clock cycles, vhich
is 9 clock cycles longer, or more than tvice as slov as a burst transaction.
1his is vhere the DRAM Burst Length 8QW BIOS teature comes in. It is a BIOS teature
that allovs you to control the length ot a burst trans action.
When this teature is set to Disabled, a burst transaction can only be comprised ot up to four
When this teature is set to Lnabled, a burst transaction can only be comprised ot up to eight
lor example, it the memory controller vants to vrite a block ot contiguous data eight units
long to memory, it can do it as a sini e burst transaction 8 units long or tuo burst transactions,
each 4 units in length. 1he hypothetical latencies incurred by the single 8-unit long transaction
vould be 4-1-1-1-1-1-1-1 vith a total time ot 11 clock cycles tor the entire transaction.
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Data Path Width LCC Code Length
8-bit 3 LCC bits
16-bit 6 LCC bits
32-bit 7 LCC bits
64-bit 8 LCC bits
128-bit 9 LCC bits
Hovever, it the eight vrites are vritten to memory as tvo burst transactions ot 4 units in
length, the hypothetical latencies incurred vould be 4-1-1-1-4-1-1-1.1he time taken tor the
tvo transactions to complete vould be 14 clock cycles. As you can see, this is slover than a sin-
gle transaction, vhich is 8 units long.
1heretore, it is recommended that you enable this BIOS teature tor better pertormance.
DRAM Doto Intogrity Modo
Connon Options: LCC, Non-LCC
1his BIOS teature controls the LCC teature ot the memory controller.
LCC, vhich stands tor Lrror Checking and Correction, enables the memory controller to
detect and correct single-bit sott memory errors. 1he memory controller also is able to detect
double-bit errors, although it is not able to correct them.1his provides increased data integrity
and system stability. Hovever, this teature can only be enabled it you are using s pecial LCC
memory modules.
Nov, this type ot memory module is special (and more expensive', because it comes vith extra
memory chips and a vider path.1his is because the chipset needs to append a certain number
ot extra LCC bits (called LCC code, to each data vord that is vritten to the memory module.
When the data vord is read back, the memory controller recalculates the LCC code ot the read
data vord and compares it to the original LCC code that vas vritten to memory earlier. It the
codes are identical, then the data is valid.
Hovever, it there`s a single-bit error in the data vord, the memory controller can identity the
detective bit by analyzing the ditterences in the tvo LCC codes.1hat bit then can be corrected
by simply tlipping it to the opposite state (trom 0 to 1, and vice versa,.
Here is a list ot LCC code length required tor various data path vidths using the current
Hamming code LCC algorithm:
0AM 0aIa InIcgrIy Modc 107
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Because present day processors use 64-bit vide data paths, 72-bit (64-bit data 8-bit LCC,
LCC memory modules are required to implement LCC. Please note that the maximum data
transter rate ot the 72-bit LCC memory module is the same as the 64-bit memory module.
1he extra 8-bits are only tor the LCC code and do not carry any data. So, using 72-bit memo-
ry modules does not give you any boost in pertormance.
In tact, because the memory controller has to calculate the LCC code tor e:er data vord that is
read or vritten, there is some pertormance degradation, roughly in the region ot 3-S.1his is
one ot the reasons vhy LCC memory modules are not popular among desktop users .1hrov in
the tact that LCC memory modules are both expensive and hard to come by, and you have the
top three reasons vhy LCC memory modules vill never be mainstream solutions.
Hovever, it data integrity is ot utmost importance to you, and you can`t attord to have your
data corrupted or your system is dovn due to errant cosmic rays or radiation trom DPAM
packaging, LCC memory is the vay to go.1he loss ot 3S in memory pertormance is really
nothing compared to the peace ot mind that LCC can give. In any cas e, the matter ot this
BIOS teature is much easier to settle.
It you are using standard 64-bit memory modules, you must select the Non-LCC option.
Hovever, it you have already torked out the money tor 72-bit LCC memory modules, you
should enable the LCC teature, no matter vhat people say about losing some memory per-
tormance. It doesn`t make sense to buy expensive LCC memory modules and then disable
LCC' Pemember, you are not really losing pertormance.You are just trading it tor greater
stability and data integrity.
DRAM Idlo linor
Connon Options: 01, 81, 161, 641, Intinite, Auto
1he memory controller allovs a number ot memory pages to remain open. It a processor cycle
to the SDPAM talls vithin those open pages, it can be satistied vithout delay. 1his naturally
improves pertormance.
Hovever, these pages can only remain open tor so long. 1hey eventually have to be closed and
precharged. It the page closes vhen the memory controller attempts to read trom it, then the
read operation is stalled until the page is activated again. Such a page miss is expensive in terms
ot clock cycles.
1his is vhere the SDRAM Idle Linit BIOS teature comes in.1his teature sets the number ot
idle cycles alloved betore the memory controller torces such open pages to close and precharge.
It can be set to a variety ot clock cycles trom 01 to 641. 1his sets the number ot clock cycles
the open pages are alloved to idle betore they are closed and precharged.1here`s also an
Infinite option as vell as an Auto option.
It you select Infinite, the memory controller never precharges the open pages prematurely. 1he
open pages are lett activated until they have to be precharged.
It you select Auto, the memory controller uses the manutacturer`s preset detault setting.
Most manutacturers use a detault value ot 81, vhich allovs the memory controller to
precharge the open pages atter eight idle cycles have passed.
Increasing the SDPAM Idle Iimit to more than the detault ot 81 allovs the SDPAM bank to
delay recharging longer during times ot no activity so that it a read or vrite command comes
along, it can be instantly satistied.
Hovever, this is limited by the retresh cycle already set by the BIOS. 1hat means the open
page retreshes vhen it needs to be recharged vhether the number ot idle cycles have reached
the SDPAM Idle Iimit or not. So, the SDPAM Idle Iimit setting can only be used to torce
the retres hing ot the SDPAM bank |ef ore the set retresh cycle but not to actually delay the
retresh cycle.
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Peducing the number ot cycles trom the detault ot 8 cycles to 01 torces the memory con-
troller to close all open pages atter no valid requests are sent to the memory controller. In short,
the open pages are retreshed as soon as data requests stop coming.1heoretically, this ma
increase the etticiency ot the memory s ubsystem as the ettects ot retres hing the open pages are
masked by precharging during idle cycles. Hovever, any data requests that comes along atter the
page is closed have to vait until it is retreshed and activated betore they can be satistied.
Because retreshes do not occur that otten (usually only about once every 64 msec,, the impact
ot retreshes on memory pertormance is really quite minimal.1he apparent benetits ot masking
the retreshes during idle cycles is not noticeable, especially s ince memory systems these days
already use bank interleaving to mask retreshes.
With a 01 setting, data requests are also likely to get stalled because even a single idle cycle
causes the memory controller to close all open pages' In desktop applications, most memory
reads tavor the spatial locality concept vhereby it one data bit is read, chances are high that
the next data bit also needs to be read.1hat`s vhy closing open pages prematurely using
SDPAM Idle Iimit usually causes reduced pertormance in desktop applications.
On the other hand, using a 0 or 8 idle cycles limit ensures that all memory contents are
retreshed more otten, thereby preventing the loss ot data due to insutticiently retreshed memory
cells. lorcing the memory controller to precharge open pages more otten also ensures that in
the event ot a very long read, the pages can be opened long enough to tultill the data request.
lor general desktop use, it is recommended that you choose the Infinite option, so precharging
can be delayed tor as long as possible.1his reduces the number ot retreshes and increases the
ettective memory bandvidth.
you select 01 because subsequent data requests are most likely tultilled by other pages. Closing
open pages to precharge prepares those pages tor the next data request that hits them. Increased
data integrity is an added benetit ot having more trequent retreshes.
Alternatively, you can greatly increase the value ot the Refresh Interval or Refresh Mode
Select teature to boost bandvidth and use this BIOS teature to maintain the data integrity ot
the memory cells .As ultra-long retresh intervals (tor example, 64 or 128 sec, can cause memo-
ry cells to lose their contents, setting a lov SDPAM Idle Iimit like 01 or 81 allovs the mem-
ory cells to be retreshed more otten, vith a high chance ot those retreshes being done during
idle cycles. 1his appears to combine the best ot both vorldsa long bank active period vhen
the memory controller is being stressed and more retreshes vhen the memory controller is idle.
In reality, hovever, this is not a reliable vay ot ens uring sutticient retresh cycles because it
depends on the vagaries ot memory usage to provide sutticient idle cycles to trigger the retresh-
es. It your memory subsystem is under extended load, there may not be any idle cycle to trigger
an early retresh.1his may caus e the memory cells to lose their contents.
1heretore, it is recommended that you maintain a proper retres h interval and select the Infinite
option (tor desktops,.1his allovs you to boost memory bandvidth by delaying retreshes tor as
long as possible and still maintain the data integrity ot the memory cells through regular and
reliable retresh cycles.
lor servers, it is recommended that you maintain a proper retresh interval and use the 01
setting. 1his precharges all open pages vhenever there`s an idle cycle.
0AM Id|c Jmcr 100
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DRAM Intorloovo lino
Connon Options: 0ms, 0.3ms
1his BIOS teature determines the amount ot aooitionai delay betveen successive bank accesses
vhen the SDRAM Bank Interleave teature has been enabled. Naturally, the shorter the
delay, the tas ter the memory module can svitch betveen banks and, consequently, increases
pertormance.
1heretore, it is recommended that you set the DRAM Interleave 1ine as lov as possible tor
better memory pertormance. In this case, it vould be 0ns, vhich introduces no additional delay
betveen bank accesses. Increase the DRAM Interleave 1ine to 0.Sns only it you experience
instability vith the 0ms setting.
DRAM ProChrg to Act CMD
Whenever a read command is issued, a memory rov is activated using the RAS (Rov Address
Strobe). 1hen, to read data trom the target memory cell, the appropriate column is activated
using the CAS (Colunn Address Strobe). Multiple cells can be read trom the same active
rov by applying the appropriate CAS signals.
But vhen data has to be read trom a ditterent rov, the active rov has to be deactivated. 1his
introduces a short delay betore the another rov can be activated.1his delay is knovn as the
RAS Precharge Time or tRP.
specitications, it is the thiro number in the three or tour number sequence. lor example, it your
memory module has the rated timings ot 2-3-4-7, its rated tPP delay vould be 4 clock cycles.
Iike SDRAM 1rp 1ining Value, this BIOS teature controls the PAS precharge time (tPP,.
1his constitutes the time it takes tor the Precharge command to complete and the rov to be
available tor activation. Hence, the name DRAM PreChrg to Act CMD, vhich is short tor
DRAM Precharge Connand to Activate Connand.
It the PAS precharge time is too long, it reduces pertormance by delaying all rov activations.
Peducing the precharge time to 21 improves pertormance by alloving a nev rov to be acti-
vated earlier.
Hovever, the short precharge time ot 21 may be insutticient tor some memory modules. In
such cases, the active rov may lose its contents betore they can be returned to the memory
bank and the rov deactivated.1his may cause data loss or corruption vhen the memory con-
troller attempts to read trom or vrite to the active rov.
1heretore, it is recommended that you reduce the PAS precharge time to 21 tor better per-
tormance but increase it to 3T or 4T it you experience system s tability issues atter reducing the
precharge time.
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DRAM Rotio (CPU:DRAM)
Connon Options: 1:1, 3:2, 3:4, 4:3, 3:4
1he choice ot options in this BIOS teature depends entirely on the setting ot the DRAM
Ratio H/W Strap or N/B Strap CPU As BIOS teature.
When DRAM Ratio H/W Strap has been set to Lov, the available options are 1:1 and 3:4.
When DRAM Ratio H/W Strap has been set to High, the available options are 1:1 and 4:S.
When N/B Strap CPU As has been set to PSB800, the available options are 1:1, 3.2, and S:4.
When N/B Strap CPU As has been set to PSBS33, the available options are 1:1 and 4:S.
When N/B Strap CPU As has been set to PSB400, the only available option is 3:4.
1he options ot 1:1, 3:2, 3:4, and 4:S reter to the available CPL-to-DPAM (or CPL:DPAM,
ratios.
Please note that vhile the Pentium 4 processor is said to have a 400MHz, 333MHz, or 800MHz
FSB (front side bus,, the tront side bus (also knovn as CPL bus, is actually only running at
100MHz, 133MHz, or 200MHz, respectively.1his is because the Pentium 4 bus is a Quad
Data Rate or QDR bus, vhich transters tour times as much data as a single data rate bus.
lor marketing reasons, the Pentium 4 bus is labeled as running at 400MHz, 333MHz, or
800MHz vhen it is actually running at only 100MHz, 133MHz, and 200MHz, respectively. It is
important to keep this in mind vhen setting this BIOS teature.
lor example, it you set a 3:2 ratio vith a 200MHz (800MH: DP, CPL bus, the memory bus
vill run at (200MHz 3, 2 = 133MHz or 266MHz DDR. Belov are other examples.
It you use a 100MHz (4ooMHz QDR, CPL bus vith a:
3:2 ratio, the DPAM controller runs at 66MHz (or 133MHz DDP,
S:4 ratio, the DPAM controller runs at 80MHz (or 1oMHz DDP,
1:1 ratio, the DPAM controller runs at 100MHz (or 2ooMHz DDP,
4:S ratio, the DPAM controller runs at 12SMHz (or 23oMHz DDP,
It you use a 133MHz (333MHz QDR, CPL bus vith:
3:2 ratio, the DPAM controller runs at 89MHz (or 1'8MHz DDP,
S:4 ratio, the DPAM controller runs at 106MHz (or 213MHz DDP,
4:S ratio, the DPAM controller runs at 166MHz (or 333MHz DDP,
It you use a 200MHz (8ooMHz QDR, CPL bus vith:
S:4 ratio, the DPAM controller runs at 160MHz (or 32oMHz DDP,
1:1 ratio, the DPAM controller runs at 200MHz (or 4ooMHz DDP,
4:S ratio, the DPAM controller runs at 2S0MHz (or 3ooMHz DDP,
0AM aIo (LPu:0AM) 201
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By detault, this BIOS teature is set to By SPD. 1his allovs the chipset to query the SPD
(Serial Presence Detect, chip on every memory module and use the appropriate ratio.
It is recommended that you select the ratio that allovs you to maximize your memory modules`
capabilities. Hovever, bear in mind that synchronous operation using the 1:1 ratio is also highly
desirable because it allovs a high throughput.
DRAM Rotio H/W Strop
Connon Options: High, Iov, By CPL
Intel i843-series ot chipsets. In those chipsets, Intel has chosen to limit the choices ot available
CPL-to-DPAM ratios according to the clock speed ot the CPL bus (also knovn as tront side
bus or lSB,.
to 1:1 or 3:4.
to 1:1 or 4:S.
As you can see, this greatly limits the tlexibility in selecting the best CPL-to-DPAM ratio tor
your system. lortunately, this BIOS teature allovs you to circumvent that limitation.
1he DRAM Ratio H/W Strap BIOS teature actually controls the setting ot the external
hardvare reset strap assigned to the MCH (Menory Controller Hub, ot the chipset. By set-
ting it High or Lov, you can trick the chipset into thinking that the 400MHz FSB or the
S33MHz FSB is being us ed.
When this BIOS teature is set to High, you are able to access the S33MHz CPL-to-DPAM
ratios ot 1:1 and 4:S.
When this BIOS teature is set to Lov, you are able to access the 400MHz CPL-to-DPAM
ratios ot 1:1 and 3:4.
require access to the CPL-to-DPAM ratio that vould normally not be available to you, then
this BIOS teature vould be very helptul indeed.
DRAM Rood Lotch Doloy
1his teature is similar to the Delay DRAM Read Latch BIOS teature. It tine-tunes the
DPAM loading increases as the number ot memory modules increase. It also increases it you
use, the greater the DPAM loading. As such, a lone, single-sided memory module provides the
lovest DPAM load possible.
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the manutacturer.
delay.
1he longer the delay, the poorer the read pertormance ot your memory modules. Hovever, the
stability ot your memory modules von`t increase together vith the length ot the delay.
Pemember, the purpose ot the teature is only to ensure that the memory controller able to
latch onto the DPAM device vith all sorts ot DPAM loadings.
1he amount ot delay should just be enough to allov the memory controller to latch onto the
DPAM device in your particular situation. Don`t unnecessarily increase the delay. It isn`t going
to increas e stability. In tact, it may just make things vorse' So, start vith 0.Sns and vork your
vay up until your system stabilizes.
No Delay option.1his torces the memory controller to latch onto the DPAM devices uithout
oeia, even it the BIOS presets indicate that a delay is required. Naturally, this can potentially
cause stability problems it you actually have a heavy DPAM load. 1heretore, it your system
becomes unstable atter using the No Delay option, simply revert back to the detault value ot
Auto, so the BIOS can adjust the read latch delay to suit the DPAM load.
DRAM RoIrosh Roto
Memory cells normally need to be retreshed every 64 msec. Hovever, simultaneously retreshing
all the rovs in a typical memory chip causes a big surge in pover requirements. In addition, a
simultaneous retresh causes all data requests to stall, vhich greatly impacts pertormance.
1o avoid both problems, retreshes are normally staggered according to the number ot rovs.
Because a typical memory chip contains 4096 rovs, the memory controller usually retreshes a
ditterent rov every 1S.6 sec (64,000 sec 4096 rovs = 13.6 sec,. 1his reduces the amount
ot current used during each retresh, and it allovs data to be accessed trom rovs that are not
being retreshed.
Lsually, memory modules that use 128Mbit or smaller memory chips have 4096 rovs vhile
memory chips vith higher capacity (236Mbit and above, have 8192 rovs. lor memory chips
that come vith 8192 rovs, the retresh interval needs to be halved to 7.8 sec because there are
nov tvice as many rovs to be serviced vithin the stipulated 64 msec tor the entire chip.
0AM cfrcsh aIc 208
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1heretore, the typical retresh interval tor 128Mbit (not MB', or smaller memory chips is 1S.6
sec vhile those tor 236Mbit or larger memory chips is 7.8 sec. Please note that it you are
using a mix ot 128Mbit and 236Mbit memory modules, the tail-sate DPAM Petresh Pate is
7.8 sec, not 13.6 sec.
Although LDLC standards call tor a 64 nsec retresh cycle, memory chips these days can actu-
ally hold data tor longer than that. So, using a longer retresh cycle is quite possible.With a
longer retresh cycle, the memory chips are retreshed less otten, reducing both the amount ot
bandvidth vasted on retreshes and the amount ot pover consumed (vhich is great tor laptops
and other portable devices,.
lor better pertormance, you should consider increasing the DRAM Refresh Rate trom the
larger memory chips, up to 128 sec. Please note that it you increase the DRAM Refresh
Rate too much, the memory cells may lose their contents.
1heretore, you should start vith small increases in the DRAM Refresh Rate and test your
system atter each hike betore increasing it turther. It you tace stability problems upon increasing
Duplo Soloct
Connon Options: lull-Duplex, Halt-Duplex
1he Duple Select option is usually tound under the Onboard Serial Port 2 BIOS teature.
It is slaved to the second serial port, so it you disable that serial port, this option disappears trom
the screen or appears grayed out.
1his BIOS teature allovs you to determine the transmission mode ot the IP (Intra-Ped, com-
munications port.
Selecting Full-Duple permits simultaneous tvo-vay transmis sion, like a conversation over the
phone.
Selecting Half-Duple, on the other hand, only permits transmission in one direction at any
one time, vhich is more like a conversation over a valkie-talkie.
Naturally, the Full-Duple mode is the taster and more desirable choice.You should use Full-
Duple it possible.
Consult your IP peripheral`s manual to determine it it supports Full-Duple transmission. 1he
IP peripheral must support Full-Duple tor this option to vork.
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LCP Modo Uso DMA
Connon Options: Channel 1, Channel 3
1his BIOS teature is usually tound under the Parallel Port Mode teature. It is slaved to the
LCP (Ltended Capabilities Port) option. 1heretore, it you do not enable either LCP or
LCP+LPP, this teature disappears trom the screen or appears grayed out.
1his BIOS teature determines vhich DMA channel the parallel port should use vhen it is in
LCP mode.
1he LCP mode uses the DMA protocol to achieve data transter rates ot up to 2.S Mbits/s and
provides symmetric bidirectional communications. lor all this, it requires the use ot a DMA
channel.
By detault, the parallel port uses DMA Channel 3 vhen it is in LCP mode.1his vorks tine in
most situations.
1his teature vas provided just in case one ot your add-on cards requires the use ot DMA
Channel 3. In such a case, you can use this BIOS teature to torce the parallel port to use the
alternate DMA Channel 1.
Please note that there is no pertormance advantage in choosing DMA Channel 3 over DMA
Channel 1 or vice versa. As long as either Channel 3 or Channel 1 is available tor your parallel
port to use, the parallel port is able to tunction properly in LCP mode.
LPP Modo Soloct
Connon Options: LPP 1.7, LPP 1.9
1his BIOS teature is usually tound under the Parallel Port Mode teature. It`s slaved to the
LPP (Lnhanced Parallel Port, option. 1heretore, it you do not enable either LPP or
LCP+LPP, this teature disappears trom the screen or appears grayed out.
1here are tvo versions ot the LPP transter protocolLPP 1.7 and LPP 1.9. 1his BIOS tea-
ture allovs you to select the version ot LPP that the parallel port should use.
In both versions ot the LPP protocol, the port asserts a Pequest strobe, vhich tells the connect-
ed device that the port vishes to read or vrite data.1he data is then vritten to or read trom
the device. At this point, the connected device returns an Acknovledge strobe.
Once the transaction is complete, the port negates the Pequest s trobe vhile t he connected
device negates its Acknovledge s trobe. 1he port and device is nov ready tor t he next
transaction.
1he ditterence betveen LPP 1.7 and LPP 1.9 lies in their handling ot the connected device`s
Acknovledge strobe.
LPP Modc Sc|ccI 206
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An LPP 1.7 port von`t bother checking it the connected device has actually negated its
acknovledge strobe to shov that it is ready tor the next transaction. It just assumes that the
device is ready tor a nev transaction atter a delay ot 123ns.
Hovever, this creates problems vith long cables becaus e the delay may not be sutticient tor
the device to note the cessation ot the Pequest strobe trom the port and prepare tor a nev
transaction.
An LPP 1.9 port does not have this problem because it actually vaits tor the connected device
to negate the Acknovledge strobe betore it begins a nev cycle. 1his allovs the use ot longer
cables.
Generally, LPP 1.9 is the preterred setting because it supports the never LPP 1.9 devices and
most LPP 1.7 devices, and it otters advantages like support tor longer cables. Hovever, because
certain LPP 1.7 devices cannot vork properly vith an LPP 1.9 port, this BIOS teature vas
implemented to allov you to set the LPP mode to LPP 1.7 vhen s uch an issue crops up.
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Iost R-W lurn Around
When the memory cont roller receives a vrite command immediately atter a read command,
an additional period ot delay is normally introduced betore the vrite command is actually
initiated.
Please note that this extra delay is only introduced vhen there is a svitch trom reads to vrites.
Svitching trom vrites to reads does not sutter trom such a delay.
As its name suggests, this BIOS teature allovs you to skip that delay, so the memory controller
can svitch or turn aroundtrom reads to vrites taster than normal.1his improves the vrite
pertormance ot the memory subsystem. 1heretore, it is recommended that you enable this tea-
ture tor taster read-to-vrite turnarounds.
Hovever, not all memory modules can vork vith the tighter read-to-vrite turn-around. It
your memory modules cannot handle the taster turn-around, the data that vas vritten to the
memory module may be lost or become corrupted. So, vhen you tace stability issues, disable
this teature to correct the problem.
Iost Writo to Rood lurnoround
last valid vrite operation and the next read command to the same internal bank ot the DDP
device.
Please note that this is only applicable tor read commands that tollov a vrite operation.
Consecutive read operations or vrites that tollov reads are not attected.
It this BIOS teature is enabled, every read command that tollovs a vrite operation is delayed
one clock cycle betore it is issued.
It this BIOS teature is disabled, every read command that tollovs a vrite operation is delayed
tvo clock cycles betore it is issued.
Lnabling this BIOS teature naturally allovs taster svitching trom vrites to reads and, conse-
quently, improves pertormance.
Disabling this BIOS teature reduces read pertormance but it improves stability, especially at
normally possible.
FasI WrIc Io cad Jurnaround 207
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By detault, this BIOS teature is disabled. 1his meets LDLC`s specitication ot 2 clock cycles tor
vrite-to-read command delay in DDP400 memory modules. DDP266 and DDP333 memory
modules require a vrite-to-read command delay ot only 1 clock cycle.
It is recommended that you enable this BIOS teature tor better memory read pertormance it
you are using DDP266 or DDP333 memory modules.You can also try enabling it vith
DDP400 memory modules. Hovever, it you tace stability issues, revert to the detault setting ot
Disabled.
Iirst Boot Dovico
IAN, Disabled
1his BIOS teature allovs you to select the first device trom vhich the BIOS attempts to load
through this teature, it doesn`t load another operating system, even it you have one on a ditter-
ent device.
lor example, it you set Floppy as the tirst boot device, the BIOS ignores the Windovs XP
installation on your hard disk and loads up the DOS 3.3 boot disk, vhich you have placed in
the tloppy drive instead. In short, this teature allovs you to choose the tirst device trom vhich
to boot. 1his is particularly usetul vhen you need to load a boot disk tor troubleshooting pur-
poses or tor installing a nev operating system.
By detault, Floppy is the tirst boot device in practically all motherboards.Lnless you boot otten
trom the tloppy drive, it is better to set your hard disk (usually HDD-0, as the tirst boot device.
1his shortens the booting process because the BIOS no longer needs to check the tloppy drive
tor a bootable operating system.
1o install operating systems that come on bootable CD-POMs (tor example, Microsott
Windovs XP, in a nev hard dis k, you need to select CDROM as the tirst boot device.1his
enables you to boot directly trom the CD-POM and load the operating system`s installation
routine.
Ilosh BIOS Protoction
One trustrating problem taced by many users and motherboard manutacturers is the corruption
ot the BIOS by viruses or tailed BIOS updates .1his has been a problem since motherboards
started shipping vith llash BIOS POMs instead ot s tatic BIOS POMs.
Because such an issue could potentially mean high numbers ot really needless PMAs, many
manutacturers nov vrite-protect the BIOS code and only allov vrite access to the llash
POM vhen the user specitically toggles a svitch.1he svitch can be physical (a jumper or DIP
svitch, or it can be sottvare-based (BIOS option,.
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1he Flash BIOS Protection teature is a sottvare toggle that controls vrite access to the
BIOS. When it is enabled, the BIOS code is vrite-protected and cannot be changed.1his pro-
tects it trom any attempt to modity it, including BIOS updates and virus attacks. 1heretore, it
you intend to update the BIOS, you need to disable this teature tirst.
It is highly recommended that you enable this teature at all times.You should only disable it
vhen you intend to update the BIOS. Atter updating the BIOS, you should immediately re-
enable it to protect the BIOS against virus es.
Iloppy 3 Modo Support
Connon Options: Disabled, Drive A, Drive B, Both
lor reasons best knovn to the apanese, their computers come vith special 3 mode 3.3 tloppy
drives.While physically similar to the standard 3.3 tloppy drives used by the rest ot the vorld,
these 3 mode tloppy drives ditter in the disk tormats they support.
Lnlike normal tloppy drives, 3 mode tloppy drives support three ditterent tloppy disk tormats
1.44MB, 1.2MB, and 720KB, hence, their name.1hey allov the sys tem to support the apanese
1.2MB tloppy disk tormat as vell as the s tandard 1.44MB and 720KB (obsolete, disk tormats.
It you ovn a 3 mode tloppy drive and need to use the apanese 1.2MB disk tormat, you must
enable this teature by selecting either Drive A, Drive B, or Both (it you have tvo 3 mode
tloppy drives,. Othervise, your 3 mode tloppy drive von`t be able to read the special 1.2MB
tormat properly.
Hovever, it you only have a standard tloppy drive, disable this teature or your tloppy drive may
not tunction properly.
Iloppy Disk Accoss Control
Connon Options: PW, Pead Only
1his BIOS teature controls vrite access to the tloppy drive.
Setting this BIOS teature to R/W (Read/Write, allovs tull access to the tloppy drive.You vill
be alloved to vrite to tloppy disks as vell as read trom them.
Setting this BIOS teature to Read Only prevents vrite access to the tloppy drive.You vill be
alloved to read trom tloppy disks but you cannot vrite to them.
1his BIOS teature is usetul it you vish to prevent anyone trom copying data out trom a system
that is only equipped vith a tloppy drive.
It is recommended that you set this BIOS teature to R/W, so you have tull access to the tloppy
drive. Set it to Read Only it you do not vish to provide vrite access to the tloppy drive.
F|oppy 0sk Acccss LonIro| 200
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Iorco 4-Woy Intorloovo
1his BIOS teature allovs you to torce the memory controller to use the 4-bank SDPAM
interleave mode, vhich provides better pertormance than the 2-bank interleave mode. Hovever,
you must have at least 4 banks ot memory in the system tor this teature to vork properly.
Please note that ve are talking about memory banks here, not the number ot memory modules.
A SDPAM module is internally made up ot one or more memory banks that can be accessed
simultaneously.
Normally, SDPAM modules that use 16Mbit memory chips (usually 32MB or smaller in size,
have only tvo memory banks. So, it you are using s uch a small capacity DIMM, you should
disable lorce 4-Way Interleave.
Hovever, it you use tvo or more ot such DIMMs, you can still enable lorce-4-Way Interleave.
ust tvo DIMMs is sutticient to provide the tour memory banks required tor the tour-bank
interleave mode to vork.
SDPAM modules that use 64Mbit or larger memory chips are tour-banked in nature.1hese
modules are at least 64MB in size. It you are using such tour-banked modules, it no longer mat-
ters it you are using just one module or several ot them.You can enable lorce 4-Way Interleave
vithout tear.
1heretore, it is recommended that you enable this BIOS teature it you are using 4MP or i arer
memor moouies or at ieast tuo '2MP or smai ier memor moouies. Othervise, it is best to disable
this BIOS teature.
lor more intormation on memory bank interleaving, you should check out the details ot the
SDRAM Bank Interleave BIOS teature.
Iorco Updoto LSCD
1he LSCD (Ltended Systen Configuration Data, is a teature ot the Plug and Play BIOS
that allovs the BIOS to re-use system contiguration data.
Whenever the BIOS boots up, it needs to contigure the ISA, PCI, and AGP devices in the sys-
tem (Plug and Play-capable or othervise,. Hovever, because the installed devices are unlikely to
change trom one booting to another, the system contiguration data actually remains the same.
1heretore, it it can be stored and re-used, the BIOS can skip contiguring the same devices every
time you boot up the system.
1his is vhere the LSCD teature comes in. It stores the IPQ, DMA, IO and memory contigu-
rations ot your system`s devices in a special area ot the BIOS llash POM.1he BIOS s noops and
re-uses the stored contiguration data vhen it boots up the system. As long as there are no hard-
vare changes, the BIOS does not need to recontigure the LSCD.
BIOS automatically detects the changes and recontigures the LSCD.1heretore, there is usually
no need to manually torce the BIOS to recontigure the LSCD.
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result.1his is vhere the Force Update LSCD BIOS teature comes in.
rebooting.
IPU OPCODL Conpotiblo Modo
In Intel IA-32 (P6 tamily, Pentium 4, and so torth, processors, the x87 lPL stores the opcode
ot the last executed non-control instruction (also knovn as the fopcode or FOP code, in an
11-bit register. 1his is to provide state intormation tor exception handlers .
Because the tirst
3 bits ot the
tirst opcode byte
are the same tor
all lPL opcodes,
only the last
3 bits ot the tirst
opcode byte are
stored in the reg-
ister.1he second
opcode byte
provides the
remaining 8-bits
ot data.
In previous implementations, the tinal opcode (or lOP, to be stored in the lOP register is
alvays the lOP ot the last non-transparent tloating point instruction executed betore an
lSAVL, lS1LNV, or lXSAVL instruction.
Hovever, to improve lPL pertormance, the Pentium 4 and Xeon processors only store the
lOP ot the last non-transparent tloating point instruction that had an unmasked exception. lor
backvard compatibility, the Pentium 4 and Xeon processors allov programmable control ot the
lOP register. 1his is vhere the FPU OPCODL Conpatible Mode BIOS teature comes in.
When enabled, the processor reverts to the lOP code compatibility mode and stores the last
non-transparent tloating point instruction in the 11-bit lOP register. Intel recommends that this
teature should only be enabled it the sottvare vas designed to use the topcode to analyze pro-
gram pertormance or to res tart the program atter an exception has been handled.
When disabled, the processor turns ott the lOP code compatibility mode and stores only the
lOP ot the last non-transparent tloating point instruction that had an unmasked exception.1his
allovs tor better lPL pertormance.
FPu 0PL00L LompaIh|c Modc 211
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7 2 0 7 0
10 8 7 0
1st nst ruct ion Byte 2nd nstruction Byte
x87 FPU Opcode Register
(Courtes of Intei Corporation)
1heretore, it is recommended that you disable this teature.1his allovs tor better lPL pertorm-
ance, although some older programs may require you to enable this teature to allov recovery
trom lPL exceptions.
ISB Sprood Spoctrun
erated create LMI (Llectronagnetic Interference,. 1his LMI interteres vith other electron-
ics in the area.1here are also claims that it may allov electronic eavesdropping ot the data that is
being transmitted.
1his BIOS teature allovs you to reduce the LMI ot the front side bus (also knovn as the
FSB or processor bus, by modulating the signals it generates so that the spikes are reduced to
tlatter curves. It achieves this by varying the trequency si ihti so that the signal does not use any
particular trequency tor more than a moment.1his reduces the amount ot LMI generated by
the motherboard.
1he BIOS usually otters tvo levels ot modulation0.S or 1.0.1hey denote the amount ot
modulation or jitter trom the baseline signal. 1he greater the modulation, the greater the reduc-
tion ot LMI. 1heretore, it you need to signiticantly reduce the tront side bus LMI, a modulation
ot 1.0 is recommended.
Hovever, system stability may be compromised it you are overclocking the tront side bus. Ot
course, this depends on the amount ot modulation, the extent ot overclocking, and other tactors
like temperature, and so torth. As such, the problem may not manitest itselt immediately.
1heretore, it is recommended that you disable this teature it you are overclocking the tront side
bus.1he risk ot crashing your system is not vorth the reduction in LMI. Ot course, it LMI
reduction is important to you, enable this teature by all means. Hovever, you should reduce the
Lnless you have LMI problems or sensitive data that must be sateguarded trom electronic eaves-
dropping, it is best to disable this teature to remove the possibility ot stability issues.
Iull Scroon Logo
1his BIOS teature determines vhether the motherboard or system manutacturer`s logo appears
instead ot the usual boot-up screen.
When it is enabled, the BIOS displays the tull-screen logo during the boot-up sequence.
When it is disabled, the BIOS dis plays the usual boot-up screen instead ot the tull-screen logo.
Please note that enabling this BIOS teature otten adds 23 seconds ot delay to the booting
sequence. 1his delay ensures that the logo is displayed tor a sutticient amount ot time.
1heretore, it is recommended that you disable this BIOS teature tor a taster boot-up time.
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Goto A20 Option
Connon Options: Normal, last
1his BIOS teature is used to determine the method by vhich Gate A20 is controlled.1he
Nornal option torces the chipset to use the slov keyboard controller to do the svitching.1he
Fast option, on the other hand, allovs the chipset to use its ovn 0x92 port tor taster svitching.
No candy tor guessing vhich is the recommended setting'
Please note this teature is only important tor operating systems that svitch a lot betveen real
mode and protected mode.1hese operating systems include 16-bit operating systems, such as
MS-DOS and 16-bit32-bit hybrid operating systems like Microsott Windovs 98.
1his teature has no ettect it the operating system only runs in real mode (no operating system
currently in use does that, as tar as I knov',, or it the operating system operates entirely in pro-
tected mode (tor example, Microsott Windovs XP,.1his is because it A20 mode svitching is
not required, then it does not matter at all it the svitching vas done by the slov keyboard con-
troller or the taster 0x92 port.
With all that said and done, the recommended setting tor this BIOS teature is still Fast, even
vith operating systems that don`t do much mode svitching.Although using the 0x92 port to
control Gate A20 has been knovn to cause spontaneous reboots in very rare instances, there is
really no reason vhy you should keep using the slov keyboard controller to turn A20 on or ott.
Grophic Win Sizo
Connon Options: 4, 8, 16, 32, 64, 128, 236
1his BIOS teature does tvo things. It selects the size ot the AGP aperture (hence, the name
Graphic Windovs Size,, and it determines the size ot the GAR1 (Graphics Address
Relocation 1able,.
0raphc Wn Szc 218
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size.1his is because the graphics card has more local memory to dedicate to texture storage. So,
it you upgrade to a graphics card vith more memory, you shouldn`t be deceived into thinking
that you need even more AGP memory' On the contrary, a smaller AGP memory space is
required.
size.
Grophic Window WR Conbin
Conbining, vrite combine butters. Somehov, they had to give it the badly mangled name ot
Graphic Windov WR Conbin.
It enabled, the vrite combine butters vill accumulate and combine partial or smaller graphics
It disabled, the vrite combine butters vill be disabled. All graphics vrites trom the processor
vill be vritten to the graphics card directly.
pertormance.
Lnabling this teature vith such graphics cards vill cause a host ot problems, such as graphics
artitacts, system crashes, and even the inability to boot up properly.
Grophics Aporturo Sizo
Connon Options: 4, 8, 16, 32, 64, 128, 236
1his BIOS teature does tvo things: It selects the size ot the AGP aperture, and it determines the
memory address space, vhereas the GAP1 is a translation table that translates AGP memory
G
size.1his is because the graphics card vill have more local memory to dedicate to texture stor-
age. So, it you upgrade to a graphics card vith more memory, you shouldn`t be deceived into
thinking that you vill need even more AGP memory' On the contrary, a smaller AGP memory
space vill be required.
actually need extra memory tor texture storage. It vill also keep the GAP1 (Graphics Address
Pelocation 1able, vithin a reas onable size.
0raphcs ApcrIurc Szc 216
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Hordworo Rosot Protoct
1his BIOS teature is very usetul tor tile servers and routers that need to be running 24 hours a
day, 363 days a year. When it is enabled, the hardvare reset button is disabled.1his prevents
the possibility ot any accidental resets.When disabled, the reset button tunctions as normal.
It you are running a mission-critical server or have kids vho just love to press little red buttons,
it is highly recommended that you enable this teature. Othervise, it is really up to your preter-
ence. Naturally, people using buggy operating s ystems or applications are advised to keep this
teature disabled tor more convenient reboots.
HDD S.M.A.R.l. Copobility
1his BIOS teature controls support tor the hard disk`s S.M.A.R.1. (Self Monitoring
Analysis And Reporting 1echnology, capability.
S.M.A.P.1. is supported by all current hard disks and it allovs the early prediction and varning
ot impending hard disk disasters.You should enable it it you vant to use S.M.A.P.1.-avare
utilities to monitor the hard disk`s condition. Lnabling it also allovs the monitoring ot the hard
disk`s condition over a netvork.
Hovever, there is a possibility that enabling S.M.A.P.1. may cause spontaneous reboots vith
netvorked computers. )ohnathan P. Dinan reported such an issue. Apparently, S.M.A.P.1.
continuous ly sends packets ot data through the netvork even vhen there is nothing receiving
thos e data packets. 1his may cause the computer to spontaneously reboot. 1heretore, it you
experience spontaneous reboots or crashes vith a netvorked computer, try disabling this
teature.
While S.M.A.P.1. looks like a really great satety teature, it isn`t really that usetul or even neces-
sary tor most users. lor S.M.A.P.1. to vork, it is not just a matter ot enabling it in the BIOS.
You must also keep a S.M.A.P.1.-avare hardvare monitoring utility running in the back-
ground all the time. 1his means using up some memory and processor time just to monitor
S.M.A.P.1. data trom the hard disk.
1hat`s quite alright it the hard disk you are us ing has a spotty reputation and you need advanced
varning ot any impending tailure. Hovever, hard disks these days are mostly reliable enough to
make S.M.A.P.1. redundant. Lnless you are running mission-critical applications, it is very
unlikely that S.M.A.P.1. is ot any use at all.
Lven then, you must not be misled into thinking that S.M.A.P.1. is a toolproot vay to get early
varning ot impending hard disk tailure. S.M.A.P.1. can only detect certain conditions that can
lead to hard disk tailures. Lven vith S.M.A.P.1. enabled, a hard disk can still tail vithout prior
varning.
With that said, S.M.A.P.1. is still usetul in providing a modicum ot data loss prevention by con-
tinuously monitoring hard disks tor signs ot impending tailure. It you have critical or irreplace-
able data, you should enable this BIOS teature and use a S.M.A.P.1.-avare hardvare
monitoring sottvare. ust don`t rely completely on it' Back up your data on a CD or DVD'
Please note that even it you do not use any S.M.A.P.1.-avare utility, enabling S.M.A.P.1. in
the BIOS uses up some bandvidth because the hard disk continuously sends out data packets.
So, it you do not use S.M.A.P.1.-avare utilities, or it you do not need that level ot real-time
reporting, disable HDD S.M.A.P.1. Capability tor better overall pertormance.
Some ot the never BIOSes nov come vith S.M.A.P.1. monitoring support built-in.When
you enable HDD S.M.A.P.1. Capability, these nev BIOSes automatically check the hard disk`s
S.M.A.P.1. status at boot-up. Hovever, such a teature has very limited utility because it can
only tell you the status ot the hard disk at boot-up.
It cannot keep track ot the hard disk`s condition during operation and, theretore, it is tar less
usetul than a proper S.M.A.P.1.-avare monitoring utility. In addition, there have been reports
ot talse alarms raised by such built-in sottvare.1heretore, it is still advisable tor you to disable
HDD S.M.A.P.1. Capability unless you use a proper S.M.A.P.1.-avare monitoring utility.
Host Bus In-Ordor Quouo Dopth
lor greater pertormance at high clock speeds, motherboard chips ets nov teature a pipelined
processor bus. 1he multiple stages in this pipeline can also be used to queue up multiple com-
mands to the processor.1his command queuing greatly improves pertormance because it ettec-
tively masks the latency ot the processor bus. In optimal situations, the amount ot latency
betveen each succeeding command can be reduced to only a single clock cycle'
4,, (1 and 8,, or (1 and 12,. 1his is because this BIOS teature does not actually allov you to
select the number ot commands that can be queued.
It merely allovs you to disable or enable the command queuing capability ot the processor bus
pipeline.1his is becaus e the number ot commands that can be queued depends entirely on the
number ot stages in the pipeline. As such, you can expect to see this teature associated vith
options like Lnabled and Disabled in some motherboards.
ing any outstanding commands. It selected, each command is only issued atter the processor has
vith 12 stages.
As you can see, this reduces pertormance as the processor has to vait tor each command to til-
ter dovn the pipeline.1he severity ot the ettect depends greatly on the depth ot the pipeline.
1he deeper the pipeline, the greater the ettect.
It the second queue depth option is 4, this means that the processor bus pipeline has 4 stages in
it. Selecting this option allovs the queuing ot up to 4 commands in the pipeline. Lach com-
mand can then be processed successively vith a latency ot only 1 clock cycle.
hosI 8us In-0rdcr 0ucuc 0cpIh 217
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H
It the second queue depth option is 12, this means that the processor bus pipeline has 12 stages
in it. Selecting this option allovs the queuing ot up to 12 commands in the pipeline. Lach com-
Please note that the latency ot only 1 clock cycle is only possible it the pipeline is compi etei
tilled up. It the pipeline is only partially tilled up, then the latency attecting one or more ot the
commands is more than 1 clock cycle. Still, the average latency tor each command is much
lover than it vould be vith command queuing disabled.
abling command queuing.1his may reduce pertormance, but it makes the processor more sta-
ble and may allov it to be turther overclocked.
Please note that the pertormance deticit associated vith deeper pipelines (8 or 12 stages, may
not be vorth the increase in processor overclockability. 1his is because the deep proces sor bus
pipelines have very long latencies. It they are not masked by command queuing, the processor
may be stalled so badly that you end up vith poorer pertormance even it you are able to turther
overclock the processor. So, it is recommended that you enable command queuing tor deep
pipelines, even it it means reduced overclockability.
Hypor-lhrooding lochnology
1he Intel Hyper-1hreading 1echnology is an extension to the IA-32 architecture, vhich
allovs a single processor to execute tuo or more separate threads concurrently. When hyper-
threading is enabled, multi-threaded sottvare applications can execute their threads in parallel,
thereby improving the processor`s pertormance.
1he current implementation involves tuo logical processors sharing the processor`s execution
engine and its bus intertace. Lach logical processor, hovever, comes vith its ovn APIC. 1he
other teatures ot the processor are either shared or duplicated in each logical proces sor.
Here is a list ot the teatures duplicated in each logical processor:
General registers (LAX, LBX, LCX, LDX, LSI, LDI, LSP, and LBP,
Segment registers (CS, DS, SS, LS, lS, and GS,
LlIAGS and LIP registers
x87 lPL regis ters (S10 to S17, status vord, control vord, tag vord, data operand
pointer, and instruction pointer,
MMX registers (MM0 to MM7,
XMM registers (XMM0 to XMM7,
hypcr-Jhrcadng Jcchno|ogy 210
H
MXCSP register
Control registers (CP0, CP2, CP3, CP4,
System table pointer registers (GD1P, ID1P, ID1P, task register,
Debug registers (DP0, DP1, DP2, DP3, DP6, DP7,
Debug control MSP (IA32_DLBLGC1I,
Machine check global status MSP (IA32_MCG_S1A1LS,
Machine check capability MSP (IA32_MCG_CAP,
1hermal clock modulation and ACPI pover management control MSPs
1ime stamp counter MSPs
Most ot the other MSP registers including Page Attribute 1able (PA1,
Iocal APIC registers
Here are the teatures shared by the tvo logical processors:
A32_MISC_LNABIL MSP
Memory type range registers (M1PPs,
1he tolloving are teatures that can be duplicated or shared according to requirements:
Machine check architecture (MCA, MSPs
Pertormance monitoring control and counter MSPs
only those 3.06GHz and taster, and the Intel Xeon processors. Note that tor Hyper-1hreading
to vork, you should have the tolloving:
Intel processor that supports Hyper-1hreading
Motherboard vith a chipset and BIOS that support Hyper-1hreading
Operating system that supports Hyper-1hreading (Microsott Windovs XP or
Iinux 2.4.x,
It is highly recommended that you enable Hyper-1hreading 1echnology tor improved proces-
sor pertormance.
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IDL Bus Mostor Support
DMA transter modes allov IDL devices to transter large amounts ot data trom the hard disk to
the system memory and vice versa vith minimal processor intervention. It ditters trom the older
and processor-intensive PIO (Progranned Input/Output) transter modes by ottloading the
task ot data transter trom the processor to the chipset.
Previously, this teature vas only available atter an operating system supporting DMA transters
(through the appropriate device driver, vas loaded. Nov, hovever, many BIOS come vith a
built-in 16-bit driver that allovs DMA transters.1his allovs the onboard IDL controller to per-
torm DMA transters even betore the operating system is loaded'
When this BIOS teature is disabled, the BIOS vill not load up the 16-bit busmastering driver
tor the onboard IDL controller. 1he IDL controller then transters data through PIO.
1heretore, it is recommended that you enable IDL Bus Mas ter Support.1his greatly improves
the IDL transter rate and reduces CPL utilization during the booting process or vhen you are
using real-mode DOS. Lsers ot DOS-based dis k utilities, such as Norton Ghost, can expect to
benetit a lot trom this teature.
Please note that because current operating systems (tor example,Windovs XP, load up their
ovn 32-bit busmastering driver, this teature has no ettect vhen such an operating system loads
up. Still, it is recommended that you enable this teature to improve pertormance prior to the
loading ot the operating system`s ovn driver.
IDL HDD Block Modo
When you enable this teature, the BIOS automatically detects vhether your hard disk supports
block transters and sets the proper block transter settings tor it. Depending on the IDL con-
troller, up to 64KB ot data can be transterred per interrupt vhen block transters are enabled.
Because all current hard disks support block transters, there is usuaii no reason vhy IDL HDD
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InI 0sp|ay FrsI 221
Hovever, it you are running on Windovs N1 4.0, you might need to disable this BIOS teature
because Windovs N1 4.0 has a problem vith block transters. According to Chris Bope,
Windovs N1 does not support IDL HDD Block Mode and enabling this teature can cause data
to be corrupted.
According to a Microsott article (Lnhanced IDL operation under Windovs N1 4.0,, IDL HDD
Block Mode and 32-bit Disk Acces s have been tound to cause data corruption in some cases.
1heretore, Microsott recommends that Windovs N1 4.0 users disable IDL HDD Block Mode.
Pack 2.1heretore, it is sate to enable IDL HDD Block Mode in a Windovs N1 4.0 system, so
long as it has been upgraded vith Service Pack 2.
Please note that it you disable IDL HDD Block Mode, only S12 bytes ot data can transter per
ot data corruption (vith an unpatched version ot Windovs N1 4.0,. Othervise, it is highly rec-
ommended that you enable this BIOS teature tor signiticantly better hard disk pertormance'
Init Disploy Iirst
Although the AGP bus vas designed exclusively tor the graphics subsystem, some users still have
to use PCI graphics cards tor multi-monitor support. 1his is because there can be only one AGP
port' So, it you vant to use multiple monitors, you must either get an AGP card that provides
multi-monitor support or use PCI graphics cards.
lor those vho upgraded trom a PCI graphics card to an AGP card, it is certainly enticing to use
the old PCI graphics card to support a second monitor. 1he PCI card does the job just tine
because it merely sends display data to the second monitor.You don`t need a povertul graphics
card to run the second monitor because Microsott Windovs 2000XP does not support 3D
graphics acceleration on the second monitor.
When it comes to a case ot an AGP graphics card vorking in tandem vith a PCI graphics card,
the BIOS has to determine vhich graphics card is the primary graphics card. Naturally, the
detault vould be the AGP graphics card because, in most cases, it is the taster card.
Hovever, a BIOS svitch that allovs you to manually select the graphics card vith vhich to
boot the system is still required.1his is particularly important it you have AGP and PCI graphics
cards but only one monitor.1his is vhere the Init Display First teature comes in. It allovs
you to select vhether to boot the system using the AGP graphics card or the PCI graphics card.
example, it you only use an AGP graphics card, then setting Init Display lirst to AGP may
speed up your system`s booting-up process .
1heretore, it you are only using a single graphics card, it is recommended that you set the Init
Display lirst teature to the proper setting tor your system (AGP tor a single AGP card and PCI
tor a single PCI card,.
Hovever, it you are using multiple graphics cards, it is up to you vhich card you vant to use
as your primary display card. It is recommended that you select the tastest graphics card as the
primary display card.
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In-Ordor Quouo Dopth
processor bus. 1he multiple stages in this pipeline can also be used to queue up multiple com-
4,, (1 and 8,, or (1 and 12,. 1his is because this BIOS teature does not actually allov you to
select the number ot commands that can be queued.
vith 12 stages.
mand then can be processed successively vith a latency ot only 1 clock cycle.
Interestingly, this teature can also be used as an aid in overclocking the processor.Although the
unstable at overclocked speeds. 1o overclock beyond vhat`s normally possible, you can try
disabling command queuing. 1his may reduce pertormance, but it makes the processor more
stable and may allov it to be turther overclocked.
InIcrrupI Modc 228
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Intorrupt Modo
Connon Options: PIC, APIC
Progrannable Interrupt Controller,.1he APIC is a nev distributed set ot devices that
make up an interrupt controller. In current implementations , it consists ot three partsa local
APIC, an IO APIC, and an APIC bus.
1he local APIC delivers interrupts to a specitic processor, so each processor in a system has to
have its ovn local APIC.1heretore, a dual processor system must have tvo local APICs. Because
a local APIC has been integrated into every proces sor since the debut ot the original Intel
Pentium P34C processor, there`s no need to vorry about the number ot local APICs.
1he IO APIC is the replacement tor the old chained 82S9 PIC (Progrannable Interrupt
Controller, still in use in many motherboards. It collects interrupt signals trom IO devices and
sends messages to the local APICs through the APIC bus that connects it to the local APICs.
1here can be up to eight IO APICs in a system, each supporting anyvhere trom 24 (usually,
to 64 interrupt lines. As you can see, this allovs a lot more IPQs than is currently possible vith
the 8239 PIC. Note that vithout at least one IO APIC, the local APIC is useless and the sys-
tem tunctions as it it`s based on the 8239 PIC.
1o sum it all up, APIC provides multiprocessor support, more IPQs, and taster interrupt han-
dling, all ot vhich are not possible vith the old 8239 PIC. Although they can be used in single-
processor boards, you are more likely to tind them in multi-processor motherboards. 1his is
because APIC is only s upported in Windovs N1, 2000, and XP. It is not supported in operating
systems that are required to support MS-DOS device drivers, such as Windovs 9398. Hovever,
as users transition to Windovs XP, you can expect more manutacturers to ship single-process or
boards vith IO APICs.
It your single-processor motherboard supports APIC and you are using a Win32 operating sys-
tem (Windovs N1, 2000, and XP,, it is recommended that you select APIC to allov taster and
better IPQ handling. It you are using a multiprocessor motherboard, you must select APIC
because it is required tor IPQ handling in multiprocessor systems.
Hovever, it you are running Windovs 9398 or a DOS-based operating system on a single-
processor motherboard, you must select PIC instead.1his is because MS-DOS drivers assume
they can vrite directly to the 8239 PIC (APIC did not exist yet in those days', and its associated
ID1 (Interrupt Descriptor 1able) entries. Selecting PIC torces the APIC to revert to the
legacy 8239 PIC mode.
IOQD
processor bus. 1he multiple stages in this pipeline also can be used to queue up multiple com-
(1 and 4,, (1 and 8,, or (1 and 12,.1his is because this BIOS teature does not actually allov you
to select the number ot commands that can be queued.
vith 12 stages.
It the second queue depth option is 4, this means the processor bus pipeline has 4 stages in it.
Selecting this option allovs the queuing ot up to 4 commands in the pipeline. Lach command
then can be processed successively vith a latency ot only 1 clock cycle.
option ot 4812 or, in some cases, Lnabled. 1his allovs the processor bus pipeline to mask its
latency by queuing outstanding commands.You can expect a signiticant boost in pertormance
vith this teature enabled.
unstable at overclocked speeds. 1o overclock beyond vhat`s normally possible, you can try
disabling command queuing. 1his may reduce pertormance but it makes the processor more
stable and may allov it to be turther overclocked.
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ISA Lnah|c 8I 226
ISA 14.318MHz Clock
1he ISA bus (also knovn as the A1 bus, vas originally an 8-bit bus running at just 4.77MHz.
It vas then expanded to include a 16-bit bus running initially at 6MHz and later at 8MHz.
Lventually, the ISA bus vas standardized to run at a maximum speed ot 8.33MHz.
Because each ISA data transter takes anyvhere trom tvo to eight clock cycles to complete, this
yields a maximum bandvidth ot only 4.77MB/s tor 8-bit cards and 8.33MB/s tor 16-bit
cards.
Maximum bandvidth tor the 8-bit ISA bus = 8.33MHz 1 byte (8|its, 2 clock cycles per
transter = 4.77MBs
Maximum bandvidth tor the 16-bit ISA bus = 8.33MHz 2 bytes (1|its, 2 clock cycles
per transter = 8.33MBs
1his BIOS teature allovs you to overclock the ISA bus using the reterence clock generator
speed ot 14.318MHz. 1his greatly improves the ISA bus speed by running the bus 72 taster
than normal.At this clock speed, 8-bit cards have a bandvidth ot 7.16MB/s vhile 16-bit cards
have a bandvidth ot 14.32MB/s.
In most cases, it is recommended that you enable this teature to give the ISA bus a pertorm-
ance boost. Ot course, this is only usetul it you have ISA devices in your system. Othervise, this
teature is redundant.
Please note that vhile never ISA cards are capable ot running at this out-ot-specspeed, older
ones may not vork properly at this speed. 1heretore, it your ISA card tails to tunction properly,
disable this teature.
ISA Lnoblo Bit
1his is similar to the AGP ISA Aliasing BIOS teature.
1he origin ot this teature can be traced back all the vay to the original IBM PC. When the
IBM PC vas designed, it only had 10 address lines (10-bits, tor IO space allocation.
1heretore, the IO space back in those days vas only 1KB or 1024 bytes in size. Out ot those
1024 available addresses, the tirst 2S6 addresses vere reserved exclusively tor the motherboard`s
use, leaving the last 768 addresses tor use by add-in devices. 1his vould become a critical
tactor later on.
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I
Iater, motherboards began to utilize 1 address lines tor IO space allocation.1his vas supposed
to create a contiguous IO space ot 64KB in size. Lntortunately, many ISA devices by then
vere only capable ot doing 10-bit decodes. 1his vas because they vere designed tor computers
based on the original IBM design, vhich only supported 10 address lines.
1o circumvent this problem, they tragmented the 64KB IO space into 1KB chunks.
Lntortunately, because the tirst 236 addresses must be reserved exclusively tor the motherboard,
this means that only the tirst (or lover, 236 bytes ot each 1KB chunk vould be decoded in tull
16-bits. All 10-bits-decoding ISA devices are, theretore, restricted to the last (or top, 768 bytes
ot the 1KB chunk ot IO space.
As a result, such ISA devices only have 768 IO locations to use. Because there vere so many
ISA devices back then, this limitation created a lot ot compatibility problems because the
chances ot tvo ISA cards using the same IO space vere high.When that happened, one or
both ot the cards vould not vork. Although they tried to reduce the chance ot such contlicts
by standardizing the IO locations used by ditterent classes ot ISA devices, it still vas not good
enough.
Lventually, they came up vith a vorkaround. Instead ot giving each ISA device all the IO
space it vanted in the 10-bit range, they gave each ISA device a smaller number ot IO loca-
tions and made up tor the ditterence by borroving them trom the 16-bit IO space' Here`s
hov they do it.
1he ISA device vould tirst take up a small number ot IO locations in the 10-bit range. It then
extends its IO space by using 16-bit aliases ot the tev 10-bit IO locations taken up earlier.
Because each IO location in the 10-bit decode area has sity-three 16-bit aliases, the total
number ot IO locations expands trom just 768 locations to a maximum ot 49,132 locations'
More importantly, each ISA card nov requires very tev IO locations in the 10-bit range.1his
drastically reduced the chances ot tvo ISA cards contlicting each other in the limited 10-bit
IO space. 1his vorkaround naturally became knovn as ISA Aliasing.
Nov, that`s all vell and good tor ISA devices. Lntortunately, the 10-bit limitation ot ISA
devices becomes a liability to devices that require 16-bit addressing. AGP and PCI devices come
to mind.As noted earlier, only the tirst 236 addresses ot the 1KB chunks support 16-bit address-
ing. What that really means is all 16-bit addressing devices are thus limited to only 236 bytes ot
contiuous IO space'
When a 16-bit addressing device requires a larger contiuous IO space, it has to encroach on the
10-bit ISA IO space. lor example, it an AGP card requires 8KB ot contiguous IO space, it
takes up eiht ot the 1KB IO chunks (vhich are made up ot eight 16-bit areas and eight 10-bit
areas',. Because ISA devices are using ISA Aliasing to extend their IO space, there is nov a
high chance ot IO space contlicts betveen ISA devices and the AGP card.When that happens,
the attected cards vill most likely tail to vork.
1here are tvo vays out ot this mess. Obviously, you can limit the AGP card to a maximum ot
236 bytes ot contiguous IO space. Ot course, this is not an acceptable solution.
1he second, and the preterred method, is to throv avay the restriction and provide the AGP
card vith all the contiguous IO space it vants.
Here is vhere the ISA Lnable Bit BIOS teature comes in.1he detault setting ot Lnabled
torces the system controller to alias ISA addresses using address bits [13:10|the last 6-bits.
Only the tirst 10-bits (address bits 0 to 9, are used tor decoding. 1his restricts all 16-bit address-
ing devices to a maximum contiguous IO space ot 236 bytes.
tull 64KB IO space.
It is recommended that you disable ISA Lnable Bit tor optimal AGP (and PCI, pertormance. It
also prevents your AGP or PCI cards trom contlicting vith your ISA cards . Lnable it only it
you have ISA devices that are contlicting vith each other.
ISA Lnah|c 8I 227
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R
R1 CLR_ClL Soloct
Connon Options: Detault, Optimal
As the name suggests, this is an AMD-specitic BIOS teature. It controls the Clock Control
(CLK_C1L, Model Specific Register (MSR,, vhich is part ot the AMD Athlon`s pover
management control system.
lirst ot all, ve should be avare that the AMD Athlon tamily ot processors has tour ditterent
pover management states:
Working State (C0,
Halt State (C1,
Stop Grant States (C2 and S1,
Probe State
1he Athlon processor can svitch to its pover-saving mode vhen it is in the Halt state or one
ot the Stop Grant states. In those pover management states, the processor sends a HI1 or S1P-
CIK4 special bus cycle to the north bridge, vhich disconnects the Athlon system bus. 1he
processor then enters into its pover-saving mode.
Nov, unlike the Intel Pentium 4 processor, the Athlon processor saves pover by actually reduc-
ing its internai clock speed. 1he Athlon bus clock speed remains constant, but by using an inter-
nal clock divider, the Athlon processor can reduce its internal clock speed to 1/64th (Palomino
cores and older, or 1/8th (1horoughbred cores and never, ot its nominal clock speed.1hat
means a 2.0GHz Athlon processor vith a Palomino or older core has an internal clock speed ot
only 31.2SMHz in pover-saving mode' Hovever, it the same processor has a 1horoughbred
core, the internal clock speed in pover-saving mode is 2S0MHz.
As you can see, the older Athlon cores run at a much lover internal speed compared to the
never cores.1his translates into a much lover pover consumption in pover-saving modes. lor
example, Athlon processors vith Palomino cores use only 0.86W ot pover in pover-saving
mode. In contrast, the never Athlon 1horoughbred-B processors in pover-saving mode con-
sume about 8.9W ot pover. Hovever, the extremely lov internal clock speed in the older
Athlon cores meant that these cores take a much longer time to ramp up to tull clock speed
vhen it vakes up trom its pover-saving mode.1his can sometimes cause problems.
1he older Athlons have a bug (Lrrata No. 11, called ILL :ershoot on 1akep from Disconnect
Causes utoCompensation Circuit to Iaii . What happens is the processor can sometimes overshoot
the nominal clock speed vhen it ramps up atter a pover-saving sess ion.1his causes a reduction
in the Athlon bus IO drive strength levels, vhich the auto-compensation circuitry attempts to
correct. Hovever, because there is not enough time, the proper drive strengths cannot be
attained betore the processor reconnects to the system bus. 1his causes the system bus to tail,
vhich results in a system hang.
K
1his bug is particularly prominent in the older Athlons that use the 164 internal divider
because they normally require a longer ramp-up time, vhich increases the chance tor the
processor to overshoot the nominal clock speed. Hence, a vorkaround tor this bug vas devised
vhereupon the BIOS manually reprograms the CIK_C1I register to reouce the ramp-up time.
With a reduced ramp-up time, there is very little chance ot the processor overshooting and
causing a tailure ot the system bus.
By detault, the BIOS programs the CIK_C1I register vith a value ot 6003_1223h during the
POS1 routine.1o increase the ramp-up speed, the BIOS has to change the value to
2003_1223h.
1his is vhere the K7 CLK_C1L Select BIOS teature comes in.When set to Default, the
BIOS programs the CIK_C1I register vith a value ot 6003_1223h. Setting to Optinal causes
the BIOS to program the CIK_C1I register vith a value ot 2003_1223h.
It you are using an AMD Athlon processor vith a Iaiomino or oioer core, it is recommended that
you set K7 CLK_C1L Select to Optinal.1his prevents Lrrata No. 11 trom manitesting itselt
and may even provide a speed boost by alloving the processor to disconnect and connect to the
system bus taster.
lrom the 1horoughbred-A core (CPLID 680, onvard, AMD started using an internal clock
divider ot only 1/8 vith the CIK_C1I value ot 6003_1223h.While this means that the never
cores consume more pover during pover-saving states, the 18 divider allovs a much taster
ramp-up time.1his neatly circumvents the Lrrata No. 11 problem, although AMD also correct-
ed that bug.With such processors, the CIK_C1I should be set to the Default value ot
6003_1223h.
Lntortunately, AMD then did an about-tace vith the 1horoughbred-B core (CPLID 681, and
changed the value associated vith the 1/8 divider trom 6003_1223h to 2003_1223h. Lnless the
BIOS vas updated to recognize this ditterence, it probably vould vrite the 6003_1223h value
used tor the 1horoughbred-A core into the register instead ot the correct 2003_1223h required
by the 1horoughbred-B core.When this happens, the processor may become unstable during
transitions trom sleep mode to active mode.
1heretore, tor 1horoughbred-B cores and above, you should set the K7 CLK_C1L Select
BIOS teature to Optinal setting to ensure proper setting ot the internal clock divider.
RBC Input Clock Soloct
Connon Options: 8MHz, 12MHz, 16MHz
1he PS2 keyboard communicates vith the keyboard controller on the motherboard through a
serial data link.1he speed ot the data link depends on the clock signal generated by the key-
board controller.1he higher the clock speed, the taster the keyboard intertace.1his translates
into a more responsive keyboard, although not all keyboards can vork vith higher clock speeds.
1his BIOS teature allovs you to adjust the keyboard intertace clock tor a better response or to
tix a keyboard problem. It is recommended that you select the 16MHz option tor a better key-
board response. Hovever, it the keyboard pertorms erratically or tails to initialize, try a lover
clock speed.
k8L InpuI L|ock Sc|ccI 220
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Royboord Auto-Ropoot Doloy
Connon Options: 14 Sec, 12 Sec, 34 Sec, 1 Sec
1his BIOS teature determines hov long, in tractions ot a second, the keyboard controller vaits
betore it starts repeating the keystroke that you have pressed continuously.1he longer the delay,
the longer the keyboard controller vaits betore it starts repeating the keys troke.
Royboord Auto-Ropoot Roto
Connon Options: 6Sec, 8Sec, 10Sec, 12Sec, 20Sec, 24Sec, 30Sec
1his BIOS teature determines the rate at vhich the keyboard repeats a keystroke it you press it
continuously.
1he available settings are in characters per second.1heretore, a typematic rate ot 30/Sec causes
the keyboard to repeat the keystroke at a rate ot 30 characters per second it you press a particu-
lar key continuously.1he higher the typematic rate, the taster the keyboard repeats the key-
stroke.
1he choice ot vhat setting to use is entirely up to your personal preterence. Please note that
through the BIOS, like MS-DOS. 1he typematic rate in operating systems like Windovs XP is
controlled by the keyboard driver`s settings .
K
L3 Lachc 281
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L
L3 Cocho
In addition to the Ievel 1 and Ievel 2 caches, some processors come vith an additional cache
called Level 3 cache or L3 cache.
1his Ievel 3 cache is designed to handle data requests that the Ievel 1 and Ievel 2 caches tail to
satisty. Although slover than the Ievel 2 cache, the Ievel 3 cache compensates by being much
larger in size.While the largest Ievel 2 cache at this time is only 312KB, Ievel 3 caches can be
as large as 4MB'
more data than the Ievel 2 cache.1his gives it a high probability ot satistying cache misses trom
the Ievel 2 cache.With three caches vorking together, the chance ot the processor stalling due
to the need to access the much slover PAM is very small.
1his is vhere the L3 Cache BIOS teature comes in. It controls the tunctionality ot the proces-
sor`s Ievel 3 cache.
Currently, this is an Intel Xeon MP-specitic BIOS teature. 1he Intel Xeon MP processor tea-
tures an on-die Ievel 3 cache that can be 312KB, 1MB, or 2MB in size. It is an 8-vay set asso-
ciative sectored cache vith 64-byte cache lines.
processor.
is a :er |ao idea. It the Ievel 3 cache is disabled, the processor may stall trequently, especially
vhen the system is running memory-intensive applications.
Lovol 2 Cocho Lotoncy
Connon Options: Auto, 1 to 13
Whenever the processor`s Level 2 cache receives a readvrite command, a certain period ot
time passes betore the cache can actually process the command.1his delay is called latency and
the shorter the latency, the taster the Ievel 2 cache can service data readsvrites.
1his BIOS teature enables you to change the latency ot the processor`s Ievel 2 cache. By
detault, this teature is set to Auto, vhich means that the processor`s Ievel 2 cache is lett to its
detault latency setting. 1his is the satest option.
You can als o manually s elect the latency ot the cache. lor this purpose, this BIOS teature pro-
vides options ranging trom 1 clock cycle to 1S clock cycles . Please note that setting the latency
too lov can cause the Ievel 2 cache to lose data integrity or tail altogether. 1his vill manitest as
a system crash or an inability to boot-up altogether.
1heretore, it is recommended that you start vith a high latency and vork your vay dovn until
you start to encounter stability issues.1his allovs you to tigure out the lovest latency your
processor`s Ievel 2 cache can support. Select that latency tor optimal pertormance vithout sta-
bility issues.
Please note that this is a processor-dependent teature. Not all processors support BIOS manipu-
lation ot the Ievel 2 cache latency. It the processor does not allov any manipulation ot its Ievel
2 cache latency, this BIOS teature vill not have any ettect, irrespective ot vhat vas selected.
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PIO Data
1ransfer Mode Mainun 1hroughput
PIO Mode 0 3.3 MBs
PIO Mode 1 3.2 MBs
PIO Mode 2 8.3 MBs
PIO Mode 3 11.1 MBs
PIO Mode 4 16.6 MBs
M
Mostor Drivo PIO Modo
1his BIOS teature is usually tound under the Onboard IDL-1 Controller or Onboard
IDL-2 Controller teature. It is linked to one ot the IDL channels, so it you disable one, the
corresponding Master Drive PIO Mode option tor that IDL channel either disappears or
becomes grayed out.
Master IDL drive attached to that particular IDL channel. Here is a table ot the ditterent PIO
transter rates and their corresponding maximum throughputs.
MasIcr 0rvc PI0 Modc 288
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tor.
vith the current PIO mode (tor example, vhen the PCI bus is overclocked,
DMA
1ransfer Mode Mainun 1hroughput
DMA Mode 0 4.16 MBs
DMA Mode 1 13.3 MBs
DMA Mode 2 16.6 MBs
LltraDMA 33 33.3 MBs
LltraDMA100 100.0 MBs
Mostor Drivo UltroDMA
corresponding Master Drive LltraDMA tunction tor that IDL channel either disappears or is
grayed out.
available, tor the Master IDL device attached to that particular IDL channel. lor easy reterence,
here is a table ot the ditterent DMA transter rates and their corresponding maximum through-
puts.
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drive.
Normally, you should leave it as Auto and let the BIOS auto-detect the drive`s DMA support. It
the drive supports DMA transters, the proper DMA transter mode is enabled tor that drive,
mode supported,.
MasIcr ProrIy oIaIon 286
In Windovs 9x, this can be accomplished by ticking the DMA checkbo in the properties
sheet ot the IDL drive in question. In Windovs 2000XP, you have to set the transter mode ot
the IDL device to DMA If Available in the Advanced Settings tab ot the associated IDL chan-
nel`s properties page.
Mostor Priority Rototion
Connon Options: 1 PCI, 2 PCI, 3 PCI
1his BIOS teature controls the priority ot the processor`s accesses to the PCI bus.
It you choose 1 PCI, the processor is alvays granted access right atter the current PCI bus
master completes its transaction, irres pective ot hov many other PCI bus masters are on the
queue.1his improves processor-to-PCI pertormance, at the expense ot other PCI transactions.
It you choose 2 PCI, the processor is alvays granted access right atter the second PCI bus
master on the queue completes its transaction. 1his means the processor has to vait tor just tvo
PCI bus masters to complete their transactions on the PCI bus betore it can gain access to the
PCI bus itselt. 1his means slightly poorer processor-to-PCI pertormance but PCI bus masters
enjoy slightly better pertormance.
It you choose 3 PCI, the processor is alvays granted access right atter the third PCI bus master
on the queue completes its transaction.1his means the processor has to vait tor three PCI bus
masters to complete their transactions on the PCI bus betore it can gain access to the PCI bus
itselt.1his means poorer processor-to-PCI pertormance, but PCI bus masters enjoy better per-
tormance.
No matter vhat you choose, the processor is guaranteed access to the PCI bus atter a certain
number ot PCI bus master grants. It doesn`t matter it there are numerous PCI bus masters on
the queue or vhen the processor requests access to the PCI bus.1he processor is alvays granted
access atter one PCI bus master transaction (1 PCI,, tvo transactions (2 PCI,, or three transac-
tions (3 PCI,.
lor better overall pertormance, it is recommended that you select the 1 PCI option as this
allovs the processor to access the PCI bus vith minimal delay. Hovever, it you vish to improve
the pertormance ot your PCI devices, you can try the 2 PCI or 3 PCI options.1hey ensure
that your PCI cards receive greater PCI bus priority.
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MD Driving Strongth
Connon Options: Hi, Io High, Iov
1here is no auto-compensation mechanis m tor the memory bus. So, it is up to the motherboard
designer to determine the amount ot driving strength needed to compensate tor the mother-
board`s impedance on the memory bus. 1he BIOS then loads up the preset driving strength
value vhen it boots up the motherboard.
1he detault driving s trength is usually sutticient tor normal DPAM loads. It is kept lov in
order to reduce LMI (Llectronagnetic Interference, and pover consumption. Hovever, this
means that the detault driving strength may not be sutticient tor heavy DPAM loads (tor exam-
ple, multiple double-sided memory modules,.
1his is vhere the MD Driving Strength BIOS teature comes in. It otters simplitied control ot
the memory data bus driving strength.
1he detault value is Lo or Lov.With heavy DPAM loads, you might vant to set this teature
to Hi or High.
Due to the nature ot this BIOS teature, it is possible to use it as an aid in overclocking the
memory bus.Your memory module may not overclock as vell as you vant it to. By raising the
driving strength ot the memory bus, it is possible to improve its stability at overclocked speeds.
Hovever, this is not a suretire vay ot overclocking the memory bus. All you may get at the end
ot the day is increased LMI and pover consumption.
Please note too that increasing the memory bus drive strength does not improve the pertorm-
ance ot your memory subsystem.
1heretore, it is recommended that you leave the MD Driving Strength at its detault Lo or Lov
setting. Set it to Hi or High only it you have a heavy DPAM load or it you are trying to stabi-
lize an overclocked memory module.
Monory Holo At 1$M-1M
Certain ISA cards require exclusive access to the 1MB block ot memory, trom the 13th to the
16th megabyte, to vork properly. 1his BIOS teature allovs you to reserve that 1MB block ot
memory tor such cards to use.
It you enable this teature, 1MB ot memory (the 13th MB, is reserved exclusively tor the ISA
card`s use.1his ettectively reduces the total amount ot memory available to the operating system
by 1MB. 1heretore, it you have 236MB ot memory, the usable amount ot memory is reduced to
233MB.
Please note that in certain motherboards, enabling this teature may actually render all memory
above the 13th MB unavailable to the operating system' In such cases, you end up vith only
14MB ot usable memory, irrespective ot hov much memory your system actually has.
It you disable this teature, the 13th MB ot PAM is not reserved tor the ISA card`s use. 1he tull
range ot memory is theretore available tor the operating system to use. Hovever, it your ISA
card requires the use ot that memory area, it may tail to vork.
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MP Lapah|c 8I IdcnIfy 287
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(Continueo)
Because ISA cards are a thing ot the pas t, it is highly recommended that you disable this tea-
ture. Lven it you have an ISA card that you absolutely have to use, you may not actually need to
enable this teature.
Most ISA cards do not need exclusive access to this memory area. Make sure that your ISA card
requires this memory area betore enabling this teature.You should use this BIOS teature only in
a last-ditch attempt to get a stubborn ISA card to vork.
MP Copoblo Bit IdontiIy
1here are a tev tlavors ot the AMD Athlon processor, namely the Duron, Athlon XP, Athlon
MP, and the mobile Athlon XP (Athlon XP-M,. Hovever, they all have the same CPLID. So,
processor identitication has to be done on the basis ot clock speed and I2 cache size variations.
1his is not a problem tor the Duron and Athlon XP-M processors.
Lntortunately, there is nothing to distinguish the Athlon MP trom the Athlon XP. Neither clock
speed nor I2 cache size can be used to ditterentiate the tvo processors.
In addition, AMD don`t hardcode the processor name string into the AMD Athlon processors.
1he BIOS actually detects the processor model during the boot-up process and vrites the
appropriate name string into the processor. So, the Athlon MP cannot be detected by querying
the processor name string.
1he only thing that truly distinguishes the Athlon MP processor trom the Athlon XP processor
is its multi-processing capability.
1o solve this problem, AMD used bit 19 ot Athlon`s Lxtended leature llags to denote multi-
processing capability. It is also knovn as the MP Capable bit, MP tor multi-processing.
1his bit is set to 0 in the Athlon XP processors and set to 1 in the Athlon MP processors.
Belov is a table ot the MP Capable bit settings tor the ditterent AMD Athlon processors.
lhe MI Capa|i e Pit in 1arious MD Irocessors.
LHIBI1 A: 1able 3, Page 31, AMD Processor Pecognition Appl ication Note Pev. 3.07.
Processor CPUID MP Capable Platforn Reconnended
(bit 19 of Segnent Nane String
1
Ltended
Feature
Flags)
AMD Athlon Model 6 660 or 661 Peserved Mul tiprocessing AMD Athlon MP
AMD Athlon Model 6 660 or 661 Peserved Desktop AMD Athlon
AMD Athlon Model 660 or 661 Peserved Mobile mobile AMD Athl on 4
AMD Athlon Model 6 662 0 Mul tiprocessing AMD Athlon XP
[xxxxx|
2
AMD Athlon Model 6 662 1 Mul tiprocessing AMD Athlon MP
[xxxxx|
2
AMD Athlon Model 6 662 NA Desktop AMD Athlon XP
[xxxxx|
2
AMD Athlon Model 6 662 NA Mobile mobile AMD Athl on 4
Processor CPUID MP Capable Platforn Reconnended
(bit 19 of Segnent Nane String
1
Ltended
Feature
Flags)
AMD Duron Model 6 NA
3
NA Desktop AMD Duron
3
NA Mobile mobil e AMD Duron
3
Peserved Desktop AMD Duron
3
Peserved Mobile mobile AMD Duron
AMD Athlon Model 8 NA
3
0 Mul tiprocessing AMD Athlon XP
[xxxxx|
2
3
1 Mul tiprocessing AMD Athlon MP
[xxxxx|
2
3
0 Desktop AMD Athlon XP
[xxxxx|
2
3
1 Desktop AMD Athlon MP
[xxxxx|
2
3
NA Mobile mobile AMD Athlon
XP [xxxxx|
2
3
0 Desktop AMD Athlon XP
[xxxxx|
2
3
1 Mul tiprocessing AMD Athlon MP
[xxxxx|
2
3
NA OPGA Mobil e mobile AMD Athlon
XP-M [xxxxx|
2
3
NA PGA Mobile AMD
mobile Athlon XP-M (IV,
[xxxxx|
2
1. 1his name string must be programmed into the processor by the BIOS. See the document,
Displaying and Programming the Processor Name Str ing BIOS Application Note, order4 90036.
2. See 1able 7 on page 33 and 1able 3 on page 31 ot AMD Processor Pecognition Application Note,
Publication 420734, lebruary 2004 (Advanced Micro Devices, Inc.,, tor proper model number to
inser t into name string.
3. Pecommended name str ings tor the AMD Duron processors models 6 and 7 and the AMD Athlon
processors model s 8 and 10 do not vary by CPLID stepping value.
2004 o:anceo Micro De:ices, Inc. Peprinteo uith permission. MD, the MD ioo, MD
thi on, MD Duron, ano com|inations thereof are traoemarks of o:anceo Micro De:ices, Inc.
1heretore, it the BIOS detects a processor vith the MP Capable bit set to 1, it vrites the
processor name string ot AMD Athlon (tm, MP into the processor.
1his BIOS teature determines it the BIOS should query the MP Capable bit to correctly iden-
tity an AMD Athlon MP processor.
When set to Lnabled, the BIOS vill query the MP Capable bit at boot-up. It it detects a MP
Capable bit setting ot 1, it vrites the Athlon MP processor string name into the appropriate
registers.
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MPS cvson 280
When set to Disabled, the BIOS vill not query the MP Capable bit at boot-up.1he Athlon
MP processor vill be indistinguishable trom the Athlon XP processor, as tar as the processor
identitication is concerned.
It you are using an AMD Athlon MP processor, it is recommended that you enable this BIOS
teature to allov proper identitication ot the processor. It you are using other Athlon processors,
you should disable this BIOS teature as the BIOS does not need to query the MP Capable bit
to detect the processor correctly.
MPS Control Vorsion Ior OS
processors.
Please note that MPS version 1.4 is required tor a motherboard to support a secondary PCI bus
vithout the need tor a PCI bridge.
the secondary PCI bus on a motherboard that doesn`t come vith a PCI bridge.1his is because
only MPS 1.4 supports a bridgeless secondary PCI bus.
MPS 1.1.
As tar as Microsott operating systems are concerned, Windovs N12000XP support
MPS 1.4.
ble problem vith the MPS version set to 1.4. If you set the MPS version to 1.4 in the ABI1
problem, set the MPS Version Control lor OS to 1.1.
MPS Rovision
processors.
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Please note that MPS version 1.4 is required tor a motherboard to support a secondary PCI bus
vithout the need tor a PCI bridge.
the secondary PCI bus on a motherboard that doesn`t come vith a PCI bridge.1his is because
only MPS 1.4 supports a bridgeless secondary PCI bus.
MPS 1.1.
MPS 1.4.
problem, set the MPS Pevision to 1.1.
Multi-Soctor lronsIors
Connon Options: Disabled, 2 Sectors, 4 Sectors, 8 Sectors, 16 Sectors, 32 Sectors, Maximum
1here are a tev available options, trom Disabled to Mainun and a tev ditterent multiple
sectors options.
1he Disabled option torces your IDL controller to transter only a single sector (312 bytes, per
1he selection ot 2 Sectors to 32 Sectors allovs you to manually select the number ot sectors
that the IDL controller is alloved to transter per interrupt.
1he Mainun option allovs your IDL controller to transter as many sectors per interrupt as
the hard disk is able to support.
Because all current hard disks support block transters, there is usuaii no reason vhy Multi-
Sector 1ransters should be disabled.
Hovever, it you are running on Windovs N1 4.0, you might need to disable this BIOS teature
because Windovs N1 4.0 has a problem vith block transters. According to a Microsott article
(Lnhanceo IDL peration unoer 1inoous ^l 4.0,, IDL HDD Block Mode and 32-bit Disk
Access have been tound to cause data corruption in some cases.1heretore, Microsott recom-
mends that Windovs N1 4.0 users disable IDL HDD Block Mode.
Microsott took a serious viev ot the issue and corrected it through the Windovs N1 4.0
Service Pack 2.1heretore, it is sate to enable Multi-Sector 1ransters in a Windovs N1 4.0 sys-
tem, so long as it has been upgraded vith Service Pack 2.
1heretore, you should disable Multi-Sector 1ransters oni it you actually tace the possibility ot
data corruption (vith an unpatched version ot Windovs N1 4.0,. Othervise, it is highly recom-
mended that you select the Mainun option tor signiticantly better hard disk pertormance'
1he manual selection ot 2 to 32 sectors is usetul it you notice data corruption vith the
Mainun option. It allovs you to scale back the multi-sector transter teature to correct the
problem vithout losing too much pertormance.
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N
N/B Strop CPU As
Connon Options: By CPL, PSB400, PSB333, PSB800
never Intel i863i873-series ot chipsets. In thos e chipsets, Intel has chosen to limit the choices
ot available CPL-to-DPAM ratios according to the clock speed ot the CPU bus (also knovn
as front side bus or FSB,.
When a 400MHz FSB processor is installed, the choice ot CPL-to-DPAM ratio is limited
to 3:4.
to 1:1 or 4:S.
to 1:1, 3:2 or S:4.
As you can see, this greatly limits the tlexibility in selecting the best CPL-to-DPAM ratio tor
your system. lortunately, this BIOS teature allovs you to circumvent that limitation.
1he N/B Strap CPU As BIOS teature actually controls the setting ot the external hardvare
reset strap assigned to the MCH (Menory Controller Hub, ot the chipset. By setting it to
PSB400, PSBS33, or PSB800, you can trick the chipset into thinking that the 400MHz FSB,
S33MHz FSB, or the 800MHz FSBis being used.
DPAM ratios ot 1:1, 3.2 and S:4.
When this BIOS teature is set to PSBS33, you are able to access the S33MHz CPL-to-
DPAM ratios ot 1:1 and 4:S.
DPAM ratio ot 3:4.
require access to the CPL-to-DPAM ratio that normally vould not be available to you, then
this BIOS teature vill be very helptul indeed.
No Mosk oI SBA IL
1his BIOS teature controls the masking ot the signal used to calibrate the SBA (Sideband
Address, port. It is used to tix compatibility issues vith certain graphics cards.
No Mask of S8A FL 241
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AGP 3.0-compatible chipsets usually implement dynamic compensation to recalibrate the AGP
bus over time. 1he SBA port ot the AGP bus also undergoes recalibration af ter an AGP bus
recalibration cycle. 1he entire process consists ot a critical si clock cycle vaiting period and
a subsequent tvo cycle recalibration period.
In certain situations, the recalibration ot the SBA port has been knovn to cause the graphics
card to hang. 1his may be a result ot the graphics chip glitching on the SBA strobe lines during
the six clock cycle-long vaiting period vhen the strobes must be completely lov. Or it could
be due to the graphics chip resuming SBA activity betore the chipset can tinish recalibrating the
SBA port.
Whatever the cause, this BIOS teature vas implemented to tix the problem by just preventing
the SBA port trom pertorming dynamic recalibrations.
When enabled, the chipset masks (hides, the SBA calibration s ignal, so the graphics chip does
not initiate the SBA calibration cycle. Since the SBA port is never recalibrated, the issue ot the
graphics card hanging due to SBA recalibration is avoided.
When disabled, the graphics chip is alloved to initiate the SBA calibration cycle right atter the
AGP bus calibration cycle.
Lsers ot A1I P3xx-based graphics cards (tor example, Padeon 9700 Pro, Padeon 9800, are
advised to enable this BIOS teature it the graphic card hangs or crashes during 3D benchmark-
ing or gaming.
Lsers ot other unattected graphics cards are advised to disable this teature, so the chipset can
dynamically calibrate the SBA port.
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0nhoard F00 LonIro||cr 248
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Onboord IDC Swop A & B
Connon Options: No Svap, Svap AB
When this BIOS teature is set to Svap AB, the tloppy drive that originally vas mapped to
drive A: is remapped to drive B: and vice versa tor the drive that vas originally set as drive B:.
When this BIOS teature is set to No Svap, the tloppy drive mapping remains as set by the
drive connector arrangement.
tant it you are using tvo tloppy drives ot ditterent torm tactors (3.3 and 3.2,, and you need to
boot trom the second drive. Because the BIOS can only boot trom drive A:, you have to physi-
cally svap the drive connections or use this BIOS teature to do it logically.
need to set this teature to Svap AB. Ieave it at the detault setting ot No Svap.
Onboord IDD Controllor
1his BIOS teature allovs you to enable or disable the onboard tloppy drive controller.
When enabled, the motherboard`s onboard tloppy drive controller is enabled.
When disabled, the motherboard`s onboard tloppy drive controller is disabled.1his trees up the
IPQ used by the tloppy drive controller.
It you are using a tloppy drive connected to the motherboard`s built-in tloppy drive controller,
select the Lnabled option.
It you are using an add-on tloppy drive controller card or it you are not using any tloppy drive
at all, set it to Disabled to save an IPQ that can be used by other devices.
O
O
channels. Hovever, it has become common practice to label the tvo IDL channels as IDL con
troii ers.
1heretore, vhile the name ot this BIOS teature suggests that it controls the tunctionality ot the
first IDL controller, it actually controls only the tirst IDL channel ot the motherboard`s single
IDL controller.
It you are not attaching any IDL devices to this IDL channel (or it you are using a SCSIadd-
sequence.
channels. Hovever, it has become common practice to label the tvo IDL channels as IDL con
troii ers.
1heretore, vhile the name ot this BIOS teature suggests that it controls the tunctionality ot the
secono IDL controller, it actually controls only the second IDL channel ot the motherboard`s s in-
gle IDL controller.
0nhoard Para||c| PorI 246
It you are not attaching any IDL devices to this IDL channel (or it you are using a SCSIadd-
sequence.
Onboord IR Iunction
Connon Options: IrDA (HPSIP, mode, ASK IP (Amplitude Shitt Keyed IP, mode,
Disabled
1his BIOS teature is usually tound under the Onboard Serial Port 2 teature because it is
slaved to the second serial port. It you disable the second serial port, this BIOS teature either
disappears or is greyed out.
1here are tvo ditterent IR (Infra-Red, modesIrDA and ASK IR.
IrDA, named tor the Infrared Data Association, provides up to 11S.2 kbps ot bandvidth tor
a distance ot about 2 neters.
ASK IR, on the other hand, is an old IP protocol developed by Sharp tor its Wizard organizer
and Zaurus PDA. It vas also used by Apple tor their Nevton PDAs. Originally, it provided up
to 9.6 kbps ot bandvidth up to 1 neter but Apple eventually extended the protocol so that it
could provide up to 38.4 kbps ot bandvidth. Currently, the maximum speed vith this protocol
is S7.6 kbps.
You should select the IP mode that is supported by your external IP device. Choosing the
vrong IP mode prevents your computer trom communicating vith the external IP device.
It there is a choice betveen IrDA and ASK IP, the natural choice vould be IrDA, ot course'
IrDA is taster and has a longer range.
Please note that such IP communications require an IP beam kit to be plugged into the IP
header on the motherboard. Without the IP beam kit, this teature von`t have any ettect.
You should also note that enabling this IP tunction prevents the second serial port trom being
used by normal serial devices.1heretore, it you do not need to use the onboard IP tunction,
disable this BIOS teature, so the second serial port can be used by normal serial devices.
Onboord Porollol Port
Connon Options: 3BChIPQ7, 278hIPQ3, 378hIPQ7, Disabled
1his BIOS teature allovs you to select the IO address and IPQ tor the onboard parallel port.
1he detault IO address ot 378h and IPQ ot 7 should vork vell in most cases. Lnles s you
have a problem vith the parallel port, you should leave it at the detault settings.
You should only select an alternative IO address or IPQ it the detault settings are causing a
contlict vith other devices.
You can als o disable the onboard parallel port it you do not need to use it. Doing so trees up
the IO port and IPQ used by the parallel port. 1hose resources can then be reallocated tor
other devices to use.
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port.
It is recommended that you leave it as Auto, so that the BIOS can select the best settings tor it.
Hovever, it you need a particular IO port or IPQ that has been taken up by this serial port,
you can manually select an alternative IO port or IPQ tor it.
to use.
port.
It is recommended that you leave it as Auto, so the BIOS can select the best settings tor it.
Hovever, it you need a particular IO port or IPQ that has been taken up by this serial port,
you can manually select an alternative IO port or IPQ tor it.
to use.
Onboord USB Controllor
1his BIOS teature is somevhat similar to Assign IRQ For USB. It enables or disables the
motherboard`s onboard LSB controller.
Hovever, instead ot controlling the assignment ot an IPQ to the onboard LSB controller, this
teature directly controls the LSB controller`s tunctionality.
It is recommended that you enable this teature, so you can use the onboard LSB controller to
It you disable this teature, the LSB controller is disabled, and you are not able to use it to
communicate vith any LSB device.1his trees up an IPQ tor other devices to use.1his is usetul
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any LSB device, or it you are using a ditterent LSB controller tor your LSB needs.
Disabling this teature is not necessary vith APIC-capable motherboards because they come
vith more IPQs.
OS/2 Onboord Monory > 4M
When there is more than 64MB ot memory in a computer, older versions ot IBM`s OS2 oper-
It you are running an old, unpatched version ot OS2, you must select the Yes option. Please
note that this is only true tor oioer versions ot OS2 that haven`t been upgraded using IBM`s
lixPaks.
1heretore, it you are using OS2 Warp v3.0 or higher, you should select No instead.You should
also select No it you have upgraded an older version ot OS2 vith the lixPaks that IBM has
been releasing over the years.
It you select the Yes option vith a never or updated version (v3.0 or higher, ot OS2, it
register as 16MB. Or it you have more than 64MB ot memory, it may register as only 64MB
ot memory.
option. Doing othervise causes memory errors it you have more than 64MB ot memory in
your system.
In conclusion:
Yes.
No.
installed all the relevant IBM lixPaks, you should select No.
option.
0Sj2 0nhoard Mcmory > 84M 247
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OS Soloct Ior DRAM > 4MB
Connon Options: OS2, Non-OS2
When there is more than 64MB ot memory in a computer, older vers ions ot IBM`s OS2 oper-
It you are running an old, unpatched version ot OS2, you must select the OS/2 option. Please
note that this is only true tor oioer versions ot OS2 that haven`t been upgraded using IBM`s
lixPaks.
1heretore, it you are using OS2 Warp v3.0 or higher, you should select Non-OS/2 instead.
You should also select Non-OS/2 it you have upgraded an older version ot OS2 vith the
lixPaks that IBM has been releasing over the years.
It you select the OS/2 option vith a never or updated version (v3.0 or higher, ot OS2, it
register as 16MB. Or it you have more than 64MB ot memory, it may register as only 64MB ot
memory.
Lsers ot non-OS2 operating systems (like Microsott Windovs XP, should select the Non-
OS/2 option. Doing othervise causes memory errors it you have more than 64MB ot memory
in your system.
In conclusion:
OS/2.
Non-OS/2.
installed all the relevant IBM lixPaks, you should select Non-OS/2.
Lsers ot non-OS2 operating systems (like Microsott Windovs XP, should select the Non-
OS/2 option.
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P
P2C/C2P Concurroncy
1he BIOS teature allovs PCI-to-CPL and CPL-to-PCI trattic to occur concurrently.1his
means PCI trattic to the CPL and CPL trattic to the PCI bus can occur simultaneously.
1his prevents the CPL trom being locked up during PCI transters. It also allovs PCI trattic
to the processor to occur vithout delay even vhen the processor is vriting to the PCI bus.1his
may prevent pertormance issues vith certain PCI cards.
1heretore, it is recommended that you enable this teature tor better pertormance.
Porollol Port Modo
Connon Options: Normal (SPP,, LCP, LPP, LCPLPP
1his BIOS teature is usually tound under the Onboard Parallel Port teature. It is linked to
the parallel port, so it you disable the parallel port, this BIOS teature either disappears or is
grayed out.
By detault, the parallel port is usually set to the Nornal (SPP) mode. SPP stands tor
Standard Parallel Port. It is the original transter protocol tor the parallel port. 1heretore, it
vorks vith all parallel port devices.
Although the SPP vas a unidirectional port originally, it vas eventually adapted to vork bidi-
rectionally. Such bidirectional SPP ports are also knovn as PS2 parallel ports. So, contrary to
popular opinion, the SPP mode is capable ot bidirectional transters.
Hovever, it can only receive 4-bits ot data per cycle in this bidirectional mode. Its output, tor-
tunately, remains at 8-bits per cycle.1his gives the parallel port in SPP mode an output rate ot
1S0KB/s and an input rate ot S0KB/s (due to sottvare reasons,.
1he LCP (Ltended Capabilities Port, transter mode vas introduced by Microsott and
Hevlett-Packard to provide tast, bidirectional communication betveen the computer and high-
pertormance printers and scanners. It uses the DMA protocol to achieve data transter rates ot up
to 2MB/s and provides smmetric bidirectional communication.
On the other hand, LPP (Lnhanced Parallel Port,, nov knovn as ILLL 1284, uses existing
parallel port signals to provide asmmetric bidirectional communication. It vas also designed tor
high-speed communications, ottering transter rates ot up to 2MB/s.
As you can see, SPP is a very slov transter mode. It should only be selected vhen taster transter
modes cannot be used (tor example, vith old printers or scanners,. With modern parallel port
devices, the LCP and LPP modes are the transter modes ot choice.
Generally, because ot its lIlOs and the DMA channel it uses, LCP is good at large data trans-
ters. 1heretore, it is the transter mode that vorks best vith scanners and printers. LPP is better
vith devices that svitch betveen reads and vrites trequently (like ZIP drives and hard disks,.
Para||c| PorI Modc 240
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Hovever, you should check your parallel port device`s documentation betore you set the trans-
ter mode. 1he manutacturer ot your parallel port peripheral may have designated a preterred
transter mode tor the device in question. In that case, it is best to tollov their recommendation.
It the device documentation did not state any preterred transter mode and you still do not
knov vhat mode to s elect, you can select the LCP+LPP mode. It you select this mode, the
BIOS automatically determines the transter mode to use tor your device.
Hovever, this should be considered as a last resort because you may be needlessly tying up a
DMA channel tor nothing it your device does not use LCP at all. Or the BIOS may not actual-
ly select the best parallel port mode tor the device. It possible, set the parallel port to the transter
mode that best suits your parallel port device.
Possivo Rolooso
the chipset has an integrated vrite butter to s ervice the processor`s PCI vrites.
Whenever the processor vants to vrite to the PCI bus, it no longer needs to arbitrate tor the
PCI bus and vait tor its turn. It can immediately vrite up to tour vords ot PCI vrites to the
vrite butter.1his trees up the processor and allovs it to vork on other tasks.
1his BIOS teature controls the passive release teature ot the CPU to PCI Write Buffer.
1heretore, it the vrite butter is disabled, this BIOS teature does not have any ettect. Hovever,
the reverse is not true. 1he CPU to PCI Write Buffer teature still vorks even it Passive
Release is disabled.
When Passive Pelease is enabled, the vrite butter independently vrites the data to the PCI
bus at the tirst available opportunity. It can do so even vhen the processor is busy doing some-
thing else.
When Passive Pelease is disabled, the vrite butter vaits until the process or reasserts (retries,
the vrite request. Only then does it vrite to the PCI bus.1his still improves pertormance
because the process or does not need to resend the data.1he vrite butter is ready to ottload the
data the moment the PCI bus arbiter releases control ot the bus to the processor. Hovever, the
vrite butter still loses some ot its ettectiveness because it has to vait tor the CPL to retry the
transaction.
1his can be a particularly big problem vhen an ISA device engages the ISA bus. Because the
ISA bus is very slov, this ties up the PCI bus and prevents the processor trom accessing it tor a
very long time. It the CPL-to-PCI vrite butter is enabled, the processor can vrite to the butter
instead.1his allovs the processor to engage in other tasks. Hovever, it Passive Pelease is dis-
abled, the vrite butter cannot vrite its contents to the PCI bus until both the processor is tree
to retry the vrite and the PCI bus is tree to receive.
Passive Pelease helps in this situation by alloving the vrite butter to passively vriteto the
PCI bus vithout the processor`s intervention and even vhile the ISA device is engaging the
PCI bus.1his essentially allovs the processor to indirectly vrite to the PCI bus, even vhen the
ISA device has control over it. Without this teature, the PCI bus arbiter only allovs other (non-
CPL, PCI masters to access the PCI bus.
PLI 2.1 Lomp|ancc 261
lor best pertormance, it is highly recommended that you enable Passive Pelease. 1his dramati-
cally reduces the ettect ot slov ISA devices hogging the PCI bus. Hovever, some ISA cards may
not vork vell vith Passive Pelease. In such cases, disable Passive Pelease or better yet, throv
the card avay and get a PCI version instead'
It you don`t use any ISA device, this teature should still be enabled because it allovs the vrite
butter to ottload its data to the PCI bus vithout vaiting tor the processor to retry the transac-
tion.1his improves the pertormance ot the processor and PCI bus.
Buffer.
PCI#2 Accoss #1 Rotry
1his BIOS teature is linked to CPU to PCI Write Buffer. 1heretore, it the vrite butter is
disabled, this BIOS teature does not have any ettect. Hovever, the reverse is not true.1he
CPU to PCI Write Buffer teature still vorks even it PCI2 Access 1 Retry is disabled.
When the butter is enabled, the processor vrites directly to the butter instead ot the PCI bus.
1he butter then attempts to vrite the data to the PCI bus by Passive Release. 1his allovs the
processor to pertorm other tasks vithout vaiting tor its data to be vritten to the PCI bus.
Hovever, the attempted butter vrite to the PCI bus may tail because the PCI bus may still be
occupied by another device. When that happens, this BIOS teature determines vhether the
butter vrite should be reattempted or sent back tor arbitration.
It this BIOS teature is enabled, the butter attempts to vrite to the PCI bus until it is successtul.
It this BIOS teature is disabled, the butter tlushes its contents and registers the transaction as
tailed.1he processor nov has to vrite again to the vrite butter.
Generally, it is recommended that you enable this teature because it improves the processor`s
pertormance.
Hovever, it you have many PCI devices and their pertormance is more important, you may
vant to disable this teature.1his prevents excessive generation ot retries by the vrite butter,
vhich may severely tax the PCI bus. Disabling this teature improves the PCI bus pertormance,
especially vith slov PCI devices that hog the bus tor long periods ot time at a stretch.
Buffer.
PCI 2.1 Conplionco
1his is the same as the Delayed 1ransaction BIOS teature because it reters to the PCI
Delayed 1ransaction teature, vhich is part ot the PCI Pevision 2.1 specitications.
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When a master device reaos trom a target device on the PCI bus but tails to meet the latency
to rearbitrate tor bus access. Hovever, it PCI Delayed 1ransaction had been enabled, the tar-
get device can independently continue the read transaction. So, vhen the master device success-
tully gains control ot the bus and reissues the read command, the target device has the data
ready tor immediate delivery.1his ensures that the retried read transaction can be completed
vithin the stipulated latency period.
It the delayed transaction is a urite, the target device latches on the data and terminates the
bus initiates a non-postable transaction, and yet still adhere to the PCI ordering rules. 1he
can occur.
As you can see, the PCI Delayed 1ransaction teature uses the PCI bus more etticiently,
resulting in better PCI pertormance by alloving vrite-posting to occur concurrently vith non-
postable transactions. In this BIOS, the PCI 2.1 Conpliance option allovs you to enable or
disable the PCI Delayed 1ransaction teature.
It is highly recommended that you enable PCI 2.1 Compliance tor better PCI pertormance
butter tor taster PCI-to-ISA vrites, they are incorrect' 1his BIOS teature is not ISA bus-specitic
PCI Choining
1his BIOS teature is designed to speed up vrites trom the processor to the PCI bus by alloving
vrite combining to occur at the PCI intertace.
PLI L|ock j LPu FS8 L|ock 268
When PCI chaining is enabled, up to tour quadvords ot processor vrites to contiuous PCI
addresses are chained together and vritten to the PCI bus as a single PCI burst vrite.
When PCI chaining is disabled, each processor vrite to the PCI bus is handled as separate
non-burstable vrites.
Needless to say, vriting tour quadvords ot data in a single PCI vrite is much taster than doing
so in tour separate non-burstable vrites. A single PCI burst vrite also reduces the amount ot
time the processor has to vait vhile vriting to the PCI bus.
1heretore, it is recommended that you enable this teature tor better CPL to PCI vrite
pertormance.
PCI Clock / CPU ISB Clock
Connon Options: 12, 13, 14, 13, 16
1he PCI bus vas designed to run at a maximum clock speed ot 33MHz. 1he processor bus, on
the other hand, alvays has a much higher clock s peed than the PCI bus. Lven the sloves t
processors these days run on a 100MHz processor bus. Never proces sors utilize process or buses
that run trom 133MHz to 200MHz.
Knovledge about the clock speed ot your processor bus is important becaus e the PCI bus speed
is actually derived trom the processor`s bus speed. It does this vith the use ot clock speed
dividers.
lor example, it you have a 100MHz processor bus, a 13 PCI bus divider is used to allov the
PCI bus to run at the specitied clock speed ot 33MHz. Systems that use a 133MHz processor
bus utilize a 14 divider to maintain the PCI bus at the standard 33MHz clock speed.
Please note that motherboards claiming to have 200MHz to 800MHz processor bus speeds are
actually only running trom 100MHz to 200MHz. lor example, current AMD-based mother-
boards sport bus speeds ot 200MHz and 266MHz, although the processor bus is only running at
100MHz and 133MHz, respectively. 1his is achieved by transterring data on both edges ot the
clock signal, thereby doubling the bandvidth ot the process or bus.
1he same goes tor Intel-based motherboards that tout 400MHz, 333MHz, and 800MHz proces-
sor buses.1hese actually run at 100MHz, 133MHz, and 200MHz, respectively.1he 400MHz,
333MHz, and 800MHz Intel processor buses are actually quad-pumped.While they actually run
at only 100MHz, 133MHz, and 200MHz, they can transter tour times as much data per clock
cycle.
So, vhen you vant to calculate the suitable PCI bus divider tor your system, please take the
intormation above into account. As tar as this BIOS teature is concerned, such motherboards are
only running at 100MHz to 133MHz. It you do not calculate properly, you torce the PCI bus
to run beyond its rated speed ot 33MHz.1his may result in an unstable system and corruption
ot data on your hard disk.
1his BIOS teature allovs you to manually select the PCI bus clock divider. Because this divider
determines the speed at vhich the PCI bus runs, manipulation ot this teature allovs you some
control over the PCI bus speed.
It vas meant to keep the PCI bus running vithin specitications vhen you overclock the
processor bus, but you can also use it to overclock the PCI bus. With that said, you should keep
in mind that the recommended sate limit tor an overclocked PCI bus is 37.SMHz.1his is the
speed at vhich practically all nev PCI cards can run vithout breaking a sveat.
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Ot course, running at a higher speed is detinitely possible. Hovever, the risk ot data corruption
is particularly vorrisome because the IDL controller runs ott the PCI bus. It you intend to
overclock beyond 37.3MHz, test your system thoroughly and make sure that your IDL devices
are running tine betore you do any serious vork'
Selecting the clock divider ot 1/2 makes the PCI bus run at halt the processor bus speed. It
your processor bus is set to 100MHz, the PCI bus speed is 30MHz.As such, this clock divider is
usetul tor processor bus speeds ot 66MHz to 7SMHz. Within that range, the PCI bus runs
trom 33MHz to 37.3MHz.
Selecting the clock divider ot 1/3 makes the PCI bus run at a third ot the processor bus speed.
As such, this clock divider is usetul tor processor bus speeds ot 100MHz to 112.SMHz.Within
that range, the PCI bus runs trom 33MHz to 37.3MHz.
Selecting the clock divider ot 1/4 makes the PCI bus run at a quarter ot the processor bus
speed. As such, this clock divider is usetul tor processor bus speeds ot 133MHz to 1S0MHz.
Within that range, the PCI bus runs trom 33MHz to 37.3MHz.
Selecting the clock divider ot 1/S makes the PCI bus run at a titth ot the processor bus speed.
As such, this clock divider is usetul tor processor bus speeds ot 166MHz to 187.SMHz.Within
Selecting the clock divider ot 1/6 makes the PCI bus run at a sixth ot the processor bus speed.
As such, this clock divider is usetul tor processor bus speeds ot 200MHz to 22SMHz.Within
You are probably vondering about the gaps in the processor bus speeds listed above. lor your
convenience, only processor bus speeds that produce PCI clock speeds vithin the range ot opti-
mal PCI clock speeds (33MHz to 37.3MHz, are displayed above. 1he other processor bus speeds
either produce a slov PCI bus or an excessively overclocked one.
1heretore, tor optimal PCI bus pertormance, try to shoot tor one ot the processor bus speed-
divider combinations shovn above.
PCI Doloy lronsoction
When a master device reaos trom a target device on the PCI bus but tails to meet the latency
to rearbitrate tor bus access. Hovever, it PCI Delayed 1ransaction had been enabled, the tar-
get device can independently continue the read transaction. So, vhen the master device success-
tully gains control ot the bus and reissues the read command, the target device has the data
ready tor immediate delivery.1his ensures that the retried read transaction can be completed
vithin the stipulated latency period.
It the delayed transaction is a urite, the target device latches on the data and terminates the
bus initiates a non-postable transaction, and yet still adhere to the PCI ordering rules. 1he
can occur.
As you can see, the PCI Delayed 1ransaction teature uses the PCI bus more etticiently as
vell as increases PCI pertormance by alloving vrite-posting to occur concurrently vith non-
postable transactions. In this BIOS, the PCI Delay 1ransaction option allovs you to enable or
disable the PCI Delayed 1ransaction teature.
It is highly recommended that you enable PCI Delay 1ransaction tor better PCI pertormance
PCI Dynonic Bursting
1his BIOS teature is similar to the Byte Merge teature.
the chipset has an integrated PCI vrite butter that allovs the CPL to immediately vrite up to
four vords (or 64-bits, ot PCI vrites to it.1his trees up the CPL to vork on other tasks
vhile the PCI vrite butter vrites them to the PCI bus.
Nov, the CPL doesn`t alvays vrite 32-bit data to the PCI bus. 8-bit and 16-bit vrites can also
take place. Hovever, vhile the CPL may only vrite 8-bits ot data to the PCI bus, it is still con-
sidered a single PCI transaction.1his makes it equivalent to a 16-bit or 32-bit vrite in terms ot
PCI bandvidth' 1his reduces the ettective PCI bandvidth, especially it there are many 8-bit or
16-bit CPL-to-PCI vrites.
1o solve this problem, the vrite butter can be programmed to accumulate and merge 8-bit and
16-bit vrites into 32-bit vrites.1he butter then vrites the merged data to the PCI bus. As you
can see, merging the smaller 8-bit or 16-bit vrites into a tev large 32-bit vrites reduces the
number ot PCI transactions required. 1his increases the etticiency ot the PCI bus and improves
its bandvidth.
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1his is vhere the PCI Dynanic Bursting BIOS teature comes in. It controls the byte merg-
ing capability ot the PCI vrite butter.
It it is enabled, every vrite transaction goes straight to the vrite butter.1hey are accumulated
until there is enough to be vritten to the PCI bus in a single burst.1his improves the PCI bus
pertormance.
It you disable byte merging, all vrites s till go to the PCI vrite butter (it the CPU to PCI
Write Buffer teature has been enabled,. Hovever, the butter does not accumulate and merge
the data. 1he data is vritten to the PCI bus as soon as the bus becomes tree.1his reduces PCI
bus etticiency, particularly vhen 8-bit or 16-bit data is vritten to the PCI bus.
1heretore, it is recommended that you enable PCI Dynamic Bursting tor better pertormance.
Please note that, like Byte Merge, this teature may not be compatible vith certain PCI net-
vork intertace cards. lor example, 3Com`s 3C903-series ot NICs von`t vork properly vith
Byte Merge enabled.
So, it your NIC (Netvork Intertace Card, von`t vork properly, try disabling Byte Merge.
Othervise, you should enable Byte Merge tor better pertormance.
PCI IDL Busnostor
DMA transter modes allov IDL devices to transter large amounts ot data trom the hard disk to
the system memory and vice versa vith minimal processor intervention. It ditters trom the older
and processor-intensive PIO (Progranned Input/Output) transter modes by ottloading the
task ot data transter trom the processor to the chipset.
Previously, this teature is only available atter an operating system that s upports DMA transters
(through the appropriate device driver, is loaded up. Nov, many BIOS come vith a built-in
16-bit driver that allovs DMA transters. 1his allovs the onboard IDL controller to pertorm
DMA transters even betore the operating system is loaded up'
When this BIOS teature is disabled, the BIOS does not load up the 16-bit busmastering driver
tor the onboard IDL controller. 1he IDL controller then transters data through PIO.
1heretore, it is recommended that you enable PCI IDL Busmaster.1his greatly improves the
IDL transter rate and reduces the CPL utilization during the booting process or vhen you are
using real-mode DOS. Lsers ot DOS-based dis k utilities like Norton Ghost can expect to ben-
etit a lot trom this teature.
Please note that because current operating systems (tor example,Windovs XP, load up their
ovn 32-bit busmastering driver, this teature has no ettect once such an operating system loads
up. Still, it is recommended that you enable this teature to improve pertormance prior to the
loading ot the operating system`s ovn driver.
PCI IRQ Activotod By
Connon Options: Ldge, Ievel
1his BIOS teature allovs you to set the method by vhich the IPQs tor your PCI devices are
activated or triggered.
ISA and old PCI devices are edge-triggered (using a single voltage level, vhile never PCI
and AGP devices are level-triggered (using multiple voltage levels,. 1his is important mainly
because PCI devices must be level-triggered to s hare IPQs.
1he multiple voltage levels supported by level-triggered cards are used to activate the proper
device among multiple devices sharing the same IPQ. Ldge-triggered devices only support a
single voltage level, vhich can only be used to activate or deactivate their IPQs. 1heretore,
IPQs allocated to edge-triggered devices cannot be shared vith other devices.
When PCI devices vere initially introduced, they vere almost alvays eoetriereo and, there-
tore, did not support IPQ sharing.1hat is vhy the detault and recommended setting tor such
devices vas invariably Ldge. Lntortunately, that misled people into thinking that it vould be
the same tor never PCI devices.
Current PCI devices are all ie:eitriereo and so support IPQ sharing. 1his is critical in alloving
the use ot the numerous PCI devices in current computers. Without IPQ sharing, IPQ con-
tlicts make PCI contiguration a real hassle.
Ot course, the introduction ot the Advanced Progrannable Interrupt Controller or
APIC solves this problem completely by providing anyvhere trom 24 to 312 IPQ lines'
Hovever, until all motherboards ship vith APIC, IPQ sharing vill continue to play an impor-
tant role in alloving multiple PCI devices to vork in harmony.
Because all PCI devices currently in the market are level-triggered, it is recommended that you
set this BIOS teature to Level, so your PCI devices can share IPQs.
Hovever, it you are still using old edge-triggered devices, select Ldge to torce the chipset to
allov only edge-triggering ot PCI devices.1his may cause contiguration problems it there are
IPQ contlicts, but it prevents system lockups that can occur it the chipset erroneously attempts
to level-trigger an edge-triggered PCI device.
PCI Lotoncy linor
Connon Options: 0233
1his BIOS teature controls hov long a PCI device can hold the PCI bus betore another takes
over. 1he longer the latency, the longer the PCI device can retain control ot the bus betore
handing it over to another PCI device.
As each access to the bus comes vith an initial delay betore any transaction can be made, a
short PCI latency time reduces the ettective PCI bandvidth because the PCI device only has a
short time to pertorm transactions on the PCI bus. Ionger latencies actually improve the ettec-
tive PCI bandvidth by alloving the PCI device to pertorm more transactions vith the same
amount ot delay.
On the other hand, the response time ot PCI devices sutters vith longer PCI latencies. A long
PCI latency allovs the active PCI device to use the bus longer but at the expense ot other PCI
devices queuing up to use the bus. All PCI devices theretore have to vait longer betore gaining
access to the bus.
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Normally, the PCI Iatency 1imer is set to 32 cycles. 1his means the active PCI device has to
complete its transactions vithin 32 clock cycles or hand it over to the next PCI device.
lor better PCI pertormance, a longer latency should be used.1ry increasing it to 64 cycles or
even 128 cycles.1he optimal value tor every system is ditterent.You should benchmark your
PCI cards` pertormance atter each change to determine the optimal PCI latency time tor
your system.
Please note that a longer PCI latency isn`t necessarily better. A long latency can also reduce per-
tormance because the other PCI devices queuing up may be stalled tor too long. 1his is espe-
cially true vith systems vith many PCI devices or PCI devices that continuously vrite short
bursts ot data to the PCI bus. Such systems vork better vith shorter PCI latencies because they
allov rapid access to the PCI bus.
In addition, some time-critical PCI devices may not agree vith a long latency. Such devices
require priority access to the PCI bus, vhich may not be possible it the PCI bus is held up by
another device tor a long period. In such cases, it is recommended that you keep to the detault
PCI latency ot 32 cycles.
PCI Mostor 0 WS Rood
1his BIOS teature determines vhether the chipset inserts a delay betore any reads trom the PCI
bus.
It PCI Master 0 WS Read is enabled, read requests to the PCI bus are executed immediately
(vith zero vait states,, it the PCI bus is ready to send data.
It PCI Master 0 WS Pead is disabled, every read request to the PCI bus is delayed by one vait
state.
It is recommended that you enable this teature tor better PCI read pertormance.
PCI Mostor 0 WS Writo
1his BIOS teature determines vhether the chipset inserts a delay betore any vrites trom the
PCI bus.
It PCI Master 0 WS Write is enabled, vrite requests to the PCI bus are executed immedi-
ately (vith zero vait states,, it the PCI bus is ready to send data.
It PCI Master 0 WS Write is disabled, every vrite request to the PCI bus is delayed by one
vait state.
It is recommended that you enable this teature tor better PCI vrite pertormance.
PCI Mostor Rood Coching
1his is an AMD-specitic BIOS teature. It determines vhether the processor`s I2 cache is used
to cache PCI bus master reads . Hovever, like Video RAM Cacheable, this BIOS teature may
actually reduce pertormance.
It this teature is enabled, the processor`s I2 cache is used to cache PCI bus master reads. 1his
boosts the pertormance ot PCI bus masters. On the other hand, it reduces the processor`s per-
tormance because it uses up some ot the precious I2 cache.
1his is vhy motherboard manutacturers like ASLS recommend that only systems using AMD
Athlon processors should enable this teature. Duron users should disable this teature because
its small I2 cache is not able to cache the PCI reads vithout causing a massive hit to memory
bandvidth.
Hovever, it is questionable that even AMD Athlon systems benetit trom this teature. lor one
thing, the Athlon is not so vell-endoved in I2 cache that using some ot it to boost the per-
tormance ot PCI bus masters von`t detrimentally attect its pertormance.
In addition, such a caching scheme requires the tvo-vay use ot the Athlon processor bus .1his
reduces its etticiency and bandvidth as vell as the processor`s pertormance.
So, does the boost in PCI bus master pertormance justity the loss in processor and memory per-
tormance Although the tinal vord is still in the air, I recommend disabling this teature.1he
use ot precious I2 cache to cache PCI bus masters is not vorth the potential benetit in PCI bus
pertormance.
PCI Pipolining
1his BIOS teature determines vhether PCI transactions to the memory subsystem are
pipelined.
1he pipelining ot PCI transactions allovs their latencies to be masked (hidden,.1his greatly
improves the etticiency ot the PCI bus. Hovever, this is only true tor multiple transactions in
the same direction. Pipelining doesn`t help vith PCI devices that svitch betveen reads and
vrites otten.
1his teature is ditterent trom a burst transter vhere multiple data transactions are executed con-
secutively vith a single command. In PCI pipelining, ditterent transactions are progressively
processed in the pipeline vithout vaiting tor the current transaction to tinish. Normally, out-
standing transactions have to vait tor the current one to complete betore they are initiated.
It the PCI pipeline teature is enabled, the memory controller allovs PCI transactions to be
pipelined. 1his masks the latency ot each PCI transaction and improves the etticiency ot the
PCI bus.
Please note that once the transactions are pipelined, they are tlagged as pertormed, even though
they have not actually been completed. As such, data coherency problems ma occur vhen other
devices vrite to the same memory block.1his may cause valid data to be overvritten by out-
dated or expired data, causing problems like data corruption or system lock-ups.
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It the PCI pipeline teature is disabled, the memory controller is torced to check tor outstand-
ing transactions trom other devices to the same block address that each PCI transaction is
targeting.
It there is a match, the PCI transaction is stalled until the outstanding transaction to the same
memory block is complete. 1his essentially torces the memory controller to hold the PCI bus
until the PCI transaction is cleared to proceed. It also prevents other PCI transactions trom
being pipelined. Both tactors greatly reduce pertormance.
lor better PCI pertormance, the PCI pipeline should be enabled. 1his allovs the latency ot the
bus to be masked tor consecutive transactions.
Hovever, it your system constantly locks up tor no apparent reason, try disabling this teature.
Disabling PCI Pipelining reduces pertormance but ensures that data coherency is strictly main-
tained tor maximum reliability.
PCI ProIotch
1his teature controls the system controller`s PCI Prefetch capability. When enabled, the sys-
tem controller pretetches eight quadvords (one cache line, ot data vhenever a PCI device reads
trom the system memory. Here`s hov it vorks.
Whenever the system controller reads PCI-requested data trom the system memory, it also reads
the subsequent cache line ot data. 1his is done on the assumption that the PCI device requests
the subsequent cache line.When the PCI device actually initiates a read command tor that
cache line, the system controller can immediately send it to the PCI device.
1his speeds up PCI reads because the PCI device doesn`t need to vait tor the system controller
to read trom the system memory. As such, PCI Pretetch allovs contiguous memory reads by the
Please note that PCI vrites to the system memory do not benetit trom this teature.
PCI lorgot Lotoncy
1his BIOS teature determines vhether the system controller s hould contorm to the PCI maxi-
mum target latency rule.
According to the PCI maximum target latency rule, the PCI device must service a read request
vithin 16 PCI clock cycles (32 PCI clock cycles it it is a host bus bridge, tor the initiai read
and 8 PCI clock cycles tor each su|seuent read. Please note that this only applies to the PCI
bus. It does not apply to the AGP bus.
When this teature is enabled, the system controller disconnects the PCI bus master vhen it
cannot service a read request vithin 32 PCI clock cycles tor the initial read and 8 PCI clock
cycles tor subsequent reads.1he PCI bus master then rearbitrates tor access to the PCI bus.
When this teature is disabled, the PCI bus master is not disconnected vhen it cannot service a
read request vithin the stipulated 32 PCI clock cycles tor the initial read and 8 PCI clock
cycles tor subsequent reads.1he PCI bus master is alloved to complete vith its transactions.
Compliance to the PCI maximum target latency rule is important because it ensures that tair
access tor all PCI devices to the PCI bus. In addition, it a PCI device hogs the PCI bus beyond
the target latency, it may cause the system to lock-up vhen there is PCI to AGP trattic.
It is recommended that you enable this teature to entorce the PCI maximum target latency
rule and prevent potential deadlocks.
PCI to DRAM ProIotch
1his teature controls the system controller`s PCI pretetch capability.When enabled, the system
controller pretetches eight quadvords (one cache line, ot data vhenever a PCI device reads
trom the system memory. Here`s hov it vorks.
Whenever the system controller reads PCI-requested data trom the system memory, it also reads
the subsequent cache line ot data. 1his is done on the assumption that the PCI device requests
the subsequent cache line.When the PCI device actually initiates a read command tor that
cache line, the system controller can immediately send it to the PCI device.
1his speeds up PCI reads because the PCI device doesn`t need to vait tor the system controller
to read trom the system memory. As such, PCI to DPAM Pretetch allovs contiguous memory
reads by the PCI device to proceed vith minimal delay.
Please note that PCI vrites to the system memory do not benetit trom this teature.
PCI/VGA Polotto Snoop
1his BIOS teature determines vhether your graphics card should allov VGA palette snooping
by a tixed tunction dis play card. It is only usetul it you use a tixed-tunction display card that
requires a VGA-compatible graphics card to be present ( tor example, MPLG decoder card,.
Such tixed-tunction display cards generally do not have their ovn VGA palette. So, they have to
snoopVGA palette data trom the graphics card to generate the proper colors. Normally, the
graphics card`s Feature Connector is used tor this purpose.
When this teature is enabled, the graphics card does not respond to tramebutter vrites. It tor-
vards them to the tixed-tunction display card through its leature Connector. 1he tixed-
tunction display card then snoops the palette data and generates the proper colors.
1his ensures accurate color reproduction. It also prevents the monitor trom displaying a blank
screen atter the tixed-tunction card`s capabilities are not required (tor example, vhen you stop
playing MPLG video using the MPLG decoder card,.
When this teature is disabled, the graphics card displays all tramebutter vrites.
It is recommended that you disable this teature it you do not use any tixed-tunction display
card like a MPLG decoder card.
Hovever, it you are using a tixed-tunction display card that requires palette snooping, enable this
teature. Othervise, the colors displayed may not be accurate and the monitor vill blank out
once you stop using the tixed-tunction display card.
PLIjv0A Pa|cIIc Snoop 21
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PIO Data 1ransfer Mode Mainun 1hroughput
PIO Mode 0 3.3 MBs
PIO Mode 1 3.2 MBs
PIO Mode 2 8.3 MBs
PIO Mode 3 11.1 MBs
PIO Mode 4 16.6 MBs
PIO Modo
IDL drive. Here is a table ot the ditterent PIO transter rates and their corresponding maximum
throughputs.
P
tor.
PIRQ Uso IRQ No.
Connon Options: Auto, 3, 4, 3, 7, 9, 10, 11, 12, 14, 13
1his BIOS teature allovs you to manually set the IPQ tor a particular device installed on the
AGP and PCI buses.
It is especially usetul vhen you are transterring a hard disk trom one computer to another and
you don`t vant to reinstall your operating system to redetect the IPQ settings. By setting the
IPQs to tit the original settings, you can circumvent a lot ot contiguration problems atter
installing the hard disk in a nev system. Hovever, this is only true tor non-ACPI systems.
Here are some important notes trom the reterence motherboard (may vary betveen motherboards,:
It you specity a particular IPQ here, you can`t specity the same IPQ tor the ISA bus. It
you do, you vill cause a hardvare contlict.
Lach PCI slot is capable ot activating up to 4 interrupts[md|IN1 A, IN1 B, IN1 C, and
IN1 D.
1he AGP slot is capable ot activating up to 2 interrupts[md|IN1 A and IN1 B.
Normally, each s lot is allocated IN1 A.1he other interrupts are reserves and used only vhen
the PCIAGP device requires more than one IPQ or it the IPQ requested has been used up.
1he AGP slot and PCI slot 41 share the s ame IPQ.
PCI slot 44 and 43 share the same IPQs.
LSB uses PIPQ_4.
1he tolloving is a table shoving the relationship betveen PIPQ (Programmable Interrupt
Pequest, signals and IN1 in the reterence motherboard:
PI0 x usc I0 No. 28
P
Signals AGP Slot/ PCI Slot 2 PCI Slot 3 PCI Slot 4/
PCI Slot 1 PCI Slot S
PIPQ_0 IN1 A IN1 D IN1 C IN1 B
PIPQ_1 IN1 B IN1 A IN1 D IN1 C
PIPQ_2 IN1 C IN1 B IN1 A IN1 D
PIPQ_3 IN1 D IN1 C IN1 B IN1 A
Notice that the interrupts are staggered, so contlicts do not happen easily. 1he IN1 A entries are
in bold to highlight the staggered arrangement.
Lven then, you should try not to use up paired slots that s hare the same set ot IPQs. In this ret-
erence motherboard, such paired slots are AGP slot and PCI slot 1 or PCI slots 4 and S. In
such cases, it is recommended that you use only one ot the tvo s lots.
In most cases, you should just leave the setting as Auto.1his allovs the motherboard to assign
the IPQs automatically. Hovever, it you need to assign a particular IPQ to a device on the
AGP or PCI bus, here is hov you can make use ot this BIOS teature.
1. Determine the slot in vhich the device is located.
2. Check your motherboard`s PIRQ table (in the manual, to determine the slot`s primary
PIPQ. lor example, it you have a PCI netvork card in PCI slot 3, the table above shovs
that the slot`s primary PIPQ is PIPQ_2. Pemember, all slots are tirst allocated IN1 A it
it is available.
3. You then select the IPQ you vant by as signing the IPQ to the appropriate PIPQ. In
our netvork card example, it the card requires IPQ 7, set PIPQ_2 to use IPQ 7.1he
BIOS then allocates IPQ 7 to PCI slot 3. It is that easy':
ust remember that the BIOS alvays tries to allocate the PIPQ linked to IN1 A tor each slot.
So, in our reterence motherboard, the primary PIPQ tor the AGP slot and PCI slot 1 is
PIPQ_0, vhile the primary PIPQ tor PCI slot 2 is PIPQ_1, and so on. It is just a matter ot
linking the IPQ you vant to the correct PIPQ tor that slot.
P
Please note the table, notes , and IN1 details are only examples provided by the reterence moth-
erboard.1hey may vary betveen motherboards. lor example, Intel i8xx chipsets have 8 inter-
rupt lines (IN1 A to IN1 H,. In i8xx motherboards, the AGP slot alvays has its ovn IPQ.
PNP OS Instollod
1his BIOS teature is quite misleading becaus e its name suggests that you should set it to Yes it
you have an operating system that supports Plug and Play (PnP,. Lntortunately, it isn`t quite
so simple.
What this BIOS teature actually does is determine vhat devices are contigured by the BIOS
vhen the computer boots up and vhat are lett to the operating system. 1his is rather ditterent
trom vhat the name implies, right
Betore you can determine the appropriate setting tor this teature, you should tirst determine the
kind ot BIOS that came vith your motherboard. lor the purpose ot this discussion, the BIOS
can be divided into tvo typesACPI BIOS and Non-ACPI BIOS.
You also need to tind out it your operating system supports ano is currently running in ACPI
mode. Please note that vhile an operating system may tout ACPI support, it is possible to torce
the operating system to use the older PnP mode. So, tind out it your operating sys tem is actually
running in ACPI mode. Ot course, this is only possible it your motherboard comes vith an
ACPI BIOS.With a Non-ACPI BIOS, all ACPI-compliant operating systems automatically
revert to PnP mode.
Non-ACPI BIOSes are tound in older motherboards that do not support the nev ACPI
(Advanced Configuration and Pover Interface, initiative.1his can be either the ancient
non-PnP BIOS (or Iegacy BIOS, or the never PnP BIOS.With such a BIOS, setting the PNP
OS Installed teature to No allovs the BIOS to contigure all devices under the assumption that
the operating system cannot do so. 1heretore, all hardvare settings are tixed by the BIOS at
boot up and are not changed by the operating system.
On the other hand, it you set the teature to Yes, the BIOS only contigures critical devices
required to boot up the system, tor example, the graphics card and the hard disk. 1he other
devices are then contigured by the operating system.1his allovs the operating system some
tlexibility in shuttling system resources, like IPQs and IO ports, to avoid contlicts. It also gives
you some degree ot treedom vhen you vant to manually assign system resources.
While all this tlexibility in hardvare contiguration sounds like a good idea, shuttling resources
can sometimes cause problems, especially vith a buggy BIOS.1heretore, it is recommended that
you set this teature to No to allov the BIOS to contigure all devices.You should only set this
teature to Yes it the Non-ACPI BIOS cannot contigure the devices properly or it you vant to
manually reallocate hardvare resources in the operating system.
Ot course, all current motherboards nov ship vith the nev ACPI BIOS. It you are using an
ACPI-compliant operating system (such as Windovs 98 and above, vith an ACPI BIOS, then
this PNP OS Installed teature is no longer relevant. It actually does not matter vhat setting you
select.1his is because the operating system uses the ACPI BIOS intertace to contigure all
devices as vell as retrieve system intormation. 1here is no longer a need to specitically split the
job up betveen the BIOS and the operating system.
PNP 0S InsIa||cd 26
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Hovever, it your operating sys tem does not support ACPI, then the BIOS talls back to PNP
mode. In this situation, consider the BIOS as you vould a Non-ACPI BIOS. It there is no
need to contigure any hardvare manually, it is again recommended that you s et this teature
to No.
Please note that bugs in some ACPI BIOS can cause even an ACPI-compliant operating system
to disable ACPI.1his reverts the BIOS to PnP mode. Hovever, there is an additional catch to it.
Certain operating systems (tor example,Windovs 98 and above, only access the buggy BIOS in
reaooni mode.1his means the operating system relies entirely on the BIOS to contigure all
devices and provide it vith the hardvare contiguration. As such, you must set the teature to No
it you have a buggy ACPI BIOS.
Iinux is not really PnP-compatible, but most distributions use a sottvare called ISAP-
NP1OOIS to set up ISA cards. It PnP OS is set to No, the BIOS vill attempt to contigure the
ISA cards, but that von`t vork vith Iinux. Worse, it ISAPNP1OOIS is used to contigure the
ISA cards as vell, it may lead to contlicts betveen the tvo.
1heretore, it is recommended that you set PnP OS to Yes in Iinux and allov ISAPNP1OOIS
to handle the task instead.
As tar as OS2 is concerned, PnP OS should be set to No, especially in a multi-boot system. In
addition, it you add or change hardvare, you should enable tull hardvare detection during the
initial boot s equence ot OS2.1his allovs OS2 to properly register the hardvare changes.You
can do so by pressing Alt-l1 at the boot screen, and then pressing the l3 key.
Pobert Kirk ot IBM has this to say about PnP OS :
ctuaii, the settin InI :` is reai i misnameo. |etter thin uoui o |e to sa oo
ou uant the sstem to attempt to resoi:e resource conf iicts, or oo ou uant the : to
resoi:e sstem confi ict`` :ettin the sstem to InI : sas that e:en if the machine
oetermines some kino of resource pro|iem, it shouio not attempt to hanoie it . . . .
Pather, it shoui o pass it on to the : to resoi:e the is sue. nfortunatei, the : can`t
resoi:e some issues . . . . uhich sometimes resui ts in a iock or other pro|i ems.
Ior sta|iiit reasons, it is |etter to set L1LPY mother|oaro`s InI : option to No,
rearoiess of manufacturer, |ut stiii aiiou the PI: to autoconfiure InI oe:ices. ]ust
iea:e the InI : to No. It uon`t hurt a thin, ou iose nothin, our machine uiii
stiii autoconfiure InI oe:ices, ano it uiii make our sstem more sta|ie.`
1o sum it all up, except tor certain cases, it is highly recommended that you to set this BIOS
teature to No, irrespective ot the operating sys tem you actually use. Lxceptions to this vould be
the inability ot the BIOS to contigure the devices properly in PnP mode and a specitic need to
manually contigure one or more ot the devices.
Post Writo Conbino
1his is similar to the USWC Write Posting BIOS teature.
Current proces sors are heavily optimized tor burst operations, vhich allovs tor very high mem-
ory bandvidth. Lntortunately, graphics vrites trom the processor are mostly pixel vrites that
are 8 to 32-bits in nature. Because they do not till up an entire cache line, such vrites are not
burstable.1his results in poor graphics vrite pertormance.
1o correct this deticiency, processors nov come vith one or more internal vrite combine
butters.1hese butters are designed to accumulate graphics vrites trom the processor. 1hese par-
tial or smaller vrites are then combined and vritten to the graphics card as burst vrites.
1he use ot these internal vrite combine butters provides many benetits:
1. Partial or smaller graphics vrites trom the process or are nov combined into burstable
vrites.1his greatly increases the pertormance ot the processor and AGP (or PCI, buses.
2. Graphics vrites require tever transactions on the processor and AGP (or PCI, bus. 1his
improves the bandvidth ot those buses.
3. 1he processor only needs to vrite to its internal vrite combine butters instead ot to the
processor bus. 1his improves its pertormance by alloving it to vork on other tasks vhile
the vrite combine butters handle the actual vrite transaction.
Because the vrite combine butters allov speculative reads, this teature is knovn as the USWC
(Uncached Speculative Write Conbining, teature.1he older method ot vriting all proces-
sor vrites directly to the graphics card is knovn as UC (UnCached,.
pertormance.
Please note that this teature also must be supported by the graphics card, the operating system,
and the graphics driver tor it to vork properly.
All Microsott operating systems trom Windovs N1 4.0 onvard support LSWC, so you do not
need to vorry it you are using a Windovs N1 4.0 or never operating system trom Microsott.
Because this teature has been around tor some time, drivers ot LSWC-compatible graphics
cards tully support this teature.
Older graphics cards make use ot a FIFO (First In, First Out, IO model, vhich can only
support the UnCached (UC, type ot transaction. Lnabling this teature vith such graphics cards
causes a host ot problems such as graphics artitacts, system crashes, and even the inability to boot
up properly.
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Prmary 0raphcs AdapIcr 27
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Powor On Iunction
Connon Options: Button Only, Keyboard 98, Hot Key, Mouse Iett, Mouse Pight
1his BIOS teature allovs you to select the method vith vhich to turn on your computer.
By detault, this teature is set to Button Only.1his allovs your computer to be started up only
through the use ot the pover button or svitch. Other available options:
A Keyboard 98-compatible keyboard (that comes vith a vake-up button,
A keyboard hot key (tor non-Keyboard 98 keyboards,
A mouse button (either the right or lett button,
It you select the Mouse Left option, the lett button ot the mouse is used to start up the sys-
tem.1he Mouse Right option selects the right mouse button as the pover on button instead.
Please note that only PS2 mice support the Mouse Left or Mouse Right options. Mice
using serial or LSB connections do not support this pover on tunction.
1he Keyboard 98 option only vorks it you are using Windovs 98 or better and have the
appropriate keyboard. 1hen you can use the keyboard`s vake-up or pover-on button to start up
the computer.
Older keyboards that do not contorm to the Ke|oaro 98 standard, and theretore do not have
the special vake-up button, can use the Hot Key option instead. 1here are 12 hot keys avail-
able: Ctrl-F1 through Ctrl-F12. Select the hot key you vant and you vill be able to start up
the computer using that hot key.
1here is no pertormance advantage in choosing any ot the options above. So, choose the option
that you are most comtortable vith.
Prinory Grophics Adoptor
the old PCI graphics card to support a second monitor. 1he PCI card can do the job just tine
detault vould be the AGP graphics card because, in most cases, it vould be the taster card.
Hovever, a BIOS svitch that allovs you to manually select the graphics card to boot the system
vith is still required.1his is particularly important it you have AGP and PCI graphics cards but
only one monitor. 1his is vhere the Prinary Graphics Adapter teature comes in. It allovs
you to select vhether to boot the system using the AGP graphics card or the PCI graphics card.
example, it you only use an AGP graphics card, then setting Primary Graphics Adapter to AGP
may speed up your system`s booting-up process.
Primary Graphics Adapter teature to the proper setting tor your system (AGP tor a single AGP
card and PCI tor a single PCI card,.
mary display card.
Prinory VGA BIOS
Connon Options: AGP VGA Card, PCI VGA Card
the old PCI graphics card to support a second monitor. 1he PCI card can do the job just tine
detault vould be the AGP graphics card because, in most cases, it vould be the taster card.
Hovever, a BIOS svitch that allovs you to manually select the graphics card to boot the system
vith is still required.1his is particularly important it you have AGP and PCI graphics cards but
only one monitor. 1his is vhere the Prinary VGA BIOS teature comes in. It allovs you to
select vhether to boot the system using the AGP graphics card or the PCI graphics card.
example, it you only use an AGP graphics card, then setting Primary VGA BIOS to AGP VGA
Card may speed up your system`s booting-up process .
Primary VGA BIOS teature to the proper setting tor your system (AGP VGA Card tor a single
AGP card and PCI VGA Card tor a single PCI card,.
Hovever, it you are using multiple graphics cards, it is up to you vhich card you vant to use
as your primary display card. It is recommended that you select the tastest graphics card as the
primary display card.
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PSj2 Mousc FuncIon LonIro| 20
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Procossor Nunbor Iooturo
1his BIOS teature allovs you to control the use ot the processor`s embedded unique identi-
fication nunber.1heretore, it is only valid it you are using a processor that teatures s uch
a teature.
1his intamous teature debuted in the Intel Pentium III processor and is mainly tound only in
that processor.1he 1ransmeta Crusoe processor also supports this teature. Hovever, most manu-
tacturers have retrained trom integrating such a teature in their processors. Lven Intel has
declined to add this teature to the Intel Pentium 4 processors.
It enabled, the processor`s identitication number can be read by external programs. It used to
be required tor certain secure transactions. Hovever, this is no longer true because the initiative
has long been abandoned.
It disabled, the processor`s identitication number cannot be read by external programs.
It is highly advisable that you disable this teature because it no longer has a use. Lven vorse, it
can actually be misused to track your online activities. Disabling this teature sateguards your pri-
vacy by preventing the identitication ot your computer by the processor`s identitication number.
PS/2 Mouso Iunction Control
Connon Options: Lnabled, Auto
IPQ12 is the interrupt usually reserved tor the PS2 mous e`s use.1his BIOS teature determines
vhether the BIOS should reserve IPQ12 tor the PS2 mouse or allov other devices to make
use ot this IPQ.
Setting this BIOS teature to Auto allovs the BIOS to allocate IPQ12 to the PS2 mouse it
the mouse is detected at startup. Othervise, IPQ12 is released tor use by other devices in the
system.
Setting this BIOS teature to Lnabled torces the BIOS to reserve IPQ12 even it a PS2 mouse
vas not detected at startup.
your BIOS to release IPQ12 tor other devices to use it it doesn`t detect the presence ot a PS2
mouse during startup.
Q
Q
Quick Boot
Hovever, it is not the same as the Quick Pover On Self 1est teature, vhich just shortens or
skips certain system tests. Quick Boot turther shortens the booting process by using a tev addi-
tional tricks.1heretore, the Quick Pover On Selt 1est should be considered a subset ot the
Quick Boot teature.
It enabled, the BIOS shortens the booting process by skipping some tests and shortening oth-
ers. In addition, it also pertorms the tolloving tricks to turther speed up the booting process:
Spin up the hard disks as soon as pover is supplied (or as soon as possible,
Initialize only critical parts ot the chipset
Pead memory size trom the SPD (Serial Presence Detect, chip on the memory
modules
Lliminate logo delays (inserted by many manutacturers,
diagnostic tests to detect any problems that may slip past Quick Boot`s abbreviated testing
scheme.
Quick Powor On SolI lost
It enabled, the BIOS shortens the booting process by skipping some tests and shortening
others.
diagnostic tests to detect any problems that may slip past the abbreviated testing scheme.
R
Ronk Intorloovo
Pank is a nev term used to ditterentiate physical banks on a particular memory module trom
internal banks vithin the memory chip. Single-sided memory modules have a single rank vhile
double-sided memory modules have tvo ranks.
1his BIOS teature is similar to SDRAM Bank Interleave. Interleaving allovs banks ot
SDPAM to alternate their retresh and access cycles. One bank undergoes its retresh cycle vhile
another is being accessed.1his improves memory pertormance by masking the retresh cycles ot
each memory bank.1he only ditterence is that Rank Interleave vorks betveen ditterent phys-
ical banks or, as they are called nov, ranks.
Because a minimum ot tvo ranks are required tor interleaving to be supported, double-sided
memory modules are a must it you vish to enable Pank Interleave. Lnabling Pank Interleave
vith single-sided memory modules does not result in any pertormance boost.
Please note that Pank Interleave currently vorks only it you are using double-sided memory
modules. Pank Interleave does not vork vith tvo or more single-sided memory modules.1he
interleaving ranks must be on the same memory module.
It is highly recommended that you enable Pank Interleave tor better memory pertormance.
You can als o enable Pank Interleave it you are using a mixture ot single- and double-sided
memory modules. Hovever, it you are using only single-sided memory modules, it`s advisable
to disable Pank Interleave.
Rood-Around-Writo
1his BIOS teature allovs the processor to execute read commands out ot order as it they are
independent trom the vrite commands. It does this by using a Pead-Around-Write butter.
It this BIOS teature is enabled, all processor vrites to memory are tirst accumulated in that
butter.1his allovs the processor to execute read commands vithout vaiting tor the vrite com-
mands to be completed.
1he butter then combines the vrites and vrites them to memory as burst transters.1his reduces
the number ot vrites to memory and boosts the process or`s vrite pertormance.
Incidentally, until its contents have been vritten to memory, the Pead-Around-Write butter
also serves as a cache ot the data that it is storing.1hese tend to be the most up-to-date data
because the process or has just vritten them to the butter.
1heretore, it the processor sends out a read command vhose memory address shovs that the
latest copy is still in the Pead-Around-Write butter, the processor can read directly trom the
butter instead.1his greatly improves read pertormance because the processor does not need to
vait tor the memory controller to access the data.1he butter is much closer logically, so reading
trom it is much taster than reading trom memory.
cad-Around-WrIc 271
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It this BIOS teature is disabled, the processor vrites directly to the memory controller.All
vrites have to be completed betore the processor can execute a read command. It also prevents
the butter trom being used as a temporary cache ot processor vrites.1his reduces the processor`s
read pertormance.
1heretore, it is highly recommended that you enable this teature tor better processor read and
vrite pertormance.
Rood Woit Stoto
1his BIOS teature determines hov long the memory controller should vait betore sending read
data to the data requester (tor example, processor, graphics card, and so torth,.
It this teature is set to 1 Cycle, the memory controller imposes a delay ot one clock cycle
betore the data is sent to the requester. 1his reduces memory read pertormance because the
memory controller delays the transter ot each piece ot requested data by one clock cycle.
In addition, read and vrite requests can overlap each other vhen the Pead Wait State is set to
1 Cycle. 1o prevent this, vhen this BIOS teature is set to 1 Cycle, the memory controller
automatically inserts an additional delay cycle betveen every read cycle that is tolloved imme-
diately by a vrite cycle.
1his is similar to disabling the Fast R-W 1urn Around teature. 1his results in reduced mem-
ory vrite pertormance.
It this teature is set to 0 Cycle, the memory controller transters read data to the data requester
vithout any delay.1his improves memory read pertormance. It also improves memory vrite
pertormance because there is no longer a need to insert an additional delay cycle to prevent
read and vrite requests trom overlapping each other.
1heretore, it is recommended that you set the Pead Wait State to 0 Cycle tor better memory
read and vrite pertormance.
Please note that this may cause system instabilities in certain contigurations.When that happens,
just reset the value to 1 Cycle.
RoIrosh Intorvol
Connon Options: 7.8 sec, 13.6 sec, 31.2 sec, 64 sec, 128 sec, Auto
ditterent rov every 1S.6 sec (64,000 sec 4096 rovs = 13.6 sec,. 1his reduces the amount
being retreshed.
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cfrcsh Modc Sc|ccI 278
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Lsually, memory modules that use 128Mbit or smaller memory chips have 4096 rovs vhile
nov tvice as many rovs to serviced vithin the stipulated 64 msec tor the entire chip.
sec, vhile those tor 236Mbit or larger memory chips are 7.8 sec. Please note that it you are
using a mix ot 128Mbit and 236Mbit memory modules, the tail-sate Petresh Interval is 7.8
sec, not 13.6 sec.
lor better pertormance, you should consider increasing the Refresh Interval trom the detault
values (13.6 sec tor 128Mbit or smaller memory chips and 7.8 sec tor 236Mbit or larger
memory chips, up to 128 sec. Please note that it you increase the Refresh Interval too
much, the memory cells may lose their contents.
1heretore, you should start vith small increases in the Refresh Interval and test your system
atter each hike betore increasing it turther. It you tace stability problems upon increasing the
retresh interval, reduce the retresh interval step by step until the system is stable.
RoIrosh Modo Soloct
ditterent rov every 1S.6 sec (64,000 sec 4096 rovs = 13.6 sec,.1his reduces the amount
being retreshed.
Lsually, memory modules that use 128Mbit or smaller memory chips have 4096 rovs, vhile
nov tvice as many rovs to serviced vithin the stipulated 64 msec tor the entire chip.
sec, vhile those tor 236Mbit or larger memory chips is 7.8 sec. Please note that it you are
using a mix ot 128Mbit and 236Mbit memory modules, the tail-sate Petresh Mode Select is
7.8 sec, not 13.6 sec.
lor better pertormance, you should consider increasing the Refresh Mode Select trom the
larger memory chips, up to 128 sec. Please note that it you increase the Refresh Mode
Select too much, the memory cells may lose their contents.
1heretore, you should start vith small increases in the Refresh Mode Select and test your sys-
tem atter each hike betore increasing it turther. It you tace stability problems upon increasing
Roport No IDD Ior Win9$
1his BIOS teature allovs you to set vhether the BIOS should report the absence ot a tloppy
disk drive to Windovs 93.
lor some reason, the Microsott Windovs 93 operating system requires a tloppy dis k drive to be
present. Hovever, in an age ot LSB tlash media and CDDVD vriters, not all computers come
vith a tloppy disk drive. Such computers tail to boot up Windovs 93 vithout a tloppy disk
drive.
1heretore, to meet Microsott Windovs 93`s logo certitication, and yet allov computers sans
tloppy disk drives to boot Windovs 93 normally, motherboards provide this BIOS teature.
It this teature is enabled, the BIOS assigns IPQ 6 (vhich is designated tor the tloppy disk
drive`s use, to another device, presumably to trick Windovs 93 into thinking that a tloppy
disk drive exists. 1his allovs computers vith no tloppy disk drives to boot into Windovs 93
normally.
It this teature is disabled,Windovs 93 detects the absence ot the tloppy disk drive and halts the
system vith an error message.
It you are using Windovs 93 uithout a tloppy disk drive, you have to enable this teature to
allov Windovs 93 to boot up normally.
It you are using Windovs 93 uith a tloppy disk drive, you can enable or disable this teature.
Windovs 93 boots up normally either vay.
Please note that this BIOS teature has no relevance in other operating systems. Only Windovs 93
is attected. It does not matter vhat you s et this BIOS option to it you are using other operating
systems.
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Rosot ConIigurotion Doto
1he LSCD (Ltended Systen Configuration Data, is a teature ot the Plug and Play BIOS
that allovs the BIOS to re-use system contiguration data.
Whenever the BIOS boots up, it needs to contigure the ISA, PCI and AGP devices in the sys-
tem (Plug and Play-capable or othervise,. Hovever, because the installed devices are unlikely to
change trom one booting to another, the system contiguration data actually remains the same.
1heretore, it it can be stored and re-used, the BIOS can skip contiguring the same devices every
time you boot up the system.
1his is vhere the LSCD teature comes in. It stores the IPQ, DMA, IO and memory contigu-
rations ot your system`s devices in a special area ot the BIOS llash POM.1he BIOS s noops and
re-uses the stored contiguration data vhen it boots up the system. As long as there are no hard-
vare changes, the BIOS does not need to recontigure the LSCD.
BIOS automatically detects the changes and recontigures the LSCD.1heretore, there is usually
no need to manually torce the BIOS to recontigure the LSCD.
result.1his is vhere the Reset Configuration Data BIOS teature comes in.
rebooting.
Rosourco Controllod By
1his BIOS teature determines vhether the BIOS should automatically contigure IPQ and
DMA resources.
It this teature is set to Auto, the BIOS automatically assigns IPQs and DMA channels tor all
your devices. All IPQ and DMA assignment tields belov this BIOS teature disappear or
become grayed out.
It this teature is set to Manual, the BIOS allovs you to manually contigure the IPQs and
DMA channels tor your devices.
1he BIOS is generally capable ot automatically contiguring IPQ and DMA resources tor the
devices in your computer.1heretore, it is advis able that you set this teature to Auto.
Hovever, it the BIOS has problems assigning the resources properly, you can select the Manual
option to reveal the IPQ and DMA assignment tields.You can then assign each IPQ or DMA
channel to either Legacy ISA or PCI/ISA PnP devices.
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Legacy ISA devices are compliant vith the original PC A1 bus specitication and require a spe-
citic interrupt andor DMA channel to tunction properly. PCI/ISA PnP devices, on the other
hand, adhere to the Plug and Play standard and can use any interrupt or DMA channel.
RD, lD Activo
Connon Options: Hi, Hi or Io, Io or Hi, Io or Io, Hi
polarity.
out.
1here are tour options available, based on combinations ot Hi and Io.You`ll need to consult
your IP peripheral`s documentation to determine the correct polarity. Choosing the vrong
polarity prevents a proper IP connection trom being established vith the IP peripheral.
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S2R Bus Driving Strongth
1he S2K bus is another name tor the AMD Athlon processor bus.1heretore, this BIOS teature
determines vhether the motherboard chipset should automatically adjust the drive strength ot
the Athlon processor bus or allov manual contiguration.
It you set this teature to Auto, the chipset is alloved to dynamically adjust the S2K bus strength
or use values pre-set by the manutacturer.
It you set this teature to Manual, the chipset`s dynamic compensation circuitry tor the S2K bus
is turned ott.You can then manually set the S2K bus strength.
Generally, it is recommended that you set this teature to Auto, so the S2K bus strength can be
dynamically adjusted by the chipset. Hovever, there may be occasions vhen manual contigura-
tion ot the S2K bus driving strength may be desirable.
It is possible to make use ot this teature tor overclocking purposes. Increasing the drive strength
increases the stability ot the S2K bus by reducing the impedance trom the motherboard and
boosting the signal strength. Hovever, please be very circumspect vhen you increase the S2K
bus drive strength vith an overclocked processor because you may irreversibly damage the
processor'
It you vant to manually contigure the S2K bus driving strength, you must set the S2K Bus
Driving Strength to Manual. 1his allovs you to manually set the S2K bus driving strength
value through the S2K Strobe P Control and S2K Strobe N Control BIOS teatures.
S2R Strobo N Control
1his BIOS teature determines the N transistor drive strength ot the S2K bus. It is used in con-
junction vith S2K Bus Driving Strength and S2K Strobe P Control to bypass the moth-
erboard chipset`s dynamic compensation tor the S2K bus.
It is slaved to the Manual option ot the S2K Bus Driving Strength teature.1heretore, it you
set S2K Bus Driving Strength to Auto, then the value you choose tor this tunction has no
ettect. lor this tunction to have any ettect, you must set S2K Bus Driving Strength to Manual.
1he N transistor drive strength is represented by Hex values trom 0 to F (0 to 1S in decimal,.
1he detault N transistor drive strength ditters betveen motherboards. Hovever, the higher the
bus. A higher N (and P, transistor drive strength may be just vhat you need to overclock the
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increase the N transistor drive strength unnecessarily.
S2R Strobo P Control
1his BIOS teature determines the P transistor drive strength ot the S2K bus. It is used in con-
junction vith S2K Bus Driving Strength and S2K Strobe P Control to bypass the moth-
erboard chipset`s dynamic compensation tor the S2K bus.
It is slaved to the Manual option ot the S2K Bus Driving Strength teature.1heretore, it you
set S2K Bus Driving Strength to Auto, then the value you choose tor this tunction has no
ettect. lor this tunction to have any ettect, you must set S2K Bus Driving Strength to Manual.
1he P transistor drive strength is represented by Hex values trom 0 to F (0 to 1S in decimal,.
1he detault P transistor drive strength ditters betveen motherboards. Hovever, the higher the
bus. A higher P (and N, transistor drive strength may be just vhat you need to overclock the
increase the P transistor drive s trength unnecessarily.
SDRAM 1l Connond
Whenever there is a memory read request trom the operating system, the memory controller
does not actually receive the physical memory addresses vhere the data is located. It is only
given a virtual address space, vhich it has to translate into physical memory addresses. Only then
can it issue the proper read commands.1his produces a slight delay at the start ot every nev
memory transaction.
Instead ot immediately issuing the read commands, the memory controller asserts the Chip
Select signal to the physical bank that contains the requested data. What this Chip Select signal
does is activate the bank, so it is ready to accept the commands. In the meantime, the memory
controller is busy translating the memory addresses. Atter the memory controller has the physical
memory addresses, it starts issuing read commands to the activated memory bank.
As you can see, the command delay is not caused by any latency inherent in the memory mod-
ule. Pather, it is determined by the time taken by the memory controller to translate the virtual
address space into physical memory addresses.
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Naturally, because the delay is due to translation ot addresses, the memory controller requires
more time to translate addresses in high-density memory modules due to the higher number ot
addresses.1he memory controller also takes a longer time it there is a large number ot physical
banks.
bank.
clock cycle or 11.
cycles or 21.
command delay.
corruption.
lortunately, all unbuttered SDPAM modules are capable ot a 11 command delay up to tour
memory banks per channel. Atter that, a 21 command delay may be required. Hovever, support
tor 11 command delay varies betveen chipsets and even betveen motherboard models.You
should consult your motherboard manutacturer to see vhether your motherboard supports a
command delay ot 11.
It is recommended that you enable SDPAM 11 Command tor better memory pertormance.
Hovever, it you tace stability is sues, disable this BIOS teature.
SDRAM 1l Connond Control
given a virtual address space, vhich it has to translate into physical memory addresses. Only then
memory transaction.
controller is busy translating the memory addresses. Atter the memory controller has the physical
memory addresses, it starts issuing read commands to the activated memory bank.
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banks.
bank.
clock cycle or 11.
cycles or 21.
command delay.
to translate the addresses in time and the bad commands that result cause data loss and cor-
ruption.
should consult your motherboard manutacturer to see vhether your motherboard supports a
command delay ot 11.
It is recommended that you enable SDPAM 11 Command Control tor better memory per-
tormance. Hovever, it you tace stability issues, disable this BIOS teature.
SDRAM Activo to Prochorgo Doloy
Whenever a read command is issued, a memory rov is activated using the RAS (Rov Address
Strobe,.1hen, to read data trom the target memory cell, the appropriate column is activated
using the CAS (Colunn Address Strobe,. Multiple cells can be read trom the same active
rov by applying the appropriate CAS signals.
Hovever, vhen data has to be read trom a ditterent rov, the active rov has to be deactivated.
Hovever, the rov cannot be deactivated until the Mininun Rov Active 1ine or tRAS has
elapsed.
specitications, it is the fourth number in the tour-number sequence. lor example, it your memo-
ry module has the rated timings ot 2-3-4-7, its rated tPAS delay vould be 7 clock cycles.
Iike DRAM Act to PreChrg CMD, this BIOS teature controls the memory bank`s tRAS.
1his constitutes the time vhen a rov is activated until the time the same rov can be deactivated.
It is also the length ot time the rov vill remain open tor data transters.
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SDRAM Bonk Intorloovo
Connon Options: 2-Bank, 4-Bank, Disabled
1his BIOS teature enables you to set the interleave mode ot the SDPAM intertace.
Interleaving allovs banks ot SDPAM to alternate their retresh and access cycles. One bank
undergoes its retresh cycle vhile another is being accessed.1his improves memory pertormance
by masking the retresh cycles ot each memory bank. A close examination reveals that because
the retresh cycles ot all the memory banks are staggered, this produces a kind ot pipelining
ettect.
It there are tour banks in the system, the processor can ideally send one data request to each
memory bank in just tour clock cycles. In the tirst clock cycle, the processor sends an address to
Bank 0 and then sends the next address to Bank 1 in the second clock cycle betore sending the
third and tourth addresses to Banks 2 and 3 in the third and tourth clock cycles, res pectively.
1he sequence looks something like this:
1. Processor sends address 0 to Bank 0
2. Processor sends address 1 to Bank 1 and receives data 0 trom Bank 0
S. Processor receives data 3 trom Bank 3
As you can see, the data trom all tour requests arrives consecutively trom the memory banks
vithout any delay in betveen. Hovever, it interleaving vas not enabled, the same 4-address
transaction may appear like this (vorst-case scenario,:
1. SDPAM retreshes
2. Processor sends address 0 to SDPAM
3. Processor receives data 0 trom SDPAM
4. SDPAM retreshes
S. Processor sends address 1 to SDPAM
7. SDPAM retreshes
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10. SDPAM retreshes
With interleaving enabled, the tirst bank can start transterring data to the processor in the same
cycle that the second bank receives an address. Hovever, it interleaving is disabled, the processor
has to send the address to the memory bank, receive the requested data, and then vait tor the
memory bank to retresh betore initiating the second data transaction. 1his vastes a lot ot clock
cycles and res ults in reduced bandvidth.
Interleaving allovs you to mask the retresh cycles. 1his essentially produces a pipelining ettect
that greatly increases throughput.
Hovever, bank interleaving only vorks it the addresses requested consecutively are not in the
same bank. It they are in the same memory bank, then the data transactions behave as it the
banks vere not interleaved.1he processor has to vait until the tirst data transaction clears and
that memory bank retreshes betore it can send another address to that bank.
Lach SDPAM module is internally divided into either tvo or four banks ot memory. Double-
banked SDPAM modules generally use 16Mbit SDPAM chips and are usually 32MB or
smaller in size. Quad-banked SDPAM modules, on the other hand, usually use higher density
(64Mbit-2S6Mbit, SDPAM chips. All SDPAM modules ot at least 64MB in size are quad-
banked in nature.
It you are using a sinie double-banked SDPAM module, set this teature to 2-Bank.1his is the
only option available tor the single double-banked SDPAM module.
It you are using at least tuo double-banked SDPAM modules, you can use the 4-Bank option
as vell as the 2-Bank option. Ot course, it is recommended that you select 4-Bank tor better
interleaving pertormance.
It you are using quad-banked SDPAM modules, you can use either interleave options. Ot
course, it is recommended that you select 4-Bank tor better interleaving pertormance.
Because a 4-bank interleave alvays allovs tor better interleaving pertormance, it is highly rec-
ommended that you select the 4-Bank option it your system supports it. Lse the 2-Bank
option only it you are using a single double-banked SDPAM module.
Please note that Avard (nov part ot Phoeni 1echnologies, recommends that SDPAM bank
interleaving be disabled it 16Mbit SDPAM modules are used.1his is because early 16Mbit
SDPAM modules have stability problems vith bank interleaving.1he good nevs is all current
SDPAM modules support bank interleaving.
1he Bank-to-Bank Delay or tRRD is a DDP timing parameter that specities the minimum
amount ot time betveen success ive AC1IVA1L commands to the same DDP device, even to
different internal banks.1he shorter the delay, the taster the next bank can be activated tor read
or vrite operations. Hovever, because rov activation requires a lot ot current, using a short
delay may cause excessive current surges.
important.1his is because the desktop PC essentially has an unlimited pover supply and even
the most basic desktop cooling solution is sutticient to dispel any extra thermal load that the
current surges may impose. 1he pertormance benetit ot using the shorter 2 cycles delay is ot tar
greater interest. 1he shorter delay means every back-to-back bank activation takes one clock
cycle less to pertorm. 1his improves the DDP device`s read and vrite pertormance.
are stability problems vith the 2 cycles setting.
In mobile devices like laptops hovever, it is advisable to use the longer delay ot 3 cycles. Doing
so limits the current surges that accompany rov activations. 1his reduces the DDP device`s
pover consumption and thermal output, both ot vhich should be ot great interest to the road
varrior.
SDRAM Burst Lon
1his is the same as the SDRAM Burst Length BIOS teature, only vith a veirdly truncated
name. Surprisingly, many manutacturers are using it.Why Only they knov.:
column.1he subsequent reads or vrites in that burst sequence then can tollov behind vithout
burst transactions.
is 9 clock cycles longer or more than tvice as slov as a burst transaction.
1his is vhere the SDRAM Burst Len BIOS teature comes in. It is a BIOS teature that allovs
you to control the length ot a burst transaction.
four vrites.
eight vrites.
S0AM 8ursI Lcn 288
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lor example, it the memory controller vants to vrite a block ot contiguous data 8 units long
to memory, it can do it as a sinie burst transaction 8 units long or tuo burst transactions, each
4 units in length. 1he hypothetical latencies incurred by the single 8-unit long transaction
gle transaction 8 units long.
SDRAM Burst Longth
column.1he subsequent reads or vrites in that burst sequence then can tollov behind vithout
burst transactions.
is 9 clock cycles longer or more than tvice as slov as a burst transaction.
1his is vhere the SDRAM Burst Length BIOS teature comes in. It is a BIOS teature that
allovs you to control the length ot a burst transaction.
four vrites.
eight vrites.
lor example, it the memory controller vants to vrite a block ot contiguous data 8 units long
to memory, it can do it as a sinie burst transaction 8 units long or tuo burst transactions, each
4 units in length. 1he hypothetical latencies incurred by the single 8-unit long transaction
gle transaction 8 units long.
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S0AM Lommand Lcadoff Jmc 286
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SDRAM CAS Lotoncy lino
Whenever a read command is issued, a memory rov is activated using the RAS.1hen, to read
data trom the target memory cell, the appropriate column is activated using the CAS.
Multiple cells can be read trom the same active rov by applying the appropriate CAS signals.
Hovever, there is a short delay atter each assertion ot the CAS s ignal betore data can be read
trom the target memory cell.1his delay is knovn as the CAS latency.
specitications, it is the first number in the three or tour number sequence. lor example, it your
memory module has the rated timings ot 2-3-4-7, its rated CAS latency vould be 2 clock
cycles.
1his BIOS teature controls the delay (in clock cycles, betveen the assertion ot the CAS signal
and the availability ot the data trom the target memory cell. It also determines the number ot
clock cycles required tor the completion ot the tirst part ot a burst transter. In other vords, the
lover the CAS latency, the taster memory reads or vrites can occur.
Because column activation occurs every time a nev memory cell is read trom, the ettect ot
CAS latency on memory pertormance is signiticant, especially vith SDP SDPAM. Its ettect is
les s obvious in DDP SDPAM.
1his is particularly true tor DDP SDPAM memory because CAS latency has much less ettect
on pertormance vith such memory, compared to the older SDP memory.1he improvement in
overclockability vith higher CAS latencies cannot be underestimated. It you are interested in
overclocking your DDP SDPAM modules, you might vant to consider increasing the CAS
latency. 1he huge increase in overclockability tar outveighs the minor loss in pertormance.
SDRAM Connond LoodoII lino
1o meet ditterent timing requirements, the memory controller drives signals onto the address
and command lines one clock cycle betore they are actually needed.1his gives the memory
controller some additional time to meet the timing requirements ot the motherboard.
Although you may think that the early assertion ot the address and command lines helps
improve pertormance, that is not true. Lven it the memory controller drives the address and
command signals one clock cycle earlier, those signals are only latched onto the memory
module vhen none ot the memory banks are active.
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Once the signals are latched onto the memory module, the target bank is activated and the
memory controller starts reading trom the active bank. Nov, because ot the pre-driving ot the
address and command lines, the activation ot the target memory bank is controlled by the con-
nand leadoff tine.
the memory module.
SDPAM Command Ieadott 1ime to 3 clock cycles tor better memory pertormance.
SDRAM Connond Roto
given a virtual address space that it has to translate into physical memory addresses. Only then
memory transaction.
controller is busy translating the memory addresses. Once the memory controller has the physi-
cal memory addresses, it starts issuing read commands to the activated memory bank.
banks.
bank.
corruption.
should consult your motherboard manutacturer to see it your motherboard supports a command
delay ot 11.
It is recommended that you try the 11 command delay tor better memory pertormance.
Hovever, it you tace stability is sues, increase the command delay to 21.
SDRAM Cyclo Longth
Multiple cells can be read trom the same active rov by applying the appropriate CAS signals.
Hovever, there is a short delay atter each assertion ot the CAS s ignal betore data can be read
trom the target memory cell.1his delay is knovn as the CAS latency.
specitications, it is the first number in the three or tour number sequence. lor example, it your
memory module has the rated timings ot 2-3-4-7, its rated CAS latency vould be 2 clock
cycles.
1his BIOS teature is same as the SDRAM CAS Latency 1ine BIOS teature. It controls the
delay (in clock cycles, betveen the assertion ot the CAS signal and the availability ot the data
trom the target memory cell. It also determines the number ot clock cycles required tor the
completion ot the tirst part ot a burst transter. In other vords , the lover the CAS latency, the
taster memory reads or vrites can occur.
Because column activation occurs every time a nev memory cell is read trom, the ettect ot
CAS latency on memory pertormance is signiticant, especially vith SDP SDPAM. Its ettect is
les s obvious in DDP SDPAM.
1his is particularly true tor DDP SDPAM memory because CAS latency has much less ettect
on pertormance vith such memory compared to the older SDP memory. 1he improvement in
overclockability vith higher CAS latencies cannot be underestimated. It you are interested in
overclocking your DDP SDPAM modules, you might vant to consider increasing the CAS
latency. 1he huge increase in overclockability tar outveighs the minor loss in pertormance.
S0AM Lyc|c LcngIh 287
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SDRAM Cyclo lino lros/lrc
1his BIOS teature determines the tRAS and the tRC parameters ot the SDPAM memory
module.
tRAS reters to the SDPAM Rov Active 1ine, vhich is the length ot time the rov remains
open tor data transters.
tRC, on the other hand, reters to the SDPAM Rov Cycle 1ine, vhich determines the mini-
mum number ot clock cycles a memory rov takes to complete a tull cycle, trom rov activation
up to the precharging ot the active rov.
1he detault setting is 6/8, vhich is more stable and slover than S/6.1he S/6 setting cycles
taster, hovever, it may not leave the rov open long enough tor burst transactions to complete.
When this happens, data may be lost and the contents ot the memory cells may be corrupted.
1his is especially true at clock speeds above 100MHz.
lor better memory pertormance, you should try the S/6 setting. Hovever, increase it to 6/8 it
your system becomes uns table.You can also use the slover 6/8 setting it you are trying to over-
clock your memory modules because increasing the timings may allov them to run at a higher
clock speed.
SDRAM LCC Sotting
Connon Options: Disabled, Check Only, Correct Lrrors , CorrectScrub
1his BIOS teature is the extended version ot the DRAM Data Integrity Mode BIOS tea-
ture. It is tound in never chipsets that support more than just simple LCC (Lrror Checking
and Correction,.
1his BIOS teature controls the enhanced error correcting capabilities ot the memory controller,
vhich includes memory scrubbing.1here are actually tive LCC modes, although only tour are
ot practical use and available through this BIOS teature:
Disabled
Check Only
Correct Lrrors
CorrectScrub
1he tirst mode is Disabled, vhich disables the memory controller`s LCC capabilities. It you are
not using LCC memory modules, you must select this option. It you are using LCC memory
modules, this mode provides the best memory pertormance, although it doesn`t improve data
integrity at all.
1he Check Only mode torces the memory controller to only check tor errors. 1he memory
controller detects and reports single- and double-bit errors, hovever, it does not correct them.
1his mode otters minimal pertormance degradation, but it doesn`t improve data integrity at all.
It you select the Correct Lrrors mode, the memory controller not only checks tor and detects
single- and double-bit errors, it also corrects single-bit errors.1he correction ot single-bit errors
takes up one extra clock cycle, so this mode has a higher overhead.1he plus side is it improves data
integrity by seamlessly correcting single-bit errors. Double-bit errors are not corrected, hovever.
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S0AM Id|c LmI 280
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1he tinal LCC mode is Correct+Scrub, vhich is the most reliable LCC mode. It combines
LCC vith memory scrubbing.With this mode enabled, the memory controller not only detects
multiple-bit errors and corrects single-bit errors, it also vrites the corrected single-bit value
back into memory' 1his otters the highest level ot data integrity ot all tour modes. Hovever, the
scrubbing operation results in even more overhead.
Generally speaking, the Check Only mode isn`t particularly usetul because it only otters error
checking and reporting. Lsers ot LCC memory modules s hould tocus mainly on the Correct
Lrrors and Correct+Scrub modes because they actually improve data integrity by correcting
single-bit errors. Ot course, it you are using normal, non-LCC memory modules, you must
select the Disabled mode'
lor more intormation on hov LCC vorks, please reter to the DRAM Data Integrity Mode
BIOS teature.
SDRAM Idlo Linit
Connon Options: Disabled, 0 Cycle, 8 Cycles, 12 Cycles, 16 Cycles, 24 Cycles, 32 Cycles,
48 Cycles
1he memory controller allovs a number ot memory pages to remain open. It a processor cycle
to the SDPAM talls vithin those open pages, it can be satistied vithout delay. 1his naturally
Hovever, these pages can only remain open tor so long. 1hey eventually have to be closed and
precharged. It the page closes vhen the memory controller attempts to read trom it, then the
read operation is stalled until the page is activated again. Such a page miss is expensive in terms
ot clock cycles.
1his is vhere the SDRAM Idle Linit BIOS teature comes in.1his teature sets the number ot
idle cycles that is alloved betore the memory controller torces such open pages to close and
precharge.
concept, the longer the open page is lett idle, the less likely it is accessed again betore it needs to
be precharged.1heretore, it vould be better to prematurely close and precharge the page, so it
It can be set to a variety ot clock cycles trom 0 Cycle to 48 Cycles.1his sets the number ot
clock cycles the open pages are alloved to idle betore they are closed and precharged. Disabled
is also an option.
It you select Disabled, the memory controller never precharges the open pages prematurely.
1he open pages are lett activated until they have to be precharged.
1he detault value is 8 cycles, vhich allovs the memory controller to precharge the open pages
atter 8 idle cycles have passed.
Increasing the SDPAM Idle Iimit to more than the detault ot 8 cycles allovs the SDPAM
bank to delay recharging longer during times ot no activity, so it a read or vrite command
comes along, it can be instantly satistied.
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Hovever, this is limited by the retresh cycle already set by the BIOS.1hat means the open page
retreshes vhen it needs to be recharged vhether or not the number ot idle cycles have reached
the SDPAM Idle Iimit. So, the SDPAM Idle Iimit setting only can be used to torce the
retreshing ot the SDPAM bank |efore the set retresh cycle but not to actually delay the retresh
cycle.
Peducing the number ot cycles trom the detault ot 8 cycles to 0 cycles torces the memory
controller to close all open pages atter no valid requests are sent to the memory controller. In
short, the open pages are retreshed as soon as data reques ts stop coming.1heoretically, this ma
increase the etticiency ot the memory s ubsystem becaus e the ettects ot retreshing the open
pages are masked by precharging during idle cycles. Hovever, any data requests that comes
along atter the page is closed have to vait until it is retreshed and activated betore they can
be satistied.
Because retreshes do not occur that otten (usually only about once every 64 msec,, the impact
ot retreshes on memory pertormance is really quite minimal.1he apparent benetits ot masking
the retreshes during idle cycles is not noticeable, especially because memory systems these days
already use bank interleaving to mask retreshes.
With a 0 cycle setting, data requests are also likely to get stalled because even a single idle cycle
causes the memory controller to close aii open pages' In desktop applications, most memory
reads tavor the spatial locality concept vhereby it one data bit is read, chances are high that
the next data bit is also read.1hat`s vhy closing open pages prematurely using SDPAM Idle
Iimit mos t likely causes reduced pertormance in desktop applications.
On the other hand, using a 0 or 8 idle cycles limit ensures that all memory contents are
retreshed more otten, thereby preventing the loss ot data due to insutticiently retreshed memory
cells. lorcing the memory controller to precharge open pages more otten also ensures that in
the event ot a very long read, the pages can be opened long enough to tultill the data request.
lor general desktop use, it is recommended that you disable this teature, so precharging can be
delayed tor as long as possible.1his reduces the number ot retreshes and increases the ettective
memory bandvidth.
you select 0 Cycle because subsequent data requests are most likely tultilled by other pages.
Closing open pages to precharge prepares those pages tor the next data request that hits them.
1here`s also the added benetit ot increased data integrity due to more trequent retreshes.
Alternatively, you can greatly increase the value ot the Refresh Interval or Refresh Mode
Select teature to boost bandvidth and use this BIOS teature to maintain the data integrity ot
the memory cells .As ultra-long retresh intervals (tor example, 64 or 128 sec, can cause memo-
ry cells to lose their contents, setting a lov SDPAM Idle Iimit, like 0 Cycle or 8 Cycles,
allovs the memory cells to be retreshed more otten vith a high chance ot those retreshes being
done during idle cycles.1his appears to combine the best ot both vorldsa long bank active
period vhen the memory controller is being stressed and more retreshes vhen the memory
controller is idle.
In reality, hovever, this is not a reliable vay ot ens uring sutticient retresh cycles because it
depends on the vagaries ot memory usage to provide sutticient idle cycles to trigger the retresh-
es. It your memory subsystem is under extended load, there may not be any idle cycle to trigger
an early retresh.1his may caus e the memory cells to lose their contents.
1heretore, it is recommended that you maintain a proper retres h interval and disable this tea-
ture (tor desktops,. 1his allovs you to boost memory bandvidth, by delaying retreshes tor as
long as possible, and still maintain the data integrity ot the memory cells through regular and
reliable retresh cycles.
lor servers, it is recommended that you maintain a proper retresh interval and use the 0 Cycle
setting. 1his precharges all open pages vhenever there`s an idle cycle.
SDRAM LoodoII Connond
1his BIOS teature is actually a misnomer. It actually should be called the SDRAM Connand
Leadoff 1ine.
1o meet ditterent timing requirements, the memory controller vill drive signals onto the
address and command lines one clock cycle betore they are actually needed. 1his gives the
memory controller some additional time to meet the timing requirements ot the motherboard.
Although you may think that the early assertion ot the address and command lines vill help
improve pertormance, that is not true. Lven it the memory controller drives the address and
command signals one clock cycle earlier, those signals are only latched onto the memory mod-
ule vhen none ot the memory banks are active.
Once the signals are latched onto the memory module, the target bank is activated and the
memory controller starts reading trom the active bank. Nov, because ot the pre-driving ot the
address and command lines, the activation ot the target memory bank is controlled by the con-
nand leadoff tine.
the memory module.
SDPAM Ieadott Command to 3 clock cycles tor better memory pertormance.
SDRAM Pogo Closing Policy
Connon Options: One Bank, All Banks
1his BIOS teature is similar to SDRAM Precharge Control.
1he memory controller allovs up to tour pages to be opened at any one time. 1hese pages have
to be in separate memory banks and only one page may be open in each memory bank. It a
read request to the SDPAM talls vithin those open pages, it can be satistied vithout delay.1his
naturally improves pertormance.
S0AM Pagc L|osng Po|cy 201
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Hovever, it a read request cannot be satistied by any ot the tour open pages, there are tvo pos-
sibilities. Lither one page is closed and the correct page opened or all open pages are closed and
nev pages opened up. Lither vay, the read request sutters the tull latency penalty.
1his BIOS teature determines it the chipset should try to leave the pages open (by closing just
one open page, or keep them closed (by closing all open pages, vhenever there is a page miss.
1he One Bank setting torces the memory controller to close only one page vhenever a page
miss occurs.1his allovs the other open pages to be accessed at the cost ot only one clock cycle.
cause up to four tull latency reads to occur. Naturally, this greatly impacts memory pertormance.
lortunately, atter the tour tull latency reads, the memory controller can otten predict vhat pages
are needed next. It then can open them tor minimum latency reads.1his somevhat reduces the
negative ettect ot consecutive page misses.
1he All Banks setting, on the other hand, torces the memory controller to send an All Banks
Precharge Connand to the SDPAM intertace vhenever there is a page miss.1his causes all
the open pages to close (precharge,.1heretore, subsequent reads only need to activate the neces-
sary memory bank.
1his is usetul in cases vhere subsequent data requests also result in page misses. 1his is because
the memory banks already are precharged and ready to be activated. 1here is no need to vait
tor the memory banks to precharge betore they can be activated. Hovever, it also means that
you von`t be able to benetit trom data accesses that could have been satistied by the previously
opened pages.
better pertormance vith the One Bank setting because the open pages allov very tast accesses.
1he All Banks setting, hovever, has the advantage ot keeping the memory contents retreshed
1heretore, it is recommended that you select the One Bank setting tor better memory per-
tormance.1he All Banks setting can improve data integrity but it you are keeping the
SDPAM retresh interval vithin specitication, then it is ot little use.
SDRAM Pogo Hit Linit
is knovn as a page hit.
Normally, consecutive page hits otter the best memory pertormance tor the requesting device.
Hovever, a tlood ot consecutive page hit requests can cause non-page hit requests to be delayed
tor an extended period ot time.1his does not allov tair system memory access to all devices
and may cause problems tor devices that generate non-page hit requests.
request.
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Please note that vhatever you set tor this BIOS teature determines the maximum number ot
consecutive page hits, irrespective ot vhether the page hits are trom the same memory bank or
ditterent memory banks.1he detault value is otten 8 consecutive page hit accesses (described
erroneously as cycles,.
Generally, the detault value ot 8 Cycles should provide a balance betveen pertormance and
tair memory access to all devices. Hovever, you can try using a higher value (16 Cycles, tor
better memory pertormance by giving priority to a larger number ot consecutive page hit
requests. A lover value is not advisable because this normally results in a higher number ot
page interruptions.
SDRAM PH Linit
is knovn as a page hit (PH,.
Normally, consecutive page hits otter the best memory pertormance tor the requesting device.
Hovever, a tlood ot consecutive page hit requests can cause non-page hit requests to be delayed
tor an extended period ot time.1his does not allov tair system memory access to all devices
and may cause problems tor devices that generate non-page hit requests.
request.
Please note that vhatever you set tor this BIOS teature determines the maximum number ot
consecutive page hits, irrespective ot vhether the page hits are trom the same memory bank or
ditterent memory banks.1he detault value is otten 8 consecutive page hit accesses (described
erroneously as cycles,.
Generally, the detault value ot 8 Cycles should provide a balance betveen pertormance and
tair memory access to all devices. Hovever, you can try using a higher value (16 Cycles, tor
better memory pertormance by giving priority to a larger number ot consecutive page hit
requests. A lover value is not advisable because this normally results in a higher number ot
page interruptions.
SDRAM Prochorgo Control
1his BIOS teature is similar to SDRAM Page Closing Policy.
naturally improves pertormance.
S0AM Prcchargc LonIro| 208
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Hovever, it a read request cannot be satistied by any ot the tour open pages, there are tvo pos-
sibilities. Lither one page is closed and the correct page opened or all open pages are closed and
nev pages opened up. Lither vay, the read request sutters the tull latency penalty.
1his BIOS teature determines vhether the chipset s hould try to leave the pages open (by clos-
ing just one open page, or keep them closed (by closing all open pages, vhenever there is a
page miss.
When enabled, the memory controller only closes one page vhenever a page miss occurs.1his
allovs the other open pages to be accessed at the cost ot only one clock cycle.
cause up to four tull latency reads to occur. Naturally, this greatly impacts memory pertormance.
lortunately, atter the tour tull latency reads, the memory controller can otten predict vhat pages
are needed next. It can then open them tor minimum latency reads.1his somevhat reduces the
negative ettect ot consecutive page misses.
When disabled, the memory controller sends an All Banks Precharge Connand to the
SDPAM intertace vhenever there is a page miss. 1his causes all the open pages to close
(precharge,.1heretore, subsequent reads only need to activate the necessary memory bank.
1his is usetul in cases vhere subsequent data requests also result in page misses. 1his is because
the memory banks already are precharged and ready to be activated. 1here is no need to vait
tor the memory banks to precharge betore they can be activated. Hovever, it also means that
you von`t be able to benetit trom data accesses that could have been satistied by the previously
opened pages.
better pertormance vith this teature enabled because the open pages allov very tast acces ses.
Disabling this teature, hovever, has the advantage ot keeping the memory contents retreshed
1heretore, it is recommended that you enable this teature tor better memory pertormance.
Disabling this teature can improve data integrity, hovever, it you are keeping the SDPAM
retresh interval vithin specitication, then it is ot little use.
SDRAM RAS Prochorgo Doloy
data trom the target memory cell, the appropriate column is activated using the CAS. Multiple
cells can be read trom the same active rov by applying the appropriate CAS signals .
1his introduces a short delay betore another rov can be activated.1his delay is knovn as the
RAS Precharge 1ine or tRP.
memory module has the rated timings ot 2-3-4-7, its rated PAS Precharge delay vould be 4
clock cycles.
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betore another rov can be activated. It the PAS Precharge 1ime is too long, it vill reduce per-
1heretore, it is recommended that you reduce the SDPAM PAS Precharge Delay to 2 tor bet-
ter pertormance but increase it to 3 or 4 it you experience system stability issues atter reducing
the precharge time.
SDRAM RAS Prochorgo lino
1his introduces a short delay betore the another rov can be activated.1his delay is knovn as
the RAS Precharge 1ine or tRP.
specitications, it is the thiro number in the three- or tour-number sequence. lor example, it your
memory module has the rated timings ot 2-3-4-7, its rated PAS Precharge delay is 4 clock
cycles.
betore another rov can be activated. It the PAS Precharge 1ime is too long, it reduces per-
1heretore, it is recommended that you reduce the SDPAM PAS Precharge 1ime to 2 tor bet-
ter pertormance but increase it to 3 or 4 it you experience system stability issues atter reducing
the precharge time.
SDRAM RAS Pulso Width
S0AM AS Pu|sc WdIh 206
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Hovever, the rov cannot be deactivated until the Mininun RAS Pulse Width or tRAS has
elapsed.
ry module has the rated timings ot 2-3-4-7, its rated tPAS delay is 7 clock cycles.
Hovever, it you start getting memory errors or system crashes, increase the tPCD value one
SDRAM RAS-to-CAS Doloy
Hovever, there is a short delay betore the CAS signal can be applied. Because this delay occurs
betveen the Pov Address Strobe and the Column Addres s Strobe, it is knovn as the RAS-to-
CAS Delay or tRCD.Atter this delay, multiple columns on the same rov can be activated sub-
sequently vithout incurring the same PAS-to-CAS delay, unless a nev rov is activated or the
rov is retreshed.
specitications, it is the secono number in the three or tour number sequence. lor example, it your
memory module has the rated timings ot 2-3-4-7, its rated PAS-to-CAS delay is 3 clock
cycles.
1his BIOS teature allovs you to set the delay betveen the PAS and CAS signals. Because this
delay occurs vhenever the rov is retreshed or a nev rov is activated, reducing the delay
1heretore, it is recommended that you reduce the delay to 3 or 2 tor better memory pertorm-
ance. Hovever, the improvement in pertormance vhen you reduce the PAS-to-CAS delay isn`t
as signiticant as vhen you reduce the CAS latency.
Please note that it you use a value that is too lov tor your memory module, the memory con-
troller may generate the CAS s ignal betore the active rov is ready. 1his can cause the system to
be unstable. It your system becomes unstable atter you reduce the PAS-to-CAS delay, you
should increase the delay or reset it to the rated delay.
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Interestingly, increasing the PAS-to-CAS delay may allov the memory module to run at a
increasing the PAS-to-CAS delay.
SDRAM Row Activo lino
elapsed.
specitications, it is the fourth number in the tour-number sequence. lor example, it your memo-
same rov can be deactivated. It is also the length ot time the rov remains open tor data trans-
ters.
SDRAM Row Cyclo lino
Connon Options: 7, 8, 9, 10, 11, 12, 13
1his BIOS teature controls the memory module`s Rov Cycle 1ine or tRC.1he rov cycle
1he appropriate delay tor the tRAS delay is retlected in your memory module`s rated timings.
In LDLC specitications, it is the f ourth number in the tour number sequence. lor example, it
your memory module has the rated timings ot 2-3-4-7, its rated tPAS delay is 7 clock cycles.
S0AM ow Lyc|c Jmc 207
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1he appropriate delay tor the tRP delay is retlected in your memory module`s rated timings. In
LDLC specitications, it is the thiro number in the three or tour number sequence. lor example,
it your memory module has the rated timings ot 2-3-4-7, its rated tPP delay is 4 clock cycles.
to begin earlier.
lor optimal pertormance, use the lovest value you can, according to the tRC = tRAS + tRP
SDRAM lros lining Voluo
elapsed.
rov active time (tRAS,. 1his constitutes the time vhen a rov is activated until the time the
same rov can be deactivated. It is also the length ot time the rov remains open tor data transters.
SDRAM lrc lining Voluo
Connon Options: 7, 8, 9, 10, 11, 12, 13
1his BIOS teature controls the memory module`s Rov Cycle 1ine or tRC.1he rov cycle
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1he appropriate delay tor the tRAS delay is retlected in your memory module`s rated timings.
In LDLC specitications, it is the f ourth number in the tour-number sequence. lor example, it
your memory module has the rated timings ot 2-3-4-7, its rated tPAS delay is 7 clock cycles.
1he appropriate delay tor the tRP delay is retlected in your memory module`s rated timings. In
LDLC specitications, it is the thiro number in the three or tour number sequence. lor example,
it your memory module has the rated timings ot 2-3-4-7, its rated tPP delay is 4 clock cycles.
to begin earlier.
lor optimal pertormance, use the lovest value you can, according to the tRC = tRAS + tRP
SDRAM lrcd lining Voluo
Hovever, there is a short delay betore the CAS signal can be applied. Because this delay occurs
betveen the Pov Address Strobe and the Column Addres s Strobe, it is knovn as the tRCD
tining value or tRCD.Atter this delay, multiple columns on the same rov can be activated
subsequently vithout incurring the same tPCD delay, unless a nev rov is activated or the rov
is retreshed.
specitications, it is the secono number in the three or tour number sequence. lor example, it your
memory module has the rated timings ot 2-3-4-7, its rated tPCD timing value is 3 clock
cycles.
1his BIOS teature allovs you to set the delay betveen the PAS and CAS signals. Because this
delay occurs vhenever the rov is retreshed or a nev rov is activated, reducing the delay
1heretore, it is recommended that you reduce the delay to 3 or 2 tor better memory pertorm-
ance. Hovever, the improvement in pertormance vhen you reduce the tPCD timing value
von`t be as signiticant as vhen you reduce the CAS latency.
Please note that it you use a value that is too lov tor your memory module, the memory con-
troller may generate the CAS s ignal betore the active rov is ready. 1his can cause the system to
be unstable. It your system becomes unstable atter you reduce the tPCD timing value, you
should increase the delay or reset it to the rated delay.
Interestingly, increasing the tPCD timing value may allov the memory module to run at a
increasing the tPCD timing value.
S0AM Jrcd Jmng va|uc 200
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SDRAM lrp lining Voluo
Hovever, vhen data is read trom a ditterent rov, the active rov must be deactivated. 1his intro-
duces a short delay betore the another rov can be activated.1his delay is knovn as the RAS
Precharge 1ine or tRP.
memory module has the rated timings ot 2-3-4-7, its rated tPP delay is 4 clock cycles.
betore another rov can be activated. It the tPP timing value is too long, it reduces pertormance
by delaying all rov activations. Peducing the precharge time to 2 improves pertormance by
alloving a nev rov to be activated earlier.
1heretore, it is recommended that you reduce the SDPAM tPP timing value to 2 tor better
pertormance but increase it to 3 or 4 it you experience system stability issues atter reducing the
precharge time.
SDRAM lrrd lining Voluo
1he Bank-to-Bank Delay or tRRD is a DDP timing parameter vhich specities the mini-
mum amount ot time betveen successive AC1IVA1L commands to the sane DDP device,
even to different internal banks. 1he shorter the delay, the taster the next bank can be activated
tor read or vrite operations. Hovever, because rov activation requires a lot ot current, using a
short delay may cause excessive current surges.
important.1his is because the desktop PC essentially has an unlimited pover supply and even
the most basic desktop cooling solution is sutticient to dispel any extra thermal load that the
current surges may impose. 1he pertormance benetit ot using the shorter 2 cycles delay is ot tar
greater interest. 1he shorter delay means every back-to-back bank activation takes one clock
cycle less to pertorm. 1his improves the DDP device`s read and vrite pertormance.
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are stability problems vith the 2 cycles setting.
In mobile devices like laptops hovever, it is advisable to use the longer delay ot 3 cycles. Doing
so limits the current surges that accompany rov activations. 1his reduces the DDP device`s
pover consumption and thermal output, both ot vhich should be ot great interest to the road
varrior.
SDRAM Writo Rocovory lino
It the delay is too short, the bank may be precharged betore the active bank has enough time to
store the vrite data in the memory cells.1his causes data to be lost or corrupted.
Please note that this BIOS teature does not determine the time it takes tor the bank to
precharge. It only controls hov soon the bank can start precharging right atter a vrite operation
to the same bank.
1he detault value is 2 Cycles, vhich meets LDLC specitications in DDP200 and DDP266
memory modules. DDP333 and DDP400 memory modules require a Write Pecovery 1ime ot
3 Cycles.
using a shorter delay tor better memory pertormance, hovever, it you tace stability issues, revert
to the specitied delay to correct the problem.
SDRAM Writo to Rood Connond Doloy
last valid vrite operation and the next reao command to the sane internal bank ot the DDP
device.
It a 1 Cycle delay is selected, every read command that tollovs a vrite operation is delayed
S0AM WrIc Io cad Lommand 0c|ay 801
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It a 2 Cycles delay is selected, every read command that tollovs a vrite operation is delayed
1he 2 Cycles option reduces read pertormance, hovever, it improves stability, especially at
normally possible.
By detault, this BIOS teature is set to 2 Cycles. 1his meets LDLC`s specitication ot 2 clock
cycles tor vrite-to-read command delay in DDP400 memory modules. DDP266 and
DDP333 memory modules require a vrite-to-read command delay ot only 1 clock cycle.
Socond Boot Dovico
IAN, Disabled
1his BIOS teature allovs you to select the second device trom vhich the BIOS attempts to
load an operating system. It the BIOS tinds and loads an operating system trom the device
selected through this teature, it doesn`t load another operating system, even it you have one on a
ditterent device.
lor example, it you set Floppy as the tirst boot device and HDD-0 as the second boot device,
the BIOS boots straight into the Windovs 98 installation on your hard disk and ignores the
Windovs XP installation CD in your CD-POM drive if there is no bootable disk in the tloppy
drive. In short, this teature allovs you to choose the second device trom vhich to boot.
By detault, HDD-0 is the second boot device in practically all motherboards. Hovever, unless
you boot otten trom the tloppy drive (vhich is otten the tirst boot device, , it is better to set
your hard disk (HDD-0, as the tirst boot device.1his shortens the boot process because the
BIOS no longer needs to check the tloppy drive tor a bootable operating system.
Socurity Sotup
Connon Options: System, Setup
1his BIOS teature controls the application ot the BIOS` passvord protection. It only vorks atter
you have created a passvord through the Passvord Setting option in the main BIOS screen.
Selecting the Systen option torces the BIOS to ask tor the passvord every time the system
boots up.
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It you choose Setup, then the passvord is only required tor access to the BIOS.1his option is
usetul tor system administrators or computer resellers vho need to keep novice users trom
messing around vith the BIOS.:
Shodowing Addross Rongos
Connon Options: C8000-CBlll, CC000-Cllll, D0000-D3ll, D4000-D7lll, D8000-
DBlll, DC000-Dllll, Disabled
1his BIOS teature allovs you to cordon ott specitic memory blocks (xxxx-xxxx, to shadov the
BIOS ot certain add-on cards. 1his improves the pertormance ot cards that are accessed and
controlled through their BIOS, as opposed to drivers. Currently, this is mostly limited to
bootable netvork cards.
lor most users, there is absolutely no need tor this teature as modern operating systems directly
access hardvare through drivers. Shadoving your device`s BIOS just vastes memory.1heretore,
it is recommended that you disable this teature.
According to the Microsott article :haoouin PI: noer 1in^l 4.0, shadoving the BIOS
(irrespective ot vhat BIOS it is, does not bring about any pertormance enhancements because
it is not used by Windovs N1. It only vastes memory. Although the article did not say anything
about other versions ot Microsott Windovs, this is true tor all versions ot Microsott Windovs,
trom Windovs 93 onvard.
In addition, it you are using an add-on card that uses the CXXXX-Lllll area tor IO, shad-
oving that memory block may prevent the card trom vorking because read or vrite requests
might not be passed on to the ISA bus.
Shoro Monory Sizo
Some motherboard chipsets come vith an integrated GPU (Graphics Processing Unit,.1his
GPL usually makes use ot the UMA (Unified Menory Architecture, tor its memory
requirements.1his means the graphics processor vill take a portion ot the system memory to
use as its ovn memory butter.
Lsing a portion ot system memory tor the graphics processor`s use allovs the motherboard
manutacturer to otter a lov-cost graphics solution. It also allovs the user to change the size ot
the graphics memory butter to suit ditterent applications.
Hovever, this technology has the tolloving disadvantages:
Allocating system memory to the GPL reduces the amount ot system memory available
tor the operating system and programs to use.
Sharing system memory vith the GPL saturates the memory bus and reduces the amount
ot memory bandvidth tor both the processor and the graphics processor.
1heretore, integrated GPLs are usually unsuitable tor high-demand 3D applications and games.
1hey are bes t used tor bas ic 2D graphics and video tunctions.
Sharc Mcmory Szc 808
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PIO Data 1ransfer Mode Mainun 1hroughput
PIO Mode 0 3.3 MBs
PIO Mode 1 3.2 MBs
PIO Mode 2 8.3 MBs
PIO Mode 3 11.1 MBs
PIO Mode 4 16.6 MBs
GPL.
Please note that unlike the AGP Aperture Size, once the system memory ia allocated to the
Slovo Drivo PIO Modo
corresponding Slave Drive PIO Mode option tor that IDL channel either dis appears or
becomes grayed out.
Slave IDL drive attached to that particular IDL channel. Here is a table ot the ditterent PIO
transter rates and their corresponding maximum throughputs.
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DMA 1ransfer Mode Mainun 1hroughput
DMA Mode 0 4.16 MBs
DMA Mode 1 13.3 MBs
DMA Mode 2 16.6 MBs
Normally, you should leave it as Auto and let the BIOS autodetect the IDL drive`s PIO mode.
tor.
Slovo Drivo UltroDMA
corresponding Slave Drive LltraDMA tunction tor that IDL channel either disappears or is
grayed out.
1his BIOS teature allovs you to enable or disable DMA (Direct Menory Access, s upport
(it available, tor the Slave IDL device attached to that particular IDL channel. lor easy reter-
ence, here is a table ot the ditterent DMA transter rates and their corresponding maximum
throughputs.
S|avc 0rvc u|Ira0MA 806
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Setting this BIOS teature to Auto lets the BIOS autodetect the IDL drive`s maximum support-
ed DMA mode at boot-up.
drive.
Normally, you should leave it as Auto and let the BIOS autodetect the drive`s DMA support. It
the drive supports DMA transters, the proper DMA transter mode is enabled tor that drive,
mode supported,.
not run properly using DMA transters vhen the PCI bus is overclocked. Disabling DMA sup-
properly vith the higher PCI bus speed.
Spood Lrror Hold
1his BIOS teature prevents accidental overclocking by preventing the s ystem trom booting up it
the processor clock speed vas not properly set.
It is very usetul tor novice us ers vho vant nothing to do vith overclocking.Yet, they may inad-
vertently set the vrong processor speed in the BIOS and either prevent the system trom boot-
ing up at all or cause the system to crash or hang.
When enabled, the BIOS checks the processor clock speed at boot up and halts the boot
process it the clock speed is ditterent trom that imprinted in the processor ID. It also displays an
error message to varn you that the processor is running at the vrong speed.
1o correct the situation, you have to access the BIOS and correct the processor speed. Most
BIOSes, hovever, automatically reset the processor to the correct speed. All you have to do then
is access the BIOS, verity the clock speed, and save the changes made in the BIOS.
It you are thinking ot overclocking the processor, you must disable this teature because it pre-
vents the motherboard trom booting up vith an overclocked processor.When disabled, the
BIOS does not check the processor clock speed at boot up. It allovs the system to boot vith the
clock speed set in the BIOS, even it it does not match the processor`s rated clock speed (as
imprinted in the proces sor ID,.
Although this may seem really obvious, I have seen countless overclocking initiates puzzling
over the error message vhenever they try to overclock their processors. So, betore you start
pulling your hair out and screaming hysterically that Intel or AMD has tinally implemented a
clock speed lock on their proces sors, try disabling this teature.
Split Lock Oporotions
1his is a debug teature specitic to the Intel Pentium 4 and the Intel Pentium 4 Xeon processors.
It allovs you to prevent the processor trom issuing split lock cycles to the processor bus it such
operations cause problems.
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Split lock cycles can potentially cause problems in certain situationstor example, the Split
Lock Cycles bug in the Intel 82860 MCH.1his bug causes the system to hang vhen tvo
split-locked cycles are issued to a vrite-only PAM (Progrannable Attribute Map, region,
tolloved by tvo more vrites to the same region.
Lsually, it is recommended that you leave Split Iock Operation at its detault setting ot
Lnabled. 1his allovs the processor to issue split lock cycles to the processor bus.
Hovever, it you are using a motherboard based on the Intel 82860 chipset, you should disable
this teature.1his torces the processor to issue Alignment Check (4AC, exceptions to the
processor bus instead ot split lock cycles.
1here may be other situations vhere split lock cycles can cause problems. It your sys tem hangs
or crashes tor no apparent reason, you can try disabling this teature and see it it solves the prob-
lem. Othervise, leave it Lnabled.
Sprood Spoctrun
Connon Options: 0.23, 0.3, Smart Clock, Disabled
erated create LMI (Llectronagnetic Interference,.1his LMI interteres vith other electronics
in the area.1here are also claims that it may allov electronic eavesdropping ot the data that is
being transmitted.
1his BIOS teature allovs you to reduce the LMI ot your motherboard by modulating the sig-
nals it generates, so the spikes are reduced to tlatter curves. It achieves this by varying the tre-
quency siihti, so the signal does not use any particular trequency tor more than a moment.
1his reduces the amount ot LMI generated by the motherboard.
1he BIOS usually otters tvo levels ot modulation0.2S or 0.S.1hey denote the amount
ot modulation or jitter trom the baseline signal.1he greater the modulation, the greater the
reduction ot LMI. 1heretore, it you need to signiticantly reduce your motherboard`s LMI, a
modulation ot 0.S is recommended.
Hovever, system stability may be slightly compromised in certain situations. lor example, this
BIOS teature may cause improper tunctioning ot timing-critical devices, such as clock-s ensitive
SCSI devices.
Spread Spectrum can also cause problems vith overclocked systems, especially those that have
been taken to extremes. Lven a slight modulation ot trequency may cause the processor or any
other overclocked components ot the system to tail, leading to very predictable consequences.
Ot course, this depends on the amount ot modulation, the extent ot overclocking and other tac-
tors like temperature, and so torth.As such, the problem may not manitest itselt immediately.
1heretore, it is recommended that you disable this teature it you are overclocking your system.
Hovever, unless you have LMI problems or sensitive data that must be sateguarded trom elec-
tronic eavesdropping, it is best to disable this teature to remove the possibility ot stability issues.
Sprcad SpccIrum 807
S
Some BIOSes also otter a Snart Clock option.1his vorks ditterently trom Spread Spectrum,
although it is usually ottered as a Spread Spectrum option.
Instead ot modulating the trequency ot signals over time, Smart Clock turns ott the AGP, PCI,
and SDPAM clock signals that are not in use.1heretore, LMI can be reduced uithout compro-
mising system stability. As a bonus, using Smart Clock also helps reduce pover consumption.
1he degree ot LMI and pover reduction depends on the number ot empty AGP, PCI, and
SDPAM slots. Hovever, generally, Smart Clock is unable to reduce LMI as ettectively as simple
trequency modulation.
With that said, it is recommended that you enable Snart Clock instead ot using the 0.2S
or S option, it the option is available to you. It allovs you to reduce some LMI vithout any
risk ot compromising your computer`s stability.
Supor Byposs Modo
1his BIOS teature basically allovs the nenory request organizer (MRO, ot the memory
controller to skip certain pipeline stages vhile transterring data to and trom the memory sub-
system.
1his improves memory pertormance by alloving lover latency accesses to the memory subsys-
tem. Hovever, this teature only can be sately enabled it the tolloving conditions are true:
1. 1he system only has a sinie processor present. Systems using dual-processor motherboards
can enable this teature it only one processor is present.
2. 1he processor clock speed multiplier must be 4 or reater. 1his means the processor must
be running at least tour times taster than its bus speed.
lor better memory pertormance, it is recommended that you enable this teature. Hovever, you
must make sure that you are only using a single processor that is running at least tour times
taster than the processor bus.You should disable this teature it your system does not meet the
tvo requirements stated above.
Supor Byposs Woit Stoto
1his BIOS teature is used to tine-tune the Super Bypass teature to correct tor internal timing
variations.
When set to 0 Cycle, the memory controller initiates all super bypass requests vithout delay.
When set to 1 Cycle, the memory controller torces a vait state delay tor all super bypass
requests.
Otticial documents recommend that a vait state be added tor a 133MHz (266MHz DDP,
memory bus. Systems using a 100MHz (200MHz DDP, memory bus do not need this delay.
Ot course, those are just sate, otticial recommendations tor this teature.
S
lorcing a vait state on all super bypass requests reduces the ettectiveness ot the Super Bypass
teature.1heretore, it is recommended that you try using the 0 Cycle setting tor maximum per-
tormance. It should vork even vith memory clock speeds that are greater than 133MHz
(266MHz DDP,.
Hovever, it you experience system stability issues atter using this 0 Cycle setting, set this tea-
ture to 1 Cycle. 1his slovs dovn super bypass transactions but allovs your system to use the
Super Bypass teature at higher clock speeds.
SuporStobility Modo
1his is a NVIDIA nForce chipset-specitic BIOS teature. It controls the hitherto hidden tea-
ture ot the nlorce chipset, vhich iocks the memory clock at 200MHz instead ot the rated
266MHz vhen it detects a memory module that is not compatible vith the motherboard.1his
allovs the us e ot substandard or incompatible memory modules, albeit at reduced pertormance.
At boot-up, the nlorce chipset reads the SPD values trom each memory module to detect its
rated speed, timings, and size. 1his is vhere the SuperStability teature kicks in.
1he chipset only allovs the memory clock to be set at 266MHz vhen it is satistied that each
and every memory module installed has met its standard. It even a s ingle module tails to meet
the standard, the chipset locks the memory clock at 200MHz, irrespective ot the clock speed at
vhich it vas set to run. Lven it you attempt to run it at a higher speed, the memory clock
remains locked at 200MHz.
Although NVIDIA claims that this teature allovs nlorce motherboards to vork vith substan-
dard or incompatible memory modules that vould othervise be unusable, there have been
reports that even compatible memory modules are being locked dovn to 200MHz. Apparently,
loading the second s lot (Slot B, ot the second memory controller vith a double-sided DIMM
also causes SuperStability to kick in.
As you knov, the NVIDIA nlorce is the tirst chipset to otter a dual-channel DDP intertace,
albeit vith only three DIMM slots. NVIDIA arranged it so the tirst DIMM slot has a memory
controller all to itselt, vhile the second and third DIMM slots have to share the second memory
controller. It is the second slot ot this second memory controller that is not compatible vith
double-sided memory modules.
Hovever, it is not clear it this is due to a bug in the chipset or because the slot vas not
designed or rated tor double-sided modules.What is clear is that it a double-sided module is
inserted into the second slot (Slot B, ot the second memory controller, it causes the
SuperStability teature ot the nlorce chipset to lock the memory clock at 200MHz.
Please note that Slot B ot the second memory controller is not neces sarily the third DIMM
slot. It can vary betveen motherboard models.1he only vay to identity Slot B ot the second
memory controller is to test it yourselt.
Atter this teature vas discovered by Chris Connolly ot GamePC, the BIOS vas revised to
include this SuperStability Mode teature.1his allovs you to svitch the SuperStability teature
on or ott.
When lett at the detault setting ot Lnabled, the nlorce chipset lock the memory clock at
200MHz it it detects an incompatible memory module or it Slot B ot the second memory
controller is tilled vith a double-sided memory module.
SupcrSIah|Iy Modc 800
S
When disabled, the nlorce chipset does not check the memory modules tor incompatibility or
Slot B ot the second memory controller tor a double-sided memory module.1he memory
modules are alloved to run at the clock speed you set.
It is highly recommended that you disable SuperStability Mode tor better SDPAM pertorm-
ance, especially it you use all three DIMM slots.1here is really no need to enable it because you
can lover the memory clock speed yourselt or increase their timings in order to use incompati-
ble memory modules.
Swop Iloppy Drivo
When this BIOS teature is enabled, the tloppy drive that originally vas mapped to drive A: is
remapped to drive B: and vice versa tor the drive that vas originally set as drive B:.
When this BIOS teature is disabled, the tloppy drive mapping remains as that set by the drive
connector arrangement.
tant it you are using tvo tloppy drives ot ditterent torm tactors (3.3 and 3.23, and you need
to boot trom the second drive. Because the BIOS can only boot trom drive A:, you have to
physically svap the drive connections or use this teature to do it logically.
need to enable this teature. Ieave it at the detault setting ot disabled.
Synchronous Modo Soloct
Connon Options: Synchronous,Asynchronous
1his BIOS teature controls the signal synchronization ot the DPAM-CPL intertace.
When set to Synchronous, the chipset synchronizes the signals trom the DPAM controller
vith signals trom the CPL bus (or tront side bus,. Please note that tor the signals to be synchro-
nous, the DPAM controller and the CPL bus must run at the same clock speed.
When set to Asynchronous, the chipset decouples the DPAM controller trom the CPL bus.
1his allovs the DPAM controller and the CPL bus to run at ditterent clock speeds.
Generally, it is advisable to use the Synchronous setting because a synchronized intertace
allovs data transters to occur vithout delay.1his results in a much higher throughput betveen
the CPL bus and the DPAM controller.
S
Hovever, the Asynchronous mode does have its uses. Lsers ot multiplier-locked processors
and slov memory modules may tind that using the Asynchronous mode allovs them to over-
clock the processor much higher vithout the need to buy taster memory modules.
1he Asynchronous mode is also usetul tor those vho have very tast memory modules and
multiplier-locked processors vith lov bus speeds. Punning the tast memory modules synchro-
nously vith the lov CPL bus speed torces the memory modules to run at the same slov speed.
Punning asynchronously, theretore, allovs the memory modules to run at a much higher speed
than the CPL bus.
Hovever, please note that the pertormance gains ot running synchronously cannot be underesti-
mated. Synchronous operations are generally much taster than asynchronous operations running
at a higher clock speed. It is advisable that you compare benchmark scores ot your computer
running asynchronously (at a higher clock speed, and synchronously to determine the best
option tor your system.
Syston BIOS Cochooblo
1his BIOS teature is only valid it the motherboard BIOS is shadoved. Hovever, because moth-
erboard BIOS shadoving is hardvired into most motherboards, this is really a moot point.
Lnabling this teature allovs the caching ot the motherboard BIOS POM trom F0000h to
FFFFFh by the processor`s Level 2 cache.1his greatly speeds up accesses to the BIOS.
Hovever, this does not translate into better system pertormance because modern operating sys-
tems like Microsott Windovs XP do not need to communicate vith the hardvare through the
BIOS. Current operating systems make use ot drivers to access the hardvare directly.
1heretore, it vould be a vaste ot the Ievel 2 cache`s bandvidth it the motherboard BIOS vas
cached instead ot data that are more critical to the system`s pertormance. 1he motherboard
BIOS is loaded only vhen the computer boots up and rarely thereatter. It is very unlikely to be
requested again, so it is really quite pointless to cache it.
In addition, it any errant program vrites into this memory area, it results in a system crash.
1heretore, it is highly recommended that you disable this teature tor better system
pertormance.
You should only consider enabling this BIOS teature it you are using an operating system that
still communicates vith hardvare through the BIOS like MS-DOS. It so, caching the mother-
board BIOS boosts pertormance.
SysIcm 8I0S Lachcah|c 811
S
l
lhird Boot Dovico
IAN, Disabled
1his BIOS teature allovs you to select the third device trom vhich the BIOS attempt to load
through this teature, it von`t load another operating system, even it you have one on a ditterent
device.
lor example, it you set Floppy as the tirst boot device, HDD-0 as the second boot device, and
SCSI as the third boot device, the BIOS boots straight into the Windovs 98 installation on
your SCSI hard disk and ignores the Windovs XP installation CD in your CD-POM drive if
there is no bootable IDL hard disk or bootable tloppy disk. In short, this teature allovs you to
choose the third device trom vhich to boot.
By detault, LS/ZIP is the third boot device in practically all motherboards. Because the third
boot device is only tried atter no bootable operating system can be tound in the tirst tvo boot
devices, it is ot little consequence vhat you set here.1heretore, the choice ot boot device tor
this BIOS teature is entirely up to your personal preterence.
l, R Invorting Lnoblo
Connon Options: No-No, No-Yes,Yes-No,Yes-Yes
polarity.
out.
1here are tour options available, based on combinations ot Yes (read as High, and No (read as
Lov,.You`ll need to consult your IP peripheral`s documentation to determine the correct
polarity. Choosing the vrong polarity prevents a proper IP connection trom being established
vith the IP peripheral.
lyponotic Roto
Connon Options: 6, 8, 10, 12, 13, 20, 24, 30
1his BIOS teature only vorks it the 1ypenatic Rate Setting teature has been enabled.
1his teature determines the rate at vhich the keyboard repeats a keystroke it you press it
continuously.
1
1he available settings are in characters per second.1heretore, a typematic rate ot 30 causes the
keyboard to repeat the keystroke at a rate ot 30 characters per second it you press a particular
key continuously. 1he higher the typematic rate, the taster the keyboard repeats the keystroke.
1he choice ot vhat setting to use is entirely up to your personal preterence. Hovever, note that
through the BIOS, like MS-DOS. 1he typematic rate in operating systems like Windovs XP
are controlled by the keyboard driver`s settings.
lyponotic Roto Doloy
Connon Options: 230, 300, 730, 1000
1his BIOS setting only vorks it the 1ypenatic Rate Setting teature has been enabled.
1his teature determines hov long, in nilliseconds (thousandths ot a second,, the keyboard
controller vaits betore it starts repeating the keystroke that you have pressed continuously.1he
longer the delay, the longer the keyboard controller vaits betore it starts repeating the keystroke.
lyponotic Roto Sotting
1his BIOS teature allovs you to gain manual control ot the keystroke repeat teature.
When enabled, you are given access to these tvo typematic controls:
1ypematic Pate
1ypematic Pate Delay
1hey allov you to manually adjust the 1ypenatic Rate and the 1ypenatic Rate Delay.
It you disable this teature, the tvo typematic controls are disabled and grayed out.1he key-
board controller thereby uses the detault typematic rate and typematic rate delay.
JypcmaIc aIc ScIIng 818
1
DMA 1ransfer Mode Mainun 1hroughput
DMA Mode 0 4.16 MBs
DMA Mode 1 13.3 MBs
DMA Mode 2 16.6 MBs
U
Ultro DMA Modo
Connon Options: Disabled, 0, 1, 2, 3, 4, 3, 6, Auto
available, tor the IDL device. lor easy reterence, here is a table ot the ditterent DMA transter
rates and their corresponding maximum throughputs.
L
drive.
Setting this BIOS teature to S torces the BIOS to use UltraDMA 100 tor DMA transters.
alloving it to burst data trom anyvhere betveen 33MBs to 133MBs (depending on the trans-
ter mode supported,.
not run properly using DMA transters vhen the PCI bus is overclocked. Disabling DMA sup-
port torces the drive to use the slover PIO transter mode. 1his may allov the drive to vork
properly vith the higher PCI bus speed.
Please note that setting this to Auto or any ot the DMA options does not enable DMA transters
tor IDL devices that do not support DMA transters. It your drive does not support DMA trans-
ters, the BIOS automatically sets the drive to do PIO transters only.
and only tor operating systems that do not load their ovn drivers tor IDL tunctions. lor oper-
ating systems that use their ovn IDL drivers (tor example, Windovs 9x2000XP,, you have to
ovn IDL controller.1his extra LltraDMA100 IDL controller is otten added to provide
LltraDMA100 support in motherboards vith chipsets that do not support LltraDMA100.
Lven it the motherboard`s chipset has an IDL controller that supports LltraDMA100, it is not
controlled by this BIOS teature. 1his BIOS teature is only us ed to control the additional IDL
controller built into the motherboard.
1o avoid contusion, I shall hencetorth reter to the chipset`s IDL controller as the internal IDL
controller vhile the additional IDL controller vill be knovn as the eternal IDL controller.
u|Ira0MA-133 I0L LonIro||cr 816
L
UltroDMA- IDL Controllor
L
USB Controllor
1his BIOS teature is somevhat similar to Assign IRQ For USB. It enables or disables the
motherboard`s onboard LSB controller.
Hovever, instead ot controlling the assignment ot an IPQ to the onboard LSB controller, this
teature directly controls the LSB controller`s tunctionality.
It is recommend that you enable this teature, so you can use the onboard LSB controller to
It you disable this teature, the LSB controller is disabled and you are unable to use it to com-
any LSB device or it you are using a ditterent LSB controller tor your LSB needs.
Disabling this teature is unnecessary vith APIC-capable motherboards because they come vith
more IPQs.
USB Royboord Support
1his BIOS teature determines vhether support tor the LSB keyboard s hould be provided by
the operating system or the BIOS. 1heretore, it only attects those vho are using LSB key-
boards.
It your operating system otters native support tor LSB keyboards, you should select the OS
option.1his provides much greater tunctionality. Hovever, it you are using DOS or operating
systems that do not otter support tor LSB keyboards, then using the OS optionessentially dis-
ables the keyboard because these operating systems cannot detect or vork vith LSB keyboards.
LSB keyboard.You are able to use the keyboard vith both operating systems that do not sup-
port LSB keyboards and those that do.
Hovever, the BIOS option otters only rudimentary support tor the LSB keyboard, so using it
strips the keyboard ot all except basic tunctions.1heretore, you should not select this option it
you are using an operating system that supports LSB keyboards. It is recommended that you
select the OS option it you are using a current operating system like Windovs XP.
Hovever, don`t torget to svitch trom the OS option to the BIOS option vhenever you vant
system like Windovs XP, it vill not support the LSB keyboard.
uS8 kcyhoard SupporI 817
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USB Mouso Support
1his BIOS teature determines vhether support tor the LSB mouse should be provided by the
operating system or the BIOS.1heretore, it only attects those vho are using LSB mice.
It your operating system otters native support tor LSB mice, you should select the OS option.
1his provides much greater tunctionality. Hovever, it you are using DOS or operating systems
that do not otter support tor LSB mice, then using the OS option essentially disables the mouse
because thes e operating systems cannot detect or vork vith LSB mice.
LSB mouse.You are able to use the mouse vith both operating systems that do not support
LSB mice and those that do.
Hovever, the BIOS option otters only rudimentary support tor the LSB mouse, so using it
strips the mouse ot all except basic tunctions. 1heretore, you should not select this option it you
are us ing an operating system that supports LSB mice. It is recommended that you select the
OS option it you are using a current operating system like Windovs XP.
Hovever, don`t torget to svitch trom the OS option to the BIOS option vhenever you vant
system like Windovs XP, it does not support the LSB mouse.
USWC Writo Posting
ory bandvidth. Lntortunately, graphics vrites trom the processor are mostly pixel vrites, vhich
are 8- to 32-bits in nature. Because they do not till up an entire cache line, such vrites are not
3. 1he processor only needs to vrite to its internal vrite combine butters instead ot the
L
pertormance.
Please note that this teature must also be supported by the graphics card, the operating system,
causes a host ot problems, such as graphics artitacts, system crashes, and even the inability to
boot up properly.
uSWL WrIc PosIng 810
L
V
Vidoo BIOS Cochooblo
1his BIOS teature aims to turther boost the pertormance ot a shadoved video BIOS by
caching it using the processor`s Ievel 2 cache. It vorks in conjunction vith Video BIOS
Shadoving and is only valid vhen the Video BIOS Shadoving teature is enabled.
It this BIOS teature is enabled, a 32KB block ot the video BIOS trom C0000h-C7FFFh is
cached by the processor`s Ievel 2 cache.1his greatly speeds up su|seuent consecuti:e accesses to
the video BIOS.
It this BIOS teature is disabled, the video BIOS is not cached. 1he video BIOS is read trom
the system memory (it it has been shadoved, or directly trom the BIOS chip.
Hovever, caching the video BIOS does not necessarily translate into better system pertormance.
lirst ot all, modern operating systems like Microsott Windovs XP do not need to use the video
BIOS. 1hey bypass the BIOS completely and use the graphics card`s driver instead. 1his provides
the operating systems vith direct access to the graphics card and allovs them to make tull use
ot the card`s capabilities.With such a driver, these operating systems do not need to make any
BIOS calls.1heretore, absolutely no benetit can be realized by caching the BIOS.
And unlike system memory, vhich can be a gigabyte or more, the processor`s I2 cache is a lim-
ited resource. Most processors come vith I2 caches ot only 128KB to 312KB in size. Diverting
such a large portion ot the I2 cache tor the purpose ot caching the video BIOS deprives the
processor ot I2 cache tor its ovn data. Consequently, there is a signiticant deterioration in
processor pertormance vhenever the video BIOS is cached.
1here are some vho reason that becaus e the video BIOS is only cached vhen needed, the
processor does not actually lose 32KB ot I2 cache.1he video BIOS is tlushed out ot the I2
cache vhen it is not needed. 1hat`s true. Hovever, vhenever the video BIOS is cached, it still
takes up 32KB ot I2 cache and the processor`s pertormance sutters at that point.
As vith the Video BIOS Shadoving teature, llash POM upgrades should not be attempted
it the video BIOS is cached. It the video BIOS is cached, any attempt at tlashing the video
BIOS vill likely result in a system crash. 1his is because the location pointer tor the video
BIOS nov points to a location in the processor`s I2 cache, not the llash POM'
Worst ot all, because only 32KB ot the video BIOS is cached, part ot the nev video BIOS
overvrites that cached portion, vhile the rest vould overvrite the contents ot the llash POM.
Because the video BIOS in the llash POM vas only partially overvritten, the end result is
usually a corrupted video BIOS.
Ot course, caching the video BIOS theoretically provides a signiticant boost in real-mode DOS
games or certain operating systems in tail-sate mode. Hovever, the loss ot the processor`s I2
cache negates any pertormance advantage gained by caching the video BIOS.
1heretore, it is recommended that you disableVideo BIOS Caching, even it you play a lot ot
real-mode DOS games or vork vith operating systems running in tail-sate mode. It is better
just to rely on video BIOS shadoving to provide a boost in the video BIOS` pertormance.
V
Vidoo BIOS Shodowing
1his BIOS teature allovs taster access to the video BIOS by shaoouin or making a copy ot it in
the system memory. Shadoving the video BIOS improves its pertormance because the BIOS
nov can be read by the CPL through the 64-bit memory bus as opposed to the slov 8-bit
X1 bus (used in older motherboards, or the never IPC bus (used in current motherboards,.
1his appears quite an attractive teature because it results in at least a thousand-told improvement
in video BIOS pertormance, and the only price you pay is losing the small amount ot system
memory used to mirror the video BIOS. Lntortunately, the truth is not so simple.
Modern operating sys tems do not even use the video BIOS. 1hey bypass the BIOS completely
and use the graphics card`s driver instead.1his provides the operating system vith direct access
to the graphics card and allovs it to make tull use ot the card`s capabilities.With such a driver,
these operating systems do not need to make any BIOS calls.1heretore, absolutely no benetit
can be realized by shadoving the BIOS.
According to a Microsott article about :haoouin PI: unoer 1in^l 4.0, shadoving the BIOS
(irrespective ot vhat BIOS it is, does not bring about any pertormance enhancements because
it is not used by Windovs N1. It just vastes memory.Although the article did not say anything
about other versions ot Microsott Windovs, this is true tor all versions ot Microsott Windovs
trom Windovs 93 onvard.
In addition, shadoving the video BIOS can sometimes cause contlicts to occur. 1here is alvays
a risk ot certain sottvare vriting to the PAM region used to shadov the video BIOS. When
this happens, a contlict occurs and the system crashes. lortunately, this is no longer an issue in
current motherboards because the shadoved PAM region nov has been moved tar trom the
reach ot programs.
What could be a bigger issue is the shadoving ot just a portion ot the video BIOS. Never
video BIOSes are generally much larger than 32KB in size. Hovever, most motherboards shad-
ov only a 32KB block trom C0000 to C7FFF. It only this region ot the video BIOS is shad-
oved and the rest is lett unshadoved, applications may have trouble accessing the video BIOS
properly.1heretore, it you intend to shadov the video BIOS, you must ensure that the entire
video BIOS is shadoved.1o do this, you need to:
Lnable video BIOS shadoving (tor the C0000-C7lll region,
Lnable the shadoving ot the remaining portions, tor example C8000-CBlll, until the
entire video BIOS is shadoved.
linally, all graphics cards nov use llash POM, vhich is much taster than the POM or LLP-
POM chips used in older graphics cards. llash POM also allovs easy upgrading ot the
tirmvare by a simple BIOS tlash. Hovever, it the video BIOS is shadoved, any attempt at tlash-
ing the video BIOS vill likely result in a system crash.1his is because the location pointer tor
the video BIOS nov points to a location in the system memory, not the llash POM'
It could be even vorse it only a portion ot the video BIOS had been shadoved vhen the video
BIOS upgrade vas attempted. Part ot the nev video BIOS overvrites the portion ot the video
BIOS that vas shadoved in the system memory vhile the rest overvrites the contents ot the
llash POM. Because the video BIOS in the llash POM vas only partially overvritten, the end
result is usually a corrupted video BIOS.
vdco 8I0S Shadowng 821
V
1heretore, video BIOS shadoving must be disabled it you vant to tlash the llash POM ot the
graphics card.
Some ot you probably vonder vhy ve should continue to update the video BIOS even though
it appears to be useless in most cases.1he ansver is simplethe video BIOS does not contain
only standard VGA tunctions.1he video BIOSes ot current graphics cards also contain code tor
2D, 3D, and video acceleration. 1heretore, using the latest video BIOS is likely to boost per-
tormance as vell as correct bugs in the previous BIOS versions.1here may also be occasions
vhen the latest drivers may not vork vith older versions ot the video BIOS.1heretore, it is
advisable to keep updating the video BIOS vhether or not you use real-mode DOS.
With all that said, there may still be a use or tvo tor this BIOS teature. lor one thing, most
real-mode DOS games use the video BIOS`s VGA tunctions because they cannot directly access
the graphics processor. Such games benetit trom the shadoving ot the video BIOS. It you still
play old real-mode DOS games, you can try enabling Video BIOS Shadoving tor better per-
tormance.
Shadoving ot the video BIOS also provides pertormance benetits vhen it comes to the tail-sate
mode ot certain operating systems (tor example, Sate Mode in Microsott Windovs XP,.1hese
operating systems tall back on the video BIOS because all video BIOSes contain the same, stan-
dardized VGA tunctions. In such cases, shadoving the video BIOS can provide a substantial
boost to graphics pertormance. Ot cours e, no one uses Sate Mode in Windovs all the time'
It this BIOS teature is enabled, the video BIOS is shadoved in system memory.1his improves
graphics rendering pertormance it the VGA tunctions ot the video BIOS are used.
It this BIOS teature is disabled, the video BIOS is not shadoved in system memory. Any access
to the video BIOS has to go through the X1 or IPC bus.
Because drivers have replaced the video BIOS as the intertace betveen the graphics hardvare
and the operating system, it is recommended that you disableVideo BIOS Shadoving.1he risk
ot crashes and BIOS corruptions due to this BIOS teature is not vorth the benetits it provides
in certain circumstances.
Hovever, it you do play a lot ot old real-mode DOS games or vork a lot in sate-mode
Windovs, then you should shadov the video BIOS tor improved pertormance.
Vidoo Monory Cocho Modo
Connon Options: LSWC, LC
1his is yet another BIOS teature vith a misleading name. It does not cache the video memory
or even graphics data (such data is uncacheable anyvay,. It is actually similar to the USWC
Write Posting BIOS teature.
ory bandvidth. Lntortunately, graphics vrites trom the processor are mostly pixel vrites that
are 8- to 32-bits in nature. Because they do not till up an entire cache line, such vrites are not
V
3. 1he processor only needs to vrite to its internal vrite combine butters instead ot the
It enabled, the vrite combine butters accumulates and combines partial or smaller graphics
vrites trom the processor and vrites them to the graphics card as burst vrites.
pertormance.
Please note that this teature must also be supported by the graphics card, the operating system,
causes a host ot problems, such as graphics artitacts, system crashes, and even the inability to
boot up properly.
Vidoo RAM Cochooblo
1he Upper Menory Area (UMA, is a 384KB block ot memory at the top ot the tirst
megabyte ot memory that is reserved tor the system`s use in DOS.A portion ot this Lpper
Memory Area is reserved as video PAM memory.
1he video PAM memory area is a 128KB block trom A0000h to Bllllh. Ot this 128KB, the
tirst halt (A0000hAllllh, is reserved tor use in VGA graphics mode.1he other halt is used tor
monochrome text mode (B0000hB7lllh, and color text mode (B8000hBllllh,. 1his video
PAM memory area is the only portion ot the graphics card`s memory that the processor has
direct access to in VGA mode.
vdco AM Lachcah|c 828
V
1he graphics card and the processor use this memory area to vrite pixel data vhen the com-
puter is operating in VGA mode.1his is vhy all VGA graphics modes take up less than 64KB ot
memory. 1he most common VGA mode is mode 0x13, vhich has a resolution ot 320 x 200 in
236 colors.1his mode uses up exactly 64,000 bytes ot memory and tits nicely into the 64KB
block trom A0000h to Allllh.
1his BIOS teature aims to boost VGA graphics pertormance by using the processor`s Ievel 2
cache to cache the 64KB VGA graphics memory area trom A0000h to AFFFFh.
It this BIOS teature is enabled, the VGA graphics memory area is cached by the processor`s
Level 2 cache.1his speeds up accesses to the VGA graphics memory area.
It this BIOS teature is disabled, the VGA graphics memory area is not cached by the processor`s
Level 2 cache.
lrom vhat ve have discussed so tar, it sounds like caching the VGA graphics memory area is
logically the vay to go. Caching the VGA graphics memory area detinitely speeds up VGA
graphics pertormance by caching accesses to the graphics memory area.1his is great tor those
old DOS games, although it von`t do anything tor VGA text modes.
Hovever, reality is tar less ideal. lor one thing,VGA modes are hardly used at all these days. lor
compatibility reasons,VGA is still used in Windovs XP`s Safe Mode. It is also used in real
mode DOS, it you still use that. Other than that, there is no more use tor VGA modes. It VGA
graphics modes are not used, no benetit can possibly be realized by enabling this BIOS teature.
Lven it you use DOS modes a lot, is there even a point in caching the VGA graphics memory
area tor better pertormance Lven the slovest computer today is more than capable ot handling
VGA graphics vith ease. In short, caching the VGA graphics memory area not bring any notice-
able advantage.
On the other hand, caching this memory area vill cost you some processor pertormance.
Because some ot the processor`s Ievel 2 cache is being diverted to cache the VGA graphics
memory area, there is less to keep the processor supplied vith data. Consequently, the proces-
sor`s pertormance sutters.
It the use ot the processor`s Ievel 2 cache can bring about signiticant improvement in the per-
tormance ot the graphics subsystem, it vould have been vorth it. Lntortunately, the VGA
graphics modes are rarely used at all. Lven vhen used, there is little or no real benetit in caching
the memory area.1his BIOS teature essentially vastes the processor`s Ievel 2 cache on some-
thing that cannot possibly improve the system`s graphics pertormance.
1heretore, it is highly recommended that you disable this BIOS teature.1here is no reason to
enable it even it you use real mode DOS a lot or vork a lot in Windovs Sate Mode.
Virus Worning
1his BIOS teature provides rudimentary anti-virus protection by monitoring vrites to the boot
sector and partition table.
It this teature is enabled, the BIOS halts the system and tlashes a varning message vhenever it
detects an attempt to vrite to the boot sector or the partition table. Please note that this only
protects the boot sector and the partition table, not the entire hard disk.
It this teature is disabled, the BIOS does not monitor vrites to the boot sector and partition
table.
V
1his teature can cause problems vith sottvare that need to access the boot sector. One good
onvard. When enabled, this teature causes the installation routine to tail.Also, many disk diag-
nostic utilities that access the boot sector can also trigger the system halt and error message as
vell.1heretore, you should disable this teature betore running such sottvare.
Note that this teature is useless tor hard disks that run on external controllers vith their ovn
BIOS. Boot sector viruses bypass the system BIOS vith its anti-virus protection teatures and
vrite directly to the hard disks. Such controllers include additional IDL or SCSI controllers that
are either built into the motherboard or available through add-on cards.
VLink 8 Support
V-Link is the name ot the proprietary interchip bus used in nev VIA chipsets. Previously,VIA
used the PCI bus to connect the North Bridge and the South Bridge ot their chipsets.
Hovever, vith high-speed PCI devices already saturating the PCI bus, there vas little band-
vidth lett tor interchip communications.
So, tolloving Intel`s lead vith the Intel Hub Architecture, they designed a tast dedicated bus
to link the North Bridge vith the South Bridge chips in their chipsets.1hey christened this
nev interchip bus as the V-Iink bus.
1he initial version used a quad-pumped 8-bit bus running at 66MHz to provide 266MB/s ot
interchip bandvidth. 1his gave them a dedicated bus vith tvice the bandvidth ot the PCI bus
(vhich also has to be shared vith other PCI devices,.1he V-Iink debuted in the VIA Apollo
K1266 chipset.
VIA recently enhanced their V-Iink bus to provide even more bandvidth tor interchip commu-
nications. Starting vith the Apollo K1400 and P4X400 chipsets, the clock speed ot the V-Iink
bus has been doubled to 133MHz. 1his doubles the bandvidth ot the V-Iink bus to S33MB/s.
Although the nev bus is only tour times tas ter than the PCI bus,VIA chose to call the nev bus
8 V-Link.
1he VLink 8 Support BIOS teature is used to toggle the V-Iink bus mode betveen the
original V-Iink and the never and taster 8X V-Iink.
It this teature is enabled, the quad-pumped 8-bit V-Iink bus svitches to the nev 8X V-Iink
mode, vhich runs at 133MHz and delivers a bandvidth ot 333MBs.
It this teature is disabled, the V-Iink bus uses a clock speed ot 66MHz, essentially reverting to
the original V-Iink standard. It then delivers a bandvidth ot 266MBs.
1his BIOS teature vas most likely included tor troubleshooting purposes . It is highly recom-
mended that you enable this BIOS teature tor better pertormance.
vLnk 8X SupporI 826
V
W
Wotchdog linor
1he Watchdog 1iner (WD1) is an independent monitoring circuit built into the chipset to
detect vhen a computer maltunctions due to a sottvare or hardvare error. It does this by
employing a countdovn timer that limits the amount ot time a particular task is alloved to
take.
Lvery time the operating system pertorms a task, the countdovn timer keeps track ot the
amount ot time taken. It the task cannot be completed vithin a predetermined time, the
Watchdog 1imer assumes that the computer has locked up and initiates a number ot actions.
1hese may be attempts at correcting the problem, like generating a non-maskable interrupt, or
the Watchdog 1imer may just reboot or shut dovn the computer.
1he WD1 timer ticks approximately once every 0.6 seconds, but there is a one-tick uncertainty.
1his means that the very tirst timer tick may occur immediately vhen the timer is started or up
to 0.6 seconds later.
By detault, the WD1 timer is set to 04h, vhich allovs a timeout period ot 1.8 to 2.4 seconds.
1he timer can be set up to a maximum value ot 3Fh, vhich gives a timeout period ot approxi-
mately 37.3 seconds.
1his BIOS teature controls the operation ot the chipset`s Watchdog 1imer.
When enabled, the Watchdog 1imer vill monitor the time taken tor each task pertormed by
the operating system.Any timeout vill cause it to initiate corrective actions like generate a non-
maskable interrupt or reboot the computer.
When disabled, the Watchdog 1imer vill not monitor the time taken tor each task pertormed
by the operating system. Lven it the system locks up, the Watchdog 1imer vill not initiate any
corrective action.
It is recommended that you enable the Watchdog 1imer to automatically detect hardvare and
sottvare errors that lock up the computer.While it may do nothing more than automatically
reboot or shut dovn the computer vhen an irresolvable error occurs, there is a chance it may
allov the correction ot the problem and allov the computer to tunction normally.
Writo Doto In to Rood Doloy
device.
W
It a 1 Cycle delay is selected, every read command that tollovs a vrite operation is delayed
It a 2 Cycles delay is selected, every read command that tollovs a vrite operation is delayed
1he 2 Cycles option reduces read pertormance but it improves stability, especially at higher
clock speeds. It may also allov the memory chips to run at a higher speed. In other vords,
increasing this delay may allov you to overclock the memory module higher than is normally
possible.
By detault, this BIOS teature is set to 2 Cycles. 1his meets LDLC`s specitication ot 2 clock
cycles tor vrite-to-read command delay in DDP400 memory modules. DDP266 and
DDP333 memory modules require a vrite-to-read command delay ot only 1 clock cycle.
Writo Rocovory lino
It the delay is too short, the bank may be precharged betore the active bank has enough time to
store the vrite data in the memory cells.1his causes data to be lost or corrupted.
Please note that this BIOS teature does not determine the time it takes tor the bank to
precharge. It only controls hov soon the bank can start precharging right atter a vrite operation
to the same bank.
1he detault value is 2 Cycles, vhich meets LDLC specitications in DDP200 and DDP266
memory modules. DDP333 and DDP400 memory modules require a Write Pecovery 1ime ot
3 Cycles.
WrIc ccovcry Jmc 827
W
Acronym Iist
Acronyn Definition
=
4AC Alignment Check Interrupt
sec Microsecond
2D 1vo Dimensional
3D 1hree Dimensional
A
ACPI Advanced Contiguration and Pover Intertace
AGP Accel erated Graphics Port
AIL Arithmetic Iogic Lnit
AMD Advanced Micro Devices, Inc.
API Application Program Intertace
APIC Advanced Programmable Inter rupt Control ler
A1 Advanced 1echnology
A1A Advanced 1echnology Attachment
A1I Allied 1elesyn International
B
BIOS Basic Input Output System
C
CAS Column Address Strobe
CD Compact Disc
CD-POM Compact Disc - Pead Only Memor y
CIK Clock
CIK_C1I Clock Control
CMD Command
CMOS Complementary Metal-Oxide Semiconductor
CPL Central Processing Lnit
C1PI Control
Acronym LsI 820
D
DBI Dynamic Bus Inversion
DDP Doubl e Data Pate
DIMM Dual Inl ine Memor y Module
DIP Dual Inl ine Package
DMA Direct Memory Access
DMI Desktop Management Intertace
DOS Disk Operating System
DPAM Dynamic Pandom Access Memory
DVD Digital Versatile Disc Digital Video Disc
E
LA (LSN Pating, Lngineering Aide
LCC Lrror Checking and Correction
LCP Lxtended Capabil ities Port
LMI Llectromagnetic Interterence
LPP Lnhanced Parallel Port
LPPOM Llectrically Programmable Pead Only Memory
LSCD Lxtended System Contiguration Data
LX1 Lxtension
F
lAQ lrequently Asked Questions
lDC lloppy Disk Controll er
lDD lloppy Disk Drive
lIlO lirst In, lirst Out
lOP linal Opcode
lPL lloating-Point Lnit
lSB lront-Side Bus
C
GAP1 Graphics Address Pelocation 1able
GB Gigabyte
GBs Gigabytes per Second
8rcakng Jhrough Ihc 8I0S 8arrcr 880
GHz Gigahertz
GPL Graphics Processing Lnit
GLI Graphical Lser Intertace
H
HDD Hard Disk Dr ive
Hex Hexadecimal
HPSIP Hevlett-Packard Serial Intra-Ped
I
IBM International Business Machines Corporation
IDL Integrated Drive Llectronics
ID1 Interr upt Descr iptor 1able
ILLL Institute ot Llectr ical 8 Llectronics Lngineers
IN1 Interr upt
IO InputOutput
IP Intra-Ped
IrDA Intrared Data Association
IPQ Interr upt Pequest
ISA Industry Standard Architecture
j
LDLC oint Llectron Device Lngineer ing Council
K
KB Kil obyte
L
IAN Iocal Area Netvork
Iat Iatency
IPC Iov Pin Count
M
MB Megabyte
Mbit Megabit
MBs Megabytes per Second
MCA Micro Channel Architecture
Acronym LsI 881
MCH Memory Controller Hub
MHz Megaher tz
MMX Multi-Media Lxtensions
MPLG Moving Picture Lxperts Group
MPS Multi-Processor Specitication
MPO Memory Pequest Organizer
MS-DOS Microsott Disk Operating System
msec Mill isecond
MSP Model Specitic Pegister
M1PP Memory 1ype Pange Pegister
N
NA Not Applicable
NIC Netvork Intertace Card
ns Nanosecond
N1 Nev 1echnology
O
OLM Or iginal Lquipment Manutacturer
OS Operating System
OS2 Operating System 2 (IBM,
P
PAM Programmable Attribute Map
PC Personal Computer
PCI Per ipheral Component Interconnect
PDA Personal Digital Assistant
PH Page Hit
PIC Programmable Inter rupt Controller
PIO Programmed InputOutput
PIPQ Programmable Inter rupt Pequest
PICC Plastic Ieaded Chip Carr ier
PnP Plug and Play
POS1 Pover-On Diagnostic 1est
882 8rcakng Jhrough Ihc 8I0S 8arrcr
PPOCHO14 Processor Hot Inter rupt
PS2 Personal System 2 (IBM,
Q
QDP Quad Data Pate
QW Quadvord
R
PAID Pedundant Ar ray ot Inexpensive Disks
PAM Pandom-Access Memory
PAS Pov Address Strobe
POM Pead-Only Memory
PW PeadWrite
PxD Data Peception
8
SBA Sideband Address
SCSI Small Computer System Intertace
SDPAM Synchronous Dynamic Pandom Access Memory
Sec Second(s,
SIMD Single Instr uction-Stream, Multiple Data-Stream
S.M.A.P.1. Selt Monitoring Analysis And Peporting 1echnology
SMI System Management Inter rupt
SPD Serial Presence Detect
SPP Standard Parallel Port
SPAM Static PAM
SSL Streaming SIMD Lxtensions
S1P Suspend 1o PAM
T
1CC 1her mal Control Circuit
tPAS Minimum Pov Active 1ime
tPC Pov Cycle 1ime
tPCD Pov Address to Col umn Address Delay
tPP PAS Precharge 1ime
Acronym LsI 888
tPPD Bank-to-Bank Delay
tWP Write Pecovery 1ime
tW1P Write Data In to Pead Command Del ay
1xD Data 1ransmission
C
LC Lncached
LMA Lpper Memory Area or Lnitied Memory Architecture
LSB Lniversal Ser ial Bus
LSWC Lncacheable, Speculative Write Combine
1
VGA Video Graphics Adapter
WD1 Watchdog 1imer

A
XMM Lxtended Memor y Manager
XP Lxperience (Microsott Windovs XP,
X1 Lxtended 1echnology
884 8rcakng Jhrough Ihc 8I0S 8arrcr
Synbols
1/1 dividers, 3S
1/2 dividers, 3S
2 cycles, 32
2/3 dividers, 3S
2/S dividers, 3S
3 cycles, 32
8-bit I/O Recovery 1ine, 30, 1S0
8-bit ISA cards, 1S0
16-bit I/O Recovery 1ine, 30, 1S0
16-bit ISA cards, 1S0
32-bit Disk Access, 30, 1S1
32-bit 1ransfer Mode, 31, 1S1
A
A20 node svitching, 69, 213
ABI1 K17A-RAID notherboard,
BIOS updates for, 11
ABI1 NV7-series notherboards, S2
ABI1 S17 BIOS setup utility, 14
accessing BIOS setup utility, 14
Acronyn List, 329
Act Bank A to B CMD Delay, 32, 1S3
adapters, Prinary Graphics Adapter,
107, 267
addresses, Shadoving Address Ranges,
130, 303
Advanced Progrannable Interrupt
Controller (APIC), 41, 77
Interrupt Mode, 223
AGP 2 Mode, 32, 1S3
AGP 2 transfers, 32
AGP 4 cards, 32
AGP 4 Drive Strength, 32, 1S4-1SS
AGP 4 Mode, 33, 1SS
AGP 4 protocol, 33
AGP 8 Mode, 33, 1S6
AGP 8-capable notherboards, AGP
Capability, 34
AGP Alvays Conpensate, 33, 1S7
AGP aperture, 69, 213
AGP Aperture Size, 34, 1S7-1S9
AGP buses, 2 node, 32
AGP Capability, 34, 1S9
AGP Clock/CPU FSB Clock, 3S, 1S9
AGP Drive Strength, 32, 3S, 160-161
AGP Drive Strength N Ctrl, 36, 161
AGP Drive Strength P Ctrl, 36, 162
AGP Driving Control, 36, 161-162
AGP Driving Value, 37, 163
AGP Fast Write, 37, 164
AGP ISA Aliasing, 37, 164-16S
AGP Master 1WS Read, 38, 16S
AGP Master 1WS Write, 38, 166
AGP Prefetch, 38, 166
AGP Secondary Lat 1iner, 39, 167-168
AGP Spread Spectrun, 39, 168
AGP to DRAM Prefetch, 40, 169
AGPCLK/CPUCLK, 40, 169
aliasing, AGP ISA Aliasing, 164-16S
All Banks, 123
All Banks Precharge Connand, 123
Anti-Virus Protection, 40, 170
API (Application Progran Interface), S
APIC (Advanced Progrannable
Interrupt Controller), 41, 77
Interrupt Mode, 223
APIC Function, 41, 74, 170
Index
Application Progran Interface (API), S
ASK IR (Anplitude Shift Keyed IR)
node, 24S
Assign IRQ For USB, 41, 171
Assign IRQ For VGA, 41, 171
A1 Bus Clock, 41, 172-173
A1A100RAID IDL Controller, 42, 173
Athlon 4 SSLD Instruction, 42, 174
Auto Detect DIMM/PCI Clk, 43, 17S
Auto 1urn Off PCI Clock Pin, 43, 17S
Avard, 282
AvardFlash softvare, 12
AvardFlash utility connands, 13
B
bandvidth, quadrupling through
AGP 8 transfer protocol, 1S6
Basic Input/Output Systen. 8ee BIOS
batteries, CMOS, 19
BIOS (Basic Input/Output Systen), S
accessing BIOS setup utility, 14
corrupted BIOS, 20-21
llash BIOS Protection, 63, 208
hov it vorks, 3-6
motherboard BIOS, 6-7
optimizing, 7-8, 14
Primary VGA BIOS, 268
Video BIOS Cacheable, 320
Video BIOS Shadoving, 143-144,
321-322
BIOS chips, 6, 23
hot nashing, 22
inserting, 24
removing, 24
svapping, 24-23
BIOS drivers, 7
BIOS ash disk, preparing, 12
BIOS ash utility, 24
BIOS ID, deternining, 10
BIOS setup utility, 14
BIOS updates, 8-9
tor ABI1 K17A-PAID motherboard, 11
determining BIOS ID, 10
determining BIOS version, 9
nas hing motherboard BIOS, 12-13
obtaining, 11-12
preparing BIOS nash disk, 12
boot disks
booting up vith, 24
creating in Windovs XP, 12
Boot Other Device, 44, 176
Boot Sequence, 44, 176
Boot Sequence L1 Means, 4S, 177
Boot to OS/2, 4S, 177
Boot Up Floppy Seek, 4S, 178
Boot Up NunLock Status, 4S, 178
booting
vith boot disks, 24
Boot Other Device, 44, 176
Boot Sequence, 44, 176
Boot Sequence LX1 Means, 43, 177
Boot 1o OS2, 43, 177
Boot Lp lloppy Seek, 43, 178
Boot Lp NumIock Status, 43, 178
lirst Boot Device, 63, 208
Quick Boot, 110, 270
Second Boot Device, 130, 302
1hird Boot Device, 137, 312
burst transactions
SDPAM Burst Ien, 119
SDPAM Burst Iength, 119
bursts
DPAM Burst Iength 8QW, 196
PCI Dynamic Bursting, 233-236
SDPAM Burst Ien, 283
SDPAM Burst Iength, 284
Byte Merge, 46, 178-179
C
caching
CPL Ievel 1 Cache, 184-183
CPL Ievel 2 Cache, 183-186
CPL Ievel 3 Cache, 186
App|caIon Program InIcrfacc (API) 88
I3 Cache, 231
Ievel 2 Cache Iatency, 232
PCI Master Pead Caching, 102, 239
System BIOS Cacheable, 136, 311
Video BIOS Cacheable, 143, 320
Video Memory Cache Mode, 144,
322-323
Video PAM Cacheable, 143, 323-324
capability, AGP Capability, 1S9
capacity of BIOS chips, 6
CAS (Colunn Address Strobe), 19S
chaining, PCI Chaining, 97, 2S2
ChipAvay, 40
chips, BIOS chips, 6
CLK_C1L (Clock Control), 79
clock speed
ISA buses, 41
setting ratios betveen, 40
Clock 1hrottle, 47, 180
clocks
AGP ClockCPL lSB Clock, 33, 139
AGPCIKCPLCIK, 169
A1 Bus Clock, 172-173
Auto Detect DIMMPCI Clk, 173
Clock 1hrottle, 180
Disable Lnused PCI Clock, 36, 193
ISA 14.318MHz Clock, 78, 223
K7 CIK_C1I Select, 228-229
KBC Input Clock Select, 80, 229
PCI ClockCPL lSB Clock, 98, 233-234
CMOS battery renoval, 19
CMOS discharge junper, 18
Colunn Address Strobe (CAS), 19S
connand leadoff tine, 122
connand queues, Host Bus In-Order
Queue Depth, 73
Conpatible FPU OPCODL, 47, 67,
181, 211
conpliance, PCI 2.1, 97, 2S1-2S2
concurrency, P2C/C2P
Concurrency, 249
controllers
A1A100PAID, 42, 173
Onboard lDD Controller, 90, 243
Onboard IDL-1 Controller, 91, 244
Onboard LSB Controller, 93, 246
Lltra DMA-66 IDL Controller, 140, 316
LSB Controller, 141, 317
controls, SDRAM Precharge
Control, 124
hot nashing, 24
CPU bus, 3S, 241
CPU Drive Strength, 48, 181
CPU Fast String, 48, 182
CPU Hyper-1hreading, 49, 182-183
CPU L2 Cache LCC Checking, 49, 184
CPU Latency 1iner, S0
CPU Level 1 Cache, S0, 184-18S
CPU Level 2 Cache, S0, 18S-186
CPU Level 3 Cache, S1, 186
CPU 1hernal-1hrottling, S1, 187
CPU to PCI Post Write, S1, 188
CPU to PCI Write Buffer, S2, 189
CPU VCore Voltage, S2, 189
CPU/DRAM CLK Synch C1L, 48
CR2032 batteries, 19
Create an MS-DOS startup disk, 12
create non-local surface call, 1S8
currents, Differential Current, S6
D
data integrity, DRAM Data Integrity
Mode, S8
DBI (Dynanic Bus Inversion), S3, 191
DBI Output for AGP 1ransnitter,
S3, 191
Delay DRAM Read Latch, S3, 191
Delay IDL Initial, S4, 192
Delay Prior 1o 1hernal, S4, 193
Delayed 1ransaction, SS, 194-19S
delays
2 cycles or 3 cycles, 32
Act Ban A to B CMD Delay, 133
Delay DPAM Pead Iatch, 33, 191
Delay IDL Initial, 34, 192
Delay Prior 1o 1hermal, 194
Delayed 1ransaction, 33, 194-193
DPAM Pead Iatch Delay, 61, 202-203
Keyboard Auto-Pepeat Delay, 80, 230
PCI Delay 1ransaction, 98, 234-233
PCI Delayed 1ransaction, 33, 194
SDPAM Active to Precharge Delay,
117, 280
SDPAM Bank-to-Bank Delay, 118,
128, 282
SDPAM PAS Precharge Delay, 124, 294
SDPAM PAS-to-CAS Delay, 126, 296
SDPAM Write to Pead Command Delay,
129, 301
1ypematic Pate Delay, 138, 313
Write Data In to Pead Delay, 147, 326
Differential Current, S6
DIP (Dual In-line Package), 6, 23
Direct Menory Access (DMA), 7S
LCP Mode Lse DMA, 63, 203
IDL Bus Master Support, 220
Mas ter Drive LltraDMA, 83, 234-233
Slave Drive LltraDMA, 132, 303-306
Lltra DMA Mode, 139, 314-313
Disable Unused PCI Clock, S6, 19S
disks, creating DOS boot disks, 22-23
displays, Init Display First, 76, 221
dividers, 3S
DMA (Direct Menory Access), 7S
LCP Mode Lse DMA, 63, 203
IDL Bus Master Support, 220
Mas ter Drive LltraDMA, 83, 234-233
Slave Drive LltraDMA, 132, 303-306
Lltra DMA Mode, 139, 314-313
DOS boot disks, creating, 22-23
DOS Flat Mode, S7
DRAM
Delay DPAM Pead Iatch, 33, 191
OS Select lor DPAM ~ 64MB, 248
DRAM Act to PreChrg CMD, S7, 19S
DRAM Burst Length 8QW, S7, 196
DRAM Data Integrity Mode, S8,
197-198
DRAM Idle 1iner, S8, 198-199
DRAM Interleave 1ine, S9, 200
DRAM Page-Mode, S9
DRAM PreChrg to Act CMD, 60, 200
DRAM Ratio (CPU:DRAM), 60,
201-202
DRAM Ratio H/W Strap, 61, 202
DRAM Read Latch Delay, 61, 202-203
DRAM Refresh Rate, 203
drive strength
AGP 4X Drive Strength, 134-133
AGP Drive Strength, 160-161
AGP Drive Strength N Ctrl, 161
AGP Drive Strength P Ctrl, 162
CPL Drive Strength, 48, 181
MD Driving Strength, 236
N transistor drive strength, 113
P transistor drive strength, 116
S2K Bus Driving Strength, 277
drivers, BIOS, 7
driving controls, AGP Driving
Control, 162
driving strength
MD Driving Strength, 84
S2K Bus Driving Strength, 113
driving values, AGP Driving Value, 163
Dual In-line Package (DIP), 6, 23
Duple Select, 62, 204
Dynanic Bus Inversion (DBI), S3, 191
L
LCC (Lrror Checking and Correction),
49, S8
CPL I2 Cache LCC Checking, 184
DPAM Data Integrity Mode, 197-198
SDPAM LCC Setting, 121, 288
0c|ay I0L InIa| 888
LCP (Ltended Capabilities Port),
9S, 20S
LCP Mode Use DMA, 63, 20S
edge-trigged, 100
LMI (Llectronagnetic Interference), 43
AGP Spread Spectrum, 168
lSB Spread Spectrum, 212
Lnhanced 3DNov!, 174
Enhance IDE Operaiion Cner
inous NT, 1S1
LPP (Lnhanced Parallel Port), 9S,
20S, 249
LPP Mode Select, 63, 20S
Lrror Checking and Correction (LCC),
49, S8
CPL I2 Cache LCC Checking, 184
DPAM Data Integrity Mode, 197-198
SDPAM LCC Setting, 121, 288
errors, Speed Lrror Hold, 306
LSCD (Ltended Systen Connguration
Data), 66
lorce Lpdate LSCD, 66, 210
Peset Contguration Data, 113, 273
Ltended Capabilities Port (LCP),
9S, 20S
Ltended Systen Connguration Data
(LSCD), 66
lorce Lpdate LSCD, 66, 210
Peset Contguration Data, 113, 273
F
Fast R-W 1urn Around, 64, 207
fast string processing, 182
Fast Write to Read 1urnaround, 64, 207
FDD (oppy drive controller), 90
Onboard lDD Controller, 243
Peport No lDD lor Win93, 274
FIFO (First In, First Out), 323
nnal opcode (FOP), 67
First Boot Device, 6S, 208
First In, First Out (FIFO), 323
Flash BIOS Protection, 6S, 208
ashing notherboard BIOS, 12-13
Floppy 3 Mode Support, 6S, 209
Floppy Disk Access Control, 66, 209
oppy drive controller (FDD), 90
Onboard lDD Controller, 243
Peport No lDD lor Win93, 274
oppy drives
lloppy 3 Mode Support, 63, 209
Svap lloppy Drive, 133, 310
FOP (nnal opcode), 67
FOP code, 211
fopcode, 211
Force 4-Way Interleave, 66, 210
Force Update LSCD, 66, 210
FPU OPCODL Conpatible Mode, 47,
67, 181, 211
Frane Buffer Size, 67
franebuffer vrites, 103
FSB (front side bus), 3S
FSB Spread Spectrun, 68, 212
Full Screen Logo, 68, 212
Full-Duple, 62
functions
APIC, 170
Onboard IP lunction, 243
G
GAR1 (Graphics Address Relocation
1able), 34, 69, 213
AGP Aperture Size, 137
Graphics Aperture Size, 70, 214
Gate A20 Option, 69, 213
Gigabyte Dual BIOS, 20
Graphic Win Size, 69, 213
Graphic Windov WR Conbin, 70, 214
Graphics Address Relocation 1able
(GAR1), 34, 69, 213
AGP Aperture Size, 137
0raphcs ApcrIurc Szcs 880
H
Half-Duple, 62
Hardvare Reset Protect, 72, 216
HDD S.M.A.R.1. Capability, 72,
216-217
Host Bus In-Order Queue Depth, 73,
217-218
hot ash-capable conputers,
preparing, 23
hot ashing, 21-22
BIOS chips, 22
booting up vith boot disks, 24
corrupted BIOS chips, 24
creating DOS boot disks, 22-23
motherboards, 26-27
preparing hot nash-capable computers, 23
svapping BIOS chips, 24
Hyper-1hreading 1echnology, 73,
218-219
I
ID, deternining BIOS ID, 10
IDL
Delay IDL Initial, 192
PCI IDL Busmaster, 236
IDL Bus Master Support, 7S, 220
IDL controllers, 44
A1A100PAID IDL Controller, 173
IDL HDD Block Mode, 7S, 220
idle linits, SDRAM Idle Linit, 122,
289-291
ILLL 1284, 249
In-Order Queue Depth, 76, 222-223
Infra-Red (IR), 62, 92
infra-red reception (RD), 114
Init Display First, 76, 221
Insert key, 18
inserting BIOS chips, 24
Intel Hyper-1hreading 1echnology, 49,
73, 183
interleaves
lorce 4-Way Interleave, 210
Pank Interleave, 271
SDPAM Bank Interleave, 117, 281-282
Interrupt Mode, 77, 223
intervals, refreshing, 112
IOQD, 77, 224-22S
IR (Infra-Red), 62, 92
IrDA (HPSIR) node, 24S
IRQ
Assign IPQ lor LSB, 41, 171
Assign IPQ lor VGA, 41, 171
PCI IPQ Activated By, 100, 237
ISA, AGP ISA Aliasing, 164-16S
ISA 14.318MHz Clock, 78, 22S
ISA buses, clock speed, 41
ISA cards
8-bit ISA cards, 130
16-bit ISA cards, 130
ISA Lnable Bit, 78, 22S, 227
)-K
K7 CLK_C1L Select, 79, 228-229
KBC Input Clock Select, 80, 229
Keyboard Auto-Repeat Delay, 80, 230
Keyboard Auto-Repeat Rate, 80, 230
keyboards
resetting BIOS, 18
LSB Keyboard Support, 141, 317
L
latency
AGP Master 1WS Pead, 166
Ievel 2 Cache Iatency, 81, 232
PCI Iatency 1imer, 237
ha|f-0up|cx 840
PCI 1arget Iatency, 103, 260
SDPAM CAS Iatency 1ime, 119, 283
LD-Off Dran RD/WR Cycles, 81
Level 1 cache, 184
Level 2 cache, 49, 18S
Level 2 Cache Latency, 81, 232
Level 3 cache, 81, 187, 231
level-triggered, 100
linits
SDPAM Idle Iimit, 122, 289-291
SDPAM Page Hit Iimit, 123, 292
SDPAM PH Iimit, 124, 293
locating CMOS discharge junper, 18
logos, Full Screen Logo, 212
LS/ZIP, 137
M
nappings, svapping (Onboard FDC
Svap A & B), 90
Master Drive PIO Mode, 83, 233
Master Drive UltraDMA, 83, 234-23S
Master Priority Rotation, 84, 23S
MD Driving Strength, 84, 236
nenory
Memory Hole At 13M-16M, 83, 236
OS2 Onboard Memory ~ 64M, 94, 247
saving (AGP Aperture Size,, 138
Share Memory Size, 131, 303
Video Memory Cache Mode, 322-323
Menory Hole At 1SM-16M, 8S, 236
nenory request organizer (MRO),
134, 308
nice, USB Mouse Support, 141, 318
Microsoft Windovs 9S, Report No FDD
For Win9S, 112
Model Specinc Register (MSR), 79
notherboard BIOS, 6
nashing, 12-13
vhat it does, 7
notherboards
ABI1 NV7-series, CPL VCore Voltage, 32
AGP 8x-capable motherboards, AGP
Capability, 34
hot nashing, 26-27
nouse controls, PS/2 Mouse Function
Control, 108, 269
MP Capable Bit Identify, 8S, 237, 239
MPS (Multi-Processor Specincation),
86, 239
MPS Control Version For OS, 86, 239
MPS Revision, 86, 239
MRO (nenory request organizer),
134, 308
MSR (Model Specinc Register), 79
Multi-Processor Specincation (MPS),
86, 239
Multi-Sector 1ransfers, 87, 240
N
N transistor drive strength, 11S
N/B Strap CPU As, 88, 241
No Mask of SBA FL, 88, 241
Non-ACP BIOSes, 10S
NVIDIA nForce, SuperStability
Mode, 134
O
obtaining BIOS updates, 11-12
OLM (Original Lquipnent
Manufacturer), 8
Onboard FDC Svap A & B, 90, 243
Onboard FDD Controller, 90, 243
Onboard IR Function, 92, 24S
Onboard Parallel Port, 92, 24S
Onboard Serial Port 1, 92, 246
0nhoard Scra| PorI 1 841
Onboard USB Controller, 93, 246
OnChip VGA Mode Select, 93
One Bank, 123
operating systens, 6
BIOS, 7
optinizing BIOS, 7-8, 14
Original Lquipnent Manufacturer
(OLM), 8
OS
MPS Control Version lor OS, 239
PNP OS Installed, 264-263
OS Select For DRAM > 64MB, 94, 248
OS/2, booting to, 177
OS/2 Onboard Menory > 64M, 94, 247
overclocking, AGP 4 Drive
Strength, 1S4
P
P transistor drive strength, 116
P2C/C2P Concurrency, 9S, 249
page hits, SDRAM Page Hit Linit,
123, 292
page nodes, DRAM-Page Mode, S9
pages, SDRAM Page Closing Policy, 123
Parallel Port Mode, 9S, 249-2S0
parallel ports
Onboard Parallel Ports, 92, 243
Parallel Port Mode, 93, 249-230
Passive Release, 96, 2S0
PCI
CPL to PCI Post Write, 31
CPL to PCI Write Butter, 32
Disable Lnused PCI Clock, 36, 193
PCI 2.1 Conpliance, 97, 2S1-2S2
PCI Chaining, 97, 2S2
PCI Clock/ CPU FSB Clock, 98,
2S3-2S4
PCI Delay 1ransaction, 98, 2S4-2SS
PCI Delayed 1ransaction, SS, 97, 194
PCI devices, AGP latency, 39
PCI Dynanic Bursting, 99, 2SS-2S6
PCI IDL Busnaster, 100, 2S6
PCI IRQ Activated By, 100, 2S7
PCI Latency 1ine, 39
PCI Latency 1iner, 100, 2S7
PCI Master 0 WS Read, 101, 2S8
PCI Master 0 WS Write, 101, 2S8
PCI Master Read Caching, 102, 2S9
PCI Pipelining, 102, 2S9
PCI Prefetch, 102, 260
PCI 1arget Latency, 103, 260
PCI to DRAM Prefetch, 103, 261
PCI2 Access 1 Retry, 96, 2S1
PCI/VGA Palette Snoop, 103, 261
Phoeni 1echnologies Avard, 282
PIO (Progranned Input/Output),
7S, 220
Mas ter Drive PIO Mode, 83, 233
Share Drive PIO Mode, 304
Slave Drive PIO Mode, 131
PIO Mode, 104, 262
pipelining, PCI Pipelining, 2S9
PIRQ Use IRQ No., 104-10S, 262, 264
PLCC (Plastic Leaded Chip Carrier),
6, 23
PLL Orershooi on ake-Cp from Disconneci
Causes Auio-Compensaiion Circuii io Fail,
79, 228
PNP OS Installed, 10S-106, 264-26S
polarity (1, R Inverting Lnable), 137
ports
parallel ports
n|oaro Iaraiiei Iorts, 92, 24
Iaraii ei Iort Mooe, 9, 24920
serial ports
n|oaro :eriai Iort 1, 92, 24
n|oaro :eriai Iort 2, 9', 24
POS1 (Pover-On Diagnostic 1est), 7
Post Write Conbine, 106, 266
pover consunption, reducing, 43
0nhoard Scra| PorI 2 842
Pover On Function, 107, 267
Pover-On Diagnostic 1est (POS1), 7
prefetching
AGP Pretetch, 166
AGP to DPAM Pretetch, 169
data, system controllers, 40
PCI Pretetch, 102, 260
PCI to DPAM Pretetch, 103, 261
preparing
BIOS nash disk, 12
hot nash-capable computers, 23
Prinary Graphics Adapter, 107, 267
Prinary VGA BIOS, 108, 268
Processor Nunber Feature, 108, 269
Progranned Input/Output (PIO),
7S, 220
Master Drive PIO Mode, 83, 233
Share Drive PIO Mode, 304
Slave Drive PIO Mode, 131
protection, Anti-Virus Protection, 170
PS/2 Mouse Function Control, 108, 269
Q
QDR (Quad Data Rate), 60
quadrupling bandvidth through
AGP 8 transfer protocol, 1S6
queues
Host Bus In-Order Queue Depth,
217-218
In-Order Queue Depth, 76, 222-223
Quick Boot, 110, 270
Quick Pover On Self 1est, 110, 270
R
Rank Interleave, 111, 271
ranks, 111
RAS (Rov Address Strobe), 19S
ratios
CPL:DPAM, 88
DPAM Patio (CPL:DPAM,, 60,
201-202
DPAM Patio HW Strap, 61, 202
setting betveen clock speeds, 40
Read Wait State, 111, 272
Read-Around-Write, 111, 271
recovery nechanisns
8-bit IO Pecovery 1ime, 130
16-bit IO Pecovery 1ime, 130
reducing pover consunption, 43
Refresh Interval, 112, 272
Refresh Mode Select, 112, 273
refresh rates, DRAM Refresh Rate, 203
refreshing
Petresh Interval, 112, 272
Petresh Mode Select, 112, 273
renoving BIOS chips, 24
repeating
Keyboard Auto-Pepeat Delay, 80
Keyboard Auto-Pepeat Pate, 80
Report No FDD For Win9S, 112, 274
Reset Connguration Data, 113, 27S
resetting BIOS vith keyboard, 18
Resource Controlled By, 113, 27S
rotation, Master Priority Rotation,
84, 23S
Rov Active 1ine, 121
Rov Address Strobe (RAS), 19S
Rov Cycle 1ine, 121
RD (infra-red reception), 114
RD, 1D Active, 114, 276
S
S2K Bus Driving Strength, 11S, 277
S2K Strobe N Control, 11S, 277
S2K Strobe P Control, 116, 278
saving nenory, AGP Aperture Size, 1S8
SBA (Sideband Address), 88, 241
SDRAM 1 1 Connand, 116, 278-279
SDRAM 1 1 Connand Control, 117,
279-280
S0AM 1 J Lommand LonIro| 848
SDRAM Active Precharge Delay,
117, 280
SDRAM Bank Interleave, 117, 281-282
SDRAM Bank-to-Bank Delay, 118,
128, 282
SDRAM Burst Len, 119, 283
SDRAM Burst Length, 119, 284
SDRAM CAS Latency 1ine, 119, 28S
SDRAM Connand Leadoff 1ine,
120, 28S
SDRAM Connand Rate, 120, 286
SDRAM Cycle Length, 120, 287
SDRAM Cycle 1ine 1ras/1rc, 121, 288
SDRAM LCC Setting, 121, 288
SDRAM Idle Linit, 122, 289-291
SDRAM Leadoff Connand, 122, 291
SDRAM Page Closing Policy, 123, 291
SDRAM Page Hit Linit, 123, 292
SDRAM PH Linit, 124, 293
SDRAM Precharge Control, 124, 293
SDRAM RAS Precharge Delay, 124, 294
SDRAM RAS Precharge 1ine, 12S, 29S
SDRAM RAS Pulse Width, 12S, 29S
SDRAM RAS-to-CAS Delay, 126, 296
SDRAM Rov Active 1ine, 126, 297
SDRAM Rov Cycle 1ine, 126, 297
SDRAM 1ras 1ining Value, 127, 298
SDRAM 1rc 1ining Value, 127, 298
SDRAM 1rcd 1ining Value, 128, 299
SDRAM 1rp 1ining Value, 128, 300
SDRAM 1rrd 1ining Value, 129, 300
SDRAM Write Recovery 1ine, 129, 301
SDRAM Write to Read Connand
Delay, 129, 301
Second Boot Device, 130, 302
Security Setup, 130, 302
Self Monitoring Analysis And Reporting
1echnology (S.M.A.R.1.), 72
HDD S.M.A.P.1. Capability, 216-217
serial ports
Serial Presence Detect (SPD), 1S3, 202
shadoving,Video BIOS Shadoving,
143-144, 321-322
Shadoving Address Ranges, 130, 303
Share Menory Size, 131, 303
Sideband Address (SBA), 88, 241
sidebanding support, 1S4
sinultaneous svitching outputs, S3, 191
Slave Drive PIO Mode, 131, 304
Slave Drive UltraDMA, 132, 30S-306
S.M.A.R.1. (Self Monitoring Analysis
And Reporting 1echnology), 72
HDD S.M.A.P.1. Capability, 216-217
snooping, PCI/VGA Palette Snoop,
103, 261
softvare, AvardFlash, 12
SPD (Serial Presence Detect), 1S3, 202
Speed Lrror Hold, 132, 306
Split Lock Operations, 133, 306
Spread Spectrun, 133, 307-308
SRAM (Static RAM), 184
SSL (Streaning SIMD Ltensions), 174
SSL-optinized softvare, 43
Static RAM (SRAM), 184
Streaning SIMD Ltensions (SSL), 174
string, CPU Fast String, 182
Super Bypass Mode, 134, 308
Super Bypass Wait State, 134, 308
SuperStability Mode, 134, 309-310
Svap Floppy Drive, 13S, 310
svapping
BIOS chips, 24-23
noppy drives, 133, 310
mappings ot drives, 90, 243
Synchronous Mode Select, 136, 310
S0AM AcIvc Prcchargc 0c|ay 844
Systen BIOS Cacheable, 136, 311
systen controllers, prefetching data, 40
1
1CC (1hernal Control Circuit), S4
testing, Quick Pover On Self 1est, 270
1hird Boot Device, 137, 312
1horoughbred-A cores, 79
1horoughbred-B cores, 80
threading
CPL Hyper-1hreading, 49, 182-183
Hyper-1hreading 1echnology, 73, 218-219
throttling, CPU 1hernal-1hrottling,
187
tine
DPAM Interleave 1ime, 39, 200
SDPAM CAS Iatency 1ime, 283
SDPAM Command Ieadott 1ime, 283
SDPAM PAS Precharge 1ime, 123, 293
SDPAM Pov Active 1ime, 126, 297
SDPAM Pov Cycle 1ime, 126, 297
SDPAM 1ras 1iming Value, 127
SDPAM 1rc 1iming Value, 127, 298
SDPAM 1rcd 1iming Value, 128, 299
SDPAM 1rp 1iming Value, 128, 300
SDPAM 1rrd 1iming Value, 129, 300
SDPAM Write Pecovery 1ime, 129, 301
Write Pecovery 1ime, 148, 327
tiners
AGP Secondary Iat 1imer, 167-168
CPL Iatency 1imer, 30
DPAM Idle 1imer, 38, 198-199
PCI Iatency 1imer, 100, 237
Watchdog 1imer, 147, 326
trafnc, P2C/C2P Concurrency, 9S
transactions, PCI Delay 1ransaction,
2S4-2SS
transfers, Multi-Sector 1ransfers, 87, 240
transnission (1D), 114
tRAS, 121, 298
SDPAM PAS Pulse Width, 123
tRC, 121
troubleshooting
hot nashing, 21-22
PI: chips, 22
|ootin up uith |oot oisks, 24
corrupteo PI: chips, 24
creatin D: |oot oisks, 222'
mother|oaros, 227
preparin hot ashcapa|ie computers, 2'
suappin PI: chips, 24
unbootable systems, 17
|uiitin mechanisms that protect computers
from |ein un|oota|ie oue to incorrect
PI: settins, 17
CM: |atter remo:ai, 19
CM: oischare jumper, 18
ke|oaro resets, 18
tRRD, 300
turnarounds
last P-W 1urn Around, 207
last Write to Pead 1urnaround, 207
tWR (Write Recovery 1ine), 129,
148, 327
tW1R, 207, 326
Write Data In to Pead Delay, 147
1, R Inverting Lnable, 137, 312
1D (transnission), 114
1ypenatic Rate, 137, 312
1ypenatic Rate Delay, 138, 313
1ypenatic Rate Setting, 138, 313
U
UC (UnCached), 323
Ultra DMA Mode, 139, 314-31S
Ultra DMA-66 IDL Controller, 140, 316
Ultra DMA-100 IDL Controller,
139, 31S
Ultra DMA-133 IDL Controller,
140, 31S
unbootable systens, 17
built-in mechanisms that protect
computers trom being unbootable due to
incorrect BIOS settings, 17
unhooIah|c sysIcms 846
CMOS battery removal, 19
CMOS discharge jumper, 18
keyboard resets, 18
UnCached (UC), 323
Uncached Speculative Write Conbining
(USWC), 70, 106, 142, 214
Video Memory Cache Mode, 144
universal BIOS ash utility, 27
updating BIOS, 8-9
determining BIOS ID, 10
determining BIOS version, 9
nas hing motherboard BIOS, 12-13
obtaining BIOS updates, 11-12
preparing BIOS nash disk, 12
USB
Assign IPQ lor LSB, 171
Assign IPQ lor VGA, 171
Onboard LSB Controller, 246
USB Controller, 141, 317
assigning IPQ to, 41
USB Keyboard Support, 141, 317
USB Mouse Support, 141, 318
USWC (Uncached Speculative Write
Conbining), 70, 106, 142, 214
Video Memory Cache Mode, 144
USWC Write Posting, 142, 318-319
utilities
BIOS nash utility, 24
BIOS setup utility, 14
universal BIOS nash utility, 27
V
version of BIOS, deternining, 9
VGA, assigning IRQ to, 41
Video BIOS Cacheable, 143, 320
Video BIOS Shadoving, 143-144,
321-322
Video Menory Cache Mode, 144,
322-323
Video RAM Cacheable, 14S, 323-324
virtual addressing, 1S7
Virus Warning, 14S, 324
viruses, Anti-Virus Protection, 170
ChipAvay, 40
VLink 8 Support, 146, 32S
voltage, CPU VCore Voltage, 189
W-Z
varnings,Virus Warning, 14S, 324
Watchdog 1iner (WD1), 147, 326
Windovs 9S, Report No FDD for
Win9S, 112, 274
Windovs P, creating boot disks, 12
vrite buffer
CPL to PCI Post Write, 188
CPL to PCI Write Butter, 189
Write Data in to Read Connand Delay
(tW1R), 64, 129
Write Data In to Read Delay, 147, 326
Write Recovery 1ine (tWR), 129,
148, 327
Zary, Ondrej, 27
unhooIah|c sysIcms 84
About the Author
Adrian Wong has been part ot the online hardvare community since 1996 vhen he tirst set
up Adrian`s Pojak Pot. Since then, the author has vritten many authoritative articles and guides
on computers.
Here`s a short list ot some ot his previous vorks:
lhe Mother|oaro PI: Ii ashin uioe
lhe 1ioeo PI: Ii ashin uioe
lhe Hot Iiashin uioe
Haro Disk Mths De|unkeo:
lhe Def initi:e :uapfiie ptimi:ation uioe
lhe Def initi:e Patter Lxtenoer uioe
lhe Compression Comparison uioe
lhe Def initi:e Maxtor :iient :tore uioe
lhe 1inoous 2000 Hints lips uioe
lhe Def initi:e Disk Cache ptimi:ation uioe
lhe Def initi:e Chunksi:e ptimi:ation uioe
lhe Def initi:e IDL Piock Mooe uioe
lhe Def initi:e 1ioeo PM Cachin uioe
Adrian`s articles and guides are considered reterence material by the computer hardvare com-
munity. In tact, the author regularly receives accolades trom both peers and members ot the
industry.
Adrian currently divides his time betveen medical school and Adrian`s Pojak Pot in Melaka,
Malaysia.
840 Why Adran's o|ak PoI?
About Adrian`s Pojak Pot
Adrian initially started Adrians Rojak Pot (http:vvv.rojakpot.com, as nothing more than
a personal homepage on 1ripod in 1996. Considering that he had absolutely no knovledge ot
H1MI, it`s amazing that Adrian`s Pojak Pot vas even born'
1hanks to Microsott`s lrontPage 98, Adrian tound that it vasn`t as hard as it appeared. Ot
course, he never had to vrite a single line ot H1MI code' Nevertheless, it galvanized him to
vork on his homepage, so that on the remote chance some lost soul happened upon the page,
he vouldn`t think Adrian vas a dull boy.
Lventually, Adrian started vriting some short articles and guides on hov to optimize the com-
puter. Although he had no intention ot creating a computer hardvare site, people started visiting
his site, and he soon developed a reputation among tellov enthusiasts tor his revievs and guides.
One thing led to another and Adrian`s Pojak Pot is nov Malaysia`s top hardvare site' 1he
metamorphosis trom Adrian`s personal homepage to the current hardvare site vas long and
paintul due to Adrian`s commitment to his medical studies.
Hovever, Adrian`s Pojak Pot is nov a sleek hardvare s ite vith its ovn server and a dedicated
team to run it. In addition, it is host to a tlourishing community in its discussion torums.
It you are interested in tinding out more about Adrian`s Pojak Pot and 1eam APP, head over to
http:vvv.rojakpot.comabout_us.aspx
It you vant to visit the APP torums and hang out vith the regulars (vho label themselves
Pojakpotters,, head over to http:torums.rojakpot.com
Whot`s Rojok?
Well, rojak is a distinctly Malaysian tare. It is a dish ot truits, vegetables, crackers, tried soybean
curd, and practically anything else the connoisseur vants, mixed vell vith a spicy, sveet, and
sticky paste made ot pravns, chili, and belacan. A generous amount ot shredded peanuts are then
sprinkled on the dish.
860
Yum, um: Yes, it`s delicious, and it suits ditterent palates because it can be anything and every-
thing you vant it to be. Colloquially, rojak also means mixed up because the dish is really a
mix ot many ditterent ingredients. 1he pot that is used to mix the assorted ingredients is, ot
course, called the rojak pot, hence, the origin ot the vebsite`s name, Adrian`s Pojak Pot.Why
Pead on to tind out'
Why Adrion`s Rojok Pot?
Well, tirst ot all, you have to understand a tiny part ot the Malaysian cultureMalaysians love to
eat. Malaysia is one ot the tev places on Larth vhere you can tind tood stalls and even restau-
rants open 24 hours a day, 7 days a veek. No, no, ve`re not talking about 7-Lleven, ve`re talk-
ing about bona tide mamak and havker stalls. All ot this just to cater to the Malaysian`s desire to
eat at any time ot the day or night.
With such a national tood obsess ion, Adrian believes his vebsite should at least give a nod in
that direction, and vhat better vay to do that than to name it atter one ot Malaysia`s tavorite
dishes
In addition, the name conjures up an image ot a site that publishes a variety ot articles, as varied
and delectable as the ingredients ot rojak. It also points to the diversity ot visitors the site aims
to attract. While Adrian`s vebsite is Malaysian in origin, it does not restrict itselt to Malaysia.
1he Internet is borderless and velcomes diversity'
linally, Adrian teels that Adrian`s Pojak Pot is a unique name tor a unique site.What better
name could there be
8rcakng Jhrough Ihc 8I0S 8arrcr
861
About the BIOS
Optimization Guide
Ot all the articles and guides Adrian has vritten, none has been more highly praised or talked
about than his online PI: ptimi:ation uioe. Adrian started vriting it in uly ot 1999 atter
noticing that tar too many people had misconceptions about optimizing the BIOS.
Instead ot just telling people vhat to do, Adrian decided to vrite dovn everything he knev
about each BIOS option.1hen he vrote his recommendations and the reasons tor them. Adrian
believes this is the bes t vay to teach people about BIOS optimization.
Did he succeed Apparently so'
1he online PI: ptimi:ation uioe (or, as it is attectionately knovn, BOG, is nov the
Internet`s ultimate reterence on BIOS optimization. It is trequently quoted in online arguments
about BIOS settings. In tact, Adrian`s peers nov reter their visitors to his online PI:
ptimi:ation uioe vhenever they ask about BIOS settings.
Although untortunate, the best indicator ot the online PI: ptimi:ation uioe`s popularity is
the numerous times it has been plagiarized. As they say, imitation is the highest torm ot tlattery,
and so, plagiarism has alvays been the bane ot the guide`s existence.
1he online PI: ptimi:ation uioe has the dubious honor ot being the only free online guide
that has been plagiarized countless times by individuals and vebsites trom all over the vorld'
Currently, the online version ot lhe PI: ptimi:ation uioe is in its eighth revision, and it
covers more than 230 ditterent BIOS options. More are being added every month. It you vant
to see the online version ot lhe PI: ptimi:ation uioe, head over to
http:vvv.rojakpot.combog.aspx
Preakin lhrouh the PI: Parrier.lhe PI: ptimi:ation uioe vill not only break the BIOS
barrier, it vill also break the barrier betveen printed media and online media.1his book comes
vith a lPLL subscription to the online BIOS Optimization Guide tor a period ot three
months (valued at more than s10,. 1his gives you the best ot both vorldsa book you can
carry and consult vhenever and vherever you vant, and the latest updates to the guide'
1o register tor your lPLL subscription, log on to http:vvv.phptr.combiosguide.
AhouI Ihc 8I0S 0pImzaIon 0udc
MD Driving Strength 84 236 SDPAM Cycle 121 288
1ime 1ras1rc
Memory Hole 83 236 SDPAM LCC 121 288
At 13M-16M Setting
OS Select lor 94 248 SDPAM Idle 122 289
DPAM ~ 64MB Iimit
OS2 Onboard 94 247 SDPAM Ieadott 122 291
Memory ~ 64M Command
Pank Interleave 111 271 SDPAM Page 123 291
Closing Policy
Pead Around Write 111 271 SDPAM Page 123 292
Hit Iimit
Pead Wait State 111 272 SDPAM PH Iimit 124 293
Petresh Interval 112 272 SDPAM Precharge 124 293
Control
Petresh Mode Select 112 273 SDPAM Precharge Delay 124 294
SDPAM 11 116 278 SDPAM PAS 123 293
Command Precharge 1ime
SDPAM 11 117 279 SDPAM PAS 123 293
Command Control Pulse Width
SDPAM Active to 117 280 SDPAM PAS-to- 126 296
Precharge Delay CAS Delay
SDPAM Bank Interleave 117 281 SDPAM Pov 126 297
Active 1ime
SDPAM Bank-to- 118 282 SDPAM Pov 126 297
Bank Delay Cycle 1ime
SDPAM Burst Ien 119 283 SDPAM 1ras 127 298
1imi ng Value
SDPAM Burst Iength 119 284 SDPAM 1rc 127 298
1imi ng Value
SDPAM CAS 119 283 SDPAM 1rcd 128 299
Iatency 1ime 1iming Value
SDPAM Command 120 283 SDPAM 1rp 128 300
Ieadott 1ime 1imi ng Value
SDPAM Command Pate 120 286 SDPAM 1rrd 129 300
1imi ng Value
SDPAM Cycle Iength 120 287 SDPAM Write 129 301
Pecovery 1ime
BIOS Option Quick Detailed BIOS Option Quick Detailed
Reviev Description Reviev Description
Memory 8ulsysiem (Coniinue)
(Continueo on Insioe Pack Co:er)
Memory 8ulsysiem (Coniinue)
SDPAM Write to Pead 129 301 SuperStability 134 309
Command Delay Mode
Shadoving Address 130 303 Write Data in to 147 326
Panges Pead Delay
Super Bypass Mode 134 308 Write Pecovery 1ime 148 327
Super Bypass Wait State 134 308
Miscellaneous
Anti-Virus Protection 40 178 Parallel Port Mode 93 249
Duplex Select 62 204 Pover On lunction 107 267
llash BIOS Protection 63 208 PS2 Mouse 108 269
lunction Control
lloppy 3 Mode Support 63 209 PxD, 1xD Active 114 276
lull Screen Iogo 68 212 Security Setup 130 302
Hardvare Peset Protect 72 216 Spread Spectrum 133 307
KBC Input Clock Select 80 229 1X, PX Inverting Lnable 137 312
Keyboard Auto- 80 230 1ypematic Pate 137 312
Pepeat Delay
Keyboard Auto- 80 230 1ypematic Pate 138 313
Pepeat Pate Delay
Onboard IP lunction 92 243 1ypematic Pate 141 313
Setting
Onboard Parallel Port 92 243 LSB Controller 141 317
Onboard Serial Port 1 92 246 LSB Keyboard 141 317
Support
Onboard Serial Port 2 93 246 LSB Mouse 141 318
Support
Onboard LSB Controller 93 246 Virus Warning 143 324
Processor
Athlon 4 SSLD 42 174 CPL Drive 48 181
Instruction Strength
Auto 1urn Ott PCI 43 173 CPL last 48 182
Clock Pin String
Clock 1hrottle 47 180 CPL Hyper-1hreading 49 182
Compatible lPL 47 181 CPL I2 Cache 49 184
OPCODL LCC Checking
BIOS Option Quick Detailed BIOS Option Quick Detailed
Reviev Description Reviev Description

Breaking Through The BIOS Barrier - The Definitive BIOS Optimization Guide For PCs

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Breaking Through The BIOS Barrier - The Definitive BIOS Optimization Guide For PCs

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