Voltage Controlled Ring Oscillator with Wide Tuning Range and Fast Voltage Swing * Nicodimus Retdian, Shigetaka

a Takagi Nobuo Fujii Tokyo Institute of Technology Tokyo Institute of Technology 2-12-1 Oookayama, Meguro 2-12-1 Oookayama, Meguro Tokyo, Japan Tokyo, Japan nico, takagi@ec.ss.titech.ac.jp fuj@ec.ss.titech.ac.jp ABSTRACT A new design of a voltage controlled ring oscillator is proposed. The proposed design allows an implementation of a low frequency ring oscillator using relatively small devices and less stages. A voltage controlled ring oscillator with tuning range from 40Hz to

380MHz is achieved using the proposed method. In addition, the proposed circuit enables the output voltage to swing faster than the conventional one. Keywords ring oscillator, voltage controlled oscillator, inverter 1. INTRODUCTION A voltage controlled oscillator (VCO) is one of the important basic building blocks in analog and digital circuits [1],[2],[3]. For example, a VCO is

the main building block in phase locked loop (PLL) and clock generator circuits. There are so many different implementations of VCOs. One of them is the ring oscillator based VCO, which is commonly used in the clock generation. The conventional ring oscillator based VCO uses variable bias currents to control its oscillation frequency. However, when the bias current

is quite small, the voltage swing of the VCO will become slower (longer rise/fall time). That is not desirable in some applications. In addition, increasing bias current will make the voltage headrooms of the current source MOS transistors become narrow. Thus, a saturation * The authors are with the Dept. of Communications and Integrated Systems, Graduate

School of Sciences and Engineerings, Tokyo Institute of Technology. The author is with the Dept. of Physical Electronics, Graduate School of Sciences and Engineerings, Tokyo Institute of Technology. in f-v characteristic occurs at high oscillation frequencies (large bias currents). This paper proposes a new design method of a ring oscillator based VCO. Section 2

will describe the conventional voltage controlled ring oscillator. It will be then followed by the basic idea and implementation of the proposed circuit in section 3. Finally, simulation results and conclusions will be given in sections 4 and 5 respectively. 2. CONVENTIONAL CIRCUIT A conventional voltage controlled ring oscillator circuit is shown in Fig.1 where N is an odd number

and shows the number of inverter stages. Assume that the gate to source parasitic capacitances CGs of the NMOS and PMOS transistors are equal as is shown in Fig.2. Here the frequency of the oscillation can be found as 1 fosc = (1) 2Nt where t is the delay of one inverter stage.

Using Fig.2, the delay of each inverter stage will be given by Z Ictrl Vosc = dt (2) CG Vosc CG t = (3) Ictrl where Vosc is the oscillation amplitude. Substituting (3) into (1) will give Ictrl fosc = . (4) 2NVoscCG

Here the oscillation frequency is determined by the current Ictrl, the number of stages N, the amplitude Vosc and the parasitic capacitance CG. For a given number of stages, the oscillation frequency can be controlled by varying control current or amplitude only since CG is a fixed parameter. Control scheme by varying the current is commonly used. Equation

(4) gives an illustration that the oscillation frequency can be theoretically tuned for a wide range by changing the value of control current. However, it will not work properly for a very small current since it is difficult to keep matching between the values of the upper and lower control currents when they are too small. In addition, the small

bias current will make the voltage swing slow.

VDD Ictrl Ictrl Ictrl Ictrl Ictrl Ictrl VSS N Figure 1: Conventional voltage controlled ring oscillator. VDD Ictrl Ictrl Ictrl Ictrl VSS CG CG Figure 2: Delay approximation. 3. PROPOSED CIRCUIT 3.1 Basic Circuit The proposed circuit scheme is shown in Fig.3. Here a variable resistor RV is added at the input

terminal of each inverter. The inverter itself is made from PMOS and NMOS transistors as is shown in Fig.4. The delay of each stage tp can be calculated from Fig.5. Since the MOS transistors in each inverter can be assumed as switches, it can be replaced by a resistance 1/GM as is shown in Fig.5. If the transconductances GM s

and parasitic capacitances CGs of NMOS and PMOS transistors are equal, the delay of each inverter stage tp then will be approximately CG(1 + GM RV ) tp = . (5) GM For a very large RV such that GM RV . 1, the delay will be determined by the time constant of RV

CG regardless of the value of GM . Assuming RV = 0 will give CG tp = , (6) GM which is a delay for a simple inverter stage. Finally, the

N Figure 3: Proposed voltage controlled ring oscillator. oscillation frequency can be found as

GM fosc = . (7) 2NCG(1 + GM RV ) Equation (7) shows that the oscillation frequency depends on the values of transconductance GM , resistance RV and capacitance CG. However, GM and CG are device parameters and assumed to be constant. As a conclusion, the oscillation frequency can be controlled by changing the value of

RV . Theoretically, choosing a big value for RV will enable the implementation of a ring oscillator with a low oscillation frequency using small size devices and less stages. IN OUT IN OUT Figure 4: Inverter circuit. CG 1/GM RV RV VOUT CG VDD Figure 5: Delay approximation.

3.2 Circuit Implementation The proposed method is implemented in the circuit shown in Fig.6. Here the variable resistance is implemented using PMOS and NMOS transistors. Both types are required to enable the full swing between power supplies. The overall circuit is shown in Fig.7. Here the resistances of the MOS transistors are controlled by their gate voltage. Choosing a proper MOS

transistor sizes will guarantee the matching between transistors. 4. SIMULATION RESULTS The simulation is performed using level 28, 0.6m CMOS process parameters. Circuits used in the simulation are three-stage voltage controlled ring oscillators shown in Figs.8 and 9. The W/L ratios of the MOS transistors are shown in Table 1. The power supply VDD for both circuits is 3V.

OUTIN OUTIN VDD VP Ictrl VN Ictrl Figure 6: Circuit implementation of the inverter circuit. M1 M4 M1 M4 M1 M4 M2 M3 M2 M3 M2 M3 M1 M4 OUT VP VN Figure 7: Circuit implementation of the proposed voltage controlled ring oscillator. 4.1 Transient Characteristics Both transient simulation results of the conventional

and the proposed circuits are shown in Fig.10. The oscillation frequency for both of them are set to 370MHz. The control current Ictrl of the conventional circuit is 134A while the control voltage Vctrl of the proposed circuit is 3V. Next, Fig.11 shows the transient simulation result of the proposed circuit when the control voltage is 1V. The

oscillation frequency is 6MHz. The control current of the conventional circuit is 1.415A for the same oscillation frequency. Here the proposed circuit has a faster voltage swing than the conventional one for both high and low oscillation frequency. In case of fosc = 6MHz, the rise/fall time (10% ~ 90% of voltage swing) for the conventional and the proposed circuits

are 32.1ns and 4.3ns respectively. Here the rise/fall time of the proposed circuit is roughly 1/8 of the conventional circuit for oscillation frequency of 6MHz. Figure 12 shows the simulation result of the current dissipation of the proposed circuit for fosc = 6MHz. Here the proposed circuit dissipates a large current in the transition of the output voltage

of each inverter. As a result, the proposed circuit has a faster voltage swing than the conventional one. 4.2 F-V Characteristic Simulation result of the f-v characteristic of the proposed voltage controlled ring oscillator is shown in Fig.13. The oscillation frequency for control voltage of 0.4V and 3V are 40Hz and 380MHz respectively. Here a frequency tuning range from tens

of hertz to hundreds of megahertz is obtained. In addition implementation of low frequency oscillator using small size devices is also possible. Figure 8: Conventional three stages voltage controlled ring oscillator. Table 1: NMOS transistors W/L ratios W/L[m/m] W/L[m/m] M1 3/0.6 Ma 9/0.6 M2 9/0.6 Mb 4.5/1.2 M3 4.5/1.2 Msp 3/0.6 M4 1.5/1.2 Msn

1.5/1.2 5. CONCLUSIONS A new design of ring oscillator based VCO is proposed. The proposed design allows implementation of a voltage controlled ring oscillator with wide tuning range and fast voltage swing. Simulation results show that the rise/fall time of the proposed circuit is 1/8 of the conventional one for oscillation frequency of 6MHz. The proposed circuit also achieves

a tuning range from 40Hz to 380MHz for control voltage between 0.4V to 3V. Furthermore, the maximum oscillation frequency of the proposed circuit depends on the device sizes. Furthermore, the proposed circuit is applicable for a lower supply voltage because of its simple structure. Figure 13 shows that the proposed circuit has a linear in dB charactertistic for

control voltages less than 1V. This is because the MOST resistors are in the weak inversion region. For control voltages bigger then 1V, the MOST resistors are in the linear region and the oscillation frequency is increased by 20MHz for 0.1V increment of control voltage. The experimental chip is still under development. 6. REFERENCES [1] A.Hajimiri and T.H.Lee. The

Design of Low Noise Oscillators. Kluwer Academic Publishers, 1999. [2] A.Rezayee and K.Martin. A three-stage coupled ring oscillator with quadrature outputs. In Proceedings of Int. Symp. on Circuits and Systems. IEEE, 2001. [3] D.A.Johns and K.Martin. Analog Integrated CircuitDesign. John Wiley and Sons, New York, 1997.

VDD Vctrl OUT Msp Msn Ma Mb Msp Msp Msn Msn Ma Ma Mb Mb Vctrl Figure 9: Proposed three stages voltage controlled ring oscillator. 1 IVDD VOUT 0 3 Voltages [V] 100 2 Currents [uA] conventional proposed 344n 345n 346n 347n 348n 349n 350n 351n 352n 353n 354n 3 0 Time [s] 2 Figure 12: Current dissipation(fosc=6MHz).

1 Voltages [V] 0 Time [s] Figure 10: Transient characteristic(fosc =370MHz). 108 0.51 23 Frequency [Hz] 106 104 conventional proposed 3 Voltages [V] 2 102 1 Vctrl [V] Figure 13: F-V characteristic simulation results of 0 the proposed circuit. 41.3u 41.4u 41.5u 41.6u 41.7u Time [s]

Figure 11: Transient characteristic(fosc =6MHz).