Design of Output / Filter for Motor Drives

Anirudh Acharya.B
Dept. of Electrical Engineering Indian Institute of Science Bengaluru, India 560012 Email: anirudh ab@ee.iisc.ernet.in

Vinod John
Dept. of Electrical Engineering Indian Institute of Science Bengaluru, India 560012 Email: vjohn@ee.iisc.ernet.in

AbstractModern PWM inverter output voltage has high /, which causes problems such as voltage doubling that can lead to insulation failure, ground currents that results in electromagnetic interference concerns. The IGBT switching device used in such inverter are becoming faster, exacerbating these problems. This paper proposes a new procedure for designing the LC clamp lter. The lter increases the rise time of the output voltage of inverter, resulting in smaller /. In addition suitable selection of resonance frequency gives LCL lter conguration with improved attenuation. By adding this lter at output terminal of inverter which uses long cable, voltage doubling effect is reduced at the motor terminal. The design procedure is carried out in terms of the power converter based per unit scheme. This generalizes the design procedure to a wide range of power level and to study optimum designs. The effectiveness of the design is veried by computer simulation and experimental measurements. Index Terms/-lter, common mode voltage, IGBT motor drives

Output lters, such as /-lter, sinusoidal lter, common mode choke Reduction of common mode voltage using PWM techniques Resonant switching inverter

I. I NTRODUCTION Present day induction motor is commonly operated using two level inverters. The inverter output voltage risetime is order of few nano seconds. Generally, the switching device used is IGBT owing to their very small turn ON/turn OFF time and power handling capability. The advantage of smaller switching time is lower switching energy loss, but introduces very high /. The value of / can be as high as 10 to 20kV/s [1]. The issues in the inverter fed motor drives due to high dv/dt at inverter output are: Voltage reections in the cable, resulting in doubling of motor terminal voltage. Increased ground currents and bearing current. Electromagnetic emission from the drive. NEMA MG 1 part 31 [2] standard species the limit for peak voltage of the output that is acceptable for rated line to line voltage and species a limit for /. To suppress / and hence the common mode current many techniques have been proposed, both at inverter end and motor end. Some of the mitigation techniques proposed at motor end are: Insulated bearing and electrostatic shields between stator and rotor. Increasing the grade of the insulation. Termination to match the impedance of the motor and the cables. Similarly the methods proposed at inverter end are:

Algorithm for control of soft-switching resonant converters add constraints to PWM modulation method and needs additional switching devices therefore the cost involved is high. On the other hand, LC lter is the most commonly used low pass lter for reducing / at motor terminal. The induction motor are operated using sinusoidal voltage, to obtain such output through the lter the resonance frequency should be less than the switching frequency.The resonance frequency is selected such that it is at a factor 10 from fundamental and switching frequency. However, there is the possibility of exciting the resonance due to variable speed operation. Present day induction motors are fed through inverters whose output is non-sinusoidal on a line to ground basis. The / issue of the motor drive such as ground currents and EMI need to be on a line to ground basis. In addition the size of the lter can become large at low switching frequency in high power drives. If the lter required is only to address the / of the inverter output then the resonant frequency can be above the switching frequency. With such as lter the size of the circuit components reduces. Damping of such lter is quite difcult, instead the output is clamped to the desired DC bus voltage. Clamping lters are proposed in literature [3], [4]. The lter topology presented in [3] does not address the common mode component, this shortcoming was overcome in subsequent design proposed in [4] by connecting the neutral of the lter to dc bus mid-point (O). The proposed lter is as shown in Fig. 1, apart from addressing both common mode and differential mode components, the resonant frequency is selected so that the induction motor at high frequency behaves as inductive load and hence gives the higher order lter LCL effect. For the frequencies under consideration the motor back-emf is effectively a short circuit. In this paper design criteria and proposed procedure for design is discussed. The effectiveness of the above design is veried using PSPICE simulation and validated experimentally.

Fig. 1.

Proposed resonant LC clamp lter connected to an active front-end drive.

II. R EFLECTIONS IN C ABLE The phenomenon of travelling wave is predominant in long cable due to the fast rise time of switching devices like IGBT. The parasitic of the cable are distributed resistance, inductance and capacitance. The current through the cable charges the parasitic capacitor as it propagates through the cable. If the impedance at the termination is large, then the excess energy gets stored in the last capacitor due to which the voltage rises and goes as high as two times the applied voltage [5]. Let be the characteristic impedance of the cable, be the load impedance, and be the source impedance. The time taken by the applied voltage to reach 90% of desired voltage magnitude is rise time and the time taken by the voltage to reach the other end of the cable is propagation time . For a bare conductor, the velocity of propagation is , where = 3108 (m/s). If the cable is coated with insulating medium such as PVC etc with permittivity , the propagation velocity can be expressed as 1. = (1) Once the applied voltage reaches the motor terminal after time , it sees very large impedance, and hence the entire voltage will get reected back. The reection coefcient at load side is given by, = (2) + As load impedance is very high, 1. Therefore the voltage at the motor terminal would become, = (1 + ) = 2 (3)

reection occurs the voltage at the motor terminal is less than the applied voltage hence the voltage at the motor terminal would be less that 2 . Based on the length of the cable and the type of insulation used for cable the propagation time can be approximately calculated. Hence, this leads to the maximum length of the cable that can be used along with the inverter for a given / without having the voltage doubling effect. This length of the cable is termed as critical length, . Keeping > avoids voltage doubling effect. = (4)

Taking this in to consideration the lters have been designed in literature, which proved to be effective for known length of the cable [6]. Present day IGBT has rise times of order 109 (s) and if PVC insulated cable is used the propagation velocity will be roughly 1.6108 (m/s) and hence the propagation time for a cable length of 10m would be of the order 109 (s). Hence even for a cable length of 10m voltage doubling effect can be seen. As the rise time of IGBT gets smaller the problems related to voltage doubling and ground current gets worse. III. BASIC F ILTER T OPOLOGY The lter topology can either be passive or active ltering. Active lter requires additional switches and complex control algorithms to control them, therefore are expensive. Passive lters are effective and robust, but designing it is a challenge also it is bulkier based on type of lter adopted to address the problem. The traditional lter design focuses on producing a voltage which closely reassembles the sinusoidal voltage from the PWM pulses applied at the inverter output. Since the / is reduced signicantly by the lter, circulating ground current and bearing current reduces. However, to meet such design specication the lter dimension increases and could cause sluggish response of speed of motor as a result of phase delay of ltered output. To reduce circulating current and bearing current various lter topology are presented in literature [7]. The principle of the output lter is briey reviewed.

The reected wave will reach the inverter terminal after one propagation time . The reection co-efcient at the inverter terminal is equal to 1. The voltage will now reects back to motor terminal and gets subtracted with the voltage that would be building at motor terminal end. Now, if < after rst reection the voltage at the motor terminal would be two times the applied voltage. But, if > when the rst

Fig. 2.

Basic lter topologies (a) / reactor, (b) sinewave lter.

parasitic capacitors becomes critical for estimating the ground currents. Fig. 3(a) shows the differential mode impedance plot and Fig. 3(b) shows the common mode impedance plot obtained using a network analyzer. Impedance plot for various differential congurations were obtained and the parasitic capacitor value was calculated. From the plot it can be seen that the motor behaves as inductive load up to 48kHz in differential mode conguration, beyond which it behaves as capacitive load. The motor behaves as capacitive load between the frequency 100Hz-50kHz as seen from common mode plot.

Fig. 2(a) shows a simple /reactor, which is choke connected between the inverter output terminals to motor input terminals. The basic function of which is to increase the rise time which thereby reduces the /. Fig. 2(b) shows the conventional LC sine lter at inverter terminal with damping arrangement. The resonance frequency ( ) of such lter is less than switching frequency ( ) but greater than fundamental frequency ( ) at maximum motor speed. If the neutral point is left oating, it would address differential mode voltage alone. In addition a damping technique has to be used to decrease the Q-factor at the resonance of the LC circuit.The value of the resistor controls the amount of damping. The introduction of damping resistor increases the losses in the system. The only way to achieve loss less damping is by active damping using inverter control. If < and advanced modulation methods are used for switching PWM-VSI drives then large surge currents will ow, if the connections are made to positive, negative or mid-point of the dc bus [8]. Hence for proceeding analysis we are looking only at lters where > . The neutral point of lter when connected to either positive, negative or to both of them by properly splitting the lter capacitors, or mid-point of dc bus, will now address both the common mode and differential mode components of the output voltage. Fig. 1 shows the LC clamp lter connected at the output terminal of the inverter. Compared to the traditional LC lter the dimension of clamp lter is small. In addition the lter output is clamped to DC bus, therefore does not need a damping resistor as in RLC lter. The losses in the clamping circuit is small compared to the losses in damping resistors in Fig. 2(b). IV. H IGH FREQUENCY BEHAVIOUR OF MOTOR At high frequency the slip of induction motor 1. Therefore the induction machine can be modelled as leakage inductance at high frequencies. Also, due to repetitive voltage at very high frequency the turn to turn capacitance and conductor to ground capacitance plays signicant role. Due to high / there is a possibility for current to ow between turn to turn, thereby damaging the insulation that separates them. In random wound machine, if the last and rst turns are adjacent to each other in the worst case cenario the insulation between them may not withstand the full coil voltage, when doubling at the motor terminal occurs. Hence, modelling these

Fig. 3. High frequency impedance plot of the motor (a) in differential conguration and, (b) in common mode conguration.

The differential and common mode per phase equivalent circuit at high frequency can be modelled as shown in Fig. 4. For designing the lter the rst requirement is to meet the / criteria. The design procedure taking / as input for design is discussed in [4]. If the lter resonance frequency is placed below the frequency where the motor differential mode behaviour changes from inductive to capacitive load, then motor can still be considered to be inductive and overall lter can then be studied as an equivalent LCL lter conguration. V. T HEORY AND DESIGN OF RESONANT CLAMP FILTER A. Circuit Operation Consider the R-phase of the inverter shown in Fig. 1, at any instant either the top ( ) or bottom ( ) switch is conducting. When the top switch conducts, the voltage across the capacitor would rise as indicated by (9). When the voltage rises above the sum of pole voltage ( ) and voltage

Where, = 1 =

Fig. 4. Shows the per-phase equivalent circuit of induction motor including the parasitics (a) differential mode conguration, (b) common mode conguration.

across the snubber (connected to positive dc bus) , the clamping diode 1 would start conducting. Hence the voltage across the capacitor will be held constant close to . The 2 snubber is designed to keep the total voltage seen close to dc bus voltage ( is held to 10% of ). The small excess snubber voltage causes the inductor current to decrease at faster rate and eventually the current in the clamp diode go to zero, at this instant 1 stops conducting.When the bottom switch is conducting, the voltage would start decreasing. When lter capacitor voltage is less than the sum of and the diode 2)would conduct, the voltage is held constant ( close to 2 . The same process occurs in the other two phases. B. Design of LC lter As slip = 1, the per-phase model of lter along with induction motor is as shown in Fig. 5. Let the current through

Expressing (9), (10) in terms of per-unit, ( ) = 2() () () 2 2() ( ) () = () () ( )

(11)
()

(12) (13) (14)

= =

1 2 () ()

Fig. 5.

Equivalent circuit at high frequency of inverter and lter.

the lter inductor ( ) be and the current through the motor leakage inductance be then the resonant current through the capacitor is, = (5) Voltage across the lter capacitor be . Input voltage be . Applying KVL and KCL, (6) + = (7) (8) = Solving the (6),(7),(8) equations for and assuming zero initial conditions, { } = (1 cos ( )) (9) + } { sin ( ) (10) = =

The base quantities are selected based on inverter ratings as shown in Table 1. Filter inductance is kept far less compared to motor leakage inductance, therefore . The design procedure for the clamped LC lter is as follows: 1) Select the resonant frequency as in (11), such that is within specied limits this makes sure that rise time is higher than propagation time. Induction motor at this resonant frequency should be inductive. Resonant current should be within the required limit, so that stress on IGBT is minimal. 2) Limit on resonant current is assumed 0.1 0.5., and is calculated as in (12). 3) is obtained from (13). 4) Design is iterated until the constrains are met. Lower the lter inductance higher the magnitude of resonant current and hence the peak thermal stress on IGBT switches and inductor increases. The value of resonant current has to be such that the thermal stress does not increase signicantly. To achieve this snubber circuit is introduced between clamping lter and DC busbar. The snubber circuit helps to reduce the rms value of the current and hence higher value of resonant currents can be selected based on rating of IGBT. Selecting higher value of resonant current would increase the losses in the snubber. C. Common mode voltage and current The common mode voltage and current at the motor end is give by (15), (16) respectively = = + + 3 ( + + ) (15) (16)

If the front-end converter used is diode bridge rectier then the common mode voltage can be expressed in terms of pole voltage as, + + = (17) 3

Fig. 7.

Current through lter inductor.

Fig. 6. Common mode voltage using sine triangle PWM with = 800 , = 1.

Fig. 6 shows the common mode voltage that appears at the motor neutral when sine triangle PWM is used. The magnitude of varies in steps of . On a common mode basis 3 the parasitic capacitance from neutral of induction motor to ground dominates as seen in Fig. 3(b), if the rise time of inverter output voltage is very small, then the current ows into ground via as displacement current due to high / of . D. Design of snubber circuit 1) Need for snubber circuit: When the pole voltage is above the top diodes conducts clamping the voltage 2 across lter capacitor, this maintains the pole voltage at desired value. The current through inductor will now follow through clamping diode. The stored energy will be dissipated in ESR along the path of circulation, if snubber circuit is not used. Therefore the inductor current would eventually fall to zero, let this duration be 1 . If 1 > , the load current will ow through the top clamp diodes during negative half cycle and bottom clamp diodes during positive half cycle.The current rating of the clamp diodes have to be increased, therefore higher rating diodes have to be selected. Also, the losses in diode will increase.To avoid this the duration 1 is decreased by introducing the snubber circuit as shown in Fig. 1. The snubber steepens the rate of fall of lter inductor current ( ) when the diode(s) conduct. The resonant current must be quenched as fast as possible to decrease the stress on the clamping diodes and IGBT. Fig.7 shows the inductor current waveshape with = 0. { + = (18) (0 ) + 1 + 2) Design of snubber: If very low value of 1 is desired then it would result in a very large value of snubber capacitor voltage ( ), which would not(be practical. Hence, a suitable ) value of ( ) is selected. As, = , which used for design of lter. The value of 1 as obtained as, { } ( ) 1 (19) 1 = 2

The total charge that is discharged into the snubber per switching period can be expressed as, } 3{ = (20) ( ) 1 2 Total average current is expressed as, = Hence the snubber resistance can obtained to be, = (21)

(22)

When the diode conducts for 1 duration load current has a path to ow through clamp diode. Which may result in increase . To handle this situation, worst case energy stored in capacitor (i.e. when the three top or bottom diodes carry load current) is calculated in terms of .. as, ) 1 ( 2 = (23) 8 Limiting the maximum variation of voltage in snubber capacitor to . The value of capacitor can be obtained to be, 12 ( ) = (24) 2 + The current would ow through the diodes for a very short duration, and also the average and rms values are less. Therefore diode with average current rating greater that and peak repetitive forward current rating above load current can be selected. This results in selection of very small fast recovery diodes. VI. E XPERIMENTAL RESULTS The resonant LC diode clamp lter was built and tested using a 10kVA inverter with 100m cable. The load is disconnected and line to line voltage and line current near inverter without lter is measured as shown in Fig. 8. The dc bus voltage is maintained at 600V. It is seen that the terminal voltage is twice the applied voltage and line current has a peak of approximately 7A. Also due to high / the converter control shuts down due to false trip signals. The resonant ( ) current , diode voltage (1 ), pole voltage ( ), ) ( lter capacitor voltage is as shown in Fig. 9. The diode turns OFF when = 0. Fig. 10 shows pole voltage, lter capacitor voltage, line to ground voltage at motor terminal and resonant current measured with the proposed lter connected. It is seen that the / is reduced and hence the voltage doubling is eliminated. Also, the rise time is as desired.

Fig. 8. Voltage doubling at motor terminals (Voltage: 500V/div, Current: 5A/div), Time: 5s.

Fig. 10. Elimination of voltage doubling effect at motor terminals(Current: 1A/div, Voltage: 500V/div), Time: 10s.

per unit scheme. This generalizes the design procedure to a wide range of power level and to study optimum designs. Experimental implementation of the lter using diode bridge rectier as front-end is carried out. The active front-end operation with line side lter is currently under progress. R EFERENCES
[1] J. Steinke, C. Stulz, and P. Pohjalainen, Use of a LC lter to achieve a motor friendly performance of the PWM voltage source inverter, in Proc. 1997 Int. Electric Mach. Drives Conf., 2001. [2] NEMA MG 1, NEMA Motors and Generators Standards, Available at http://www.nema.org/stds/mg1.cfm, 2007. [3] S.J. Kim and S.K. Sul, A novel lter design for suppression of high voltage gradient in voltage-fed PWM inverter, in Proc. IEEE Appl. Power Electron. Conf., 1997, pp. 122-127. [4] Thomas G. Habetler, Rajendra Naik and Thomas A. Nondahl, Design and Implementation of an Inverter Output LC Filter Used for DV/DT Reduction, in IEEE Transactions on Power Electronics, Vol. 17, No. 3, May 2002. [5] E.Person, Transient Effects in application of PWM Inverters to Induction Motors, IEEE Trans on Industry Applications, vol 28, no 5 pp 1095-1 101, 1992. [6] A. von Jouanne, D. Rendusara, P. Enjeti, and W. Gray, Filtering techniques to minimize the effect of long motor leads on PWM inverterfed AC motor drives, in Proc. IEEE/IAS Ann. Meeting Conf., 1995, pp.37-44. [7] Choochuan.C, A survey of output lter topologies to minimize the impact of PWM inverter waveforms on three-phase AC induction motors, in IPEC 2005, pp544. [8] E.U n and A.M.Hava, Performance Analysis of Reduced Common-Mode Voltage PWM Methods and Comparison With Standard PWM Methods for Three-Phase Voltage-Source Inverters, in IEEE Transactions on Power Electronics, Vol.27, No.1, January 2009.

Fig. 9. Shows resonant current and diode clamping(ch1:5A/div , ch2: 200V/div, ch3: 250V/div, ch4: 500V/div), Time: 25s. TABLE I D EISGINED FILTER VALUES AND SIMULATION PARAMETERS Sl.No. 1 2 3 4 5 6 7 1 2 3 4 5 6 Filter parameter Resonant frequency Resonant current Filter inductance Filter Capacitance Snubber capacitance Snubber Resistor Switching frequency Base Value ( = ) Power Voltage Frequency Impedance Inductance Capacitance per unit 800 0.5 0.0083 0.0002 0.54 2.31 40 10KVA 240V 50Hz 17.28 55mH 184.3F actual 40kHz 7A 0.5mH 33nF 100F 40 2kHz

VII. C ONCLUSION The effect of / as shown in this paper can be effectively mitigated using clamp LC lter. A new approach for designing the LC lter is proposed, its effectiveness is veried experimentally. As resonance frequency is greater than switching frequency, lter is compact and can be placed within the inverter package easily. Also by connecting the neutral of the lter to the DC bus mid-point both common mode and differential mode components are addressed. The design procedure is carried out in terms of the power converter based