CONTENT

Introduction Block diagram Block diagram description Circuit diagram Circuit diagram description Pic micro controller Power supply Mems Gsm max-232 programs Future enhancement advandage Disadvandage Conclution

Block diagram discription

Vehicle theft and accident detecter circut has various compontes.

microcontroller
The pic micro controller is the heart of this circuit.Pic microcontroller have many type of ic. we are choosing 16F877A.It is 8 bit CMOS microcontroller with flash program memary.It is RISC processor with high perfance,fully static design. It has five ports. the ports are port A,port B,port C, PORT D, port E,with 33 I/O lines. the controller has 8k x 14 word s of flash program memory,368 x 8 bytes of data memoy and 256 x 8 bytes EEPROM data memory.It is program code protection the user code will be store in the flash program memory .The 5-volt supply is given to the

VDD and VSS pin of the microcontroller.4-MHZ crystal osillator is used in the micro controller.

POWE SUPPLY
The input to the power supply is 12v and the regulator Ic 7805 is used to genrate 5 volt to the circuit all ports

DISPLAY UNIT
In the part of output is the LCD display. the LCD display is connected to the D port. It is display the status of MEMS range.

MEMS
MicroElectroMechanicalSystem are miniaturized structures.

GSM:
GSM, or Global System for Mobile Communications (GSM) modems are specialized types of modems that operate over subscription based wireless networks, similar to a mobile phone. A GSM modem accepts a Subscriber Identity Module (SIM) card, and basically acts like a mobile phone for a computer. Such a modem can even be a dedicated mobile phone that the computer uses for GSM network capabilities.GSM Communications, is popular in many parts of the world, and is a chief competitor to the CDMA protocol in the United States.GSM operates on frequencies in the range of 1.9 GHz and 850 MHz. In our project gsm is user for sending and reciving purpose.

CIRCUIT DIAGRAM DISCRIPTIOM

POWE SUPPLY
the power supply unit in which is the power to 12 volt DC voltage appled and the pic micro controller need only about 5-volt so here IC 7805 is used to convert 12 volt into 5 volt. It main components are rectifier filter reguator

RECTIFIER
A rectifier such as the simconductor diode ,which is capable of

converting a sinsoidal input wave form into a unidirectional wave form ,with a non zero average compontes is called a rectifier.THe rectifier is two types namely half wave rectifier full wave rectifier in this project full wave rectifier is used.It is a rectifier,which conducts for both the cycles of input signal. full wave rectifier is two types namely. center trapped rectifier bridge rectifier As center tapped rectifier is too bulky and center tapped secondary coil is very difficult.bridge rectifier is usedin this poject.

BRIDGE RECTIFIER
In this bridge rectifier ther are four diodes are arranged inthe form of bridge. diode 1 and 3conduct and pass current from the passtive to negative of load. The conduction path will depend upon the direction of the diode,during previous half cycle.the principle featuer of the bridge circuit are the current drawn in both the primary and secondary of the supply transformer are sinusoidal the bridge circuit is then sutable for high voltage application.

FILTER
A circuit is a device,which remove the ac component of the rectifier output but allows the component to reach the load. The commonly used filter circuit is the capacitor placed across the rectifier output parallelwith the load.the pulsating dirct voltage of the rectifier output is applied across the capacitor i.e.across the terminal The pulsating output of the rectifier contain ac and dc components. The low reaction of the capacitor c bypasses the component but prevent the dc component to flow through it. therfore,only dc component reaches the load.In this way, the filter circuit i.e. capacitor c has filter the ac component from the rectifier output,allowing the dc component to reach the load.

VOLTAGE REGULATOR
Avoltage regulator is an electronic circuit that provides a stable dc voltage indepent of the load current temperatuer and ac line oltage regulator can be designed using op-amps It is quicker and easier to use ic voltage regulator.Further moer IC voltage regulation are versatile and relatively inexpensive and are with featuer such as programable output limiting,thermal shutdown and fluctuation operation for high voltage application.Here fixed output

regulator is adopted. rectifier output oltage regultions are commenly used for on-cared regulation and laborites type power supplies. Almost all power supplies use some type of voltage regulator IC.Because voltage regulation are simple to use,reliable,low in cost and above all avilable in variety of voltage and current rating. A vast number of voltage regulation are available.data sheets and appication notes are provided by the manufacturer contain information on the design and uses of the devices In this project,fixed voltage regulation 7805 is used. The 78** series contain of three terminal positive voltage regulation with seven voltage option.IC's are designed as fixed.

PIC MICROCONTROLLER
The team PIC (or)periphreal inter face controller has been conied by microchip technology to identify its single -chip technolog microcontroller. These device have been phenomenally successfully in the market place more recently,8-bit micro controllers have come further,more these micor controller are avilable with range of capabilities,packed in both dual-in line package and surface mount package. The largest part are packed in either 40 pin Dip packed (or) a44-pin surface mount package. In this porject"vehicle thefted and accident detection"PIC 16F877A microcontroller have been used.

KEY FEATURE:
operating frequency RESET(and delays) FLASH program memory EEPROM data memory Data Memory(Bytes) Interrputs Timers DC-20MHZ POR,BOR 8K 368Bytes 256Bytes 14 3

Input Output ports Capture/compare/pwm module Serial communication Parallel communication 10-bit Analog-to-digital module

ports A,B,C,D,E 2 MSSP,USART PSP 35 Instruction set

SPECIAL FEATURES
Selectable oscillator Reset Power On Reset(POR) Power Up Timer(PWRT) Oscillator Start-Up Timer(OST) Brown-On Reset(BOR) Interrupts Watch Dog Timer(WDT) SLEEP Code Protection ID location In-Circuit Serial Programming LOw Voltage In-Circuit Serial programing In-Circuit Debugger PIC 16F877A device have a watchdog timer, which can be shut-off only through configuration bits. it runs off its own RC oscillator for added reliability.Two timers offer necessary delays on power-up.One is the oscillator Start-Up Timer(OST),intended to keep the chip in RESET until the crystal oscillator is Stable.The other is the Power-Up Timer, which provides a fixed dely of 72 mintes on Power-Up only.It is designed to keep the part in RESET while the power supply stabilizes,with these two timers On-chip most applications need external RESET circuitry. SLEEP mode is designed to offer a very low current powerdown mode.The user can Wake up or from sleep through external Reset, watchdog timer wake up or through an interrupt .Several osccillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP

crystal option save the power.A set of configuration bit is used to select varion option addition a information on special features is available in the PIC microcontroller Mid-range Refence manual(DS33023)is 3FFh.

PIN DIAGRAM

RANDOM ACCESS MEMORY

RAM(Randam-access memory) is where program store information for temporary use. unlink ROM,the CPU can write to RAmM as well as read it. Any stored in RAM is lost when power is removed from the chip. Thons,with a few bytes available to user.

MEMORY ORGANIZATION
There are three memory blocks in each of the PIC16F87XA devices. The program memory and data memory have separate buses Program Memory Organization The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x 14 bit program memory space. The PIC16F876A/877A devices have 8K words x 14 bits of Flash program memory, while PIC16F873A/874A devices have 4K words x 14 bits. Accessing a location above the physically implemented address will cause a wraparound. The

Reset vector is at 0000h and the interrupt vector is at 0004h.

Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (Status<6>) and RP0 (Status<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access.

GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indirectly, through the File Select Register (FSR).

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM.The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section.

Status Register
The Status register contains the arithmetic status of the

ALU, the Reset status and the bank select bits for data memory. The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the Status register as destination may be different than intended.

I/O PORTS:
I/O(Input/Output)ports enable the PIC to read and write to external memory and other components. The PIC has four 8-bit I/O ports(port0-3).As the name suggest,the ports can act as inputs (to be read) or output (to be written). Many of the port bits have optional,alternate function relating to accessing external interrupts,and handling serial communication. BASIC-52 assign alternate. function of the remaning ports bits.Some of these functions are required by BASIC-52 while other are optional.If you don't use an alternate function, you can use the bit for any control, monitoring,or other purpose in application.

PORTA and the TRISA Register

PORTA is a 6-bit wide, bidirectional port. The correspondingdata direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations.Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the portdata latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain output.All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and the analog VREF input for both the A/D converters and the

comparators. The operation of each pin is selected by clearing/setting the appropriate control bits in the ADCON1 and/or CMCON registers. The TRISA register controls the direction of the port pins even when they are being used as analog inputs.The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

PORTB and the TRISB Register

PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting aTRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Three pins of PORTB are multiplexed with the In-Circuit Debugger and Low-Voltage Programming function: RB3/PGM, RB6/PGC and RB7/PGD. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull- up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Poweron Reset. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF.Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wakeup on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This interrupt-on-mismatch feature, together with software configurable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the application note, AN552, Implementing Wake-up on Key Stroke (DS00552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>).

PORTC and the TRISC Register

PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions. PORTC pins have Schmitt Trigger input buffers. When the I2C module is enabled, the PORTC<4:3> pins can be configured with normal I2C levels, or with SMBus levels, by using the CKE bit (SSPSTAT<6>). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin.

Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as the destination, should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.

PORTD and TRISD Registers

PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.

PORTE and TRISE Register

PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make certain that the TRISE <2:0> bits are set and that the pins are configured as digital inputs. Also, ensure that ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Register TRISE register is controls the Parallel Slave Port operation. PORTE pins are multiplexed with analog inputs. When selected for analog input, these pins will read as 0s. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs.

Parallel Slave Port

The Parallel Slave Port (PSP) is not implemented on the PIC16F873A or PIC16F876A. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin, RE0/RD/AN5, and WR control input pin, RE1/WR/AN6.

The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD/AN5 to be the RD input, RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PCFG3:PCFG0 (ADCON1<3:0>), must be set to configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches: one for data output and one for data input. The user writes 8-bit data to the PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored since the external device is controlling the direction of data flow. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), the Input Buffer Full (IBF) status flag bit (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete. The interrupt flag bit, PSPIF (PIR1<7>), is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE<5>) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immediately indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).

TIMERS AND COUNTERS: TIMER0 MODULE

The Timer0 module timer/counter has the following features:

 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CSIn Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge.The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer.

Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit TMR0IF (INTCON<2>). The interrupt can be masked by clearing bit TMR0IE (INTCON <5>). Bit TMR0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep since the timer is shut-off during Sleep.

TIMER1 MODULE:
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). Timer1 can operate in one of two modes: As a Timer As a Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit, TMR1ON (T1CON <0>).

Timer1 also has an internal Reset input. This Reset can be generated by either of the two CCP modules.When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and these pins read as 0.

TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable and is cleared on any device Reset. The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF (PIR1 <1>)). Timer2 can be shut-off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption.

SERIAL PORT
The PIC serial port automatically takes care of many of the details of serial communication .On the transmit side, the seria port translates bytes to be send into serial data, including adding start and stop bits and writing the data in a timed sequnce to serial OUT. On the receiver side, the serial port accepts serial IN and sets a flag to indicate that a byte has been BASIC - 52 uses the serial port for communication with a host computer.

exteral interrupts
INT0 AND INT1 are external interrupts inputs, which detect logic levels or transition that interrupt the CPU and cause it to branch to a predefined program location. BASIC -52 uses INTO for its optional direct memary access (DMA) function.

ADDITINAL CONTROL INTRUPUTS

Two additional control input need to be mentioned. logic high on RESET resets the chip and casuses it is begin executing the program that begin at 0in code memory. In the PIC BASIC chip, this program is the BASIC -52 interpreter. EA (external access memory) determines wheter the chip will access internal or external code memory in the area from 0 to 1fffh.In BASIC -52 systems, ea is tied high so that the chip runs the BASIC interperter in internal ROM on boot-up.

POWER SUPPLY CONNCETION

In addition, finally, the chip has two pin for connedting to a+5 volt power supply (Vcc) and ground (Vss) .that finshes our tour of the PIC BASIC chip. We are now ready to put together a working system. To +5v or use a jumper as shon in the schematic to allow you bypass BASIC - 52 and boot to an assembly language program in external memory.

CRYSTAL
XTAL1is an 11.0592 MHZ crystal that connects to pins 18 and 19 of U2. This crystal frequncy has two advantages. It gives accurate baud rate for serial communication; due to the way that PIC timer divides the system clock generate the baud rates. In addition, BASIC - 52 assumes this frequncy when it times the real-time clock, EPROM programming pulses,and serial printer port.

COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins RA0 through RA3, while the outputs are multiplexed to pins RA4 and RA5. The on-chip voltage reference (Section 13.0 Comparator Voltage Reference Module) can also be an input to the comparators
input and output multiplexers.

COMPARATOR VOLTAGE REFERENCE MODULE

The Comparator Voltage Reference Generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode 110. A programmable register controls the function of the reference generator. Register 13-1 lists the bit functions of the CVRCON register.

the resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The comparator reference supply voltage (also referred to as CVRSRC) comes directly from VDD. It should be noted, however, that the voltage at the top of the ladder is CVRSRC VSAT, where VSAT is the saturation voltage of the power switch transistor. This reference will only be as accurate as the values of CVRSRC and VSAT. The output of the reference generator may be connected to the RA2/AN2/VREF-/CVREF pin. This can be used as a simple D/A function by the user if a very highimpedance load is used. The primary purpose of this function is to provide a test path for testing the reference generator function.

Oscillator Configurations
OSCILLATOR TYPES
The PIC16F87XA can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: LP Low-Power Crystal XT Crystal/Resonator HS High-Speed Crystal/Resonator RC Resistor/Capacitor

CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKI and OSC2/CLKO pins to establish oscillation (Figure 141). The PIC16F87XA oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKI pin Power-up Timer (PWRT) The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The PWRTs time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable or disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation.

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or

wake-up from Sleep.

WATCH DOG TIMER

The watch dog timer is a free-runing on-chip RC oscillator which does not require any external components. This RC oscillator is sperate from the RC oscillator of the OSC1/CLK1 pin. That menes that the WDT run even if the clock on the OSC1/CLK0 and OSC2/CLK1 pins of the device has been stopped. During the narmal operation, aWDT time out genrators a device reset (Watch Dog Timer Reset ) If the device is in sleep mode, a WDT time out causes the device to wake-up and continued with narmal operation (Watch dog Timer Wake-Up) the T0 bit in the status regster will be cleared upon a watch dog timer time-out.The WDT premanentaly disable by clearing WDT timer time-out values may be fount. Values for the WDT prsale may be assigned using the "option+register"register.

MEMS
Micro Electro Mechonical system operation voltage is 3.3V single-supply.

Features
Selectable Sensitivity (1.5g/2g/4g/6g) . Low Current Consumption: 500 A . Sleep Mode: 3 A . Low Voltage Operation: 2.2 V . 3.6 V . 6mm x 6mm x 1.45mm QFN . High Sensitivity (800 mV/g @1.5 g) . Fast Turn On Time . High Sensitivity (1.5 g) . Integral Signal Conditioning with Low Pass Filter . Robust Design, High Shocks Survivability . Pb-Free Terminations . Environmentally Preferred Package . Low Cost
.

LCD

MAX-234
IC MAX232 is used for serial communication.Remember the GND of the serial cable and circuit should be same. The Tx/Rx (transmitter/receiver) pin (pin number 11 and 12) should be connected to our picmicrontroller. In microcontroller 16f877a the receiver line from MAX232 should be connected to P3.0 and the Tx from MAX232 should be connected to P3.1. Also GND of all the circuits should be the same.

MAX232 circuit diagram

SIM300C key features

Feature Power supply Power saving Frequency bands

Implementation Single supply voltage 3.4V 4.5V Typical power consumption in SLEEP mode to 2.5mA ( BS-PA-MFRMS=5 ) SIM300C Tri-band: EGSM 900, DCS 1800, PCS 1900. The SIM300C can search the 3 frequency bands automatically. The frequency bands also can be set by AT Compliant to GSM Phase 2/2+

GSM class Transmit power

Small MS Class 4 (2W) at EGSM900 Class 1 (1W) at DCS1800 and PCS 1900

GPRS connectivity GPRS multi-slot class 8 optional GPRS multi-slot class 10 (default) GPRS mobile station class B

Temperature range Normal operation: -30C to +70C Restricted operation: -30C to +80C Storage temperature -40C to +85C DATA GPRS: CSD:

GPRS data downlink transfer: max. 85.6 kbps GPRS data uplink transfer: max. 42.8 kbps Coding scheme: CS-1, CS-2, CS-3 and CS4 SIM300C supports the protocols PAP (Password Authentication Protocol) usually used for PPP connections. The SIM300C integrates the TCP/IP protocol. Support Packet Switched Broadcast Control Channel (PBCCH) CSD transmission rates: 2.4, 4.8, 9.6, 14.4 kbps, non-transparent Unstructured Supplementary Services Data (USSD) support

SMS MT, MO, CB, Text and PDU mode SMS storage: SIM card Support transmission of SMS alternatively over CSD or GPRS. User can choose preferred mode. FAX SIM interface External antenna Audio features Group 3 Class 1 Support SIM card: 1.8V ,3V Connected via 50 Ohm antenna connector or antenna pad Speech codec modes: Half Rate (ETS 06.20) Full Rate (ETS 06.10) Enhanced Full Rate (ETS 06.50 / 06.60 / 06.80) Echo suppression

Monitoring power supply To monitor the supply voltage, you can use the AT+CBC command which include three parameters: charge state, percent of battery capacity and voltage value (in mV). It

returns charge state the percent of battery capacity and actual value measured at VBAT and GND.

1.6 Flow control

Flow control is very important for correct communication between the GSM and user. For in the case such as a data or fax call or msg, the sending device is transferring data faster than the receiving side is ready to accept. When the receiving buffer reaches its capacity, the receiving device should be capable to cause the sending device to pause until it catches up. There are basically two approaches to achieve data flow control: software flow control and hardware flow control. SIM300D support both two kinds of flow control. In Multiplex mode, it is recommended to use the hardware flow control.

1.6.1 Software flow control (XON/XOFF flow control)

Software flow control sends different characters to stop (XOFF, decimal 19) and resume (XON, decimal 17) data flow. It is quite useful in some applications that only use three wires on the serial interface. The default flow control approach of SIM300D is hardware flow control (RTS/CTS flow control), to enable software flow control in the DTE interface and within GSM engine, type the following AT command: AT+IFC=1, 1 This setting is stored volatile, for use after restart, AT+IFC=1, 1 should be stored to the user profile with AT&W

Hardware flow control (RTS/CTS flow control)

Hardware flow control achieves the data flow control by controlling the RTS/CTS line. When the data transfer should be suspended, the CTS line is set inactive until the transfer from the receiving buffer has completed. When the receiving buffer is ok to receive more data, CTS goes active once again. To achieve hardware flow control,

GSM COMMENTS
We can enter several AT commands on the same line. In this case, you do not need to type the AT or at prefix before every command. Instead, you only need type AT or or at the beginning of the command line. We are use a semicolon as command delimiter. The command line buffer can accept a maximum of 256 characters. If the characters entered exceeded this number then none of the command will executed and TA will returns ERROR.

When we need to enter a series of AT commands on separate lines, we need to wait the final response ( OK, CME error, CMS error) of last AT command you entered before you enter the next AT command.

Overview of AT Commands Command Description

AT+CMGD AT+CMGF AT+CMGL STORE AT+CMGR AT+CMGS AT+CMGW AT+CMSS AT+CMGC AT+CNMI AT+CPMS AT+CRES AT+CSAS AT+CSCA AT+CSCB AT+CSDH AT+CSMP AT+CSMS

DELETE SMS MESSAGE SELECT SMS MESSAGE FORMAT LIST SMS MESSAGES FROM PREFERRED READ SMS MESSAGE SEND SMS MESSAGE WRITE SMS MESSAGE TO MEMORY SEND SMS MESSAGE FROM STORAGE SEND SMS COMMAND NEW SMS MESSAGE INDICATIONS PREFERRED SMS MESSAGE STORAGE RESTORE SMS SETTINGS SAVE SMS SETTINGS SMS SERVICE CENTER ADDRESS SELECT CELL BROADCAST SMS MESSAGES SHOW SMS TEXT MODE PARAMETERS SET SMS TEXT MODE PARAMETERS SELECT MESSAGE SERVICE

The sim 300 have many comments. but we are useing two comments. the two comments are the AT+CMGR and AT+CMGS comments

AT+CMGS Send SMS message

Test Command

AT+CMGS=?
Response

OK SIM300D AT Command Set Confidential SIMCOM

SIM300D_AT_V1.00 Page 85 of 180

Parameters

<da> GSM 03.40 TP-Destination-Address Address-Value field in string format; BCD numbers (or GSM default alphabet characters) are converted to characters of the currently selected TE character set (specified by +CSCS);; type of address given by <toda> <toda> GSM 04.11 TP-Destination-Address Type-of-Address octet in integer format 129 Unknown type(IDSN format number) 128 Unknown type(unknown number format) 161 National number type(IDSN format) 145 International number type(ISDN format ) 177 Network specific number(ISDN format) <length> integer type value indicating in the text mode (+CMGF=1) the length of the message body <data> (or <cdata>) in characters; or in PDU mode (+CMGF=0), the length of the actual TP data unit in octets (i.e. the RP layer SMSC address octets are not counted in the length)
Write Command

1) If text mode (+CMGF=1): +CMGS=<da>[,< toda>]<CR> text is entered <ctrl-Z/ESC> ESC quits without sending 2) If PDU mode (+CMGF=0): +CMGS=<length ><CR> PDU is given <ctrl-Z/ESC>
Response

TA transmits SMS message from a TE to the network (SMS-SUBMIT). Message reference value <mr> is returned to the TE on successful message delivery. Value can be used to identify message upon unsolicited delivery status report result code. 1) If text mode(+CMGF=1) and sending successful: +CMGS: <mr> OK 2) If PDU mode(+CMGF=0) and sending successful: +CMGS: <mr> OK 3)If error is related to ME functionality: +CMS ERROR: <err>
Parameters

<mr> GSM 03.40 TP-Message-Reference in integer format

PROGRAM
#if defined(__PCM__) #include <16F877A.h> #include <gsmpic.h> #DEVICE ADC=8 #define RS PIN_E0 #define RW PIN_E1 #define EN PIN_E2 unsigned int8 value,rcv_cnt,temp,x,y; unsigned char string[50],i; int1 data_recieved,rx=0; void dat(unsigned char dat_val) { output_d(dat_val); output_high(RS); output_low(RW); output_high(EN); delay_us(500); output_low(EN); delay_ms(10); } void cmd(unsigned char cmd_val) { output_d(cmd_val); output_low(RS); output_low(RW); output_high(EN); delay_us(500); output_low(EN); delay_ms(10); } void lcd_init(void) { cmd(0x38); cmd(0x0E); cmd(0x01); } void conv(unsigned int8 conv_val)

{ unsigned int8 val1,val2,val3; val1=(conv_val/100)+0x30; val2=((conv_val%100)/10)+0x30; val3=(conv_val%10)+0x30; dat(val1); dat(val2); dat(val3); } void send_digit(unsigned int8 conv_val) { unsigned int8 val1,val2,val3; val1=(conv_val/100)+0x30; val2=((conv_val%100)/10)+0x30; val3=(conv_val%10)+0x30; putc(val1); putc(val2); putc(val3); } void serial_send(unsigned char tx_val) { unsigned char temp; putc(tx_val); temp=getc(); } void serial_send1(unsigned char tx_val) { unsigned char temp; putc(tx_val); temp=getc(); dat(temp); delay_ms(100); } #int_rda void serial_isr() { string[rcv_cnt]=getc(); temp=string[rcv_cnt]; data_recieved=1; rcv_cnt++; } void gsm_init(void) { disable_interrupts(int_rda);

serial_send("AT+CMGF=1"); serial_send(0x0D); enable_interrupts(int_rda); while(rcv_cnt!=6); } disable_interrupts(int_rda); rcv_cnt=0; delay_ms(2000); disable_interrupts(int_rda); serial_send("AT+CMGD=1"); serial_send(0x0D); enable_interrupts(int_rda); while(rcv_cnt!=6); } void send_sms(void) { disable_interrupts(int_rda); serial_send("AT+CMGS="); serial_send('"'); serial_send("9841994606"); serial_send('"'); serial_send(0x0D); data_recieved=0; rcv_cnt=0; enable_interrupts(int_rda); while(rcv_cnt!=2); if(string[2]=='>'){ rcv_cnt=0; disable_interrupts(int_rda); serial_send("Vehicle Theft"); serial_send(0x1A); enable_interrupts(int_rda); while(rcv_cnt!=7); rcv_cnt=0; } disable_interrupts(int_rda); } void send_sms1(void) { disable_interrupts(int_rda); serial_send("AT+CMGS="); serial_send('"'); serial_send("7502957567"); serial_send('"'); serial_send(0x0D);

data_recieved=0; rcv_cnt=0; enable_interrupts(int_rda); while(rcv_cnt!=2); if(string[2]=='>') { rcv_cnt=0; disable_interrupts(int_rda); serial_send("Accident Occured"); serial_send(0x1A); enable_interrupts(int_rda); while(rcv_cnt!=7); rcv_cnt=0; } disable_interrupts(int_rda); } void recieve_sms(void) { rcv_cnt=0; enable_interrupts(int_rda); while(rcv_cnt!=16); disable_interrupts(int_rda); delay_ms(2000); serial_send1("AT+CMGR=1"); serial_send1(0x0D); enable_interrupts(int_rda); while(rcv_cnt!=63); rcv_cnt=0; while(string[rcv_cnt-1]!=0x0D); rcv_cnt=0; while(rcv_cnt!=5); } void main() { port_b_pullups(TRUE); setup_adc_ports(AN0_AN1_AN3); setup_adc(ADC_CLOCK_INTERNAL); setup_vref(FALSE); enable_interrupts(GLOBAL); output_low(PIN_B0); lcd_init(); gsm_init(); while(TRUE)

{ set_adc_channel(0); delay_ms(200); x=read_adc(); cmd(0xC0); conv(x); set_adc_channel(1); delay_ms(200); y=read_adc(); cmd(0xC8); conv(y); if(input(PIN_B7)) { if(x<82 || x>84 || y<83 || Y>84) { send_sms(); recieve_sms(); if(string[1]=='*'&&string[2]=='9'&&string[3]=='9'&&string[4]=='9'&&string[5]= ='*'&&string[6]=='1'&&string[7]=='#') { output_high(PIN_B0); while(TRUE); } if(string[1]=='*'&&string[2]=='9'&&string[3]=='9'&&string[4]=='9'&&string[5]= ='*'&&string[6]=='2'&&string[7]=='#') { output_low(PIN_B0); while(TRUE); } } } if(!input(PIN_B7)){ if(x<75 || x>95 || y<75 || Y>95) { send_sms1(); while(TRUE); } } } }