MICROCONTROLLER

Technology trends in flash MCUs

Makoto Mizuno
Senior Engineer of MCU Development
Dept.1
MCU Technology Div., MCU Business
Group
Renesas Technology Corp.

Prior to the advent of the on-chip

flash memory microcontroller
(flash MCU), mask ROM was used
to store program code in micro-
controllers that stored programs
internally. Since modifying the
program required modifying the
mask in a mask ROM MCU, devel-
opment times and development
costs were serious issues in mask
ROM microcontrollers. The flash
MCU, which is replacing mask
ROM with flash memory, has
been evolving recently because
it helps shorten system devel- Figure 1: Trends in high-end MCU flash capacity.
opment time and cost radically
since users can re-program the
embedded flash memory even
after the MCU has been mounted
on the product.
The trend of embedded flash
memory technology which sup-
plies program code to a CPU in
microcontrollers has developed
with different from general-pur-
pose flash memories.
In addition, microcontrollers
are subject to strong demands
for real-time performance from
embedded equipment applica-
tion users. The general-purpose
flash memory, such as NAND flash
memory, used for file storage is
aimed at low cost and large ca-
pacity applications. The technol-
ogy trend in NAND flash memory Figure 2: Trends in high-end MCU performance.
is for importance to be placed on
large number of rewrite cycles required characteristics and the Law and have evolved greatly Cost—At each technology
and high through rates in burst previous technology trends and at each technology generation generation, flash microcontrollers
reading. There is little pressure to then we will discuss the new due to ever smaller feature sizes. can be divided into three cat-
reduce latency times. In contrast, requirements of the next genera- What has driven this evolution egories: high-end products that
since supply of program code is tions of this technology. Finally, we is the need for improved cost- focus on performance, generic
the main use for the flash memory will tackle the technological issues performance ratios. The most im- products that balance cost and
in flash MCUs, NOR flash memory that must be resolved to achieve portant aspect of performance in performance, and cost-conscious
is the mainstream here, and com- the requirements presented. microcontrollers is computational products that focus on cost.
patibility with the logic circuits performance. In the remainder The cost of a microcontroller is
with which it is combined is im- Previous tech trends of this section, we discuss flash strongly dependent on the chip
portant for CPU performance. Until now, not only microcon- memory technology from the (silicon) area required: in general,
In this article, we will first trollers but most integrated standpoints of cost and compu- generic products have a chip area
discuss the background for the circuits have followed Moore’s tational performance. about one half that of high-end

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products, and cost-conscious
products have a chip area about
one half that of generic products.
The evolution of semiconduc-
tor technology usually achieves
a doubling of both gate density
and on-chip memory capacity at
each generation (figure 1). This
means that the generic products
of the next generation usually
achieve the performance of the
high-end products of the previ-
ous generation, and the cost-con-
scious products of the following
generation also achieve that level
of performance. It is vital for the
cost aspect of these technology
trends that the same performance
be achieved in one half the area at
each generation due to reduced
feature sizes. Since it is extremely
difficult to achieve a significant
reduction (that is, a 50 per cent Figure 3: Logic capability regarding Flash technology.
reduction) in area with just circuit
design efforts, easy compatibil-
ity with smaller features sizes will
become a critical point for flash
memory technology in the future.
Computational performance—
Computation performance is
increased by increasing the clock
frequency and by improvements
in CPU architecture. High-end
products have achieved a 20-fold
increase in performance over the
last 10 years, and the requirement
to continue this trend is to achieve
a factor of 2.5 improvement at
each technology generation (fig-
ure 2).
Although it is necessary to pro-
vide an amount of program code
storage capacity appropriate for
the CPU performance level in the Table 1: General trends in high-end MCU.
flash memory (code flash memo-
ry) that holds the program code crocontroller flash memory, there flash memory read speeds by the CPU and flash memory, the
(instructions, parameters, and is also some demand for data stor- extending existing technologies. increasing complexity of cache
data), rewriting of this memory age flash memory. At this point, the microcontroller memory systems, and the increas-
is not required. In contrast, since Throughout the period up to with cache memory appeared ing power consumption due to
the flash memory write speed is the point microcontroller clock which wasn’t need for flash read the use of multiple CPU cores,
extremely slow compared to the frequencies reached about 40 speed improvements to meet the need to reconsider the tech-
clock speed for data used in CPU MHz (the 0.35 µm generation), the performance requirements. nologies that give priority to both
calculations, data is provided to the CPU and the flash memory Both these microcontrollers and power consumption and latency
the CPU from registers or SRAM. were able to operate at the same ones that adopted high-speed in microcontroller is getting to be
Portions of data that need to be clock frequency due to increases flash memory were able to meet important.
saved temporarily can be written in basic device performance due the computation performance
asynchronously to flash memory to the decreasing feature size requirements at that generation. Next gen requirements
or EEPROM. Therefore, while the at each generation. However, However, now with the increasing It is now necessary to improve
code flash memory in which read when the CPU clock frequency severity of the problems associat- microcontroller functionality and
performance is the main concern is 60 MHz or higher, it becomes ed with the increasing difference performance along with the evo-
is seen as the most important mi- extremely difficult to increase between the operating speeds of lution of semiconductor technol-

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ogies to respond to user require-
ments. Basically, any elemental
technology has only a limit range
of applicability, it is important to
judge the applicability of a tech-
nology at an appropriate time.
In the following, we will discuss
three major requirements that
have come to light along with
the progress from earlier times to
the current technological state.
Reducing power consump-
tion—Although the power con-
sumption per unit area is tending
to increase with each generation,
recently the amount of that in-
crease has tended to be on the
order of 1.3 to 2.0 times due to the
increasing difficulty of Vdd scaling.
Therefore, there have been cases
where microcontroller computa-
tional performance has been lim-
ited by power consumption, and
technologies that suppress power
Figure 4: Cache simplification study.
consumption have become im-
portant elements for increas- there are now increasing needs Implementing EEPROM emulation we see the split-gate cell as prom-
ing performance. At the same for microcontrollers that include (data flash) and operating multiple ising for use in microcontroller
time, cache memories, which EEPROM functionality. However, modules at the same time flash memory.
are responsible for performance since the EEPROM cell structure Cost—Matching with process Microcontroller perfor-
improvements, are occupying differs from that of the flash feature size reduction. Core and mance—Selecting between
40 per cent of overall CPU power memory cell due to the empha- logic supply voltages are falling cache-dependent and flash-de-
consumption, and technologies sis on write performance, there due to the reductions in feature pendent approaches
that simplify cache systems are are technological problems with sizes. However, since current NOR In microcontrollers that do
now required. combining EEPROM on the same flash memory requires a read not include a cache memory
Handling multiple CPU cores— chip. Also, there will be needs for word voltage in the 2.5 to 4.0 system, microcontroller perfor-
Parallelism based on multiple CPU including multiple, independent V range, this technology is at a mance directly depends on the
cores has become indispensable EEPROMs in these devices starting disadvantage in both speed and flash memory operating fre-
to improve computational per- in 2010, and it will be necessary to power consumption. In contrast, quency. However, when a cache
formance. Since it has become achieve simultaneous read and the read voltage can be reduced is used the CPU computational
extremely difficult to achieve the write operations, that is, methods with the split-gate flash memory performance is strongly depen-
desired 2.5-fold performance for ameliorating interference will cell in which the read and write dent on the cache. There are
increase at each generation with be required. circuits can be separated as shown two candidates for designing a
improvements in pipelining and in Figure 3. Furthermore there are flash memory architecture that
higher clock rates in individual Next generation flash MCU excellent features which were dif- includes cache: complex cache
CPUs, we now design performance We will summarize the develop- ficult to solve for the conventional system + slow flash (case 1) and
improvements with multiple CPU ment issues for the next genera- NOR-type flash cell such as avoid- simple cache + fast flash (case 2).
parallelism and clock speed op- tion of flash memory technolo- ing the over-erasure problem and The differences between these
timization. In parallel-processing gies and propose directions for improving write efficiency, and approaches appears as a differ-
systems, the CPU stall penalty is developing the next generation thus has features that make it ence in power consumption at
large, and technologies such as of flash-MUCs as shown in Table advantageous for microcontroller the same computational per-
more complex branch prediction 1. embedded flash. And now, it is formance, and differences also
and minimizing latency will be- going to become a wider range appear in the complexity of the
come increasingly important. Cost—Reduced features sizes where it can be applied. Focusing cache control circuit and in the
EEPROM functionality— and fusion with logic fabrication on memory element, two types cache memory capacity (includ-
EEPROM has come to be used processes of device have been proposed for ing hierarchical structures). Since
to store small amounts of data Microcontroller performance— the memory element the floating the cache miss penalty is critical
on the system board. Due to Cache simplification, latency re- gate type and the charge trap in case 1, case 1 devices are de-
the recent trend towards imple- duction, fast and low power read type, and 100 MHz read operation signed so that misses, including
mentation of applications as operations has been achieved by using the branch misses, do not occur, and
SoC (system-on-chip) devices, Achieving SoC requirements— charge trap type device. Therefore case 2 devices are designed so

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that the cache miss penalty is
minimized with high-speed flash.
As a result there is a tendency
for case 1 device to require large
complex cache systems. When
a branch instruction is read, the
power consumption differs de-
pending on whether or not there
is code in the cache because the
numbers of transistors are dif-
ferent for same code execution
as shown in Figure 4 and also
depending on the cache hit ef-
ficiency. Then, if the code flash
is not made faster than 20 or 30
MHz, a flash memory access may
require 8 cycles if the CPU oper-
ating frequency is 200 MHz or
higher. In an application in which
branch prediction is difficult and
there is a flash access once every
5 to 7 system clocks, CPU stall
countermeasures become more
complex in case 1. A study of the
influence on power consump-
tion and chip area, we learned
that the case 2 design is advanta-
geous from both aspects (figure
4). Therefore in the future, in the
age of the increasingly pipe-
lined and increasingly parallel
microcontroller, as flash speeds
increase, both pipeline operation
and latency reduction measures
will be advantageous technolo-
gies for cache simplification.
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Achieving SoC require-
ments—Implementing EEPROM
emulation and parallel operating
in multiple flash modules. The
inclusion of EEPROM functionality
has become a vital requirement
for high-end flash MCUs. In con-
trast to code flash, the EEPROM
functionality only requires a
capacity in the range 1/100 to
1/1000 of that of code flash and
has only a minimal effect on com-
putational performance. At the
same time, however, including
EEPROM cells on the same chip
as logic and code flash memory
makes fabrication extremely dif-
ficult and increases costs greatly.
As a result, the EEPROM function-
ality is preferably implemented
by modifying the operation of
a cell that is actually identical to
that of the code flash. The main
differences between EEPROM
and code flash specifications are
that the ability of write operations
must be about 1000 times greater
and that the time to write small
units of memory (byte or word
units) must be fast. Access units
and write speeds adopt measures
by modifications of the usage
procedures, but ability of write
cycles is the most difficult issue. In
one common technique, the read
time requirements are relaxed and
two cells are used to implement a
single bit. This achieves the ability
to write data from 100K to 500K
times.
When EEPROM functionality is
included, it is assumed that write
operations will be performed dur-
ing user program and application
operation. When this is the case,
a variety of structural measures
are required. These include avoid-
ing interference with CPU op-
eration, including multiple small
EEPROMs, and making it possible
to read and write at the same time.
Technologies used to implement
these measures include using a
dedicated flash control circuit and
using background operation and/
or and RWW module.
Conclusions
In this article we have discussed
both requirements for continu-
ing microcontroller technology
trends and requirements for the
next generation (from 2010 to
2015) with regard to the flash
memory technologies embed-
ded in flash MCUs. We consider
the following to be the leading
candidates for the next genera-
tion of flash modules.
1. Code flash—Modules which
apply a pipelined structure
to split-gate flash memory,
which features low-voltage
high-speed read operation.
2. Data flash—The number of
write cycles can be increased
to over 100,000 by use two
flash code cells for each bit.
3. Flash controller—Circuits
that control functions other
than the flash memory read
operation can be included
as well in order to avoid the
confliction between multi-
CPU orders.
Although we have not focused
on this issue until now, high-speed
flash memory has a significant
advantage because it can be used
to implement generic and cost-
conscious products that operate
at speeds up to 100 MHz without
the use of a cache memory.
Although fast flash memory
makes cache memories simpler,
there is a trade off between the
difficulty of making flash memory
faster and the difficulty of working
around the problems inherent in
cache memory. For the genera-
tions after the next generation, it
will be necessary to search for
flash memory technologies that
can be effective at reducing
overall microcontroller power
consumption.