Documentos de Académico
Documentos de Profesional
Documentos de Cultura
PIC16C710
RA3/AN3/VREF 2 17 RA0/AN0 RA3/AN3/VREF 2 19 RA0/AN0
PIC16C710
RA4/T0CKI 3 16 OSC1/CLKIN RA4/T0CKI 3 18 OSC1/CLKIN
MCLR/VPP 4 15 OSC2/CLKOUT MCLR/VPP 4 17 OSC2/CLKOUT
VSS 5 14 VDD VSS 5 16 VDD
RB0/INT 6 13 RB7 VSS 6 15 VDD
RB1 7 12 RB6 RB0/INT 7 14 RB7
RB2 8 11 RB5 RB1 8 13 RB6
RB3 9 10 RB4 RB2 9 12 RB5
RB3 10 11 RB4
RA2/AN2 •1 18 RA1/AN1
PIC16C71
RA3/AN3/VREF 2 17 RA0/AN0
RA4/T0CKI 3 16 OSC1/CLKIN
MCLR/VPP 4 15 OSC2/CLKOUT
VSS 5 14 VDD
RB0/INT 6 13 RB7
RB1 7 12 RB6
RB2 8 11 RB5
RB3 9 10 RB4
PIC16C72
RC1/T1OSI/CCP2
SDIP, SOIC, Windowed Side Brazed Ceramic MQFP
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
MCLR/VPP •1 28 RB7
NC
RA0/AN0 2 27 RB6
RA1/AN1 3 26 RB5
RA2/AN2 4 25 RB4
PIC16C73A
PIC16C73
RA3/AN3/VREF 5 24 RB3
44
43
42
41
40
39
38
37
36
35
34
RA4/T0CKI 6 23 RB2 RC7/RX/DT 1 33 NC
RA5/AN4/SS 7 22 RB1 RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKOUT
VSS 8 21 RB0/INT RD6/PSP6 4 30 OSC1/CLKIN
OSC1/CLKIN 9 20 VDD RD7/PSP7 5 29 VSS
VSS 6 28 VDD
OSC2/CLKOUT
RC0/T1OSO/T1CKI
10
11
19
18
VSS
RC7/RX/DT
VDD 7 PIC16C74 27 RE2/CS/AN7
RB0/INT 8 26 RE1/WR/AN6
RC1/T1OSI/CCP2 12 17 RC6/TX/CK RB1 9 25 RE0/RD/AN5
RC2/CCP1 RB2 10 24 RA5/AN4/SS
13 16 RC5/SDO
RB3 11 23 RA4/T0CKI
RC3/SCK/SCL 14 15 RC4/SDI/SDA
12
13
14
15
16
17
18
19
20
21
22
RB4
RB5
RB6
RB7
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
NC
NC
RC1/T1OSI/CCP2
RC3/SCK/SCL
RC4/SDI/SDA
RA3/AN3/VREF
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
MCLR/VPP
PLCC MQFP
RA2/AN2
RA1/AN1
RA0/AN0
TQFP
NC
RB7
RB6
RB5
RB4
NC
NC
44
43
42
41
40
39
38
37
36
35
34
44
43
42
41
40
6
5
4
3
2
1
RC7/RX/DT 1 33 NC
RA4/T0CKI 7 39 RB3 RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RA5/AN4/SS 8 38 RB2 RD5/PSP5 3 31 OSC2/CLKOUT
RE0/RD/AN5 9 37 RB1 RD6/PSP6 4 30 OSC1/CLKIN
RE1/WR/AN6 10 36 RB0/INT RD7/PSP7 5 29 VSS
RE2/CS/AN7 11 35 VDD VSS 6 28 VDD
VDD 12 PIC16C74 34 VSS VDD 7 PIC16C74A 27 RE2/CS/AN7
VSS 13 33 RD7/PSP7 RB0/INT 8 26 RE1/WR/AN6
OSC1/CLKIN
OSC2/CLKOUT
14
15
PIC16C74A 32
31
RD6/PSP6
RD5/PSP5
RB1
RB2
9
10
25
24
RE0/RD/AN5
RA5/AN4/SS
RC0/T1OSO/T1CKI 16 30 RD4/PSP4 RB3 11 23 RA4/T0CKI
12
13
14
15
16
17
18
19
20
21
22
NC 17 29 RC7/RX/DT
18
19
20
21
22
23
24
25
26
27
28
RB4
RB5
RB6
RB7
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
NC
NC
RC1/T1OSI /CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
MCLR/VPP 1 40 RB7
RA0/AN0 2 39 RB6
RA1/AN1 3 38 RB5
RA2/AN2 4 37 RB4
RA3/AN3/VREF 5 36 RB3
RA4/T0CKI 6 35 RB2
RA5/AN4/SS 7 34 RB1
PIC16C74A
PIC16C74
RE0/RD/AN5 8 33 RB0/INT
RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6
OSC1/CLKIN 13 28 RD5/PSP5
OSC2/CLKOUT 14 27 RD4/PSP4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0/PSP0 19 22 RD3/PSP3
RD1/PSP1 20 21 RD2/PSP2
DS30390D-page 6
Clock Memory Peripherals Features
H z) d s) )
r (s
(M wo u le T) ls
ion R ne g
PIC16C7X
at 14 od SA n in
er (x M ha m
p y ,U C m
or M 2C ) ra
o fO em s) W t) ts
y M te rt - bi s V ol r og
n c y ) r e /P PI/I
S o ( 8 e ( P t
m (b s P rc l se
q ue gra r y l e( pa s) ( v e t er u ge r ia e
e o o u o m t ( a r o a n e R
Fr Pr od or Sl ve R tS ut s
M em M /C tS s
e ui -o ge
um O M r u re al P l l el C on rup i n g r c n k a
im R ta e pt ri ra r P lta i c
ax EP m D te -C ow
M Da Ti Ca Se Pa A/ In I/O Vo In Br Pa
PIC16C710 20 512 36 TMR0 — — — 4 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC;
20-pin SSOP
PIC16C71 20 1K 36 TMR0 — — — 4 4 13 3.0-6.0 Yes — 18-pin DIP, SOIC
PIC16C711 20 1K 68 TMR0 — — — 4 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC;
PIC16C7X FAMILY OF DEVICES
20-pin SSOP
PIC16C72 20 2K 128 TMR0, 1 SPI/I2C — 5 8 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C73 20 4K 192 TMR0, 2 SPI/I2C, — 5 11 22 3.0-6.0 Yes — 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C73A(1) 20 4K 192 TMR0, 2 SPI/I2C, — 5 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C74 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 3.0-6.0 Yes — 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP
PIC16C74A(1) 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP, TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability.
All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
Program
Device Data Memory
Memory
PIC16C710 512 x 14 36 x 8
PIC16C71 1K x 14 36 x 8
PIC16C711 1K x 14 68 x 8
PIC16C72 2K x 14 128 x 8
PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (sym-
metrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
PIC16C710 512 x 14 36 x 8
PIC16C71 1K x 14 36 x 8
PIC16C711 1K x 14 68 x 8
STATUS reg
8
3 MUX
Power-up
Timer
Instruction
Decode & Oscillator
Start-up Timer ALU
Control
Power-on 8
Timing Reset
Generation W reg
Watchdog
OSC1/CLKIN Timer
OSC2/CLKOUT
Brown-out
Reset(2)
Timer0
Synchronous
A/D Serial Port CCP1
STATUS reg
8 PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
3 RC2/CCP1
Power-up MUX
RC3/SCK/SCL
Timer
RC4/SDI/SDA
Instruction Oscillator RC5/SDO
Decode & Start-up Timer ALU RC6/TX/CK
Control RC7/RX/DT
Power-on
Reset 8
Timing Watchdog
Generation Timer W reg
OSC1/CLKIN Brown-out
OSC2/CLKOUT Reset(2)
Synchronous
CCP1 CCP2 USART
Serial Port
STATUS reg
8 PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
3 RC2/CCP1
Power-up MUX
RC3/SCK/SCL
Timer
RC4/SDI/SDA
Instruction Oscillator RC5/SDO
Decode & Start-up Timer ALU RC6/TX/CK
Control RC7/RX/DT
Power-on
Reset 8 PORTD
Timing Watchdog
Generation Timer W reg
OSC1/CLKIN Brown-out
OSC2/CLKOUT RD7/PSP7:RD0/PSP0
Reset(2)
RE1/WR/AN6
Timer0 Timer1 Timer2 A/D
RE2/CS/AN7
Synchronous
CCP1 CCP2 USART
Serial Port
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1FFFh
Stack Level 1
Stack Level 8
1FFFh
Stack Level 8
Stack Level 8
1FFFh
1FFFh
Unimplemented data memory locations, read Unimplemented data memory locations, read
as '0'. as '0'.
Note 1: Not a physical register. Note 1: Not a physical register.
2: The PCON register is not implemented on the 2: These locations are unimplemented in Bank 1.
PIC16C71. Any access to these locations will access the
3: These locations are unimplemented in Bank 1. corresponding Bank 0 register.
Any access to these locations will access the
corresponding Bank 0 register.
7Fh FFh
Bank 0 Bank 1
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read
as '0'.
Unimplemented data memory locations, read
Note 1: Not a physical register.
as '0'. 2: These registers are not physically imple-
Note 1: Not a physical register. mented on the PIC16C73/73A, read as '0'.
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
02h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
04h(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — — PORTA Data Latch when written: PORTA pins when read ---x 0000 ---u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h — Unimplemented — —
08h ADCON0 ADCS1 ADCS0 (6) CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000
0Ah(2,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(3) INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Bank 1
80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
84h(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111
86h TRISB PORTB Data Direction Control Register 1111 1111 1111 1111
(4)
87h PCON — — — — — — POR BOR ---- --qq ---- --uu
8Ah(2,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(3) INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Bh
Bank 0
00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu
04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h — Unimplemented — —
09h — Unimplemented — —
0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Bank 1
80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(1) (4) (4)
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h — Unimplemented — —
89h — Unimplemented — —
8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000
8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh — Unimplemented — —
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
Bank 0
00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4) (7) (7)
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
(5)
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Bank 1
80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4) (7) (7)
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111
(5)
89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
Note 1: PIC16C73 and PIC16C73A devices do not have a Parallel Slave Port implemented, this bit location is
reserved on these two devices, always maintain this bit clear.
Note 1: PIC16C73 and PIC16C73A devices do not have a Parallel Slave Port implemented, this bit location is
reserved on these two devices, always maintain this bit clear.
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
not used
Data
Memory
7Fh 7Fh
Bank 0 Bank 1 Bank 2 Bank 3
For register file map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
I/O pin
D Q
N
WR TRIS
CK Q VSS
TRIS Latch Analog
input
mode
TTL
input
RD TRIS buffer
Q D
EN
EN
RD PORT
To A/D Converter
Note: I/O pin has protection diodes to VDD and VSS. The PIC16C710/71/711 devices do not have a pin RA5.
WR PORT CK Q
N RA4/T0CKI pin
Data Latch
VSS
D Q
WR TRIS Schmitt
CK Q Trigger
input
TRIS Latch buffer
RD TRIS
Q D
EN
EN
RD PORT
05h PORTA — — RA5(1) RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — TRISA5(1) TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
9Fh ADCON1 — — — — — PCFG2(2) PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: PORTA<5> and TRISA<5> are not implemented on the PIC16C710/71/711.
2: Bit PCFG2 is not implemented on the PIC16C710/71/711.
RD TRIS
Q D
RD Port EN
RB0/INT
RD Port EN RD Port EN Q1
Set RBIF Set RBIF
From other Q D Q D
RB7:RB4 pins From other
RB7:RB4 pins RD Port
EN EN
RD Port Q3
RB7:RB6 in serial programming mode RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS. Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = '1' enables weak pull-up if RBPU = '0' 2: TRISB = '1' enables weak pull-up if RBPU = '0'
(OPTION<7>). (OPTION<7>).
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
Peripheral Data-out
0
VDD
1
Data Bus D Q P
WR PORT
CK Q
Data Latch
D Q I/O pin
WR TRIS N
CK Q
RD TRIS Schmitt
Peripheral OE(2) Trigger
Q D
RD PORT
EN
EN
Peripheral input
Note 1: Port/Peripheral select signal selects between port data and peripheral output. RD PORT
2: Peripheral OE (output enable) is only activated if peripheral select is active.
3: I/O pins have diode protection to VDD and VSS.
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI/CCP2(1) bit1 ST Input/output port pin or Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL bit3 ST RC3/SCK/SCL can also be selected as the synchronous serial clock
for both SPI and I2C modes.
RC4/SDI/SDA bit4 ST RC4/SDI/SDA can also be selected as the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output
RC6/TX/CK(2) bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART
Synchronous Clock
RC7/RX/DT(2) bit7 ST Input/output port pin or USART Asynchronous Receive, or USART
Synchronous Data
Legend: ST = Schmitt Trigger input
Note 1: The CCP2 multiplexed function is not enabled on the PIC16C72.
2: The TX/CK and RX/DT multiplexed functions are not enabled on the PIC16C72.
TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other resets
BOR
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.
Data Bus
D Q
I/O pin
WR PORT CK Q
Data Latch
D Q
WR TRIS Schmitt
CK Q Trigger
input
TRIS Latch buffer
RD TRIS
Q D
EN
EN
RD PORT
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
Data Bus
D Q
I/O pin
WR PORT CK Q
Data Latch
D Q
WR TRIS Schmitt
CK Q Trigger
input
TRIS Latch buffer
RD TRIS
Q D
EN
EN
RD PORT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note:
PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB
Instruction followed by a read from PORTB.
fetched MOVWF PORTB MOVF PORTB,W
write to NOP NOP
PORTB Note that:
RB7:RB0 data setup time = (0.25TCY - TPD)
where TCY = instruction cycle
Port pin
sampled here TPD = propagation delay
TPD Therefore, at higher clock frequencies,
Instruction
executed NOP
a write followed by a read may be prob-
MOVWF PORTB MOVF PORTB,W
write to lematic.
PORTB
FIGURE 5-11: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
Data bus
D Q RDx pin
WR Port
EN
CK
Q D
TTL
RD Port EN
EN
TTL
Read
RD
Chip Select
CS
Write
WR
08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Data bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0
clocks
RA4/T0CKI Programmable 0 PSout
pin Prescaler
T0SE (2 cycle delay)
3
Set interrupt
PS2, PS1, PS0 PSA flag bit T0IF
T0CS on overflow
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Instruction
Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC PC PC +1 PC +1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h)
Instruction Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h)
executed
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
External Clock Input or misses sampling
Prescaler output (2)
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
8
M 1
0
RA4/T0CKI U M
X SYNC
pin U 2 TMR0 reg
1 0
X Cycles
T0SE
T0CS
PSA Set flag bit T0IF
on Overflow
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-out
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
2: The CCP2 module is not implemented in the PIC16C72.
3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode.
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
4 PR2 reg
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
Capture Timer1
Compare Timer1
PWM Timer2
Note: If the RC2/CCP1 is configured as an out- When the Capture mode is changed, a false capture
put, a write to the port can cause a capture interrupt may be generated. The user should keep bit
condition. CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
There are four prescaler settings, specified by bits The user must configure the RC2/CCP1 pin as an out-
CCP1M3:CCP1M0. Whenever the CCP module is put by clearing the TRISC<2> bit.
turned off, or the CCP module is not in capture mode,
Note: Clearing the CCP1CON register will force
the prescaler counter is cleared. This means that any
the RC2/CCP1 compare output latch to the
reset will clear the prescaler counter.
default low level. This is not the data latch.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will 10.2.2 TIMER1 MODE SELECTION
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recom- Timer1 must be running in Timer mode or Synchro-
mended method for switching between capture pres- nized Counter mode if the CCP module is using the
calers. This example also clears the prescaler counter compare feature. In Asynchronous Counter mode, the
and will not generate the “false” interrupt. compare operation may not work.
Special Event(1)
(PIR1<2>)
CCPR1H CCPR1L
Q S Output
Logic Comparator
RC2/CCP1 R match
Pin
TRISC<2> TMR1H TMR1L
Output Enable CCP1CON<3:0>
Mode Select
Note 1: For CCP1 (if enabled), reset Timer1, but not set
TMR1IF(PIR<0>).
For CCP2 (if enabled), reset Timer1, but not set
TMR1IF(PIR<0>), and set bit GO/DONE
(ADCON0<2>), which starts an A/D conversion.
TMR2 = PR2 Note: If the PWM duty cycle value is longer than
TMR2 = Duty Cycle the PWM period (PWM duty
cycle = 100%), the CCP1 pin will not be
TMR2 = PR2 cleared.
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
TABLE 10-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh(2) PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh(2) PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh(2) CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu
1Ch(2) CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu
1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
When initializing the SPI, several options need to be The block diagram of the SSP module, when in SPI
specified. This is done by programming the appropriate mode (Figure 11-3), shows that the SSPSR is not
control bits in the SSPCON register (SSPCON<5:0>). directly readable or writable, and can only be accessed
These control bits allow the following to be specified: from addressing the SSPBUF register. Additionally, the
• Master Mode (SCK is the clock output) SSP status register (SSPSTAT) indicates the various
• Slave Mode (SCK is the clock input) status conditions.
• Clock Polarity (Output/Input data on the FIGURE 11-3: SSP BLOCK DIAGRAM
Rising/Falling edge of SCK) (SPI MODE)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register Internal
data bus
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSB first. The Read Write
SSPBUF holds the data that was previously written to
the SSPSR, until the received data is ready. Once the SSPBUF reg
8-bits of data have been received, that information is
moved to the SSPBUF register. Then the buffer full
detect bit BF (SSPSTAT <0>) and interrupt flag bit
SSPIF (PIR1<3>) are set. This double buffering of the SSPSR reg
received data (SSPBUF) allows the next byte to start RC4/SDI/SDA bit0 shift
reception before reading the data that was received. clock
Any write to the SSPBUF register during transmission/
reception of data will be ignored, and the write collision RC5/SDO
detect bit WCOL (SSPCON<7>) will be set. User soft-
ware must clear the WCOL bit so that it can be deter-
mined if the following write(s) to the SSPBUF register SS Control
Enable
completed successfully. When the application software
is expecting to receive valid data, the SSPBUF should RA5/AN4/SS Edge
be read before the next byte of data to transfer is writ- Select
ten to the SSPBUF. Buffer full bit BF (SSPSTAT<0>)
indicates when SSPBUF has been loaded with the 2
received data (transmission is complete). When the Clock Select
SSPBUF is read, bit BF is cleared. This data may be
SSPM3:SSPM0
irrelevant if the SPI is only a transmitter. Generally the TMR2 output
SSP Interrupt is used to determine when the transmis- 4 2
sion/reception has completed. The SSPBUF can then Edge
be read (if data is meaningful) and/or the SSPBUF Select Prescaler TCY
(SSPSR) can be written. If the interrupt method is not RC3/SCK/ 4, 16, 64
going to be used, then software polling can be done to SCL
ensure that a write collision does not occur. TRISC<3>
Example 11-1 shows the loading of the SSPBUF
(SSPSR) for data transmission. The shaded instruction
is only required if the received data is meaningful.
SDO SDI
SDI SDO
Shift Register Shift Register
(SSPSR) (SSPSR)
PROCESSOR 1 PROCESSOR 2
FIGURE 11-5: SPI MODE TIMING (MASTER MODE OR SLAVE MODE W/O SS CONTROL)
SCK
(CKP = 0)
SCK
(CKP = 1)
SDI
bit7 bit0
SSPIF
Interrupt flag
SCK
(CKP = 0)
SCK
(CKP = 1)
SDI
bit7 bit0
SSPIF
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF (2)
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE (2)
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'.
Term Description
MSb LSb S
Start Clock Pulse for
S R/W ACK Condition Acknowledgment
SDA
MSB acknowledgment acknowledgment
signal from receiver byte complete signal from receiver
interrupt with receiver
clock line held low while
interrupts are serviced
SCL S 1 2 7 8 9 1 2 3•8 9 P
Start Stop
Condition Address R/W ACK Wait Data ACK
State Condition
S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P
Combined format:
Sr Slave Address R/W A Slave Address A Data A Data A/A Sr Slave Address R/W A Data A Data A P
First 7 bits Second byte First 7 bits
(write) (read)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = acknowledge (SDA low)
From master to slave A = not acknowledge (SDA high)
S = Start Condition
From slave to master P = Stop Condition
The I2C protocol allows a system to have more than Clock synchronization occurs after the devices have
one master. This is called multi-master. When two or started arbitration. This is performed using a wired-
more masters try to transfer data at the same time, arbi- AND connection to the SCL line. A high to low transition
tration and synchronization occur. on the SCL line causes the concerned devices to start
counting off their low period. Once a device clock has
11.2.4.1 ARBITRATION gone low, it will hold the SCL line low until its SCL high
state is reached. The low to high transition of this clock
Arbitration takes place on the SDA line, while the SCL
may not change the state of the SCL line, if another
line is high. The master which transmits a high when
device clock is still within its low period. The SCL line is
the other master transmits a low loses arbitration
held low by the device with the longest low period.
(Figure 11-15), and turns off its data output stage. A
Devices with shorter low periods enter a high wait-
master which lost arbitration can generate clock pulses
state, until the SCL line comes high. When the SCL line
until the end of the data byte where it lost arbitration.
comes high, all devices start counting off their high
When the master devices are addressing the same
periods. The first device to complete its high period will
device, arbitration continues into the data.
pull the SCL line low. The SCL line high time is deter-
FIGURE 11-15: MULTI-MASTER mined by the device with the shortest high period,
ARBITRATION Figure 11-16.
(TWO MASTERS) FIGURE 11-16: CLOCK SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1 SDA start counting
wait
DATA 1 state HIGH period
DATA 2 CLK
1
SDA counter
CLK reset
SCL 2
SCL
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
cleared in software From SSP interrupt
SSPBUF is written in software service routine
CKP (SSPCON<4>)
Master mode of operation is supported by interrupt In multi-master mode, the interrupt generation on the
generation on the detection of the START and STOP detection of the START and STOP conditions allows
conditions. The STOP (P) and START (S) bits are the determination of when the bus is free. The STOP
cleared from a reset or when the SSP module is dis- (P) and START (S) bits are cleared from a reset or
abled. Control of the I 2C bus may be taken when the P when the SSP module is disabled. Control of the I2C
bit is set, or the bus is idle with both the S and P bits bus may be taken when bit P (SSPSTAT<4>) is set, or
clear. the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
In master mode the SCL and SDA lines are manipu-
ate the interrupt when the STOP condition occurs.
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the In multi-master operation, the SDA line must be moni-
value(s) in PORTC<4:3>. So when transmitting data, a tored to see if the signal level is the expected output
'1' data bit must have the TRISC<4> bit set (input) and level. This check only needs to be done when a high
a '0' data bit must have the TRISC<4> bit cleared (out- level is output. If a high level is expected and a low level
put). The same scenario is true for the SCL line with the is present, the device needs to release the SDA and
TRISC<3> bit. SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, they are:
The following events will cause the SSP Interrupt Flag
bit SSPIF to be set (SSP Interrupt if enabled): • Address Transfer
• START condition • Data Transfer
• STOP condition When the slave logic is enabled, the slave continues to
• Data transfer byte transmitted/received receive. If arbitration was lost during the address trans-
fer stage, the device may be being addressed. If
Master mode of operation can be done with either the addressed an ACK pulse will be generated. If arbitra-
slave mode idle (SSPM3:SSPM0 = 1011) or with the tion was lost during the data transfer stage, the device
slave active. When both master and slave modes are will need to re-transfer the data at a later time.
enabled, the software needs to differentiate the
source(s) of the interrupt.
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other resets
BOR
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by SSP in I2C mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'.
IDLE_MODE (7-bit):
if (Addr_match) { Set interrupt;
if (R/W = 1) { Send ACK = 0;
set XMIT_MODE;
}
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((SSPBUF=Full) OR (SSPOV = 1))
{ Set SSPOV;
Do not acknowledge;
}
else { transfer SSPSR → SSPBUF;
send ACK = 0;
}
Receive 8-bits in SSPSR;
Set interrupt;
XMIT_MODE:
While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if ( ACK Received = 1) { End of transmission;
Go back to IDLE_MODE;
}
else if ( ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{ PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((SSPBUF = Full) OR ((SSPOV = 1))
{ Set SSPOV;
Do not acknowledge;
}
else { Set UA = 1;
Send ACK = 0;
While (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{ PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1)
{ if (PRIOR_ADDR_MATCH)
{ send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}
FIGURE 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other resets
BOR
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Samples
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1 2 3 4 1 2 3 4 1 2
Q2, Q4 clk
Q2, Q4 clk
Samples
TX9
Baud Rate Generator
TX9D
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
TRMT bit Transmit Shift Reg
(Transmit shift
reg. empty flag)
Write to TXREG
Word 1 Word 2
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0
TXIF bit
(interrupt reg. flag) WORD 1 WORD 2
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
SPBRG
÷ 64 MSb RSR register LSb
or
÷ 16
Baud Rate Generator Stop (8) 7 • • • 1 0 Start
RC7/RX/DT
Pin Buffer Data
and Control Recovery RX9
Interrupt RCIF
Data Bus
RCIE
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other Resets
BOR
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Write to
TXREG reg
Write word1 Write word2
TXIF bit
(Interrupt flag)
TRMT
TRMT bit
'1' '1'
TXEN bit
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other Resets
BOR
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
CK pin
Write to
SREN bit
SREN bit
CREN bit '0' '0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with SREN = '1' and BRG = '0'.
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other Resets
BOR
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other Resets
BOR
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF
000 A A A A A A A A VDD
001 A A A A VREF A A A RA3
010 A A A A A D D D VDD
011 A A A A VREF D D D RA3
100 A A D D A D D D VDD
101 A A D D VREF D D D RA3
11x D D D D D D D D —
A = Analog input
D = Digital I/O
Note 1: RE0, RE1, and RE2 are implemented on the PIC16C74/74A only.
CHS1:CHS0
11
RA3/AN3/VREF
VIN
(Input voltage) 10
RA2/AN2
01
A/D RA1/AN1
Converter
00
RA0/AN0
VDD
00 or
VREF 10 or
11
(Reference
voltage) 01
PCFG1:PCFG0
111
RE2/AN7(1)
110
RE1/AN6(1)
101
RE0/AN5(1)
100
RA5/AN4
VIN
(Input voltage) 011
RA3/AN3/VREF
010
A/D RA2/AN2
Converter
001
RA1/AN1
VDD 000
RA0/AN0
000 or
VREF 010 or
100
(Reference
voltage) 001 or
011 or
101
PCFG2:PCFG0
Note 1: Not available on PIC16C72/73/73A.
CHOLD
VA CPIN I leakage = DAC capacitance
5 pF VT = 0.6V ± 500 nA = 51.2 pF
VSS
Resolution
Freq. (MHz)(1)
4-bit 8-bit
TAD 20 1.6 µs 1.6 µs
16 2.0 µs 2.0 µs
TOSC 20 50 ns 50 ns
16 62.5 ns 62.5 ns
2TAD + N • TAD + (8 - N)(2TOSC) 20 10 µs 16 µs
16 12.5 µs 20 µs
Note 1: The PIC16C71 has a minimum TAD time of 2.0 µs.
All other PIC16C7X devices have a minimum TAD time of 1.6 µs.
(full scale)
an analog input pin (capacitor, zener diode, etc.)
255 LSb
256 LSb
0.5 LSb
1 LSb
2 LSb
3 LSb
4 LSb
should have very little leakage current at the pin.
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
A/D Clock
Yes Start of A/D SLEEP Yes Finish Conversion
Conversion Delayed Instruction? GO = 0
= RC? 1 Instruction Cycle ADIF = 1
No No
No No
Wait 2 TAD
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other Resets
BOR
0Bh/8Bh INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
08h ADCON0 ADCS1 ADCS0 — CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000
05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other Resets
BOR
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Value on:
Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR,
other Resets
BOR
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
CP0 CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
bit13 bit0 Address 2007h
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.
CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
bit13 bit0 Address 2007h
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
• HS High Speed Crystal/Resonator See Table 14-1, Table 14-2, Table 14-3 and Table 14-4 for
• RC Resistor/Capacitor recommended values of C1 and C2.
Note 1: A series resistor may be required for AT strip
14.2.2 CRYSTAL OSCILLATOR/CERAMIC cut crystals.
RESONATORS 2: For the PIC16C710/71/711 the buffer is on the
OSC2 pin, all other devices have the buffer on
In XT, LP or HS modes a crystal or ceramic resonator the OSC1 pin.
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 14-5). The FIGURE 14-6: EXTERNAL CLOCK INPUT
PIC16CXX Oscillator design requires the use of a par- OPERATION (HS, XT OR LP
allel cut crystal. Use of a series cut crystal may give a
OSC CONFIGURATION)
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/ Clock from OSC1
CLKIN pin (Figure 14-6). ext. system PIC16CXX
Open OSC2
MCLR
SLEEP
WDT WDT
Module Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset(2) S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q
OSC1
PWRT
On-chip(1)
RC OSC 10-bit Ripple counter
VDD
BVDD Max.
BVDD Min.
Internal
72 ms
Reset
VDD
BVDD Max.
BVDD Min.
Internal <72 ms
Reset 72 ms
VDD
BVDD Max.
BVDD Min.
Internal
72 ms
Reset
POR(1) TO PD
0 1 1 Power-on Reset
0 0 x Illegal, TO is set on POR
0 x 0 Illegal, PD is set on POR
1 0 1 WDT Reset
1 0 0 WDT Wake-up
1 u u MCLR Reset during normal operation
1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown
Note 1: Bit POR is not implemented on the PIC16C71.
TABLE 14-8: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C710/711/72/73A/74A
POR BOR TO PD
0 x 1 1 Power-on Reset
0 x 0 x Illegal, TO is set on POR
0 x x 0 Illegal, PD is set on POR
1 0 x x Brown-out Reset
1 1 0 1 WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Power-on Reset 000h 0001 1xxx ---- --0x ---- --0- ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu ---- --u- ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu ---- --u- ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu ---- --u- ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu ---- --u- ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0 N/A ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu ---- --u- ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded
with the interrupt vector (0004h).
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 14-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
D 10k MCLR
R
R1 40k
MCLR PIC16CXX
C PIC16CXX
VDD VDD
R1
Q1
MCLR
R2 40k
PIC16CXX
The interrupt control register (INTCON) records individ- For external interrupt events, such as the INT pin or
ual interrupt requests in flag bits. It also has individual PORTB change interrupt, the interrupt latency will be
and global interrupt enable bits. three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-
Note: Individual interrupt flag bits are set regard-
22). The latency is the same for one or two cycle
less of the status of their corresponding
instructions. Individual interrupt flag bits are set regard-
mask bit or the GIE bit.
less of the status of their corresponding mask bit or the
A global interrupt enable bit, GIE (INTCON<7>) GIE bit.
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an Note: For the PIC16C71/73/74
interrupt’s flag bit and mask bit are set, the interrupt will If an interrupt occurs while the Global Inter-
vector immediately. Individual interrupts can be dis- rupt Enable (GIE) bit is being cleared, the
abled through their corresponding enable bits in vari- GIE bit may unintentionally be re-enabled
ous registers. Individual interrupt bits are set by the user’s Interrupt Service Routine (the
regardless of the status of the GIE bit. The GIE bit is RETFIE instruction). The events that
cleared on reset. would cause this to occur are:
The “return from interrupt” instruction, RETFIE, exits 1. An instruction clears the GIE bit while
the interrupt routine as well as sets the GIE bit, which an interrupt is acknowledged.
re-enables interrupts. 2. The program branches to the Interrupt
The RB0/INT pin interrupt, the RB port change interrupt vector and executes the Interrupt Ser-
and the TMR0 overflow interrupt flags are contained in vice Routine.
the INTCON register. 3. The Interrupt Service Routine com-
The peripheral interrupt flags are contained in the spe- pletes with the execution of the RET-
cial function registers PIR1 and PIR2. The correspond- FIE instruction. This causes the GIE
ing interrupt enable bits are contained in special bit to be set (enables interrupts), and
function registers PIE1 and PIE2, and the peripheral the program returns to the instruction
interrupt enable bit is contained in special function reg- after the one which was meant to dis-
ister INTCON. able interrupts.
When an interrupt is responded to, the GIE bit is Perform the following to ensure that inter-
cleared to disable any further interrupt, the return rupts are globally disabled:
address is pushed onto the stack and the PC is loaded LOOP BCF INTCON, GIE ; Disable global
with 0004h. Once in the interrupt service routine the ; interrupt bit
source(s) of the interrupt can be determined by polling BTFSC INTCON, GIE ; Global interrupt
the interrupt flag bits. The interrupt flag bit(s) must be ; disabled?
GOTO LOOP ; NO, try again
cleared in software before re-enabling interrupts to
: ; Yes, continue
avoid recursive interrupts. ; with program
; flow
GIE
TMR1IF
Wake-up (If in SLEEP mode)
TMR1IE T0IF
T0IE
INTF
TMR2IF INTE
TMR2IE Interrupt to CPU
RBIF
RBIE
ADIF
ADIE
PEIE
GIE
CCP1IF
CCP1IE
SSPIF
SSPIE
TMR1IF
TMR1IE
TMR2IF Wake-up (If in SLEEP mode)
T0IF
TMR2IE T0IE
CCP1IF INTF
CCP1IE INTE
Interrupt to CPU
CCP2IF RBIF
CCP2IE RBIE
ADIF
ADIE
PEIE
TXIF
TXIE GIE
RCIF
RCIE
SSPIF
SSPIE
TMR1IF
TMR1IE
TMR2IF Wake-up (If in SLEEP mode)
T0IF
TMR2IE T0IE
CCP1IF INTF
CCP1IE INTE
Interrupt to CPU
CCP2IF RBIF
CCP2IE RBIE
ADIF
ADIE
PEIE
TXIF
TXIE GIE
RCIF
RCIE
SSPIF
SSPIE
PSPIF
PSPIE
CLKOUT 3
4
INT pin
1
1
INTF flag 5 Interrupt Latency 2
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h)
0
M Postscaler
1 U
WDT Timer
X 8
8 - to - 1 MUX PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 7-6)
0 1
MUX PSA
WDT
Note: PSA and PS2:PS0 are bits in the OPTION register. Time-out
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 14-1, Figure 14-2, Figure 14-3, and Figure 14-4 for operation of these bits.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction
fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
14.9 Program Verification/Code Protection The device is placed into a program/verify mode by
Applicable Devices holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
710 71 711 72 73 73A 74 74A
specification). RB6 becomes the programming clock
If the code protection bit(s) have not been pro- and RB7 becomes the programming data. Both RB6
grammed, the on-chip program memory can be read and RB7 are Schmitt Trigger inputs in this mode.
out for verification purposes.
After reset, to place the device into programming/verify
Note: Microchip does not recommend code pro- mode, the program counter (PC) is at location 00h. A 6-
tecting windowed devices. bit command is then supplied to the device. Depending
on the command, 14-bits of program data are then sup-
14.10 ID Locations plied to or from the device, depending if the command
Applicable Devices was a load or a read. For complete details of serial pro-
710 71 711 72 73 73A 74 74A gramming, please refer to the PIC16C6X/7X Program-
ming Specifications (Literature #DS30228).
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or FIGURE 14-26: TYPICAL IN-CIRCUIT SERIAL
other code-identification numbers. These locations are PROGRAMMING
not accessible during normal execution but are read- CONNECTION
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used. To Normal
Connections
External
14.11 In-Circuit Serial Programming Connector PIC16CXX
Signals
Applicable Devices
+5V VDD
710 71 711 72 73 73A 74 74A
0V VSS
PIC16CXX microcontrollers can be serially pro-
VPP MCLR/VPP
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three CLK RB6
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards Data I/O RB7
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm- VDD
ware to be programmed. To Normal
Connections
Table 15-2 lists the instructions recognized by the 15.1.2 PCL AS SOURCE OR DESTINATION
MPASM assembler.
Read, write or read-modify-write on PCL may have the
Figure 15-1 shows the three general formats that the following results:
instructions can have.
Read PC: PCL → dest
Note: To maintain upward compatibility with
Write PCL: PCLATH → PCH;
future PIC16CXX products, do not use the
8-bit destination value → PCL
OPTION and TRIS instructions.
Read-Modify-Write: PCL→ ALU operand
All examples use the following format to represent a
PCLATH → PCH;
hexadecimal number:
8-bit result → PCL
0xhh
Where PCH = program counter high byte (not an
where h signifies a hexadecimal digit. addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS 15.1.3 BIT MANIPULATION
Byte-oriented file register operations
13 8 7 6 0 All bit manipulation instructions are done by first read-
OPCODE d f (FILE #) ing the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
d = 0 for destination W
should keep this in mind when operating on special
d = 1 for destination f
f = 7-bit file register address function registers, such as ports.
Description: The contents of the W register are Description: The contents of W register are
added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The
result is placed in the W register. result is placed in the W register.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example ADDLW 0x15 Example ANDLW 0x5F
Words: 1 Cycles: 1
Before Instruction
W = 0x07
After Instruction
W = value of k8
Description: Return from subroutine. The stack is Encoding: 00 1100 dfff ffff
POPed and the top of the stack (TOS) Description: The contents of register 'f' are rotated
is loaded into the program counter. one bit to the right through the Carry
This is a two cycle instruction. Flag. If 'd' is 0 the result is placed in
Words: 1 the W register. If 'd' is 1 the result is
placed back in register 'f'.
Cycles: 2
C Register f
Example RETURN
After Interrupt Words: 1
PC = TOS
Cycles: 1
Example RRF REG1,0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 0111 0011
C = 0
Description: The contents of register 'f' are rotated Status Affected: TO, PD
one bit to the left through the Carry Encoding: 00 0000 0110 0011
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is Description: The power-down status bit, PD is
cleared. Time-out status bit, TO is
stored back in register 'f'.
set. Watchdog Timer and its pres-
C Register f caler are cleared.
The processor is put into SLEEP
Words: 1 mode with the oscillator stopped.
See Section 14.8 for more details.
Cycles: 1
Words: 1
Example RLF REG1,0
Cycles: 1
Before Instruction
REG1 = 1110 0110 Example: SLEEP
C = 0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1
Description: The W register is subtracted (2’s com- Encoding: 00 0010 dfff ffff
plement method) from the eight bit literal Description: Subtract (2’s complement method) W reg-
'k'. The result is placed in the W register. ister from register 'f'. If 'd' is 0 the result is
Words: 1 stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Cycles: 1
Words: 1
Example 1: SUBLW 0x02
Cycles: 1
Before Instruction
Example 1: SUBWF REG1,1
W = 1
C = ? Before Instruction
After Instruction REG1 = 3
W = 2
W = 1 C = ?
C = 1; result is positive
After Instruction
Example 2: Before Instruction
REG1 = 1
W = 2 W = 2
C = ? C = 1; result is positive
After Instruction Example 2: Before Instruction
W = 0 REG1 = 2
C = 1; result is zero W = 2
Example 3: Before Instruction C = ?
W = 3 After Instruction
C = ? REG1 = 0
After Instruction W = 2
C = 1; result is zero
W = 0xFF
C = 0; result is nega- Example 3: Before Instruction
tive REG1 = 1
W = 2
C = ?
After Instruction
REG1 = 0xFF
W = 2
C = 0; result is negative
Encoding: 00 1110 dfff ffff Description: The contents of the W register are
XOR’ed with the eight bit literal 'k'.
Description: The upper and lower nibbles of regis- The result is placed in the W regis-
ter 'f' are exchanged. If 'd' is 0 the ter.
result is placed in W register. If 'd' is 1
the result is placed in register 'f'.
Words: 1
Words: 1 Cycles: 1
DS30390D-page 158
PIC16C52, 54, 54A, SW007002 SW006005 SW006006 DV005001/ EM167015/ EM167201 DV007003 DV162003 DV003001
55, 56, 57, 58A DV005002 EM167101
PIC16C7X
Product TRUEGAUGE Development Kit SEEVAL Designers Kit Hopping Code Security Programmer Kit Hopping Code Security Eval/Demo Kit
All 2 wire and 3 wire N/A DV243001 N/A N/A
Serial EEPROM's
MTA11200B DV114001 N/A N/A N/A
HCS200, 300, 301 * N/A N/A PG306001 DM303001
DS30390D-page 160
PIC16C7X
IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V
HS Do not use in HS mode
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Preliminary
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 10 MHz max.
VDD: 4.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V
IDD: 52.5 µA typ. at 32 kHz, 4.0V IDD: 48 µA max. at 32 kHz, 3.0V IDD: 48 µA max. at 32 kHz, 3.0V
LP Do not use in LP mode Do not use in LP mode
IPD: 0.9 µA typ. at 4.0V IPD: 5.0 µA max. at 3.0V IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type
that ensures the specifications required.
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
VDD BVDD
35
TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 1 — — µs VDD = 5V, -40˚C to +125˚C
31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33 Tpwrt Power up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low — — 1.1 µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset pulse width 100 — — µs 3.8V ≤ VDD ≤ 4.2V
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
RA4/T0CKI
40 41
42
TMR0
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
NOTES:
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
15 pF for OSC2 output
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
11
10
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O Pins
TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 200 — — ns VDD = 5V, -40˚C to +85˚C
31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5V, -40˚C to +85˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period
33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +85˚C
34 TIOZ I/O High Impedance from MCLR — — 100 ns
Low
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
RA4/T0CKI
40 41
42
TMR0
Note: Refer to Figure 19-1 for load conditions.
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
The graphs and tables provided in this section are for R = 4.7k
4.5
design guidance and are not tested or guaranteed. In
some graphs or tables the data presented are out-
side specified operating range (e.g. outside speci- 4.0
fied VDD range). This is for information only and
devices are guaranteed to operate properly only 3.5
within the specified range.
The data presented in this section is a statistical sum- 3.0
mary of data collected on units from different lots over R = 10k
a period of time and matrix samples. 'Typical' repre- 2.5
sents the mean of the distribution while 'max' or 'min'
Fosc (MHz)
represents (mean + 3σ) and (mean - 3σ) respectively 2.0
where σ is standard deviation.
1.5
FIGURE 20-1: TYPICAL RC OSCILLATOR
Cext = 20 pF, T = 25°C
FREQUENCY VS.
1.0
TEMPERATURE
Fosc R = 100k
Fosc (25°C) 0.5
Frequency Normalized to 25°C
1.050
0.0
1.025 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Rext = 10k
Cext = 100 pF VDD (Volts)
1.000
FIGURE 20-3: TYPICAL RC OSCILLATOR
0.975 VDD = 5.5V
FREQUENCY VS. VDD
0.950
2.0
0.925 VDD = 3.5V
R = 3.3k
1.8
0.900
0.875 1.6
0.850 1.4
0 10 20 30 40 50 60 70 R = 4.7k
T(°C) 1.2
1.0
Fosc (MHz)
0.8
R = 10k
0.6
0.2 R = 100k
0.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
.1
R = 100k FIGURE 20-6: TYPICAL IPD VS. VDD
WATCHDOG TIMER ENABLED
0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 25°C
VDD (Volts)
14
FIGURE 20-5: TYPICAL IPD VS. VDD
WATCHDOG TIMER
DISABLED 25°C
12
0.6
10
0.5
IPD (µA)
0.4
6
IPD (µA)
0.3
4
0.2 2
0
0.1 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
0.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 20-7: MAXIMUM IPD VS. VDD FIGURE 20-8: MAXIMUM IPD VS. VDD
WATCHDOG DISABLED WATCHDOG ENABLED
45
25
-55°C
40 -40°C
125°C
35
20
30 125°C
25
15
IPD (µA)
20
IPD (µA)
0°C
15
10 70°C
Data based on matrix samples. See first page of this section for details.
85°C
10
85°C
70°C 5
5
0
0°C 3.0 3.5
4.0 4.5 5.0 5.5 6.0
-40°C VDD (Volts)
0 -55°C IPD, with Watchdog Timer enabled, has two components:
3.0 3.5 4.0 4.5 5.0 5.5 6.0 The leakage current which increases with higher tempera-
VDD (Volts) ture and the operating current of the Watchdog Timer logic
which increases with lower temperature. At -40°C, the latter
dominates explaining the apparently anomalous behavior.
FIGURE 20-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD
2.00
1.80
Max (-40˚C to 85˚C)
1.60
25˚C, TYP
1.40
VTH (Volts)
1.20
Min (-40˚C to 85˚C)
1.00
0.80
0.60
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 20-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD
3.00
VIH, VIL (Volts)
2.50
2.00
0.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Data based on matrix samples. See first page of this section for details.
FIGURE 20-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
VS. VDD
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (µA)
100
Data based on matrix samples. See first page of this section for details.
10
1
10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
FIGURE 20-13: MAXIMUM, IDD VS. FREQ (EXT CLOCK, -40° TO +85°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (µA)
100
10
10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
FIGURE 20-14: MAXIMUM IDD VS. FREQ WITH A/D OFF (EXT CLOCK, -55° TO +125°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (µA)
100
Data based on matrix samples. See first page of this section for details.
10
10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
FIGURE 20-15: WDT TIMER TIME-OUT FIGURE 20-16: TRANSCONDUCTANCE (gm)
PERIOD VS. VDD OF HS OSCILLATOR VS. VDD
9000
50
8000
45
7000
40 Max, -40°C
6000
35
gm (µA/V)
Max, 70°C
30 4000
Typ, 25°C
25 3000
20 Min, 85°C
Typ, 25°C 2000
Min, 0°C
15 1000
10 0
Min, -40°C 2 3 4 5 6 7
VDD (Volts)
5
2 3 4 5 6 7
VDD (Volts)
225
200 -5
Max, -40°C Min, 85°C
175
150
-10
Typ, 25°C
IOH (mA)
gm (µA/V)
125
Typ, 25°C
100 Min, 85°C -15
75
Data based on matrix samples. See first page of this section for details.
50 Max, -40°C
-20
25
0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 -25
VDD (Volts) 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
FIGURE 20-18: TRANSCONDUCTANCE (gm) FIGURE 20-20: IOH VS. VOH, VDD = 5V
OF XT OSCILLATOR VS. VDD
0
2500
-5
Max, -40°C
-10
2000
-15
IOH (mA)
-25
Typ @ 25°C
-30
1000
-35
-40
Min, 85°C Max @ -40°C
500
-45
-50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0 VOH (Volts)
2 3 4 5 6 7
VDD (Volts)
FIGURE 20-21: IOL VS. VOL, VDD = 3V FIGURE 20-22: IOL VS. VOL, VDD = 5V
35
90
Max @ -40°C
30 80
Max @ -40°C
70
25
Typ @ 25°C 60
Typ @ 25°C
20
IOL (mA)
IOL (mA)
50
15 Min @ +85°C
Min @ +85°C 40
10 30
20
5
Data based on matrix samples. See first page of this section for details.
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0
VOL (Volts) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL (Volts)
DS30390D-page 196
PIC16C7X
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
VDD BVDD
35
TABLE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40˚C to +125˚C
31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset pulse width 100 — — µs VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
RA4/T0CKI
40 41
42
RC0/T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
RC2/CCP1
(Capture Mode)
50 51
52
RC2/CCP1
(Compare or PWM Mode)
53 54
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
SDO
75, 76 77
SDI
74
73
SCL
91 93
90 92
SDA
START STOP
Condition Condition
SDA
Out
Note: Refer to Figure 21-1 for load conditions
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS30390D-page 214
PIC16C7X
IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V
HS Do not use in HS mode
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
VDD: 4.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V
IDD: 52.5 µA typ. at 32 kHz, 4.0V IDD: 48 µA max. at 32 kHz, 3.0V IDD: 48 µA max. at 32 kHz, 3.0V
LP Do not use in LP mode Do not use in LP mode
IPD: 0.9 µA typ. at 4.0V IPD: 13.5 µA max. at 3.0V IPD: 13.5 µA max. at 3.0V
Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type
that ensures the specifications required.
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C73.
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
FIGURE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
TABLE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40˚C to +85˚C
31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5V, -40˚C to +85˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33 Tpwrt Power up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +85˚C
34 TIOZ I/O Hi-impedance from MCLR Low — — 100 ns
or Watchdog Timer Reset
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
RA4/T0CKI
40 41
42
RC0/T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50 51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53 54
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 22-1 for load conditions
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
SDO
75, 76 77
SDI
74
73
SCL
91 93
90 92
SDA
START STOP
Condition Condition
SDA
Out
Note: Refer to Figure 22-1 for load conditions
RC6/TX/CK
pin 121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 22-1 for load conditions
RC6/TX/CK
pin 125
RC7/RX/DT
pin
126
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
NOTES:
DS30390D-page 236
PIC16C7X
IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V IDD: 20 mA max. at 5.5V
HS Do not use in HS mode
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V
IDD: 52.5 µA typ. at 32 kHz, 4.0V IDD: 48 µA max. at 32 kHz, 3.0V IDD: 48 µA max. at 32 kHz, 3.0V
LP Do not use in LP mode Do not use in LP mode
IPD: 0.9 µA typ. at 4.0V IPD: 5.0 µA max. at 3.0V IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device
type that ensures the specifications required.
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as coming out of the pin.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as coming out of the pin.
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C73A.
OSC1
1 3 3 4 4
2
CLKOUT
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
FIGURE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
VDD BVDD
35
TABLE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40˚C to +125˚C
31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C
34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 µs
or Watchdog Timer Reset
35 TBOR Brown-out Reset pulse width 100 — — µs VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
RA4/T0CKI
40 41
42
RC0/T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50 51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53 54
PIC16LC73A/74A 25 45 ns
54* TccF CCP1 and CCP2 output fall time PIC16C73A/74A 10 25 ns
PIC16LC73A/74A 25 45 ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 23-1 for load conditions
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
SDO
75, 76 77
SDI
74
73
SCL
91 93
90 92
SDA
START STOP
Condition Condition
SDA
Out
Note: Refer to Figure 23-1 for load conditions
RC6/TX/CK
pin 121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 23-1 for load conditions
RC6/TX/CK
pin 125
RC7/RX/DT
pin
126
A/D DATA 7 6 5 4 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
NOTES:
30
25
20
IPD(nA)
15
10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
85°C
70°C
1.000
IPD(µA)
0.100 25°C
0°C
-40°C
0.010
0.001
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
Fosc(MHz)
IPD(µA)
15
3.5
3.0
10 R = 10k
2.5
2.0
5
1.5
1.0
0 R = 100k
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5
VDD(Volts) 0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
35
-40°C
FREQUENCY vs. VDD
30 Cext = 100 pF, T = 25°C
0°C 2.4
25 2.2
R = 3.3k
2.0
IPD(µA)
20 1.8
70°C 1.6
Fosc(MHz)
15 R = 5k
1.4
85°C 1.2
10
1.0
R = 10k
5 0.8
0.6
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.4
R = 100k
VDD(Volts) 0.2
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
600
R = 5k
500
400
R = 10k
300
200
100 R = 100k
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(Volts)
1200 30
1000
25
IPD(µA)
IPD(µA)
400 Device in 15
Brown-out
200 Reset 10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5
VDD(Volts)
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
The shaded region represents the built-in hysteresis of the
Data based on matrix samples. See first page of this section for details.
VDD(Volts)
brown-out reset circuitry.
1400
1200 45
1000 40
Device NOT in
IPD(µA)
35
800 Brown-out Reset
30
600 Device in
25
IPD(µA)
Brown-out
400 Reset 20
200 15
4.3 10
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5
VDD(Volts)
0
The shaded region represents the built-in hysteresis of the 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
brown-out reset circuitry. VDD(Volts)
FIGURE 24-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C)
2000
6.0V
1800 5.5V
5.0V
1600
4.5V
1400
4.0V
1200
IDD(µA)
3.5V
1000 3.0V
800
2.5V
600
400
200
Data based on matrix samples. See first page of this section for details.
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
Shaded area is
beyond recommended range
FIGURE 24-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C)
2000 6.0V
1800 5.5V
5.0V
1600
4.5V
1400
4.0V
1200
IDD(µA)
3.5V
1000 3.0V
800
2.5V
600
400
200
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Frequency(MHz)
Shaded area is
beyond recommended range
FIGURE 24-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C)
1600
6.0V
1400 5.5V
5.0V
1200 4.5V
4.0V
1000
3.5V
IDD(µA)
3.0V
800
2.5V
600
Data based on matrix samples. See first page of this section for details.
400
200
0
0 200 400 600 800 1000 1200 1400 1600 1800
Frequency(kHz)
FIGURE 24-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C)
1600
6.0V
1400 5.5V
5.0V
1200 4.5V
4.0V
1000
3.5V
IDD(µA)
3.0V
800
2.5V
600
400
200
0
0 200 400 600 800 1000 1200 1400 1600 1800
Frequency(kHz)
FIGURE 24-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C)
1200
6.0V
5.5V
1000 5.0V
4.5V
4.0V
800
3.5V
3.0V
IDD(µA)
600
2.5V
400
Data based on matrix samples. See first page of this section for details.
200
0
0 100 200 300 400 500 600 700
Frequency(kHz)
FIGURE 24-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C)
1200
6.0V
5.5V
1000 5.0V
4.5V
4.0V
800
3.5V
3.0V
IDD(µA)
600
2.5V
400
200
0
0 100 200 300 400 500 600 700
Frequency(kHz)
gm(mA/V)
IDD(µA)
3.0V
300 2.0
0 0.0
20 pF 100 pF 300 pF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Data based on matrix samples. See first page of this section for details.
Capacitance(pF) VDD(Volts)
70
3.0
60
2.5
Startup Time(Seconds)
50
Startup Time(ms)
2.0
40
32 kHz, 33 pF/33 pF 200 kHz, 68 pF/68 pF
1.5 30
200 kHz, 47 pF/47 pF
20
1.0 1 MHz, 15 pF/15 pF
10 4 MHz, 15 pF/15 pF
0.5 200 kHz, 15 pF/15 pF
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0 VDD(Volts)
Data based on matrix samples. See first page of this section for details.
1600 6.0V
120
1400 5.5V
100
5.0V
1200
80 4.5V
1000
IDD(µA)
4.0V
60
6.0V 3.5V
800
5.5V
IDD(µA)
40 5.0V 3.0V
4.5V 600
4.0V 2.5V
20 3.5V
3.0V 400
2.5V
0
0 50 100 150 200 200
Data based on matrix samples. See first page of this section for details.
Frequency(kHz)
0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
FIGURE 24-26: MAXIMUM IDD vs. FIGURE 24-28: MAXIMUM IDD vs.
FREQUENCY FREQUENCY
(LP MODE, 85°C TO -40°C) (XT MODE, -40°C TO 85°C)
1800
6.0V
140 1600
5.5V
120 1400
5.0V
80 1000 4.0V
IDD(µA)
5.5V 3.0V
5.0V
40 4.5V 600 2.5V
4.0V
3.5V
20 3.0V
400
2.5V
0 200
0 50 100 150 200
Frequency(kHz) 0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Frequency(MHz)
4.0
IDD(mA)
3.0
3.0
2.0 6.0V
5.5V
5.0V 2.0 6.0V
1.0 4.5V 5.5V
4.0V 5.0V
1.0 4.5V
0.0 4.0V
1 2 4 6 8 10 12 14 16 18 20
0.0
Frequency(MHz) 1 2 4 6 8 10 12 14 16 18 20
Frequency(MHz)
Data based on matrix samples. See first page of this section for details.
α C
E1 E
eA
Pin No. 1 eB
Indicator
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A3 A A2
B
D1
C
E1 E
eA
Pin #1 α eB
Indicator Area
D
S1
S
Base
Plane
Seating A3 A2
Plane L
A1 A
B1 e1
B
D1
E1 E
α C
Pin No. 1
Indicator eA
Area eB
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A3 A A2
B
D1
N
α
C
E1 E
eA
Pin No. 1 eB
Indicator
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A2 A
B
D1
E1 E α
C
Pin No. 1 eA
Indicator eB
Area
B2 B1
D
S
Base
Plane
Seating
Plane L
Detail A B3 B
e1 A1 A2 A
D1 Detail A
α
E1 E C
Pin No. 1 eA
Indicator eB
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A2 A
B
D1
e
B
h x 45°
Index
Area
E H α C
Chamfer L
h x 45°
1 2 3
CP Base
Seating Plane
Plane
A1 A
e
B
h x 45°
Index
Area
E H α C
Chamfer L
h x 45°
1 2 3
CP Base
Seating Plane
Plane
A1 A
N
Index
area
E H
α
C
L
1 2 3
e B
A Base plane
CP
Seating plane
D A1
N
Index
area
E H
α
C
L
1 2 3
e B
A Base plane
CP
Seating plane
D A1
D 0.812/0.661 N Pics
0.177 1.27 .032/.026
.007 S B D-E S .050
2 Sides -H- 0.177
-A- .007 S B A S
D1 A
A1 2 Sides
-D- 3 9
D3/E3
0.101 Seating
D2 D
.004 Plane
0.38 -C-
3 .015 F-G S 4
3 -G-
8 E2
-F-
E1 E
0.38
.015 F-G S 4
-B-
3 -E- 0.177
.007 S A F-G S
10
0.812/0.661
0.254 0.254 3
.032/.026
.010 Max 11 .010 Max 11
1.524
0.508 0.508
2 -H- .060 Min
.020 .020 -H- 2
6
6
-C-
5
1.651 1.651 0.64 Min 0.533/0.331
.065 .065 .025 .021/.013
R 1.14/0.64 R 1.14/0.64
.045/.025 .045/.025 0.177
, D-E S
.007 M A F-G S
0.20 M C A-B S D S
4 D
0.20 M H A-B S D S
D1 5 7
0.05 mm/mm A-B 0.20 min.
D3
0.13 R min.
Index
area 6 PARTING
LINE
0.13/0.30 R
9
b α
L
C
E3 E1 E
1.60 Ref.
0.20 M C A-B S D S
4
TYP 4x
10
0.20 M H A-B S D S
e B 5 7
0.05 mm/mm D
A2 A
Base
Plane Seating
Plane
A1
11°/13°(4x)
Pin#1 Pin#1
2 2 0° Min
E E1
Θ
11°/13°(4x)
Detail B
e
3.0ø (0.118ø) Ref. R1 0.08 Min
Option 1 (TOP side) R 0.08/0.20
Option 2 (TOP side)
Gage Plane
A1 0.250
Base Metal Lead Finish
A2 A b S
L 0.20
L Min
Detail A c c1 L1
Detail B
1.00 Ref. 1.00 Ref
b1
Detail A Detail B
MMMMMMMMMMMMM PIC16C71-04/P
XXXXXXXXXXXXXXXX
AABBCDE 9452CBA
MMMMMM PIC16C71
XXXXXXXX /JW
AABBCDE 945/CBT
AABBCAE 9517SBP
AABBCAE 9517SBP
Note: In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
MMMMMMMMMMMMMMMM PIC16C73-10/SO
XXXXXXXXXXXXXXXXXXXX
AABBCDE 945/CAA
MMMMMMMMM PIC16C74/JW
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE AABBCDE
MMMMMMMM PIC16C74
XXXXXXXXXX -10/L
XXXXXXXXXX
AABBCDE AABBCDE
MMMMMMMM PIC16C74
XXXXXXXXXX -10/PQ
XXXXXXXXXX
AABBCDE AABBCDE
MMMMMMMM PIC16C74A
XXXXXXXXXX -10/TQ
XXXXXXXXXX
AABBCDE AABBCDE
R ta m ri op ig lta -C di at ck
ax EP Da Ti Se Sl (h In
te /O P
I Vo
M In Ad Fe Pa
Internal Oscillator,
Bandgap Reference,
Temperature Sensor,
Calibration Factors,
TMR0 I2C/ 28-pin DIP, SOIC, SSOP
PIC14000 20 4K 192 14 11 22 2.7-6.0 Yes Low Voltage Detector,
DS30390D-page 285
PIC16C7X
E.2
DS30390D-page 286
)
Hz
( M
PIC16C7X
ion
s) y
at
rd or
p er
wo em
s)
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12 M
s
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of
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cti
en
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)
(V
qu
(s
str
em
e
le
In
M
ng
u
PIC16C5X Family of Devices
Fr
es
of
a
od
Ra
r
at
ag
um
M
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ns
k
D
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Pi
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M
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PIC16C52 4 384 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC
PIC16C54 20 512 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C54A 20 512 — 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR54A 20 — 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C55 20 512 — 24 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16C56 20 1K — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C57 20 2K — 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16CR57B 20 — 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16C58A 20 2K — 73 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR58A 20 — 2K 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
H z) y
(M or
n em s)
tio M rd ge
ra o
pe r o lta )
O am 4 w
V ts
of og x1 s) e ol
y te
PIC16CXXX Family of Devices
nc Pr ( by nc s (V
e ( ( s) e ce e et
qu r y le ( s) f er ur g es
e o u o r o an R
Fr od at Re tS R ut es
M em M ar al up ns -o
um O M r p r n r r ge n k ag
im R ta e m te Pi lt a c
ax P a i m o n n te / O ow
M E D T C I I I Vo Br Pa
PIC16C554 20 512 80 TMR0 — — 3 13 2.5-6.0 — 18-pin DIP, SOIC; 20-pin SSOP
PIC16C556 20 1K 80 TMR0 — — 3 13 2.5-6.0 — 18-pin DIP, SOIC; 20-pin SSOP
PIC16C558 20 2K 128 TMR0 — — 3 13 2.5-6.0 — 18-pin DIP, SOIC; 20-pin SSOP
PIC16C620 20 512 80 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
PIC16C621 20 1K 80 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
PIC16C622 20 2K 128 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30390D-page 287
PIC16C7X
E.4
H z) y s) (
(M or le T)
on e m )
s o du g
t i M d AR in
a r M S m
DS30390D-page 288
e r m o U m
p a w M , ) a
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of t es /P I /I r t ol ro
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PIC16C7X
ue y le pa )( e rc ge ria es
e q o r u o m s v u n e R
Fr rt( la So a
em od /C lS R tS ut es
um M M r M re l Po l e u pt ins g e c ui n -o ag
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R t m p r r te l - C o c
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M
PIC16C62 20 2K — 128 TMR0, 1 SPI/I2C — 7 22 3.0-6.0 Yes — 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C6X Family of Devices
PIC16C62A(1) 20 2K — 128 TMR0, 1 SPI/I2C — 7 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16CR62(1) 20 — 2K 128 TMR0, 1 SPI/I2C — 7 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C63 20 4K — 192 TMR0, 2 SPI/I2C, — 10 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16CR63(1) 20 — 4K 192 TMR0, 2 SPI/I2C, — 10 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C64 20 2K — 128 TMR0, 1 SPI/I2C Yes 8 33 3.0-6.0 Yes — 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP
PIC16C64A(1) 20 2K — 128 TMR0, 1 SPI/I2C Yes 8 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP, TQFP
PIC16CR64(1) 20 — 2K 128 TMR0, 1 SPI/I2C Yes 8 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP, TQFP
PIC16C65 20 4K — 192 TMR0, 2 SPI/I2C, Yes 11 33 3.0-6.0 Yes — 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP
PIC16C65A(1) 20 4K — 192 TMR0, 2 SPI/I2C, Yes 11 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP, TQFP
PIC16CR65(1) 20 — 4K 192 TMR0, 2 SPI/I2C, Yes 11 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP, TQFP
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability.
All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
ta m pt r ra D te lt ow c
ax EP Da Ti Se Pa A/ In I/O Vo -C Pa
M Ca In Br
PIC16C710 20 512 36 TMR0 — — — 4 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC;
20-pin SSOP
PIC16C71 20 1K 36 TMR0 — — — 4 4 13 3.0-6.0 Yes — 18-pin DIP, SOIC
PIC16C711 20 1K 68 TMR0 — — — 4 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC;
20-pin SSOP
PIC16C72 20 2K 128 TMR0, 1 SPI/I2C — 5 8 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C73 20 4K 192 TMR0, 2 SPI/I2C, — 5 11 22 3.0-6.0 Yes — 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C73A(1) 20 4K 192 TMR0, 2 SPI/I2C, — 5 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C74 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 3.0-6.0 Yes — 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP
PIC16C74A(1) 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP, TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability.
All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
DS30390D-page 289
PIC16C7X
E.6
DS30390D-page 290
PIC16C7X
tio em
ra M
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PIC16C84 10 — 1K — 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16F84(1) 10 1K — — 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16CR84(1) 10 — — 1K 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16F83(1) 10 512 — — 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16CR83(1) 10 — — 512 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and
high I/O current capability.
All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
Hz) y )
or (s
(M u le T) ls
i on em R ne g
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PIC16C9XX Family Of Devices
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e ui -o ge
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ax m D te pu -C ow
M EP Da Ti Ca Se Pa A/ LC In I/O In Vo In Br Pa
PIC16C923 8 4K 176 TMR0, 1 SPI/I2C — — 4 Com 8 25 27 3.0-6.0 Yes — 64-pin SDIP(1), TQFP,
TMR1, TMR2 32 Seg 68-pin PLCC, DIE
PIC16C924 8 4K 176 TMR0, 1 SPI/I2C — 5 4 Com 9 25 27 3.0-6.0 Yes —
64-pin SDIP(1), TQFP,
TMR1, TMR2 32 Seg 68-pin PLCC, DIE
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip representative for availability of this package.
DS30390D-page 291
PIC16C7X
E.8
DS30390D-page 292
Clock Memory Peripherals Features
PIC16C7X
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PIC16C55, 28-pin
PIC16C57, PIC16CR57B
From: Name
Company
Address
City / State / ZIP / Country
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* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
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