1

Digital Logic Design

Computers, and other digital systems, are designed using elementary electronic circuits called gates. In this
article, Inverters, Or gates, and And gates are introduced by logical statements justifying the term "logic
design." Then, the design procedure is illustrated, and integrated circuits are discussed.
Gates
Gates are used to regulate electronic flow and to construct devices to process data, as well as to build memory
devices. There are three fundamental gates—"And," "Or," and "Not"—as well as some "hybrid" gates such as
"Nand" (Not-And) and "Nor" (Not-Or).
Not
Consider the logical statement: "The porch light is on (Z 1) when I am not home (A 0)." Z is the output; A is the
input (I am home). A corresponding binary function, of one variable, which is also binary, is called
"Complement" or "Not." "Not" is represented by "Z ~A" and its behavior is:
A Not-A (Z)
0 1 1 0
The electronic implementation of Not is the inverter, a one-transistor current amplifier with one input and one
output. A high (binary-1) input voltage, typically about 5 Volts, forces current into the amplifier's input. So, the
amplifier draws current from its output, pulling its output voltage low (binary-0), typically, close to 0 Volts. A 1
or high input gives a 0 output (the complement of the input). Since a low input voltage provides no current to
the amplifier's input, the amplifier draws no current from its output, causing a high voltage there. A low or 0
input gives a 1 output. The output is the opposite or complement (Not) of the input.
Or
Consider the logical statement: "I wear a jacket (Z 1) if it is cold (A 1) or if it rains (B 1) or…" A corresponding
binary function, of two or more binary variables, is called "Or." The behavior of "Or" is tabulated for two and
three variables:
AB Or ABC Or
00 0 000 0
01 1 001 1
10 1 010 1
11 1 011 1
100 1
101 1
110 1
111 1
One or the other or both (or "all" three) of the inputs "on" cause the output to be true. A Nor gate is like an
inverter, but with N input terminals instead of one. A high input voltage on any of the inputs causes a low
output voltage and a low voltage on all inputs causes a high output voltage. Since "Nor" is the complement of
"Or," "Or" is implemented in electronics by a "Nor-Not" tandem. "Not-Nor" or "OR." But, "Nor" has another
application.
Consider a pair of two-input "Nor" gates, and let the output of each gate be one of the other gate's inputs. Label
the unused inputs as S and R, and assume both these inputs are low. A positive pulse on S causes the
corresponding "Nor" gate's output to go low. Since both inputs to the other gate are low, its output is high. The
pair of gates remains in this state even after the pulse on S returns to 0. A positive pulse on R causes the output
of R's "Nor" gate to go low. Since both inputs to S's gate are low, its output is high. The pair of gates now
remains in this opposite state even after the pulse on R returns to 0. This pair of cross-connected "Nor" gates is
called a "Set-Reset Flip-Flop" and it is the basic binary storage element used throughout digital design. The
memory element is a 1 if S (Set) is 1, 0 if S is 0, or, what is the same, R (Reset) is 1.
And
Consider the logical statement: "I wear a hat (Z = 1) when it is cold (A = 1) and when it is raining (B = 1)
and…" A corresponding binary functionof two or more binary variables is called "And." The behavior of "And"
is tabulated for two and three variables:
 2
AB And ABC And
00 0 000 0
01 0 001 0
10 0 010 0
11 1 011 0
100 0
101 0
110 0
111 1
All inputs must be on for the output to be on.
Like a "Nor" gate, a "Nand gate" also has N input terminals and one output terminal. But, "Nand" is more
complicated than "Nor," because a low output voltage is caused by a high voltage on all the inputs, and the
output voltage is high if any of the input voltages is low. "And" is implemented in electronics by a "Nand-Not"
tandem. Again, "Not-Nand," or "Not-Not-And," hence, "And."
Design Example
Consider a binary circuit, with output X and three inputs. D and E are separate streams of binary data, and C is a
control signal so that X D when C 0 and X E when C 1. That is, the output is equal to D when C is 0, and equals
E when C is 1. C controls the output. This Binary Multiplexor's behavior is tabulated:
CDE X
000 0
001 0
010 1
011 1
100 0
101 1
110 0
111 1
Compare the output to D's value when C is 0; compare the output to E's value when C is 1. In the first four rows
of the table, X D because C 0. In the last four rows, X E because C 1. The device is called a multiplexor because
it switches ("multiplexes") between the data streams D and E under the control of C. It is a "binary multiplexor"
because it switches between or "multiplexes" among two devices, D and E. It takes turns servicing them under
the control of C. Consider two approaches for implementing this function.
Canonic And-Or Implementation.
Any binary function can be implemented in three layers of logic: (1) a layer of inverters that provides the
complement of each input if it is needed; (2) a layer with K different N-input "And" gates where the circuit has
N inputs and the circuit's output function has K one-points (one outputs); and (3) one K-input Or gate. Since the
multiplexor's output function, X, has four one-points, the canonic "And-Or"implementation has four "And"
gates, each with three inputs. The different "And" gates' inputs are appropriately inverted so each gate identifies
a different one-point (one in the output). For example, an "And" gate whose inputs are ~C, D, and ~E has a 1-
output when CDE 010. A four-input "Or" gate, with an input from each "And" gate, provides the circuit's
output. This would be (~C,D,~E) (or) (~C,D,E) (or) (C,~D,E) (or) (C,D,E) for the four one-points (one outputs)
given.
Based on the Logical Description.
We can design the multiplexor in an ad-hoc manner from its logical description. If the inputs to a two-input
"And" gate are ~C and D, this gate's output equals D when C equals 0, and is 0 when C equals 1. If the inputs to
another two-input "And" gate are C and E, this gate's output equals E when C equals 1, and equal 0 when C
equals 0. The "Or" of these two "And" gates gives X. That is, the output is D (equal to D) when C is off (~C or
C 0), the output equals E when C is on.
Obviously this second implementation, with only two two-input "And"-gates and one two-input "Or"-gate, is
less expensive than the first. This is one of the issues in design. Cost, a complex issue, is illustrated next.
 3
Integrated Circuits
Integration is the manufacture of more than one gate, an entire binary circuit, or even a whole system, on the
same silicon chip. Transistorized gates and flip-flops were made in the 1950s from discrete resistors and
transistors. Then, they were integrated onto a single chip, called a "small-scale" integrated circuit (IC). Often, a
chip's complexity is limited by the package's pin-outs. The "7400 series" of integrated circuits, introduced in the
late 1960s, is still used today. If a part is popular, its per-chip overhead is small. Then, its price covers only the
cost of materials and manufacturing— about $3 (in quantity). Allowing pins for common battery and ground, a
14-pin package has the following limits:
Max# $/gate
(12÷pins/gate)
($3÷ # of
(14 – 2, battery
gates)
and ground, =
Part#Description Pins/gate
12)
7404 Inverter 2 Hex (6) .50
2-input
7400 3 Quad(4) .75
Nand
3-input
7410 4 Triple(3) 1.00
Nand
4-input
7420 5 Dual(2) 1.50
Nand
As chip manufacturers placed more logic circuits on a single chip of silicon, integration proceeded through
three subsequent scales of fabrication. Simple binary functions are fabricated on a single chip with up to 100
transistors on a chip, in what has come to be called "Medium Scale Integration." For example, the Quad Set-
Reset Flip-Flop is a useful digital integrated circuit (IC). But, when fitting four SR-FFs within the pin
constraints of a 14-pin DIP (Dual In-Line Package), each SR-FF gets only three pins (14 2 (for battery and
ground) 12; 12 / 4 (Quad) FF's 3 pins per SR flip-flop, 2 inputs, 1 output) and only one of each flip-flop's
outputs is connected to a pin (the S or the R but not both).
More complicated digital circuits, such as binary counters and shift registers, are fabricated with many hundreds
of transistors on a chip in "LargeScale Integration." Finally, modern digital circuits—like 16-and 32-bit CPUs
and memory chips with vast amounts of binary storage—are fabricated with thousands of transistors on a chip
in "Very Large Scale Integration" (VLSI).
1) Routers operate at which layer of the OSI model?

a) physical
b) transport
c) (your answer) network - correct answer
d) MAC sublayer of the data link layer
2) Bits are packaged into frames at which layer of the OSI model?

a) data link - correct answer

b) transport
c) physical
d) presentation
e) application
3) Which of the following are benefits of using a layered network model?

a) it facilitates troubleshooting
 4
b) it breaks the complex process of networking into more manageable chunks
c) it allows layers developed by different vendors to interoperate.
d) all of the above - correct answer
4) The layers of the OSI model, from the top down, are:

a)application, presentation, session, transport, network, data link, physical - correct answer
b) session, presentation, data transport, MAC, network, physical
c) physical, data link, network, transport, session, presentation, application
d) application, encryption, network, transport, logical link control, physical
5) Which of the following operate at the presentation layer?

a) FTP and HTTP

b) SMTP
c) UDP
d) (your answer) midi and jpeg - correct answer
e) all of the above
6) Which of the following are transport layer protocols?

a) TCP and UDP - correct answer

b) ATM
c) CISC
d) HTTP and FTP
7) Which of the following are considered to be the upper layer protocols?

a) presentation and session

b) application and presentation
c) (your answer) application, presentation, and session - correct answer
d) application, presentation, session, and transport
e) application
8) Flow control takes place at which layer?

a) physical
b) Network
c) transport - correct answer
d) data link
e) application
9) Encryption takes place at which layer?

a) physical
b) presentation - correct answer
c) application
d) session
e) data link
 5
10) The network layer uses physical addresses to route data to destination hosts.

a) True
b) False - correct answer
11) Error detection and recovery takes place at which layer?

a) transport - correct answer

b) presentation
c) data link
d) netwrok
e) application
12) Which layer establishes, maintains, and terminates communications between applications located on different devices?

a) application
b) session - correct answer
c) transport
d) netwrok
e) data link
13) IP is implemented at which OSI model layer?

a) transport
b) network - correct answer
c) data link
d) presentation
e) session
14) Which layer handles the formatting of application data so that it will be readable by the destination system?

a) application
b) presentation - correct answer
c) transport
d) netwrok
e) data link
15) Packets are found at which layer?

a) data link
b) trasnport
c) network - correct answer
d) presentation
e) session

16) Which layer translates between physical (MAC) and logical addresses?

a) network - correct answer

b) data link
 6
c) transport
d) presentation
e) application
17) What does OSI stand for?

a) Organization Standards International

b) Open Systems Interconnect - correct answer
c) Operating Standard Information
d) (your answer) Operating System Interconnection
e) Open Systems Interface
18) Repeaters and hubs operate at which layer?

a) network
b) physical - correct answer
c) transport
d) data link
e) presentation
19) Bit synchronization is handled at which layer?

a) physical - correct answer

b) network
c) physical
d) data link
e) presentation
20) Most logical addresses are preset in network interface cards at the factory

a) True
b) False - correct answer
21) Bridges operate at which layer of the OSI model?

a) physical
b) data link - correct answer
c) network
d) transport
e) presentation
22) What are the sublayers of the data link layer?

a) MAC and IPX

b) hardware and frame
c) (your answer) MAC and LLC - correct answer
d) WAN and LAN
e) Mac address
23) Which layer translates between physical and logical addresses?
 7
a) the MAC sublayer of the data link layer
b) transport
c) physical
d) network - correct answer
e) presentation
24) Which layer is responsible for packet sequencing, acknowledgments, and requests for retransmission?

a) network
b) session
c) transport - correct answer
d) data link
e) presentation

• A stack is generally First In, Last Out, and a queue is First In First Out.
• Item can be added or removed only at one end in stack and in a queue insertion at the rear and deletion
from the front.
• The basic operation of stack are 'push' and 'pop', on other hand of queue are 'enque' and 'dequeue'.

A Stack is a (ordered) collection of items, where all insertions are made to the end of the sequence and all deletions
always are made from the end of the sequence. In principle a stack is a container of data items, from which we get
data items out in reverse order compared to the order they have been put into the container. We can also said that
the item that has been put last in is coming first out. That’s why a stack is also called LIFO ((Last In First Out list). We
can as well say that the item, which is put first in the container is get last out (First In Last Out: FILO).

A Queue is a (ordered) collection of items , where all insertions are made to the end of the sequence and all deletions
always are made from the beginning of the sequence. In principle a queue is container from which data items are
retrieved out in the same order they are put in. This means that the queue is a container that preserves the order of
items put there. We can also say that the item that is put last into the queue is taken last out from the queue. That’s
why a queue is sometimes called LILO (Last In Last Out list). We can also say that the item which is put first into the
queue is taken first out. (First In First Out: FIFO).