Class Notes Digital Lec22

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Ref. No............................ August 22, 2010

Dated, the………………………….
T Flip-Flop:
Q T Qn Qn+1 1 J Q
↑ 0 1
T FF
↑ 1 0 T CLK FF
K Q
Fig.: T flip-flop – logic symbol, truth table and implementation from J-K FF.
The output of a toggle flip-flop, also called a T flip-flop, changes state every time it is triggered at its T input, called
the toggle input. That is, the output becomes 1 if it was 0 and 0 if it was 1.
When both J and K inputs of the J-K flip-flop are tied to their active level, the flip-flop behaves like a toggle flip-flop,
with its clock input serving as the T input.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]
Asynchronous Inputs:
Most flip-flops have both synchronous and asynchronous inputs.
Synchronous inputs are those whose effect on the flip-flop output is synchronized with the clock input. R, S, J, K and
D inputs are all synchronous inputs.
Asynchronous inputs are those that operate independently of the synchronous inputs and the input clock signal.
These are in fact override inputs as their status overrides the status of all synchronous inputs and also the clock
input. They force the flip-flop output to go to a predefined state irrespective of the logic status of the synchronous
inputs.
PRESET
J
1 3 Q
CLK
2 4 Q
K
PRESET
CLEAR
J Q
CLK
PRESET CLEAR FF response
1 1 Clocked operation*
K Q 0 1 Q=1 (regardless of CLK)
1 0 Q=0 (regardless of CLK)
0 0 Not used
CLEAR
*Q will respond to J, K and CLK
Fig.: Clocked J-K flip-flop with asynchronous inputs.
Lec-22, Pg-01 In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)
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Dated, the………………………….
Figure shows a J-K flip-flop with two asynchronous inputs designated as PRESET and CLEAR . Their effects can
be examined as –
(1) PRESET = CLEAR =1. The asynchronous inputs are inactive and the FF is free to respond to the J, K and
CLK inputs.
(2) PRESET =0, CLEAR =1. The PRESET is activated and Q is immediately set to 1 no matter what
conditions are present at the J, K and CLK inputs.
(3) PRESET =1, CLEAR =0. The CLEAR is activated and Q is immediately cleared to 0 independent of the
conditions on the J, K or CLK inputs.
(4) PRESET = CLEAR =0. This conditions should not be used, since it can result in an ambiguous response.
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]
Master/Slave Flip-Flops:
Whenever the width of the pulse clocking the flip-flop is greater than the propagation delay of the flip-flop, the change
in state at the output is not reliable. This phenomenon is referred to as the race problem.
In the case of edge-triggered flip-flops, this pulse width would be the trigger pulse width generated by the edge
detector portion of the flip-flop and not the pulse width of the input clock signal.
J Q J Q
Master Slave
CLK FF CLK FF
K Q K Q
Fig.: Master-slave flip-flop.

One way to get over this problem is to use a master-slave configuration as shown in the figure that is constructed
with two J-K flip-flops. The first flip-flop is called the master flip-flop and the second is called the slave.
The clock to the slave flip-flop is the complement of the clock to the master flip-flop. When the clock pulse is present,
the master flip-flop is enabled while the slave flip-flop is disabled. As a result, the master flip-flop can change state
while the slave flip-flop cannot.
When the clock goes LOW, the master flip-flop gets disabled while the slave flip-flop is enabled. Therefore, the slave
J-K flip-flop changes state as per the logic states at its J and K inputs.
The contents of the master flip-flop are therefore transferred to the slave flip-flop, and the master flip-flop, being
disabled, can acquire new inputs without affecting the output.
A master-slave flip-flop, therefore, is a pulse-triggered flip-flop and not an edge-triggered one.
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Ref. No............................ August 22, 2010

Dated, the………………………….
Switch Debouncing:
+V
+V
Switch
2
1
0
Bounce
Fig.: Switch bounce phenomenon.
Owing to the switch bounce phenomenon, the mechanical switch cannot be used as such to produce a clean voltage
transition. When the switch is moved from position 1 to position 2, what is desired at the output is a clean voltage
transition from 0 to +V volts. But the output makes several transitions between 0 and +V volts for a few milliseconds
owing to contact bounce before it finally settles at +V volts.
Similarly, when it is moved from position 2 back to position 1, it makes several transitions before coming to rest at 0V.
+V +V
Switch +V 0
2
1
Switch Switch
moved moved
from Pos-1 from Pos-2
to Pos-2 to Pos-1
Fig.: Switch debounce circuit.
A NAND or a NOR latch can solve this problem and provide a clean output transition. When the switch is in position
1, the output is at a 0 level. When it is moved to position 2, the output goes to a 1 level within a few nanoseconds
after its first contact with position 2. When the switch contact bounces, it makes and breaks contact with position 2
before it finally settles at the intended position. Making of contact always leads to a 1 level at the output, and breaking
of contact also leads to a 1 level at the output owing to the fact that the contact break produces a 1 level at both
inputs of the latch which forces the output to hold its existing logic state.
When the switch is brought back to position 1 the output makes a neat transition to a 0 level.
Detecting the Sequence of Edges:
D Q
A
FF
B
CLK
Fig.: Detection of the sequence of edges.

Flip-flops can be used to detect the sequence of occurrence of rising and falling edges.
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Dated, the………………………….
Figure shows how a flip-flop can be used to detect whether a positive-going edge A follows or precedes another
positive-going edge B. The two edges are respectively applied to D and clock inputs of a positively edge-triggered D
flip-flop.
If edge A arrives first than on arrival of edge B, the output goes from 0 to 1. If it is otherwise, it stays at a 0 level.
[Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]
Shift-Registers:
A shift register is a group of FFs arranged so that the binary numbers stored in the FFs are shifted from one FF to the
next for every clock pulse. It is some kinds of cascade arrangement of flip-flops that has no specified sequence of
states.
DATA
IN
J X3 J X3 J X3 J X3
CLK CLK CLK CLK
K X3 K X2 K X1 K X0
Shift
pulses 1
Shift pulses
0
T1 T2 T3 T4
DATA IN
X3
X2
X1
X0
Fig.: Four-bit shift register.

Figure shows one way to arrange J-K flip-flops to operate as a four-bit shift register. The FFs are connected so that
the output of X3 transfers into X2, X2 into X1 and X1 into X0 upon the occurrence of the NGT of a shift pulse.
When the first NGT occurs at T1, each of the FFs X2, X1 and X0 will have the J=0, K=1 condition present at its inputs
because of the state of the FF on its left. Flip-flop X3 will have J=1, K=0 because of DATA IN. Thus, at T1 only X3 will
go HIGH, while all the other FFs remain LOW.
When the second NGT occurs at T2, flip-flop X3 will have J=0, K=1 because of DATA IN. Flip-flop X2 will have J=1,
K=0 because of the current HIGH at X3. Flip-flops X1 and X0 will still have J=0, K=1. Thus, at T2 only FF X2 will go
HIGH, FF X3 will go LOW, and FFs X1 and X0 will remain LOW.
In this way, on each NGT of the shift pulses, each FF output takes on the level that was present at the output of the
FF on its left just prior to the NGT.
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Ref. No............................ August 22, 2010

Dated, the………………………….
Parallel Data Transfer:

D Q1 Q1=X
X CLK Q1
Combinational Y
logic circuit D Q1 Q2=Y
Z
CLK Q2
D Q1 Q3=Z
1
TRANSFER
0 CLK Q3
Fig.: Parallel transfer of binary data using D FFs.

Outputs X, Y and Z from a logic circuit are to be transferred to FFs Q1, Q2 and Q3 for storage. Using the D flip-flops,
the levels present at X, Y and Z will be transferred to Q1, Q2 and Q3, respectively, upon application of a TRANSFER
pulse to the common CLK inputs. The three bits X, Y and Z are all transferred simultaneously. The FFs can store
these values for subsequent processing.
Serial Data Transfer:

Figure shows two three-bit shift registers connected so that the contents of the X register will be serially transferred
into register Y.
X Register Y Register
0 D X2 D X1 D X0 D Y2 D Y1 D Y0
CLK CLK CLK CLK CLK CLK

Shift pulses
X2 X1 X0 Y2 Y1 Y0
1 0 1 0 0 0 ←Before pulses applied
0 1 0 1 0 0 ←After first pulse
0 0 1 0 1 0 ←After second pulse
0 0 0 1 0 0 ←After third pulse
Fig.: Serial transfer of information from X register into Y register.
X0, the last FF of register X, is connected to the D input of Y2, the first FF of register Y. Thus, as the shift pulses are
applied, the information transfer takes place as follows – X2X1X0Y2Y1Y0.
To illustrate, let us assume that before any shift pulses are applied, the contents of the X register are 101 and the Y
register is at 000.
On the NGT of each pulse, each FF takes on the value that was stored in the FF on its left prior to the occurrence of
the pulse.
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Dated, the………………………….
After three pulses, the 1 that was initially in X2 is in Y2, the 0 initially in X1 is in Y1, and the 1 initially in X0 is in Y0. The
101 stored in the X register has now been shifted into the Y register. The X register is at 000 and lost its original data.
Asynchronous/Ripple Counters:
A ripple counter is a cascaded arrangement of flip-flop where the output of one flip-flop drives the clock input of the
following flip-flop.
In a ripple counter, also called an asynchronous counter or a serial counter, the clock input is applied only to the first
flip-flop, also called the input flip-flop, in the cascaded arrangement. The clock input to any subsequent flip-flop
comes from the output of its immediately preceding flip-flop.
1 1 1 1
J A J B J C J D
CLK CLK CLK CLK
K A K B K C K D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLOCK
D
DCBA (count) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010
Fig.: Four-bit asynchronous counter.

Figure above shows a four-bit asynchronous binary counter circuit where all J and K inputs are assumed to be 1. The
circuit operation can be described as –
(1) The clock pulses are applied only to the CLK input of flip-flop A. Thus, flip-flop A will toggle each time the clock
pulses make a negative transition.
(2) The normal output of flip-flop A acts as the CLK input for flip-flop B, and so flip-flop B will toggle each time the A
output goes from 1 to 0. Similarly, flip-flop C will toggle when B goes from 1 to 0, and flip-flop D will toggle when C
goes from 1 to 0.
(3) FF outputs D, C, B and A represent a four-bit binary number with D as the MSB. If all FFs have been cleared to
the 0 state initially, then a binary counting sequence from 0000 to 1111 is followed as clock pulses are
continuously applied.
(4) After the NGT of the fifteenth clock pulse has occurred, the counter FFs are in the 1111 condition. On the
sixteenth NGT, flip-flop A goes from 1 to 0, which causes flip-flop B to go from 1 to 0, and so on, until the counter
is in the 0000 state. The counter will now begin a new counting cycle as subsequent clock pulses are applied.
As the counter has 16 distinctly different states, it is a MOD-16 ripple counter. The MOD number can be increased
simply by adding more FFs to the counter. That is,
MOD number = 2N
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Ref. No............................ August 22, 2010

Dated, the………………………….
where N is the number of FFs connected in the arrangement.

Here each FF provides an output waveform that is exactly half the frequency of the waveform at its CLK input. For
example, if the clock signal of a MOD-16 ripple counter is 16kHz then the waveform at output A is an 8kHz square
wave, at output B it is 4kHz, at output C it is 2kHz and at output D it is 1kHz.
Also, the output of the last flip-flop D has a frequency equal to the original clock frequency divided by 16. Thus, it can
also be called a divide-by-16 counter.
To have a visible display of how a counter is changing states in response to the input pulses, each FF output is
connected to an INVERTER whose output provides the current path for the LED. This operates as follows –
(I) When output A is HIGH, the INVERTER output goes Low and the LED turns ON. Thus, the bright LED
indicates A=1.
(II) When output A is Low, the INVERTER output is HIGH and the LED turns OFF. Thus, the dark LED indicates
A=0.
A major problem with ripple counters arises from the propagation delay of the flip-flops constituting the counter. The
effective propagation delay in a ripple counter is equal to the sum of propagation delays due to different flip-flops. The
situation becomes worse with increase in the number of flip-flops used to construct the counter. So, an increased
propagation delay puts a limit on the maximum frequency used as clock input to the counter. The clock signal time
period must be equal to or greater than the total propagation delay. If tpd is the propagation delay in each flip-flop,
then in a counter with N flip-flops, the maximum usable clock frequency is given by fmax=1/(Nxtpd).
[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

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`~ivjvcbx t Telephone :

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dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ August 22, 2010

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ August 22, 2010

Fig.: Master-slave flip-flop.

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ August 22, 2010

Detecting the Sequence of Edges:

Fig.: Detection of the sequence of edges.

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ August 22, 2010

CLK CLK CLK CLK

Fig.: Four-bit shift register.

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ August 22, 2010

Parallel Data Transfer:

Fig.: Parallel transfer of binary data using D FFs.

Serial Data Transfer:

CLK CLK CLK CLK CLK CLK

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Ref. No............................ August 22, 2010

CLK CLK CLK CLK

Fig.: Four-bit asynchronous counter.

dwjZ c`v_© weÁvb, B‡jKUªwb· I DEPT. OF APPLIED PHYSICS, ELECTRONICS &

Ref. No............................ August 22, 2010

where N is the number of FFs connected in the arrangement.

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