LA-9863P VFKAA r10 PDF

5 4 3 2 1
DESIGN CURRENT 0.1A +3VL

B+
Ipeak=8.13A, Imax=5.69A, Iocp min=8.7 DESIGN CURRENT 5A +5VALW
PCH_PWR_EN#
P-CHANNEL
+5VALW_PCH
SUSP# AO-3413
D D
DESIGN CURRENT 2A +1.8VS
SY8032ABC
SUSP#
DESIGN CURRENT 6A +5VS

TPS22966DPUR
RT8243AZQW KB_LED
DESIGN CURRENT 400mA +5VS_LED
P-CHANNEL
AO-3413
+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191-330T1U
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413
Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 5A +3VALW
DESIGN CURRENT 330mA +3V_LAN

C WOWL_EN# C
DESIGN CURRENT 3A +3V_WLAN

P-CHANNEL
AO-3413
PCH_PWR_EN#
P-CHANNEL
+3VALW_PCH
AO-3413
SUSP#
DESIGN CURRENT 6A +3VS

TPS22966DPUR
LCD_ENVDD
DESIGN CURRENT 1.5A +LCD_VDD

APL3512ABI
DGPU_PWR_EN
DESIGN CURRENT 0.1A +3VS_DGPU
P-CHANNEL
AO-3413
VR_ON
DESIGN CURRENT 65A +CPU_CORE
NCP81012BMNR DESIGN CURRENT 40A +GFX_CORE
B B
SUSP#
Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A +1.05VS_VCCP

SY8208QKC
VGA_PWROK#
DESIGN CURRENT 3A +1.05VS_DGPU
N-CHANNEL
AO3416
VCCP_PWRGOOD
DESIGN CURRENT 6A +VCCSA
G978F11U
SYSON
Ipeak=15A, Imax=10.5A, Iocp min=18A DESIGN CURRENT 2A +1.5V
RT8207M 0.75VR_ON
DESIGN CURRENT 1.5A +0.75VS
SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
DESIGN CURRENT 2A +1.5VS
1.5_PWR_EN#
A A
N-CHANNEL DESIGN CURRENT 11A +VRAM_1.5VS

FDS6676AS
DGPU_PWR_EN
Ipeak=59A, Imax=45.7A, Iocp min=70A DESIGN CURRENT 30A +VGA_CORE
NCP81172MNTWG
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 3 of 56
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )

Voltage Rails BTO Option Table
+5VS Function SKU PCH GPU VRAM EC ISPD
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW description Optimus Panther Point N14M-GL N14P-GV2 Dual Rank EC HDMI Logo
+1.8VS
power +1.5VS explain Optimus HM76 HM70 N14M-GL N14P-GV2 Dual Rank KB9012 NPCE885N HDMI Logo
1 plane +1.05VS 1
HM76R1@ HM70R1@ N14MGL@ N14PGV2@

+0.75VS
BTO OPT@ DRANK@ 9012@ 885@ HDMI45@
+CPU_CORE N14MGLR1@ N14PGV2R1@
HM76R3@ HM70R3@
+VGA_CORE N14MGLR3@ N14PGV2R3@
+GFX_CORE
+VTT
State Function LVDS-eDP Camera & Mic USB S&C CRT Touch Screen
+VRAM_1.5VS
+3VS_DGPU description LVDS-eDP Camera & Mic 14640 14641 CRT Touch Screen
+1.05VS_DGPU
explain LVDS eDP Camera & Mic 14640 14641 w/ CRT w/o CRT Touch Screen
BTO LVDS@ IEDP@ CAM_EMI@ 14640@ 14641@ CRT@ CRT_EMI@ NOCRT@ TOUCH_EMI@
S0
O O O O O O
Function WOWL G-SENSOR ZPODD GCLK VRAM SKU for GV2
S1
O O O O O O description WOWL G-SENSOR ZPODD GCLK non-GCLK Single Rank Dual Rank
S3 explain w/ w/o G-SENSOR w/ w/o GCLK non-GCLK Single Rank Dual Rank
2 O O O O O X 2
BTO WOWL@ NOWOWL@ GSENSOR@ ZPODD@ NONZP@ GCLK@ NOGCLK@ GVSR@ GVDR@
S5 S4/AC
O O O O X X
S5 S4/ Battery only Function Sleep & Music KB Light EMI/ESD part
O O O X X X
description Sleep & Music KB Light EMI/ESD part
S5 S4/AC & Battery
don't exist
O X X X X X
explain w/ S&M w/o S&M KB Light EMI/ESD part
BTO 269@ 259@ KBL@ EMI@ ESD@
PCH SM Bus Address
Power Device HEX Address

+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
3
+3VS WLAN/WIMAX 3
+3VS Touch Pad 2C H 0010 1100 b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH
Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
+3VL Smart Charger 12 H 0001 0010 b +3VS NVIDIA GPU 9E H 1001 1010 b
S4 (Suspend to Disk) LOW LOW HIGH
+3VL USB S&C 14640 35 H 0011 0101 b +3VS G-Sensor 40 H 0100 0000 b
S5 (Soft OFF) LOW LOW LOW
G3 LOW LOW LOW

4 4

Notes List
Size Document Number
Rev
Custom 0.2
VFKAA
A B C D E
5 4 3 2 1
Stuff R41 and R42 if do not support eDP

JCPUB
100 MHz +1.05VS_VCCP
@ A28
BCLK CLK_CPU_DMI <26>
1000P_0402_50V7K 2 1 CC62 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_EDP# RC1571 LVDS@ 2 1K_0402_5%
MISC
CLOCKS
<30> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <26>
120 MHz CLK_CPU_EDP RC1581 LVDS@ 2 1K_0402_5%
T1 PAD TP_SKTOCC# AN34
ESD@ SKTOCC# A16 CLK_CPU_EDP
1 2 CC63 DPLL_REF_CLK A15 CLK_CPU_EDP <26>
180P_0402_50V8J H_PWRGOOD CLK_CPU_EDP#
DPLL_REF_CLK# CLK_CPU_EDP# <26>
D D
by ESD requestion and place near CPU T2 PAD H_CATERR# AL33 @ESD@
CATERR# H_DRAMRST# 1 2
CC34 180P_0402_50V8J
THERMAL
H_PECI AN33 R8 H_DRAMRST#
+1.05VS_VCCP <41> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
by ESD requestion and place near CPU
DDR3
MISC
RC44 2 1 62_0402_5% H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 RC56 2 1 140_0402_1%
<41> H_PROCHOT# PROCHOT# SM_RCOMP[0]
RC159 56_0402_5% A5 SM_RCOMP_1 RC59 2 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP_2 RC61 2 1 200_0402_1%
SM_RCOMP[2]
DDR3 Compensation Signals
RC45 2 1 10K_0402_5% H_PWRGOOD AN32 Layout Note:Place these
<30> H_THERMTRIP# THERMTRIP#
resistors near Processor
AP29
PRDY# AP27
PREQ#
AR26 XDP_TCK T13 PAD
TCK AR27 XDP_TMS T15 PAD
PWR MANAGEMENT
TMS
JTAG & BPM

@ H_PM_SYNC AM34 AP30 XDP_TRST# 1 2
<27> H_PM_SYNC PM_SYNC TRST#
1000P_0402_50V7K 2 1 CC70 H_PECI RC55 51_0402_5%
AR28 XDP_TDI
@ TDI AP26 XDP_TDO T7 PAD
1000P_0402_50V7K 2 1 CC67 H_PM_SYNC H_PWRGOOD 1 Rshort@ 2 H_PWRGOOD_R AP33 TDO T10 PAD
<30> H_PWRGOOD UNCOREPWRGOOD
RC183 0_0402_5%
@
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST# AL35
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8 DBR#
C SM_DRAMPWROK Close to CPU side C
RC170 130_0402_5%
AT28
BPM#[0] AR29
Please place near JCPU BPM#[1] AR30
BUF_CPU_RST# AR33 BPM#[2] AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
BPM#[6] AR32
BPM#[7]
+3VALW_PCH
2 1 DRAMPWROK +3VALW_PCH
RC11 200_0402_5% +1.5V_CPU TYCO_2013620-2_IVY BRIDGE
Conn@
1
0206: Delete 0.1uF
RC14
UC3 200_0402_5%
5
10K_0402_5% 74AHC1G09GW_TSSOP5
2
2 RC13 1 1
P
+3VS B 4 PM_SYS_PWRGD_BUF
2 O
<27> DRAMPWROK A
G
3
B B
FAN Control Circuit

+5VS
Buffered Reset to CPU
+3VS
1A
1 Rshort@ 2 +FAN1
1
+3VS R1 0_0603_5%
JFAN
R2
10K_0402_5% 6
5 G6
0206: Delete 0.1uF 4 G5
2
3 4
+1.05VS_VCCP <41> FANPWM 3
2
PLT_RST# <29,35,36,41> <41> FAN_SPEED1 2
+FAN1 1
1
1
UC2 ACES_50273-0040N-001
1 RC38 Conn@
OE# 5 75_0402_5%
VCC
1
2 RC35 1
2
IN 43_0402_1%
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# D1 C5
3 OUT 10U_0603_6.3V6M
GND BAS16_SOT23-3 2
2
A 74AHC1G125GW_SOT353-5 A

Ivy Bridge_JTAG/XDP/FAN
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical
1
impedance = 43 m ohm (4 mils)
RC1
24.9_0402_1%
PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 m ohm (12 mils)
2
J22 PEG_COMP
PEG_ICOMPI J21
D B27 PEG_ICOMPO H22 D
<27> DMI_PTX_CRX_N0 B25 DMI_RX#[0] PEG_RCOMPO
<27> DMI_PTX_CRX_N1 A25 DMI_RX#[1]
<27> DMI_PTX_CRX_N2 B24 DMI_RX#[2] K33 PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N[0..3] <13>
<27> DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_GTX_C_CRX_N1
B28 PEG_RX#[1] L34 PCIE_GTX_C_CRX_N2
<27> DMI_PTX_CRX_P0 B26 DMI_RX[0] PEG_RX#[2] J35 PCIE_GTX_C_CRX_N3
<27> DMI_PTX_CRX_P1 A24 DMI_RX[1] PEG_RX#[3] J32
DMI
<27> DMI_PTX_CRX_P2 B23 DMI_RX[2] PEG_RX#[4] H34
<27> DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5] H31
G21 PEG_RX#[6] G33
<27> DMI_CTX_PRX_N0 E22 DMI_TX#[0] PEG_RX#[7] G30
<27> DMI_CTX_PRX_N1 F21 DMI_TX#[1] PEG_RX#[8] F35
<27> DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34
<27> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32
G22 PEG_RX#[11] D33
<27> DMI_CTX_PRX_P0 D22 DMI_TX[0] PEG_RX#[12] D31
<27> DMI_CTX_PRX_P1 F20 DMI_TX[1] PEG_RX#[13] B33
<27> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
PCI EXPRESS* - GRAPHICS

C21 C32
<27> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PCIE_GTX_C_CRX_P[0..3] <13>
PCIE_GTX_C_CRX_P0
PEG_RX[0] L35 PCIE_GTX_C_CRX_P1
PEG_RX[1] K34 PCIE_GTX_C_CRX_P2
A21 PEG_RX[2] H35 PCIE_GTX_C_CRX_P3
<27> FDI_CTX_PRX_N0 H19 FDI0_TX#[0] PEG_RX[3] H32
<27> FDI_CTX_PRX_N1 E19 FDI0_TX#[1] PEG_RX[4] G34
<27> FDI_CTX_PRX_N2 F18 FDI0_TX#[2] PEG_RX[5] G31
<27> FDI_CTX_PRX_N3 B21 FDI0_TX#[3] PEG_RX[6] F33
Intel(R) FDI
<27> FDI_CTX_PRX_N4 C20 FDI1_TX#[0] PEG_RX[7] F30
<27> FDI_CTX_PRX_N5 D18 FDI1_TX#[1] PEG_RX[8] E35
<27> FDI_CTX_PRX_N6 E17 FDI1_TX#[2] PEG_RX[9] E33
<27> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32
C PEG_RX[11] D34 C
A22 PEG_RX[12] E31
<27> FDI_CTX_PRX_P0 G19 FDI0_TX[0] PEG_RX[13] C33
<27> FDI_CTX_PRX_P1 E20 FDI0_TX[1] PEG_RX[14] B32
<27> FDI_CTX_PRX_P2 G18 FDI0_TX[2] PEG_RX[15]
<27> FDI_CTX_PRX_P3 B20 FDI0_TX[3] M29 PCIE_CTX_GRX_N0 1 2 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N[0..3] <13>
CC8 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P4 C19 FDI1_TX[0] PEG_TX#[0] M32 PCIE_CTX_GRX_N1 1 2 PCIE_CTX_C_GRX_N1
CC11 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P5 D19 FDI1_TX[1] PEG_TX#[1] M31 PCIE_CTX_GRX_N2 1 2 PCIE_CTX_C_GRX_N2
CC16 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P6 F17 FDI1_TX[2] PEG_TX#[2] L32 PCIE_CTX_GRX_N3 1 2 PCIE_CTX_C_GRX_N3
CC20 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29
J18 PEG_TX#[4] K31
<27> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
J17 K28
<27> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30
H20 PEG_TX#[7] J28
<27> FDI_INT FDI_INT PEG_TX#[8] H29
J19 PEG_TX#[9] G27
<27> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
H17 E29
<27> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] F27
PEG_TX#[12] D28
PEG_TX#[13] F26
PEG_TX#[14] E25
RC2 1 2 24.9_0402_1% EDP_COMP A18 PEG_TX#[15]
+1.05VS_VCCP eDP_COMPIO PCIE_CTX_C_GRX_P[0..3] <13>
A17 M28 PCIE_CTX_GRX_P0 CC10 1 2 0.22U_0402_16V7K PCIE_CTX_C_GRX_P0
H_EDP_HPD# B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_P1 CC5 1 2 0.22U_0402_16V7K PCIE_CTX_C_GRX_P1
eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_P2 1 2 PCIE_CTX_C_GRX_P2
eDP_COMP signals should be PEG_TX[2]
CC6 0.22U_0402_16V7K
L31 PCIE_CTX_GRX_P3 CC7 1 2 0.22U_0402_16V7K PCIE_CTX_C_GRX_P3
shorted near balls and C15 PEG_TX[3] L28
<22> H_EDP_AUXP eDP_AUX PEG_TX[4]
routed with typical <22> H_EDP_AUXN
D15
eDP_AUX# PEG_TX[5]
K30
K27
impedance <25m ohm
eDP
PEG_TX[6] J29
C17 PEG_TX[7] J27
<22> H_EDP_TXP0 F16 eDP_TX[0] PEG_TX[8] H28
B <22> H_EDP_TXP1 C16 eDP_TX[1] PEG_TX[9] G28 B
G15 eDP_TX[2] PEG_TX[10] E28
eDP_TX[3] PEG_TX[11] F28
C18 PEG_TX[12] D27
<22> H_EDP_TXN0 E16 eDP_TX#[0] PEG_TX[13] E26
<22> H_EDP_TXN1 D16 eDP_TX#[1] PEG_TX[14] D25
F15 eDP_TX#[2] PEG_TX[15] PEG DG suggest AC cap
eDP_TX#[3]
+1.05VS_VCCP
TYCO_2013620-2_IVY BRIDGE Gen1/Gen2 75 nF~265 nF
Conn@ IVY Bridge
Gen3 180 nF~265 nF
2
RC9 SANDY Bridge Gen1/Gen2 180 nF~265 nF

1K_0402_5%
NV N14x Gen1/2/3 Suggest 220 nF

1
H_EDP_HPD#
1
OUT
2
<22> CPU_EDP_HPD IN
GND
QC1
DTC124EKAT146_SC59-3
3
IEDP@
A A

Ivy Bridge_DMI/PEG/FDI
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
JCPUC JCPUD
<11> DDR_A_D[0..63]
<12> DDR_B_D[0..63]
AB6 AE2
SA_CLK[0] AA6 DDRA_CLK0 <11> SB_CLK[0] AD2 DDRB_CLK0 <12>
C5 SA_CLK#[0] V9 DDRA_CLK0# <11> C9 SB_CLK#[0] R9 DDRB_CLK0# <12>
DDR_A_D0 DDR_B_D0
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDRA_CKE0 <11> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDRB_CKE0 <12>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
D C6 SA_DQ[4] SA_CLK[1] AB5 DDRA_CLK1 <11> A8 SB_DQ[4] SB_CLK[1] AD1 DDRB_CLK1 <12> D
DDR_A_D5 DDR_B_D5
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 DDRA_CLK1# <11> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 DDRB_CLK1# <12>
DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDRA_CKE1 <11> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDRB_CKE1 <12>
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
K2 SA_DQ[22] SA_CS#[0] AL3 DDRA_SCS0# <11> K7 SB_DQ[22] SB_CS#[0] AE3 DDRB_SCS0# <12>
DDR_A_D23 DDR_B_D23
M8 SA_DQ[23] SA_CS#[1] AG1 DDRA_SCS1# <11> M5 SB_DQ[23] SB_CS#[1] AD6 DDRB_SCS1# <12>
DDR_A_D24 DDR_B_D24
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
N9 SA_DQ[29] SA_ODT[0] AG3 DDRA_ODT0 <11> M2 SB_DQ[29] SB_ODT[0] AD4 DDRB_ODT0 <12>
DDR_A_D30 DDR_B_D30
DDRA_ODT1 <11> DDRB_ODT1 <12>
DDR SYSTEM MEMORY B

DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5
DDR SYSTEM MEMORY A

DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <11> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <12> C
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
AN11 SA_DQ[48] D4 DDR_A_DQS[0..7] <11> AJ11 SB_DQ[48] C7 DDR_B_DQS[0..7] <12>
DDR_A_D49 DDR_A_DQS0 DDR_B_D49 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
AL14 SA_DQ[59] DDR_A_MA[0..15] <11> AT12 SB_DQ[59]
DDR_A_D60 DDR_B_D60
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <12>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
B <11> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 <12> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 B
DDR_A_MA8 DDR_B_MA8
<11> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 <12> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3
DDR_A_MA9 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 DDR_A_MA10 <12> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<11> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <12> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR_A_MA14 DDR_B_MA14
<11> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <12> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<11> DDR_A_WE# SA_WE# SA_MA[15] <12> DDR_B_WE# SB_WE# SB_MA[15]
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Conn@ Conn@
+1.5V
1
RC76
1K_0402_5%
RC77
2
QC3 1K_0402_5%
3 1
S
DDR3_DRAMRST#_R 1 2
<5> H_DRAMRST# SM_DRAMRST# <11,12>
2
BSS138_NL_SOT23-3
RC78
G
2
4.99K_0402_1%
A A
1
1 Rshort@ 2 DRAMRST_CNTRL
<26,9> DRAMRST_CNTRL_PCH
RC73 0_0402_5%
1
CC37 Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U_0402_25V6K 2012/12/07 2013/12/07 Title
Issued Date Deciphered Date
2
Ivy Bridge_DDR3
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
JCPUF POWER +1.05VS_VCCP +1.05VS_VCCP
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
ESD@ CC17
ESD@ CC18
ESD@ CC19
1 1 1
53A
AG35 8.5A
D AG34 VCC1 AH13 2 2 2 D
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
AG31 VCC4 VCCIO3 AC10
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
VCC11 VCCIO10 by ESD requestion and place near CPU
AF34 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF29 VCC16 VCCIO15 G14
PEG AND DDR
AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
C AC32 VCC33 VCCIO31 C12 C
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
AC28 VCC37 VCCIO35 A14
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY
Y34 VCC51
Y33 VCC52 +1.05VS_VCCP +1.05VS_VCCP
Y32 VCC53
Y31 VCC54
Y30 VCC55
VCC56
1
Y29
Y28 VCC57 RC91 RC89
Y27 VCC58 130_0402_5% 75_0402_5%
Y26 VCC59
V35 VCC60
2
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 2

SVID
V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <51>

RC90 43_0402_1%
V32 VCC63 VIDSCLK AJ28 VR_SVID_CLK <51>
V31 VCC64 VIDSOUT VR_SVID_DAT <51>
B V30 VCC65 B
VCC66 Pull high resistor on VR side
V29
V28 VCC67
V27 VCC68
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78 +CPU_CORE
U26 VCC79
R35 VCC80
R34 VCC81
VCC82
2
R33
R32 VCC83
VCC84
RC93 Close to CPU
R31 100_0402_1%
R30 VCC85
R29 VCC86
1
R28 VCC87
SENSE LINES
R27 VCC88 AJ35

R26 VCC89 VCC_SENSE AJ34 VCCSENSE <51>
P35 VCC90 VSS_SENSE VSSSENSE <51>
P34 VCC91
VCC92
1
P33
P32 VCC93 B10 RC97
P31 VCC94 VCCIO_SENSE A10 VCCIO_SENSE <49>
100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO
VCC96
1
P29
2
A P28 VCC97 RC96 RC98 A

P27 VCC98 10_0402_1% 10_0402_1%
P26 VCC99
VCC100
2
+1.05VS_VCCP
Close to CPU Security Classification Compal Secret Data Compal Electronics, Inc.
Conn@
TYCO_2013620-2_IVY BRIDGE
Ivy Bridge_POWER-1
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
+GFX_CORE Intel DDR Vref M3 Place near SO-DIMM side
1
+GFX_CORE
JCPUG
POWER RC105
10_0402_1%
Close to CPU
BSS138_NL_SOT23-3
QC7
33A
2
3 1
D
+VREF_DQA_M3 +VREF_DQA
AT24 AK35
SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 VCC_AXG_SENSE <51>
D AT21 VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <51> D
G
2
AT20 VAXG3 1 RC106 2
AT18 VAXG4 10_0402_1%
AT17 VAXG5
AR24 VAXG6 DRAMRST_CNTRL_PCH <26,7>
AR23 VAXG7 +V_SM_VREF should +1.5V_CPU
VAXG8 have 20 mil trace width
2
G
AR21 RC120
AR20 VAXG9 1 1K_0402_0.5%
2
AR18 VAXG10 AL1 +V_SM_VREF 3 1
VAXG11 SM_VREF +VREF_DQB_M3 +VREF_DQB
AR17 1 1K_0402_0.5%
2
D
AP24 VAXG12 RC109 QC8
1
VREF
AP23 VAXG13 BSS138_NL_SOT23-3
AP21 VAXG14 CC65
AP20 VAXG15 B4 0.1U_0402_10V7K
VAXG16 SA_DIMM_VREFDQ +VREF_DQA_M3 2
AP18 D1
VAXG17 SB_DIMM_VREFDQ +VREF_DQB_M3
AP17
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
VAXG21
VREF traces should be at least
AN20 +1.5V_CPU
AN18 VAXG22 +1.5V_CPU Decoupling: 20 mils wide and 20 mils spacing
VAXG23 5A to other signals/planes.
DDR3 -1.5V RAILS

AN17
AM24 VAXG24 AF7 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
1X 47U (MLCC), 6X 10U
GRAPHICS
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1 1 1 1 1 1
1
AM20 AC7 CC57 CC51 CC52 CC55 CC54 CC56 CC50
AM18 VAXG28 VDDQ4 AC4 47U_0805_6.3V6M
AM17 VAXG29 VDDQ5 AC1 @
2
AL24 VAXG30 VDDQ6 Y7 2 2 2 2 2 2
AL23 VAXG31 VDDQ7 Y4
AL21 VAXG32 VDDQ8 Y1 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
AL20 VAXG33 VDDQ9 U7
C AL18 VAXG34 VDDQ10 U4 C
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK20 VAXG39 VDDQ15
AK18 VAXG40 +VCCSA Decoupling:
VAXG41
AK17
AJ24 VAXG42 1X 47U (MLCC), 3X 10U
AJ23 VAXG43
AJ21 VAXG44 +VCCSA
VAXG45 Bottom Socket Cavity VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ20
AJ18 VAXG46 6A
AJ17 VAXG47 M27
VAXG48 VCCSA1
10U_0603_6.3V6M 0 0 0.90 V
AH24 M26 For Sandy Bridge
SA RAIL
AH23 VAXG49 VCCSA2 L26

AH21 VAXG50 VCCSA3 J26
VAXG51 VCCSA4 1 1 1 0 1 0.80 V
1
AH20 J25 CC42 CC41 CC43 CC44
AH18 VAXG52 VCCSA5 J24 47U_0805_6.3V6M
AH17 VAXG53 VCCSA6 H26 @ 1 0 0.725 V
2
VAXG54 VCCSA7 H25 2 2 2
VCCSA8
10U_0603_6.3V6M 10U_0603_6.3V6M 1 1 0.675 V
VCCPLL Decoupling: Bottom Socket Edge
1.8V RAIL
1X 10U, 1x 1U VCCSA_SENSE
H23
1.2A
1 Rshort@ 2 +1.8VS_VCCPLL B6
+1.8VS VCCPLL1
RC119 0_0805_5% A6 C22
MISC
A2 VCCPLL2 VCCSA_VID[0] C24 H_VCCSA_VID0 <50>

H_VCCSA_VID1 <50>
Please kindly check whether
B VCCPLL3 VCCSA_VID[1] B
1 1 there is pull-down resister
CC59 CC60 in PWR-side or HW-side
10U_0603_6.3V6M A19 10/3: confirmed with PWR, IC intergrate PD
2 2 VCCIO_SEL
1U_0402_6.3V6K TYCO_2013620-2_IVY BRIDGE
+1.5V_CPU JP@ +1.5VS

Conn@ PJ1
2 1
+1.5V_CPU +1.5V 2 1
JUMP_43X39
Vgs=10V,Id=14.5A,Rds=6mohm +1.5V
CC46 1 2 0.1U_0402_10V7K QC4
@ 1 8
CC47 1 2 0.1U_0402_10V7K 2 S D 7
S D
2
@ 1 3 6
CC48 1 2 0.1U_0402_10V7K RC203 CC68 4 S D 5
@ 470_0805_5% 10U_0603_6.3V6M G D
CC45 1 2 0.1U_0402_10V7K FDS6676AS_SO8 RC204
@ 2 RUN_ON_CPU1.5VS3 1 2
B+
3 1
220K_0402_5%
6
1
QC5B 1
CC69 RC205 QC5A
SUSP 5 0.1U_0402_25V6 820K_0402_5%
2 SUSP
2 SUSP <43>
2N7002DW-T/R7_SOT363-6
2
2N7002DW-T/R7_SOT363-6
1
A A

Ivy Bridge_POWER-2
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
JCPUH JCPUI
JCPUE CFG Straps for Processor
AT35 AJ22 (CFG[17:0] internal pull high 5~15K to VCCIO)
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19 AH27 PAD T3
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30 AK28 VCC_DIE_SENSE AH26
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27 AK29 CFG[0] VSS_DIE_SENSE CFG2
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24 CFG2 AL26 CFG[1]
VSS7 VSS87 VSS165 VSS238 CFG[2]
1
AT16 AJ3 T30 E21 AL27
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18 CFG4 AK26 CFG[3] L7 RC79
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15 CFG5 AL29 CFG[4] RSVD28 AG7 1K_0402_1%
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13 CFG6 AL30 CFG[5] RSVD29 AE7 @
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10 CFG7 AM31 CFG[6] RSVD30 AK2
D D
2
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9 AM32 CFG[7] RSVD31
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8 AM30 CFG[8] W8
CFG
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7 T14 PAD CFG10 AM28 CFG[9] RSVD32
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6 T20 PAD CFG11 AM26 CFG[10]
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5 T23 PAD CFG12 AN28 CFG[11] AT26
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4 T18 PAD CFG13 AN31 CFG[12] RSVD33 AM33
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3 T22 PAD CFG14 AN26 CFG[13] RSVD34 AJ27
VSS19 VSS100 VSS177 VSS250 CFG[14] RSVD35 PEG Static Lane Reversal - CFG2 is for the 16x
AR7 AH16 N34 E2 T21 PAD CFG15 AM27
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1 T24 PAD CFG16 AK31 CFG[15]
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35 T25 PAD CFG17 AN29 CFG[16]
1: Normal Operation; Lane # definition matches
AP34
AP31
VSS22
VSS23
VSS24
VSS103
VSS104
VSS105
AG9
AG8
N31
N30
VSS180
VSS181
VSS182
VSS253
VSS254
VSS255
D32
D29
CFG[17]
CFG2
* socket pin map definition
AP28 AG4 N29 D26 T8
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20 RSVD37 J16
VSS26 VSS107 VSS184 VSS257 RSVD38 0:Lane Reversed
AP22 AF5 N27 D17 AJ31 H16
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34 AH31 VAXG_VAL_SENSE RSVD39 G16
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31 AJ33 VSSAXG_VAL_SENSE RSVD40 CFG4
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28 AH33 VCC_VAL_SENSE
VSS30 VSS111 VSS188 VSS261 VSS_VAL_SENSE
1
AP10 AE34 L30 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25 RC82
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 AJ26 AR35 1K_0402_1%
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10 RSVD5 RSVD_NCTF1 AT34 IEDP@
VSS34 VSS115 VSS192 VSS265 RSVD_NCTF2
RESERVED
AN30 AE30 L6 C1 AT33
2
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22 RSVD_NCTF3 AP35
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19 RSVD_NCTF4 AR34
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
RSVD_NCTF5
AN16 AE9 L1 B13 F25

AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11 F24 RSVD8
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9 F23 RSVD9
VSS42 VSS123 VSS200 VSS273 RSVD10 Embedded Display Port Presence Strap
AN7 AC8 K29 B8 D24 B34
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7 G25 RSVD11 RSVD_NCTF6 A33
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5 G24 RSVD12 RSVD_NCTF7 A34 1 : Disabled; No Physical Display Port
*
C C
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3 E23 RSVD13 RSVD_NCTF8 B35
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2 D23 RSVD14 RSVD_NCTF9 C35 attached to Embedded Display Port
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35 C30 RSVD15 RSVD_NCTF10
VSS48 VSS129 VSS206 VSS279 RSVD16 CFG4
AM16 AB34 H27 A32 A31 0 : Enabled; An external Display Port device is
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29 B30 RSVD17
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26 B29 RSVD18 connected to the Embedded Display Port
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23 D30 RSVD19 AJ32
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20 B31 RSVD20 RSVD51 AK32
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3 A30 RSVD21 RSVD52
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285 C29 RSVD22
AM1 VSS55 VSS136 AB27 H9 VSS213 RSVD23
AL34 VSS56 VSS137 AB26 H8 VSS214 AN35
AL31 VSS57 VSS138 Y9 H7 VSS215 J20 BCLK_ITP AM35 CFG6
AL28 VSS58 VSS139 Y8 H6 VSS216 B18 RSVD24 BCLK_ITP#
AL25 VSS59 VSS140 Y6 H5 VSS217 RSVD25 CFG5
AL22 VSS60 VSS141 Y5 H4 VSS218
1
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220 J15 AT2 RC83 RC84
AL13 VSS63 VSS144 W35 H1 VSS221 RSVD27 RSVD_NCTF11 AT1 1K_0402_1% 1K_0402_1%
AL10 VSS64 VSS145 W34 G35 VSS222 RSVD_NCTF12 AR1 @ @
AL7 VSS65 VSS146 W33 G32 VSS223 RSVD_NCTF13
2
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226 B1 PAD T64
AK30 VSS69 VSS150 W29 G20 VSS227 KEY
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232 TYCO_2013620-2_IVY BRIDGE
VSS75 VSS156 VSS233
PCIE Port Bifurcation Straps
AK13 U6
AK10 VSS76 VSS157 U5
VSS77 VSS158 Conn@
AK7 U3 11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10: x8, x8 - Device 1 function 1 enabled ; function 2
B B
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80
disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Conn@ Conn@
CFG7
1
RC85
1K_0402_1%
@
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

de assertion
CFG7
0: PEG Wait for BIOS for training
A A

Ivy Bridge_GND/RSVD/CFG
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
1
JDDR3L
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_A_D4
DDR_A_D5
Standard Type DDR_A_DQS[0..7] <7>
DDR_A_D1 7 DQ0 DQ5 8
1 DQ1 VSS3 DDR_A_DQS#[0..7] <7>
CD1 9 10 DDR_A_DQS#0
11 VSS4 DQS#0 12 DDR_A_DQS0
DM0 DQS0 DDR_A_D[0..63] <7>
0.1U_0402_10V7K
13 14
2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DQ2 DQ6 DDR_A_MA[0..15] <7>
DDR_A_D3 17 18 DDR_A_D7
19 DQ3 DQ7 20
D DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 D
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30
Close to JDDR3L.1 31 DQS1 RESET# 32 SM_DRAMRST# <12,7>
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
37 DQ11 DQ15 38
43 DQ17 DQ21 44
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3 +1.5V
65 DM3 DQS3 66
DQ26 DQ30
1
DDR_A_D27 69 70 DDR_A_D31
71 DQ27 DQ31 72 RD1
VSS25 VSS26 1K_0402_1%
2
73 74
<7> DDRA_CKE0 75 CKE0 CKE1 76 DDRA_CKE1 <7>
VDD1 VDD2 +VREF_DQA
77 78 DDR_A_MA15
C 79 NC1 A15 80 DDR_A_MA14 C
<7> DDR_A_BS2 BA2 A14
1
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11 RD2
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 1K_0402_1%
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
2
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
101 VDD9 VDD10 102
<7> DDRA_CLK0 103 CK0 CK1 104 DDRA_CLK1 <7>
<7> DDRA_CLK0# 105 CK0# CK1# 106 DDRA_CLK1# <7>
DDR_A_MA10 107 VDD11 VDD12 108 +1.5V
109 A10/AP BA1 110 DDR_A_BS1 <7>
<7> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <7>
VDD13 VDD14
1
113 114
<7> DDR_A_WE# 115 WE# S0# 116 DDRA_SCS0# <7>
RD6
<7> DDR_A_CAS# 117 CAS# ODT0 118 DDRA_ODT0 <7>
1K_0402_1%
DDR_A_MA13 119 VDD15 VDD16 120
121 A13 ODT1 122 DDRA_ODT1 <7>
2
<7> DDRA_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAA
127 NCTEST VREF_CA 128
VSS27 VSS28
1
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 RD7
133 DQ33 DQ37 134 1K_0402_1%
DDR_A_DQS4 137 DQS#4 DM4 138 1
2
139 DQS4 VSS31 140 DDR_A_D38 CD16
DQ34 DQ39
0.1U_0402_10V7K
B DDR_A_D35 143 144 B

145 DQ35 VSS33 146 DDR_A_D44 2
DDR_A_D41 149 DQ40 DQ45 150
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
161 DQ43 DQ47 162
close to JDDR3L.126
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170 +1.5V +1.5V +0.75VS
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55 CD8 1 2 10U_0603_6.3V6M CD20 1 2 0.1U_0402_10V7K CD24 2 1 1U_0402_6.3V6K
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60 CD9 1 2 10U_0603_6.3V6M CD17 1 2 0.1U_0402_10V7K CD21 2 1 1U_0402_6.3V6K
DDR_A_D57 183 DQ56 DQ61 184 CD10 1 2 10U_0603_6.3V6M CD18 1 2 0.1U_0402_10V7K
187 VSS48 DQS#7 188 DDR_A_DQS7 CD11 1 2 10U_0603_6.3V6M CD19 1 2 0.1U_0402_10V7K
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62 CD12 1 2 10U_0603_6.3V6M
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196 CD13 1 2 10U_0603_6.3V6M
197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS 201 VDDSPD SDA 202 PM_SMBDATA <12,26,35,42>
203 SA1 SCL 204 PM_SMBCLK <12,26,35,42>
1 +0.75VS VTT1 VTT2 +0.75VS
A 205 206 A
CD26 G1 G2
2 LCN_DAN06-K4406-0102
Conn@
0.1U_0402_10V7K
SPD setting (SA0, SA1) Security Classification Compal Secret Data Compal Electronics, Inc.
PU/PD by Channel A/B Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title
->Channel A 00
->Channel B 01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM0
Custom 0.2
VFKAA
5 4 3 2 1
A B C D E
+1.5V +1.5V
1
JDDR3H
2
DDR3 SO-DIMM B
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_B_D4
DDR_B_D5
Standard Type
DDR_B_D1 7 DQ0 DQ5 8
CD27 9 DQ1 VSS3 10 DDR_B_DQS#0
1 VSS4 DQS#0
11 12 DDR_B_DQS0
13 DM0 DQS0 14
VSS5 VSS6
0.1U_0402_10V7K
DDR_B_D2 15 16 DDR_B_D6
2 DQ2 DQ6 DDR_B_DQS#[0..7] <7>
DDR_B_D3 17 18 DDR_B_D7
1 19 DQ3 DQ7 20 1
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12 DDR_B_DQS[0..7] <7>
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
DQ9 DQ13 DDR_B_D[0..63] <7>
25 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DQS#1 DM1 DDR_B_MA[0..15] <7>
DDR_B_DQS1 29 30
31 DQS1 RESET# 32 SM_DRAMRST# <11,7>
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
Close to JDDR3H.1 DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29 +1.5V
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
VSS22 DQS#3
1
63 64 DDR_B_DQS3
65 DM3 DQS3 66 RD10
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30 1K_0402_1%
71 DQ27 DQ31 72
2
VSS25 VSS26
+VREF_DQB
73 74
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
1
75 76
2 77 VDD1 VDD2 78 DDR_B_MA15 RD11 2
79 NC1 A15 80 DDR_B_MA14 1K_0402_1%
<7> DDR_B_BS2 81 BA2 A14 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
2
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
101 VDD9 VDD10 102
<7> DDRB_CLK0 103 CK0 CK1 104 DDRB_CLK1 <7>
<7> DDRB_CLK0# 105 CK0# CK1# 106 DDRB_CLK1# <7>
DDR_B_MA10 107 VDD11 VDD12 108 +1.5V
109 A10/AP BA1 110 DDR_B_BS1 <7>
<7> DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# <7>
VDD13 VDD14
1
113 114
<7> DDR_B_WE# 115 WE# S0# 116 DDRB_SCS0# <7>
RD12
<7> DDR_B_CAS# 117 CAS# ODT0 118 DDRB_ODT0 <7>
1K_0402_1%
DDR_B_MA13 119 VDD15 VDD16 120
121 A13 ODT1 122 DDRB_ODT1 <7>
2
<7> DDRB_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAB
127 NCTEST VREF_CA 128
VSS27 VSS28
1
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37 RD13
133 DQ33 DQ37 134 CD47 1K_0402_1%
VSS29 VSS30 1
DDR_B_DQS#4 135 136
DDR_B_DQS4 137 DQS#4 DM4 138
2
DQS4 VSS31
0.1U_0402_10V7K
139 140 DDR_B_D38

3 DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 3
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
Close to JDDR3H.126 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
161 DQ43 DQ47 162
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168 +1.5V +1.5V +0.75VS
DDR_B_DQS6 171 DQS#6 DM6 172 CD31 1 2 47U_0805_6.3V6M
173 DQS6 VSS43 174 DDR_B_D54 CD33 1 2 0.1U_0402_10V7K CD45 2 1 1U_0402_6.3V6K
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55 CD41 1 2 10U_0603_6.3V6M
DDR_B_D51 177 DQ50 DQ55 178 CD29 1 2 0.1U_0402_10V7K CD42 2 1 1U_0402_6.3V6K
179 DQ51 VSS45 180 DDR_B_D60 CD36 1 2 10U_0603_6.3V6M
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61 CD30 1 2 0.1U_0402_10V7K
DDR_B_D57 183 DQ56 DQ61 184 CD37 1 2 10U_0603_6.3V6M
185 DQ57 VSS47 186 DDR_B_DQS#7 CD32 1 2 0.1U_0402_10V7K
187 VSS48 DQS#7 188 DDR_B_DQS7 CD38 1 2 10U_0603_6.3V6M
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 CD39 1 2 10U_0603_6.3V6M
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196 CD40 1 2 10U_0603_6.3V6M
197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS 2 1 201 VDDSPD SDA 202 PM_SMBDATA <11,26,35,42>
203 SA1 SCL 204 PM_SMBCLK <11,26,35,42>
1 RD15 10K_0402_5% +0.75VS +0.75VS
4 VTT1 VTT2 4
205 206
CD49 G1 G2
2 LCN_DAN06-K4806-0102
0.1U_0402_10V7K Conn@
SPD setting (SA0, SA1) Security Classification Compal Secret Data Compal Electronics, Inc.
PU/PD by Channel A/B Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title
->Channel A 00
->Channel B 01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
Custom 0.2
VFKAA
A B C D E
A B C D E
UV1A
Part 1 of 6 DV1
PCIE_GTX_C_CRX_P[0..3] PCIE_CTX_C_GRX_P0 AG6 C6 FB_CLAMP_MON 2 1
<6> PCIE_GTX_C_CRX_P[0..3] AG7 PEX_RX0 GPIO0 B2 FB_CLAMP <14,17,41> +3VS_DGPU
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6 +3VS_DGPU
RB751V40_SC76-2
2
PEX_RX1 GPIO2
G
PCIE_GTX_C_CRX_N[0..3] PCIE_CTX_C_GRX_N1 AE7 C7 OPT@ RPV1
<6> PCIE_GTX_C_CRX_N[0..3] PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 GPS_DOWN# 1 8
PEX_RX2 GPIO4 QV8
PCIE_CTX_C_GRX_N2 AF9 A3 GPU_EVENT 2 7
PEX_RX2_N GPIO5 N14PGV2@
PCIE_CTX_C_GRX_P[0..3] PCIE_CTX_C_GRX_P3 AG9 A4 FB_CLAMP_REQ# 3 1 XTAL_OUTBUFF 3 6
<6> PCIE_CTX_C_GRX_P[0..3] CLK_REQ_GC6# <41>
PCIE_CTX_C_GRX_N3 AG10 PEX_RX3 GPIO6 B6 For GC6 XTAL_SSIN 4 5
D
S
AF10 PEX_RX3_N GPIO7 A6 OVERT#_VGA
PEX_RX4 GPIO8 2N7002KW_SOT323-3
PCIE_CTX_C_GRX_N[0..3] AE10 F8 GPU_EVENT 10K_8P4R_5%
<6> PCIE_CTX_C_GRX_N[0..3] AE12 PEX_RX4_N GPIO9 C5 OPT@
1 AF12 PEX_RX5 GPIO10 E7 DGPU_VID 1
AG12 PEX_RX5_N GPIO11 D7 GPS_DOWN# DGPU_VID <54>
RPV2
AG13 PEX_RX6 GPIO12 B4 PSI GPS_DOWN# <41> VGA_EDID_CLK 1 8
GPIO
AF13 PEX_RX6_N GPIO13 B3 PSI <54> 2 7
VGA_EDID_DATA
AE13 PEX_RX7 GPIO14 C3 SMB_CLK_GPU 3 6
AE15 PEX_RX7_N GPIO15 D5 SMB_DATA_GPU 4 5
AF15 NC GPIO16 D4
AG15 NC GPIO17 C2 2.2K_8P4R_5%
AG16 NC GPIO18 F7 OPT@
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4 RPV3
AE18 NC GPIO21 VGA_CRT_CLK 1 8
AF18 NC AB6 VGA_CRT_DATA 2 7
AG18 NC NC HDCP_SDA 3 6
AG19 NC HDCP_SCL 4 5
AF19 NC
AE19 NC 2.2K_8P4R_5%
AE21 NC AG3 OPT@
AF21 NC DACA_RED AF4
AG21 NC DACA_GREEN AF3 RPV12
AG22 NC DACA_BLUE FB_CLAMP 1 8
NC FB_CLAMP_REQ# 2 7
FB_CLAMP_MON 3 6
PCIE_GTX_C_CRX_P0 CV1 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_P0 AC9 AE3 OVERT#_VGA 4 5
PEX_TX0 DACA_HSYNC
DACs
PCIE_GTX_C_CRX_N0 CV2 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N0 AB9 AE4
PCIE_GTX_C_CRX_P1 CV3 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_P1 AB10 PEX_TX0_N DACA_VSYNC 10K_8P4R_5%
PCIE_GTX_C_CRX_N1 CV4 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N1 AC10 PEX_TX1 OPT@
PCIE_GTX_C_CRX_P2 1 2 PCIE_GTX_CRX_P2 AD11 PEX_TX1_N
PCI EXPRESS
CV5 OPT@ 0.22U_0402_16V7K
PCIE_GTX_C_CRX_N2 CV6 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N2 AC11 PEX_TX2 W5 RPV13
PCIE_GTX_C_CRX_P3 1 2 PCIE_GTX_CRX_P3 AC12 PEX_TX2_N 120mA DACA_VDD AE2 CLK_REQ_GC6# 1 8
CV7 OPT@ 0.22U_0402_16V7K +3VS
PCIE_GTX_C_CRX_N3 CV8 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N3 AB12 PEX_TX3 DACA_VREF AF2 2 7
PEX_TX3_N DACA_RSET <15> JTAG_TRST
AB13 3 6
2 PEX_TX4 <15> TESTMODE 2
AC13 CLK_REQ_GPU# 4 5
AD14 PEX_TX4_N
AC14 PEX_TX5 10K_8P4R_5%
AC15 PEX_TX5_N OPT@
AB15 PEX_TX6
AB16 PEX_TX6_N B7 VGA_CRT_CLK
AC16 PEX_TX7 I2CA_SCL A7 VGA_CRT_DATA
AD17 PEX_TX7_N I2CA_SDA
AC17 NC C9 HDCP_SCL
AC18 NC I2CB_SCL C8 HDCP_SDA
NC I2CB_SDA
I2C
AB18
AB19 NC A9 VGA_EDID_CLK Internal Thermal Sensor
AC19 NC I2CC_SCL B9 VGA_EDID_DATA
AD20 NC I2CC_SDA +3VS_DGPU
AC20 NC D9 SMB_CLK_GPU
AC21 NC I2CS_SCL D8 SMB_DATA_GPU
AB21 NC I2CS_SDA
AD23 NC
AE23 NC
NC
5
AF24 OPT@
AE24 NC L6 +PLLVDD QV1B
AG24 NC 52mA CORE_PLLVDD M6 +1.05VS_DGPU SMB_CLK_GPU 4 3
LV1
AG25 NC SP_PLLVDD EC_SMB_CK2 <26,34,41>
71mA BLM18PG181SN1D_2P
NC
2
N6 +GPU_PLLVDD 1 2 OPT@ 2N7002DW-T/R7_SOT363-6
VID_PLLVDD
22U_0805_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
41mA OPT@ QV1A
CV9
CV11
CV12
CV10
CV13
1 1 1 1 1 SMB_DATA_GPU 1 6
AE8 EC_SMB_DA2 <26,34,41>
CLK_PCIE_VGA
<26> CLK_PCIE_VGA PEX_REFCLK
CLK_PCIE_VGA# AD8 OPT@ 2N7002DW-T/R7_SOT363-6
<26> CLK_PCIE_VGA# PEX_REFCLK_N
CLK_REQ_GPU# AC6 OPT@
PEX_CLKREQ_N 2 2 2 2 2
1 @ 2 PEX_TSTCLK_OUT AF22
CLK
RV4 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK_OUT C11 XTALIN

3 PEX_TSTCLK_OUT_N XTAL_IN B10 XTAL_OUT OPT@ OPT@ OPT@ 3
XTAL_OUT
AC7 A10 XTAL_SSIN CV42, CV43 under GPU
<29> PLTRST_VGA# PEX_RST_N XTAL_SSIN
AF25 C10 XTAL_OUTBUFF
PEX_TERMP XTAL_OUTBUFF close to ball : AE8,AD7
2
RV5 N14P-GV2-S-A2_FCBGA595
2.49K_0402_1% N14PGV2R3@
OPT@
1
+1.05VS_DGPU
LV2 OPT@
10U_0603_6.3V6M
+PLLVDD 1 2
OPT@ CV16
0.1U_0402_10V7K
1 2 XTALIN FBMA-L11-160808300LMA25T_2P 1
<35> VGA_X1
22U_0805_6.3V6M
OPT@ CV14
OPT@ CV15
RV8 0_0402_5% 1 1
GCLK@
under GPU
1 2
NOGCLK@ RV7 @EMI@
close to AD8 2 2
<26> CLK_REQ_VGA#
10_0402_5%
YV1 27MHZ_16PF
2
XTALIN 1 3 XTAL_OUT 1
1 3
6
CV113 @EMI@
QV2A GND GND 10P_0402_50V8J
1 2 4 1 2
2 CV17 CV18
+3VS_DGPU
2N7002DW-T/R7_SOT363-6 18P_0402_50V8J 18P_0402_50V8J
OPT@ NOGCLK@
NOGCLK@ for EMI
1
2 2
4 4

VGA_N14x PEG & DAC
Custom 0.2
A B C D E
A
VRAM Interface Place close to the first T point
MDA[15..0]
<18,20> MDA[15..0] +VRAM_1.5VS
UV1B
MDA[31..16]
<18,20> MDA[31..16]
CMDA12
MDA[47..32] CMDA14
<19,21> MDA[47..32]
Part 2 of 6 CMDA15
MDA[63..48] CMDA[30..0] <18,19,20,21> CMDA7
<19,21> MDA[63..48] MDA0 E18 C27 CMDA0
MDA1 F18 FBA_D00 FBA_CMD0 C26 CMDA1
MDA2 E16 FBA_D01 FBA_CMD1 E24 CMDA2
10
10
FBA_D02 FBA_CMD2
9
8
7
6
9
8
7
6
MDA3 F17 F24 CMDA3
MDA4 D20 FBA_D03 FBA_CMD3 D27 CMDA4 RPV4 RPV5
MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5
FBA_D05 FBA_CMD5 100_1206_10P8R_5% 100_1206_10P8R_5%
MDA6 F20 F25 CMDA6
MDA7 E21 FBA_D06 FBA_CMD6 F26 CMDA7 OPT@ OPT@
MDA8 E15 FBA_D07 FBA_CMD7 F23 CMDA8
MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10
1
2
3
4
5
1
2
3
4
5
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12
MDA13 B13 FBA_D12 FBA_CMD12 G25 CMDA13 CMDA11
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14 CMDA4
MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15 CMDA5
MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16 CMDA6
MDA17 C16 FBA_D16 FBA_CMD16 M23 CMDA17
MDA18 A13 FBA_D17 FBA_CMD17 K24 CMDA18
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20
MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21 +VRAM_1.5VS
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23 CMDA22
MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24 CMDA9
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 CMDA21
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26 CMDA24
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27
MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29
10
10
FBA_D29 FBA_CMD29
9
8
7
6
9
8
7
6
MDA30 C20 J27 CMDA30
MDA31 C21 FBA_D30 FBA_CMD30 J26 RPV6 RPV7
MDA32 R22 FBA_D31 FBA_CMD31
FBA_D32 DQMA[3..0] <18,20> 100_1206_10P8R_5% 100_1206_10P8R_5%
MDA33 R24 D19 DQMA0
INTERFACE A
MDA34 T22 FBA_D33 FBA_DQM0 D14 DQMA1 OPT@ OPT@
MDA35 R23 FBA_D34 FBA_DQM1 C17 DQMA2
MDA36 N25 FBA_D35 FBA_DQM2 C22 DQMA3
N26 FBA_D36 FBA_DQM3 P24 DQMA[7..4] <19,21>
MDA37 DQMA4
MEMORY
1
2
3
4
5
1
2
3
4
5
MDA38 N23 FBA_D37 FBA_DQM4 W24 DQMA5
MDA39 N24 FBA_D38 FBA_DQM5 AA25 DQMA6
MDA40 V23 FBA_D39 FBA_DQM6 U25 DQMA7 CMDA23
MDA41 V22 FBA_D40 FBA_DQM7 CMDA13
T23 FBA_D41 F19 DQSA#[3..0] <18,20>
MDA42 DQSA#0 CMDA8
MDA43 U22 FBA_D42 FBA_DQS_RN0 C14 DQSA#1 CMDA10
MDA44 Y24 FBA_D43 FBA_DQS_RN1 A16 DQSA#2
MDA45 AA24 FBA_D44 FBA_DQS_RN2 A22 DQSA#3
Y22 FBA_D45 FBA_DQS_RN3 P25 DQSA#[7..4] <19,21>
1 MDA46 DQSA#4 1
MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5

MDA48 AD27 FBA_D47 FBA_DQS_RN5 AB27 DQSA#6
MDA49 AB25 FBA_D48 FBA_DQS_RN6 T27 DQSA#7 +VRAM_1.5VS
MDA50 AD26 FBA_D49 FBA_DQS_RN7
AC25 FBA_D50 E19 DQSA[3..0] <18,20> RPV9
MDA51 DQSA0 RPV8
MDA52 AA27 FBA_D51 FBA_DQS_WP0 C15 DQSA1 8 1 CMDA26 CMDA28 1 8
MDA53 AA26 FBA_D52 FBA_DQS_WP1 B16 DQSA2 7 2 CMDA25 CMDA27 2 7
30ohms (ESR=0.01) FBA_D53 FBA_DQS_WP2
MDA54 W26 B22 DQSA3 6 3 CMDA27 CMDA25 3 6
MDA55 Y25 FBA_D54 FBA_DQS_WP3 R25 DQSA4 DQSA[7..4] <19,21> 5 4 CMDA28 CMDA26 4 5
+1.05VS_DGPU MDA56 R26 FBA_D55 FBA_DQS_WP4 W23 DQSA5
Close to H22 Close to P22 FBA_D56 FBA_DQS_WP5
LV3 OPT@ MDA57 T25 AB26 DQSA6 100_0804_8P4R_5% 100_0804_8P4R_5%
1 2 +FB_PLLAVDD MDA58 N27 FBA_D57 FBA_DQS_WP6 T26 DQSA7 OPT@ OPT@
FBMA-L11-160808300LMA25T_2P MDA59 R27 FBA_D58 FBA_DQS_WP7 2 1 CMDA29 2 1
FBA_D59
CV20
CV22
CV114
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV21
Place close to BGA MDA60 V26 RV10 100_0402_5% RV11 100_0402_5%

MDA61 V27 FBA_D60 OPT@ OPT@
1 2 1 1 FBA_D61
MDA62 W27 2 1 CMDA30 2 1
MDA63 W25 FBA_D62 RV12 100_0402_5% RV13 100_0402_5%
FBA_D63
OPT@
OPT@
OPT@
D24 OPT@ OPT@

2 1 2 2 FBA_CLK0 CLKA0 <18,20>
OPT@
F16 62mA D25

FB_PLLAVDD_1 FBA_CLK0_N CLKA0# <18,20>
+FB_PLLAVDD P22 62mA
FB_PLLAVDD_2 N22
FBA_CLK1 CLKA1 <19,21>
D23 M22
FB_VREF_PROBE FBA_CLK1_N CLKA1# <19,21>
Near GPU Close to F16
D18
H22 FBA_WCK01 C18
FB_DLLAVDD 35mA FBA_WCK01_N D17
F3 FBA_WCK23 D16
<13,17,41> FB_CLAMP FB_CLAMP FBA_WCK23_N Command Bit Default Pull-down
T24
FBA_WCK45 U24 ODTx 10k
TV1 PAD F22 FBA_WCK45_N V24
TV2 PAD J22 FBA_DEBUG0 FBA_WCK67 V25 DDR3 CKEx 10k
FBA_DEBUG1 FBA_WCK67_N
RST 10k
CS* No Termination
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
CMDA16 RV36 1 OPT@ 2 10K_0402_5%
CMDA19 RV37 1 OPT@ 2 10K_0402_5%
CMDA3 RV38 1 OPT@ 2 10K_0402_5%
CMDA0 RV40 1 OPT@ 2 10K_0402_5%
CMDA20 RV15 1 OPT@ 2 10K_0402_5%

N14x VRAM Interface
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
A
5 4 3 2 1
BINARY STRAPS (for N14M-GL) MULTI LEVEL STRAPS (for N14P-GV2)
Physical Logical Logical Logical Logical

Strap Pin Strap Mapping Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK SMB_ALT_ADDR PD 10k ROM_SO +3VS_DGPU FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE

UV1C
PU 10k if VBIOS ROM exists
Part 3 of 6 F11 ROM_SI SUB_VENDOR PD 10k if no VBIOS ROM
AC3 NC AD10 ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR PCI_DEVID[5] PEX_PLLEN_TERM
AC4 IFPA_TXC NC AD7
Y4 IFPA_TXC_N NC B19
IFPA_TXD0 NC ROM_SO VGA_DEVICE PD 10k (no display)
Y3 V5 ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
AA3 IFPA_TXD0_N NC V6
D IFPA_TXD1 NC STRAP0 RAMCFG[0] D
AA2 G1 STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]
AB1 IFPA_TXD1_N NC G2
IFPA_TXD2 NC STRAP1 RAMCFG[1]
NC
AA1
IFPA_TXD2_N NC
G3 Refer to RVL STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
AA4 G4 STRAP2 RAMCFG[2]
AA5 IFPA_TXD3 NC G5
IFPA_TXD3_N NC G6 STRAP2 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
NC STRAP3 RAMCFG[3]
G7
AB5 NC V1 STRAP3 +3VS_DGPU SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
IFPB_TXC NC STRAP4 PCIE_MAX_SPEED PD 10k
AB4 V2
AB3 IFPB_TXC_N NC W1 STRAP4 +3VS_DGPU RESERVED PCIE_SPEED_CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V
AB2 IFPB_TXD4 NC W2
AD3 IFPB_TXD4_N NC W3
AD2 IFPB_TXD5 NC W4
IFPB_TXD5_N NC Pull-up to +3VS
AE1 SKU Device ID biit5 to bit0 Resistor Values Pull-down to Gnd
AD1 IFPB_TXD6 _DGPU
AD4 IFPB_TXD6_N
IFPB_TXD7
OPT@ 5K 1000 0000
AD5 D11 RV16 1 2 10K_0402_5% N14P-GV2 0x1292 010010
IFPB_TXD7_N BUFRST_N
10K 1001 0001
D10
T2 NC
IFPC_L0 N14M-GL 0x1140 000000 15K 1010 0010
T3 E9
T1 IFPC_L0_N NC
IFPC_L1 20K 1011 0011
R1 E10
R2 IFPC_L1_N NC
25K 1100 0100
GENERAL
IFPC_L2
LVDS/TMDS
R3 F10
N2 IFPC_L2_N NC
IFPC_L3 30K 1101 0101
N3
IFPC_L3_N D1 STRAP0
STRAP0 35K 1110 0110
D2 STRAP1
V3 STRAP1 E4 STRAP2
IFPD_L0 STRAP2 45K 1111 0111
V4 E3 STRAP3
U3 IFPD_L0_N STRAP3 D3 STRAP4
IFPD_L1 STRAP4 MULTI LEVEL STRAPS
C U4 C1 +3VS_DGPU C
T4 IFPD_L1_N NC +3VS_DGPU
T5 IFPD_L2 N14PGV2@
R4 IFPD_L2_N F6 MULTI_STRAP_REF0_GND 1 2
IFPD_L3 MULTI_STRAP_REF0_GND
@ 1
1
@ 1
@ 1
1
10K_0402_1%
10K_0402_1%
10K_0402_1%
45.3K_0402_1%
4.99K_0402_1%
R5 F4 RV17 40.2K_0402_1%
IFPD_L3_N NC
@ 1
1
N14PGV2@
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
F5
@
NC
N14PGV2@
N14PGV2@
N1 +VGA_CORE
NC
RV19
RV18
RV20
RV21
RV22
M1
2
2
2
NC
RV23
RV24
RV25
M2 F12
2
M3 NC THERMDP STRAP0
NC
2
K2 E12 STRAP1 STRAP3 ROM_SI

K3 NC THERMDN RV26 STRAP2 STRAP4 ROM_SO
K1 NC 100_0402_1% ROM_SCLK
J1 NC OPT@
NC
@ 1
1
1
1
4.99K_0402_1%
4.99K_0402_1%
45.3K_0402_1%
45.3K_0402_1%
RV31
1
1
1
1
15K_0402_1%
N14PGV2@
N14PGV2@
N14PGV2@
N14PGV2@
10K_0402_1%
10K_0402_1%
10K_0402_1%
N14MGL@
N14MGL@
N14MGL@
M4 F2 VGA_VCC_SENSE
M5 NC VDD_SENSE VGA_VCC_SENSE <54>
NC 10K_0402_1%
RV27
RV30
RV31
RV28
RV29
L3 trace width: 16mils
2
2
2
NC N14MGL@
RV33
RV32
RV34
L4
differential voltage sensing.
2
2
2
K4 NC
NC
differential signal routing.
K5
J4 NC F1 VGA_VSS_SENSE
NC GND_SENSE VGA_VSS_SENSE <54> For X76 (N14M-GL) For X76 (N14P-GV2)
OPT@
J5 2 1
N4 NC RV35
N5 IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
TEST 100_0402_1% GPU FB Memory gDDR3 ROM_SI GPU FB Memory gDDR3 STRAP[3:0]
B P3 AD9 B
P4 IFPD_AUX_I2CX_SCL TESTMODE AE5 JTAG_TCK TESTMODE <13>
IFPD_AUX_I2CX_SDA_N JTAG_TCK PAD TV3 900MHz K4W2G1646E-BC11 900MHz K4W2G1646E-BC11
AE6 JTAG_TDI Samsung PD 45.3K Samsung 0101
JTAG_TDI PAD TV4
AF6 JTAG_TDO 1 1
JTAG_TDO PAD TV5
J2 AD6 JTAG_TMS 1GHz K4W2G1646E-BC1A 1GHz K4W2G1646E-BC1A
IFPE_AUX_I2CY_SCL JTAG_TMS PAD TV6 2 2
J3 AG4
IFPE_AUX_I2CY_SDA_N JTAG_TRST_N JTAG_TRST <13>
8 8
M Hynix 900MHz H5TQ2G63DFR-11C M Hynix 900MHz H5TQ2G63DFR-11C
H3 PD 34.8K 0110
H4 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N SERIAL 1GHz H5TQ2G63DFR-N0C 1GHz H5TQ2G63DFR-N0C
D12 x x
ROM_CS_N B12 ROM_SI 1 1
ROM_SI A12 ROM_SO
ROM_SO C12 ROM_SCLK
6 6
ROM_SCLK Micron 900MHz MT41K128M16JT-107G PD 30K Micron 900MHz MT41K128M16JT-107G 0001
N14P-GV2 N14M-GL
N14PGV2R3@
Samsung 900MHz K4W4G1646B-HC11 PD 20K Samsung 900MHz K4W4G1646B-HC11 1011
2 2
5 5
6 6
M Micron 900MHz MT41K256M16HA-107G PD 10K M Micron 900MHz MT41K256M16HA-107G 1101
x x
1 1
A 6 6 A

VGA_N14x LVDS&TMDS
Rev
Custom 0.2
5 4 3 2 1
5 4 3 2 1
midway between GPU

Under GPU Near GPU and Power supply +1.05VS_DGPU
+VRAM_1.5VS
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
Under GPU UV1D
OPT@ CV26
OPT@ CV23
OPT@ CV27
OPT@ CV28
OPT@ CV29
OPT@ CV30
OPT@ CV31
1 1 1 1 1 1 1
3500 mA Part 4 of 6 2000 mA
B26 AA10
D FBVDDQ_01 PEX_IOVDDQ_1 D
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
C25 AA12
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
FBVDDQ_02 PEX_IOVDDQ_2 2 2 2 2 2 2 2
OPT@ CV32
OPT@ CV24
OPT@ CV33
OPT@ CV34
OPT@ CV25
OPT@ CV35
1 1 1 1 1 1 E23 AA13
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
2 2 2 2 2 2 G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 +1.05VS_DGPU
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
FBVDDQ_10 PEX_IOVDDQ_10
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
G18 AD24
4.7U_0603_6.3V6K
FBVDDQ_11 PEX_IOVDDQ_11
OPT@ CV40
OPT@ CV36
OPT@ CV37
OPT@ CV38
OPT@ CV39
OPT@ CV41
OPT@ CV42
G19 AE25 1 1 1 1 1 1 1
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26
Near GPU FBVDDQ_13 PEX_IOVDDQ_13
G21 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
FBVDDQ_15 2 2 2 2 2 2 2
22U_0805_6.3V6M
10U_0603_6.3V6M
H26
FBVDDQ_16
OPT@ CV43
OPT@ CV44
1 1 J21 AA22
K21 FBVDDQ_17 PEX_IOVDD_1 AB23
L22 FBVDDQ_18 PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
POWER
2 2 L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27 +3VS_DGPU
N21 FBVDDQ_22 PEX_IOVDD_6
FBVDDQ_23
Under GPU Near GPU
R21
FBVDDQ_24
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
0.1U_0402_10V7K
T21
4.7U_0603_6.3V6K
FBVDDQ_25
OPT@ CV45
OPT@ CV47
OPT@ CV48
OPT@ CV46
OPT@ CV49
V21 1 1 1 1 1
W21 FBVDDQ_26
FBVDDQ_27 G10
VDD33_1 G12
VDD33_2 G8 2 2 2 2 2
VDD33_3 G9
VDD33_4
C V7 Near Ball C
W7 IFPAB_PLLVDD_1
AA6 IFPAB_PLLVDD_2
W6 IFPAB_RSET D22 +FB_CAL_PD_VDDQ 1 2
IFPA_IOVDD FB_CAL_PD_VDDQ +VRAM_1.5VS
Y6 40.2_0402_1% RV39
IFPB_IOVDD OPT@
C24 FB_CAL_PU_GND 2 1
FB_CAL_PU_GND 42.2_0402_1% RV41
OPT@
M7 B25 FB_CAL_TERM_GND 2 1
N7 IFPC_PLLVDD_1 FB_CAL_TERM_GND 51.1_0402_1% RV42
T6 IFPC_PLLVDD_2 OPT@
P6 IFPC_RSET
IFPC_IOVDD
T7 Under GPU
R7 IFPD_PLLVDD_2 +3VS_DGPU
Close to AH12/AG12
U6 IFPD_PLLVDD_1
Near GPU
R6 IFPD_RSET AA8
IFPD_IOVDD PEX_PLL_HVDD_1
0.1U_0402_10V7K
0.1U_0402_10V7K
AA9
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PEX_PLL_HVDD_2
OPT@ CV51
OPT@ CV53
OPT@ CV50
OPT@ CV52
1 1 1 1
AB8
PEX_SVDD_3V3
J7 +1.05VS_DGPU 2 2 2 2
K7 NC LV4
K6 NC 120mA AA14 +PEX_PLLVDD 2 1
NC PEX_PLLVDD_1
0.1U_0402_10V7K
1U_0402_6.3V6K
H6 AA15
4.7U_0603_6.3V6K
BLM18PG121SN1D_0603
NC PEX_PLLVDD_2 N14MGL@
OPT@ CV54
OPT@ CV55
OPT@ CV56
J6 1 1 1
NC
RV1
B 2 1 B
2 2 2 0_0603_5%
N14PGV2@
N14PGV2R3@
Under GPU Near GPU
A A

VGA_N14x POWER
Custom 0.2
5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCP to +1.05VS_DGPU
UV1E +VGA_CORE UV1F +VGA_CORE
A2 Part 5 of 6 K11 Part 6 of 6

A26 GND_001 GND_057 K13
AB11 GND_002 GND_058 K15 K10 V18 +1.05VS_VCCP +5VALW
AB14 GND_003 GND_059 K17 K12 VDD_001 VDD_041 V16
AB17 GND_004 GND_060 L10 K14 VDD_002 VDD_040 V14 +1.05VS_DGPU
GND_005 GND_061 VDD_003 VDD_039
1
AB20 L12 K16 V12 Vgs=4.5V,Id=6.5A,Rds<22mohm
AB24 GND_006 GND_062 L14 K18 VDD_004 VDD_038 V10 RV43
GND_007 GND_063 VDD_005 VDD_037
2
D AC2 L16 L11 U17 270K_0402_5% D
GND_008 GND_064 VDD_006 VDD_036
POWER
AC22 L18 L13 U15 OPT@ QV3 OPT@ RV44
GND_009 GND_065 VDD_007 VDD_035
1
AC26 L2 L15 U13 D OPT@ 22_0805_5%
2
AC5 GND_010 GND_066 L23 L17 VDD_008 VDD_034 U11 2
AC8 GND_011 GND_067 L25 M10 VDD_009 VDD_033 T18 AO3416_SOT23-3 G
1
AD12 GND_012 GND_068 L5 M12 VDD_010 VDD_032 T16 S 1
3
GND_013 GND_069 VDD_011 VDD_031
0.01U_0402_25V7K
AD13 M11 M14 T14
GND_014 GND_070 VDD_012 VDD_030
3
AD15 M13 M16 T12 CV57 OPT@
AD16 GND_015 GND_071 M15 M18 VDD_013 VDD_029 T10 OPT@ QV4A OPT@
AD18 GND_016 GND_072 M17 N11 VDD_014 VDD_028 R17 2 QV4B
AD19 GND_017 GND_073 N10 N13 VDD_015 VDD_027 R15 2 VGA_PWROK# 5
AD21 GND_018 GND_074 N12 N15 VDD_016 VDD_026 R13 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
GND_019 GND_075 VDD_017 VDD_025 +1.05VS_DGPU
AD22 N14 N17 R11
4
AE11 GND_020 GND_076 N16 P10 VDD_018 VDD_024 P18
AE14 GND_021 GND_077 N18 P12 VDD_019 VDD_023 P16 +5VALW
AE17 GND_022 GND_078 P11 VDD_020 VDD_022 P14
AE20 GND_023 GND_079 P13 VDD_021 1 2
AF1 GND_024 GND_080 P15 100K_0402_5% RV45
AF11 GND_025 GND_081 P17
GND
GND_026 GND_082 OPT@
6
AF14 P2 QV5A D
AF17 GND_027 GND_083 P23 VGA_PWROK 2
AF20 GND_028 GND_084 P26 G
AF23 GND_029 GND_085 P5 2N7002KDWH_SOT363-6
AF5 GND_030 GND_086 R10 OPT@ S
1
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N14P-GV2-S-A2_FCBGA595
B1 GND_034 GND_090 R18 N14PGV2R3@
B11 GND_035 GND_091 T11
B14 GND_036 GND_092 T13
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
C B23
B27
GND_039
GND_040
GND_095
GND_096
U10
U12
+1.5V to +VRAM_1.5VS C
B5 GND_041 GND_097 U14

B8 GND_042 GND_098 U16 +1.5V +VRAM_1.5VS
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047
GND_048
GND_103
GND_104
U5 For GC6 +3VS QV6 OPT@ Vgs=10V,Id=14.5A,Rds=6mohm
2
E22 V11 8 1
E25 GND_049 GND_105 V13 7 D S 2 RV46
E5 GND_050 GND_106 V15 6 D S 3 470_0805_5%
E8 GND_051 GND_107 V17 5 D S 4 OPT@ OPT@
H2 GND_052 GND_108 Y2 D G RV47
1
H23 GND_053 GND_109 Y23 FDS6676AS_SO8 VRAM_1.5VS_GATE 1 2
GND_054 GND_110 B+
H25 Y26 1 1 180K_0402_5%
GND_055 GND_111
1
5
3
0.01U_0402_25V7K
H5 Y5
4.7U_0603_6.3V6K
UV2 N14PGV2@
GND_056 GND_112 2 CV59 CV60 RV48 QV7A
G Vcc
<13,14,41> FB_CLAMP B 4 1.5V_PWR_EN OPT@ OPT@ OPT@ 820K_0402_5% QV7B
1 Y 2 2 2 1.5V_PWR_EN# 5 2N7002DW-T/R7_SOT363-6
<30,54> VGA_PWROK A 2N7002DW-T/R7_SOT363-6 OPT@
2
AA7 NC7SZ32P5X_SC70-5 OPT@
4
GND AB7 +5VALW
GND
1 2
1 2 100K_0402_5% RV49
RV50 0_0402_5% OPT@
N14P-GV2-S-A2_FCBGA595 N14MGL@
3
N14PGV2R3@ QV5B D
1.5V_PWR_EN 5
G
2N7002KDWH_SOT363-6
B OPT@ S B
4
+3VS to +3VS_DGPU
+3VS
+3VS_DGPU +VGA_CORE +3VS
2
2
RV51 RV52 2 Vgs=-4.5V,Id=3A,Rds<97mohm
470_0805_5% 470_0805_5% RV53 CV61
OPT@ OPT@ OPT@ 10K_0402_5% 0.1U_0402_10V7K
OPT@
3 1
3 1
1
3
S
RV54 QV11
G
DGPU_PWR_EN# 1 2 2 OPT@
QV9B QV2B
2N7002DW-T/R7_SOT363-6 5 DGPU_PWR_EN# 5 2N7002DW-T/R7_SOT363-6 33K_0402_5% 2 AO3413_SOT23 D
1
6
OPT@ OPT@ OPT@
QV9A CV62 +3VS_DGPU
4
OPT@ 0.01U_0402_25V7K
2 1
<29> DGPU_PWR_EN
2N7002DW-T/R7_SOT363-6
OPT@
1
A A

VGA_N14x POWER & GND
Custom 0.2
5 4 3 2 1
5 4 3 2 1
RANK 0 [31...0] Rank 0 Rank 1

Mode E
VRAM DDR3 Chips Address
CMD0
0..31
ODT
32..63 0..31
ODT
32..63
CMD1 CS1#
CMD2 CS0#
CMD3 CKE CKE
DQSA[3..0]
<14,20> DQSA[3..0]
CMD4 A9 A9 A11 A11
D DQSA#[3..0] D
<14,20> DQSA#[3..0]
CMD5 A6 A6 A7 A7
DQMA[3..0] UV3 @ UV4 @
<14,20> DQMA[3..0]
CMD6 A3 A3 BA1 BA1
MDA[31..0] +MEM_VREF_CA0 M8 E3 MDA9 +MEM_VREF_CA0 M8 E3 MDA6
<14,20> MDA[31..0] +MEM_VREF_DQ0 H1 VREFCA DQL0 F7 MDA12 +MEM_VREF_DQ0 H1 VREFCA DQL0 F7 MDA1
VREFDQ DQL1 VREFDQ DQL1 CMD7 A0 A0 A12 A12
CMDA[30..0] F2 MDA8 F2 MDA5
4,19,20,21> CMDA[30..0] CMDA7 N3 DQL2 F8 MDA15 CMDA7 N3 DQL2 F8 MDA0 Group0
A0 DQL3 A0 DQL3 CMD8 A8 A8 A8 A8
CMDA10 P7 H3 MDA13 Group1 CMDA10 P7 H3 MDA4
CMDA24 P3 A1 DQL4 H8 MDA11 CMDA24 P3 A1 DQL4 H8 MDA2
CMDA6 N2 G2 MDA10 CMDA6 N2 G2 MDA7
CMDA22 P8 A3 DQL6 H7 MDA14 CMDA22 P8 A3 DQL6 H7 MDA3
CMDA26 P2 CMDA26 P2
+VRAM_1.5VS CMDA5 R8 A5 CMDA5 R8 A5
A6 A6 CMD11 RAS# RAS# RAS# RAS#
CMDA21 R2 D7 MDA18 CMDA21 R2 D7 MDA30
CMDA8 T8 A7 DQU0 C3 MDA22 CMDA8 T8 A7 DQU0 C3 MDA26
A8 DQU1 A8 DQU1 CMD12 A13 A13 A14 A14
1
CMDA4 R3 C8 MDA16 CMDA4 R3 C8 MDA29

CMDA25 L7 A9 DQU2 C2 MDA23 CMDA25 L7 A9 DQU2 C2 MDA24 Group3
RV55
A10/AP DQU3 A10/AP DQU3 CMD13 BA1 BA1 A3 A3
1K_0402_1% CMDA23 R7 A7 MDA17 Group2 CMDA23 R7 A7 MDA28
CMDA9 N7 A11 DQU4 A2 MDA20 CMDA9 N7 A11 DQU4 A2 MDA27
OPT@
CMDA12 T3 B8 MDA19 CMDA12 T3 B8 MDA31
2
+MEM_VREF_CA0 CMDA14 T7 A13 DQU6 A3 MDA21 CMDA14 T7 A13 DQU6 A3 MDA25

+MEM_VREF_CA0 A14 DQU7 A14 DQU7 CMD15 CAS# CAS# CAS# CAS#
M7 M7
A15/BA3 A15/BA3
1
+VRAM_1.5VS +VRAM_1.5VS CMD16 ODT ODT

1
RV56 CV63
1K_0402_1% 0.01U_0402_25V7K CMDA29 M2 B2 CMDA29 M2 B2 CMD17 CS1#
OPT@ OPT@ CMDA13 N8 BA0 VDD D9 CMDA13 N8 BA0 VDD D9
2 CMDA27 M3 BA1 VDD G7 CMDA27 M3 BA1 VDD G7 CMD18 CS0#
2
BA2 VDD K2 BA2 VDD K2

VDD K8 VDD K8
VDD VDD CMD19 CKE CKE
N1 N1
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9
C CK VDD CK VDD CMD20 RST RST RST RST C
CLKA0# K7 R1 CLKA0# K7 R1
CMDA3 K9 CK VDD R9 CMDA3 K9 CK VDD R9
+VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS
CMD21 A7 A7 A6 A6
CMD22 A4 A4 A5 A5
CMDA0 K1 A1 CMDA0 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
1
CMDA2 L2 A8 CMDA2 L2 A8 CMD23 A11 A11 A9 A9

RV57 CMDA11 J3 CS/CS0 VDDQ C1 CMDA11 J3 CS/CS0 VDDQ C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
1K_0402_1%
CAS VDDQ CAS VDDQ CMD24 A2 A2 A1 A1
OPT@ CMDA28 L3 D2 CMDA28 L3 D2
WE VDDQ E9 WE VDDQ E9
310mAVDDQ CMD25 A10 A10 WE# WE#
2
+MEM_VREF_DQ0 F1 VDDQ F1
+MEM_VREF_DQ0
DQSA1 F3 VDDQ H2 DQSA0 F3
310mAVDDQ H2
DQSL VDDQ DQSL VDDQ CMD26 A5 A5 A4 A4
1
1 DQSA2 C7 H9 DQSA3 C7 H9
DQSU VDDQ DQSU VDDQ
RV58 CV64 CMD27 BA2 BA2
1K_0402_1% 0.01U_0402_25V7K
OPT@ OPT@ DQMA1 E7 A9 DQMA0 E7 A9 CMD28 WE# WE# A10 A10
2 DQMA2 D3 DML VSS B3 DQMA3 D3 DML VSS B3
2
DMU VSS E1 DMU VSS E1

VSS VSS CMD29 BA0 BA0 BA0 BA0
G8 G8
DQSA#1 G3 VSS J2 DQSA#0 G3 VSS J2
DQSL VSS DQSL VSS CMD30 BA2 BA2
DQSA#2 B7 J8 DQSA#3 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
CMDA20 T2 VSS P9 CMDA20 T2 VSS P9
RESET VSS T1 RESET VSS T1
ZQ0 L8 VSS T9 ZQ1 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
OPT@ J1 B1 OPT@ J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV60 RV61 Place close to the first T point
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
B L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 B
2
2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ E8 VSSQ E8 <14,20> CLKA0
VSSQ VSSQ
1
F9 F9
VSSQ G1 VSSQ G1 OPT@
VSSQ G9 VSSQ G9 RV63
VSSQ VSSQ 160_0402_1%
96-BALL 96-BALL
2
SDRAM DDR3 SDRAM DDR3
<14,20> CLKA0#
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
Place close to RANK0 VRAM
+VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS
22U_0805_6.3V6M
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
OPT@ CV75
OPT@ CV77
OPT@ CV67
OPT@ CV68
OPT@ CV70
OPT@ CV71
OPT@ CV73
OPT@ CV74
OPT@ CV76
OPT@ CV78
OPT@ CV79
OPT@ CV80
OPT@ CV83
OPT@ CV84
OPT@ CV85
OPT@ CV86
OPT@ CV87
OPT@ CV69
OPT@ CV72
OPT@ CV81
OPT@ CV82
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

VGA_N14x VRAM RANK 0L
5 4 3 2 1
5 4 3 2 1

Mode E
CMD0
0..31
ODT
32..63 0..31
ODT
32..63
CMD1 CS1#
CMD2 CS0#
DQSA[7..4] CMD3 CKE CKE
<14,21> DQSA[7..4]
DQSA#[7..4] CMD4 A9 A9 A11 A11
D <14,21> DQSA#[7..4] D
DQMA[7..4] UV5 @ UV6 @ CMD5 A6 A6 A7 A7
<14,21> DQMA[7..4]
MDA[63..32] +MEM_VREF_CA1 M8 E3 MDA35 +MEM_VREF_CA1 M8 E3 MDA45 CMD6 A3 A3 BA1 BA1
<14,21> MDA[63..32] +MEM_VREF_DQ1 H1 VREFCA DQL0 F7 MDA37 +MEM_VREF_DQ1 H1 VREFCA DQL0 F7 MDA41
CMDA[30..0] VREFDQ DQL1 F2 MDA32 VREFDQ DQL1 F2 MDA46
<14,18,20,21> CMDA[30..0] DQL2 DQL2 CMD7 A0 A0 A12 A12
CMDA7 N3 F8 MDA36 CMDA7 N3 F8 MDA40
CMDA10 P7 A0 DQL3 H3 MDA33 Group4 CMDA10 P7 A0 DQL3 H3 MDA44 Group5
CMDA24 P3 H8 MDA38 CMDA24 P3 H8 MDA43
CMDA6 N2 A2 DQL5 G2 MDA34 CMDA6 N2 A2 DQL5 G2 MDA47
CMDA22 P8 H7 MDA39 CMDA22 P8 H7 MDA42
CMDA26 P2 A4 DQL7 CMDA26 P2 A4 DQL7
A5 A5 CMD10 A1 A1 A2 A2
CMDA5 R8 CMDA5 R8
+VRAM_1.5VS CMDA21 R2 A6 D7 MDA58 CMDA21 R2 A6 D7 MDA54
A7 DQU0 A7 DQU0 CMD11 RAS# RAS# RAS# RAS#
CMDA8 T8 C3 MDA62 CMDA8 T8 C3 MDA50
CMDA4 R3 A8 DQU1 C8 MDA56 CMDA4 R3 A8 DQU1 C8 MDA55
1
CMDA25 L7 C2 MDA63 CMDA25 L7 C2 MDA48

CMDA23 R7 A10/AP DQU3 A7 MDA57 Group7 CMDA23 R7 A10/AP DQU3 A7 MDA53 Group6
RV59
A11 DQU4 A11 DQU4 CMD13 BA1 BA1 A3 A3
1K_0402_1% CMDA9 N7 A2 MDA61 CMDA9 N7 A2 MDA51
CMDA12 T3 A12 DQU5 B8 MDA59 CMDA12 T3 A12 DQU5 B8 MDA52
OPT@
CMDA14 T7 A3 MDA60 CMDA14 T7 A3 MDA49
2
+MEM_VREF_CA1 M7 A14 DQU7 M7 A14 DQU7

+MEM_VREF_CA1 A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD15 CAS# CAS# CAS# CAS#
1
1 CMD16 ODT ODT

RV62 CV65 CMDA29 M2 B2 CMDA29 M2 B2
CMDA13 N8 BA0 VDD D9 CMDA13 N8 BA0 VDD D9
1K_0402_1% 0.01U_0402_25V7K
BA1 VDD BA1 VDD CMD17 CS1#
OPT@ OPT@ CMDA27 M3 G7 CMDA27 M3 G7
2 BA2 VDD K2 BA2 VDD K2 CMD18 CS0#
2
VDD K8 VDD K8
VDD N1 VDD N1
VDD VDD CMD19 CKE CKE
CLKA1 J7 N9 CLKA1 J7 N9
CLKA1# K7 CK VDD R1 CLKA1# K7 CK VDD R1
C CK VDD CK VDD CMD20 RST RST RST RST C
CMDA19 K9 R9 CMDA19 K9 R9
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS
+VRAM_1.5VS
CMD21 A7 A7 A6 A6
CMDA16 K1 A1 CMDA16 K1 A1 CMD22 A4 A4 A5 A5
CMDA18 L2 ODT/ODT0 VDDQ A8 CMDA18 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ
1
CMDA11 J3 C1 CMDA11 J3 C1 CMD23 A11 A11 A9 A9

RV64 CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CMDA28 L3 CAS VDDQ D2 CMDA28 L3 CAS VDDQ D2
1K_0402_1%
WE VDDQ WE VDDQ CMD24 A2 A2 A1 A1
OPT@ 310mAVDDQ E9 310mAVDDQ E9
F1 F1 CMD25 A10 A10 WE# WE#
2
+MEM_VREF_DQ1 DQSA4 F3 VDDQ H2 DQSA5 F3 VDDQ H2

+MEM_VREF_DQ1 DQSL VDDQ DQSL VDDQ
DQSA7 C7 H9 DQSA6 C7 H9 CMD26 A5 A5 A4 A4
DQSU VDDQ DQSU VDDQ
1
1
RV65 CV66 CMD27 BA2 BA2
1K_0402_1% 0.01U_0402_25V7K DQMA4 E7 A9 DQMA5 E7 A9
DQMA7 D3 DML VSS B3 DQMA6 D3 DML VSS B3
OPT@
2
OPT@
DMU VSS DMU VSS CMD28 WE# WE# A10 A10
E1 E1
2
VSS G8 VSS G8
VSS VSS CMD29 BA0 BA0 BA0 BA0
DQSA#4 G3 J2 DQSA#5 G3 J2
DQSA#7 B7 DQSL VSS J8 DQSA#6 B7 DQSL VSS J8
DQSU VSS DQSU VSS CMD30 BA2 BA2
M1 M1
VSS M9 VSS M9
VSS P1 VSS P1
1
1
OPT@
OPT@ J1 B1 RV72 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV71
NC/CS1 VSSQ
243_0402_1%
NC/CS1 VSSQ
Place close to the first T point
243_0402_1% J9 D1 J9 D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
2
2
B NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 B
VSSQ E8 VSSQ E8 <14,21> CLKA1
VSSQ VSSQ
1
F9 F9
VSSQ G1 VSSQ G1 OPT@
VSSQ G9 VSSQ G9 RV74
VSSQ VSSQ 160_0402_1%
96-BALL 96-BALL
2
<14,21> CLKA1#
Place close to RANK1 VRAM
+VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS
22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
OPT@ CV109
OPT@ CV100
OPT@ CV101
OPT@ CV103
OPT@ CV104
OPT@ CV105
OPT@ CV106
OPT@ CV108
OPT@ CV111
DRANK@ CV112
OPT@ CV102
OPT@ CV107
OPT@ CV110
OPT@ CV93
OPT@ CV92
OPT@ CV95
OPT@ CV97
OPT@ CV98
OPT@ CV99
OPT@ CV94
OPT@ CV96
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

VGA_N14x VRAM RANK 0H
5 4 3 2 1
5 4 3 2 1

Mode E
CMD0
0..31
ODT
32..63 0..31
ODT
32..63
CMD1 CS1#
CMD2 CS0#
CMD3 CKE CKE
DQSA[3..0]
<14,18> DQSA[3..0]
CMD4 A9 A9 A11 A11
D DQSA#[3..0] D
<14,18> DQSA#[3..0]
CMD5 A6 A6 A7 A7
DQMA[3..0]
<14,18> DQMA[3..0]
CMD6 A3 A3 BA1 BA1
MDA[31..0]
<14,18> MDA[31..0]
DRANK@ CMD7 A0 A0 A12 A12
CMDA[30..0] 0.01U_0402_25V7K
<14,18,19,21> CMDA[30..0] 2 1 UV7 @ UV8 @ CMD8 A8 A8 A8 A8
CV88
M8 E3 MDA12 M8 E3 MDA1 CMD9 A12 A12 A0 A0
+MEM_VREF_CA0 +MEM_VREF_CA0
H1 VREFCA DQL0 F7 MDA9 H1 VREFCA DQL0 F7 MDA6
+MEM_VREF_DQ0 VREFDQ DQL1 +MEM_VREF_DQ0 VREFDQ DQL1
F2 MDA15 F2 MDA0 CMD10 A1 A1 A2 A2
CMDA9 N3 DQL2 F8 MDA8 CMDA9 N3 DQL2 F8 MDA5
1
CMDA24 P7 A0 DQL3 H3 MDA14 Group1 CV89 CMDA24 P7 A0 DQL3 H3 MDA3 Group0 CMD11 RAS# RAS# RAS# RAS#
CMDA10 P3 A1 DQL4 H8 MDA10 0.01U_0402_25V7K CMDA10 P3 A1 DQL4 H8 MDA7
CMDA13 N2 A2 DQL5 G2 MDA11 DRANK@ CMDA13 N2 A2 DQL5 G2 MDA2 CMD12 A13 A13 A14 A14
CMDA26 P8 A3 DQL6 H7 MDA13 2 CMDA26 P8 A3 DQL6 H7 MDA4
CMD13 BA1 BA1 A3 A3
CMDA21 R8 A5 CMDA21 R8 A5
CMDA5 R2 A6 D7 MDA22 CMDA5 R2 A6 D7 MDA26 CMD14 A14 A14 A13 A13
CMDA23 R3 A8 DQU1 C8 MDA23 CMDA23 R3 A8 DQU1 C8 MDA24
DQU2 CMD15 CAS# CAS# CAS# CAS#
CMDA28 L7 A9 DQU2 C2 MDA16 CMDA28 L7 A9 C2 MDA29
CMDA4 R7 A10/AP DQU3 A7 MDA21 Group2 CMDA4 R7 A10/AP DQU3 A7 MDA25 Group3
DQU4 CMD16 ODT ODT
CMDA7 N7 A11 DQU4 A2 MDA19 CMDA7 N7 A11 A2 MDA31
CMDA14 T3 A12 DQU5 B8 MDA20 CMDA14 T3 A12 DQU5 B8 MDA27 CMD17 CS1#
CMDA12 T7 A13 DQU6 A3 MDA17 CMDA12 T7 A13 DQU6 A3 MDA28
M7 A14 DQU7 M7 A14 DQU7
CMD18 CS0#
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD19 CKE CKE
CMDA29 M2 B2 CMDA29 M2 B2
CMDA6 N8 BA0 VDD D9 CMDA6 N8 BA0 VDD D9
C BA1 VDD BA1 VDD CMD20 RST RST RST RST C
CMDA30 M3 G7 CMDA30 M3 G7
VDD VDD CMD21 A7 A7 A6 A6
K8 K8
VDD N1 VDD N1
J7 N9 CLKA0 J7 N9
<14,18> CLKA0 K7 CK VDD R1 CLKA0# K7 CK VDD R1
<14,18> CLKA0# CK VDD CK VDD CMD23 A11 A11 A9 A9
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS CMD24 A2 A2 A1 A1
CMDA0 K1 A1 CMDA0 K1 A1 CMD25 A10 A10 WE# WE#
CMDA11 J3 CS/CS0 VDDQ C1 CMDA11 J3 CS/CS0 VDDQ C1
RAS VDDQ RAS VDDQ CMD26 A5 A5 A4 A4
CMDA15 K3 C9 CMDA15 K3 C9
WE VDDQ WE VDDQ CMD27 BA2 BA2
E9 E9
310mAVDDQ F1
310mAVDDQ F1
VDDQ VDDQ CMD28 WE# WE# A10 A10
DQSA1 F3 H2 DQSA0 F3 H2
DQSA2 C7 DQSL VDDQ H9 DQSA3 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ CMD29 BA0 BA0 BA0 BA0
CMD30 BA2 BA2
DQMA1 E7 A9 DQMA0 E7 A9
VSS G8 VSS G8
VSS M9 VSS M9
VSS P1 VSS P1
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
1
1
J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 RV78 L1 NC/ODT1 VSSQ B9
RV77 J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
2
NCZQ1 VSSQ E2 DRANK@ NCZQ1 VSSQ E2
2
DRANK@ VSSQ E8 VSSQ E8

VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
A A

VGA_N14x VRAM RANK 1L
Rev
Custom 0.2
5 4 3 2 1
5 4 3 2 1
Rank 0 Rank 1
RANK 1 [63...32] Mode E
0..31 32..63 0..31 32..63
Address
VRAM DDR3 Chips CMD0

CMD1
ODT ODT
CS1#
CMD2 CS0#
CMD3 CKE CKE
DQSA[7..4]
<14,19> DQSA[7..4]
CMD4 A9 A9 A11 A11
DQSA#[7..4]
D <14,19> DQSA#[7..4] D
CMD5 A6 A6 A7 A7
DQMA[7..4]
<14,19> DQMA[7..4]
CMD6 A3 A3 BA1 BA1
MDA[63..32]
<14,19> MDA[63..32]
CMD7 A0 A0 A12 A12
CMDA[30..0]
4,18,19,20> CMDA[30..0]
DRANK@ CMD8 A8 A8 A8 A8
0.01U_0402_25V7K
2 1 UV9 @ UV10 @ CMD9 A12 A12 A0 A0
CV90
M8 E3 MDA37 M8 E3 MDA41 CMD10 A1 A1 A2 A2
+MEM_VREF_CA1 +MEM_VREF_CA1
H1 VREFCA DQL0 F7 MDA35 H1 VREFCA DQL0 F7 MDA45
+MEM_VREF_DQ1 VREFDQ DQL1 +MEM_VREF_DQ1 VREFDQ DQL1
F2 MDA36 F2 MDA40 CMD11 RAS# RAS# RAS# RAS#
CMDA9 N3 DQL2 F8 MDA32 CMDA9 N3 DQL2 F8 MDA46
1
CMDA24 P7 A0 DQL3 H3 MDA39 Group4 CV91 CMDA24 P7 A0 DQL3 H3 MDA42 Group5 CMD12 A13 A13 A14 A14
CMDA10 P3 A1 DQL4 H8 MDA34 0.01U_0402_25V7K CMDA10 P3 A1 DQL4 H8 MDA47
CMDA13 N2 A2 DQL5 G2 MDA38 DRANK@ CMDA13 N2 A2 DQL5 G2 MDA43 CMD13 BA1 BA1 A3 A3
CMDA26 P8 A3 DQL6 H7 MDA33 2 CMDA26 P8 A3 DQL6 H7 MDA44
CMD14 A14 A14 A13 A13
CMDA21 R8 A5 CMDA21 R8 A5
CMDA5 R2 A6 D7 MDA62 CMDA5 R2 A6 D7 MDA50 CMD15 CAS# CAS# CAS# CAS#
CMDA23 R3 A8 DQU1 C8 MDA63 CMDA23 R3 A8 DQU1 C8 MDA48 CMD16 ODT ODT
CMDA28 L7 A9 DQU2 C2 MDA56 CMDA28 L7 A9 DQU2 C2 MDA55
CMDA4 R7 A10/AP DQU3 A7 MDA60 Group7 CMDA4 R7 A10/AP DQU3 A7 MDA49 Group6 CMD17 CS1#
CMDA7 N7 A11 DQU4 A2 MDA59 CMDA7 N7 A11 DQU4 A2 MDA52
CMDA14 T3 A12 DQU5 B8 MDA61 CMDA14 T3 A12 DQU5 B8 MDA51 CMD18 CS0#
CMDA12 T7 A13 DQU6 A3 MDA57 CMDA12 T7 A13 DQU6 A3 MDA53
M7 A14 DQU7 M7 A14 DQU7
CMD19 CKE CKE
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD20 RST RST RST RST
CMDA29 M2 B2 CMDA29 M2 B2
C CMDA6 N8 BA0 VDD D9 CMDA6 N8 BA0 VDD D9 C
BA1 VDD BA1 VDD CMD21 A7 A7 A6 A6
CMDA30 M3 G7 CMDA30 M3 G7
K8 K8
VDD N1 VDD N1
J7 N9 CLKA1 J7 N9
<14,19> CLKA1 K7 CK VDD R1 CLKA1# K7 CK VDD R1
<14,19> CLKA1# CK VDD CK VDD CMD24 A2 A2 A1 A1
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS CMD25 A10 A10 WE# WE#
CMDA16 K1 A1 CMDA16 K1 A1 CMD26 A5 A5 A4 A4
CMDA11 J3 CS/CS0 VDDQ C1 CMDA11 J3 CS/CS0 VDDQ C1
RAS VDDQ RAS VDDQ CMD27 BA2 BA2
CMDA15 K3 C9 CMDA15 K3 C9
WE VDDQ WE VDDQ CMD28 WE# WE# A10 A10
310mAVDDQ E9 E9
F1 VDDQ F1
VDDQ 310mAVDDQ CMD29 BA0 BA0 BA0 BA0
DQSA4 F3 H2 DQSA5 F3 H2
DQSA7 C7 DQSL VDDQ H9 DQSA6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ CMD30 BA2 BA2
DQMA4 E7 A9 DQMA5 E7 A9
VSS G8 VSS G8
VSS M9 VSS M9
VSS P1 VSS P1
B ZQ6 L8 VSS T9 ZQ7 L8 VSS T9 B
1
1
J1 B1 J1 B1
RV79 L1 NC/ODT1 VSSQ B9 RV80 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
DRANK@ L9 NC/CE1 VSSQ D8 DRANK@ L9 NC/CE1 VSSQ D8
2
2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
A A

VGA_N14x VRAM RANK 1H
Rev
Custom 0.2
5 4 3 2 1
A B C D E
For eDP Panel LCD POWER CIRCUIT

CAM_EMI@ eDP&LVDS both 3V power rail
USB20_N11_R 1 2 USB20_N11 <29>
1 2
+3VS
IEDP@ USB20_P11_R 4 3 USB20_P11 <29>
C890 1 20.1U_0402_10V7K LVDS_EDID_CLK 4 3 +LCD_VDD
<6> H_EDP_AUXP
IEDP@
W=60mils W=60mils
L55 WCM-2012-900T_0805 U16
C891 1 20.1U_0402_10V7K LVDS_EDID_DATA 1.5A 1 +LCD_VDD_OUT 1 Rshort@ 2 I rush=1.5A
<6> H_EDP_AUXN VOUT
IEDP@ Reserve for EMI request 5 R106 0_0805_5%
1 C912 1 20.1U_0402_10V7K LVDS_TXOUT0+ VIN 1
<6> H_EDP_TXP0
IEDP@ 2
C913 1 20.1U_0402_10V7K LVDS_TXOUT0- +LCD_VDD_SS 4 GND
<6> H_EDP_TXN0 SS
IEDP@
C914 1 20.1U_0402_10V7K LVDS_TXOUT1+ 1 2 3
<6> H_EDP_TXP1 EN
IEDP@ R267 0_0402_5%
1
C915 1 20.1U_0402_10V7K LVDS_TXOUT1- @TOUCH_EMI@ APL3512ABI-TRG_SOT23-5
<6> H_EDP_TXN1
C7
TOUCH_EMI@ 0.015U_0402_50V7K
2
USB20_P8_R 1 2 USB20_P8 <29>
1 2
<28> LCD_ENVDD
2
USB20_N8_R 4 3 USB20_N8 <29>
4 3 R112
L57 WCM-2012-900T_0805 100K_0402_5%
1 2
1
R266 0_0402_5%
@TOUCH_EMI@
Reserve for EMI request
For LVDS 1ch Panel LVDS colay eDP cable

1 LVDS@ 2 LVDS_TXOUT0+
<28> LCD_TXOUT0+
R262 0_0402_5%
2 1 LVDS@ 2 LVDS_TXOUT0- 2
<28> LCD_TXOUT0-
R263 0_0402_5%
1 LVDS@ 2 LVDS_TXOUT1+ +5VS
<28> LCD_TXOUT1+
R265 0_0402_5%
1 LVDS@ 2 LVDS_TXOUT1- JLVDS
<28> LCD_TXOUT1-
R264 0_0402_5% 1 +5VS_LVDS_TOUCH 1 Rshort@ 2 20mils
<28> LCD_TXOUT2+
LCD_TXOUT2+ pin1-4 Touch function for panel 1 2 USB20_N8_R R390 0_0603_5%
2 3 USB20_P8_R
LCD_TXOUT2- 3 4 BKOFF#
<28> LCD_TXOUT2- 4 5 INT_MIC_DATA
LCD_TXCLK+ 5 6 INT_MIC_CLK INT_MIC_DATA <39>
<28> LCD_TXCLK+ pin5-10 For Webcam with single or dual MIC 6 7 INT_MIC_CLK <39>
LCD_TXCLK- 7 8 USB20_P11_R +3VS
<28> LCD_TXCLK- 8 9 USB20_N11_R
1 LVDS@ 2 LVDS_EDID_CLK 9 10 +3VS_LVDS_CAM 1 Rshort@ 2
<28> LCD_EDID_CLK 10 20mils
R300 0_0402_5% 11 +LCD_VDD R389 0_0603_5%
1 LVDS@ 2 LVDS_EDID_DATA 11 12 +3VS
<28> LCD_EDID_DATA pin11-30 For LVDS or EDP panel 12 +LCD_VDD Irush=1.5A 60mils
R299 0_0402_5% 13 +3VS
13 14 LVDS_EDID_CLK
14 15 LVDS_EDID_DATA
15 16 LVDS_TXOUT0-
16 17 LVDS_TXOUT0+
17 18 LVDS_TXOUT1-
18 19 LVDS_TXOUT1+
19 20 LCD_TXOUT2-
20 21 LCD_TXOUT2+
21 22
22 23 LCD_TXCLK-
23 24 LCD_TXCLK+
24 25
25 26 LED_PWM CPU_EDP_HPD <6>
26 27 BKOFF#_R
3 27 28 3
28 29
29 30
30 +LCD_INV Irush=1.5A 60mils
31
GND 32
GND 33
GND 34
GND 35
GND B+
Irush=1.5A 60mils
Conn@ +LCD_INV
L2
Reserve for eDP panel potential issue 2 1
FBMA-L11-201209-221LMA30T_0805
+3VS EMI@
IEDP@1 2 IEDP@
5
R103 0_0402_5% U17 LED_PWM 1 2

PCH_PWM <28>
1 RB751V40_SC76-2 D17
P
BKOFF#_R 1 2 4 IN1 EC_ENBKL <28,41>

D15 RB751V40_SC76-2 O 2
IN2 BKOFF# <41>
G
1
LVDS@
1
R131
3
R113 SN74AHC1G08DCKR_SC70-5 47K_0402_5%

10K_0402_5%
2
2
1 2
R147 0_0402_5%
4 LVDS@ 4

LVDS
Rev
Custom 0.2
VFKAA
A B C D E
A B C D E
CRT CONNECTOR
1 1
T65, T66: for ATE

L3 1 2 NBQ100505T-800Y_0402 CRT_R_L JCRT
<28> UMA_CRT_R
CRT_EMI@ 6
L4 1 2 NBQ100505T-800Y_0402 CRT_G_L 11
<28> UMA_CRT_G T65 PAD
CRT_EMI@ CRT_R_L 1
L5 1 2 NBQ100505T-800Y_0402 CRT_B_L 7
<28> UMA_CRT_B
CRT_EMI@ CRT_DDC_DAT 12
CRT_G_L 2
CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ 8
HSYNC 13
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
R138 R139 R140 CRT_B_L 3
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1 9
+HDMI_5V_OUT
1
VSYNC 14 16
G
C238 C239 C240 C241 C242 C243 4 17
T66 PAD G
10
2 2 2 2 2 2 CRT_DDC_CLK 15
USE HDMI POWER 5
2
C-H_13-12201513CP
Conn@
2 2
CRT@
U49 +HDMI_5V_OUT
1 8 1 2
+HDMI_5V_OUT VCC_SYNC BYP C15 0.22U_0402_16V7K
2 3 CRT_R_L
+3VS VCC_VIDEO VIDEO1
2
7 4 CRT_G_L R153 R159
+3VS VCC_DDC VIDEO2 4.7K_0402_5% 4.7K_0402_5%
<28> UMA_CRT_DATA 10 5 CRT_B_L CRT@ CRT@
1
DDC_IN1 VIDEO3
3 3
<28> UMA_CRT_CLK 11 9 CRT_DDC_DAT

DDC_IN2 DDC_OUT1
13 12 CRT_DDC_CLK
<28> UMA_CRT_VSYNC SYNC_IN1 DDC_OUT2
R62 CRT@
15 14 VSYNC_R 1 2 22_0402_5% VSYNC
<28> UMA_CRT_HSYNC SYNC_IN2 SYNC_OUT1
R63
6 16 HSYNC_R 1 CRT@ 2 22_0402_5% HSYNC
GND SYNC_OUT2
TPD7S019-15DBQR_SSOP16
CRT@
4 4

CRT
Size
Document Number Rev
0.2
VFKAA
A B C D E
A B C D E
OE# A Y
RPY1
1 8 UMA_HDMI_CLK L L L
+3VS
2 7 UMA_HDMI_DATA
+HDMI_5V_OUT
3
4
6
5
HDMI_SCLK
HDMI_SDATA
L H H HDMI POWER CIRCUIT
H X Z VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
2.2K_0804_8P4R_5%
Current Limit: TYP=0.8A ; MAX=1A
1 1
+HDMI_5V_OUT
RY1
HDMI_HPD_U 1 2 HDMI_HPD_C +HDMI_5V_OUT
+3VS 1K_0402_5% UY2
2 1 5
OUT IN +5VS
2
RY2 CY4
100K_0402_5% 0.1U_0402_10V7K 2
1 GND
1
UY1 CY18
1 3 4
OE#
P
2 4 HDMI_HPD 0.1U_0402_10V7K FLG EN
1
A Y 2 AP2151DWG-7_SOT25-5
G
74AHCT1G125GW_SOT353-5 SA00006H000
3
2
G
UMA_HDMI_CLK 3 1 HDMI_SCLK
<28> UMA_HDMI_CLK
D
QY1
2
BSS138_NL_SOT23-3
G
2 1
+3VS
RY3
UMA_HDMI_DATA 3 1 HDMI_SDATA 2.2K_0402_5%
<28> UMA_HDMI_DATA
S
QY2 HDMI_HPD
BSS138_NL_SOT23-3 HDMI_HPD <28,30>
2 2
LY1 EMI@
CY2 1 2 0.1U_0402_10V7K HDMI_TXC- 1 2
<28> UMA_HDMI_CLK- 1 2
<28> UMA_HDMI_CLK+
CY1 1 2 0.1U_0402_10V7K HDMI_TXC+ 4
4 3
3 HDMI Connector
WCM-2012HS-900T_4P JHDMI
HDMI_HPD_C 19
18 HP_DET
+HDMI_5V_OUT +5V
17
HDMI_SDATA 16 DDC/CEC_GND
LY2 EMI@ HDMI_SCLK 15 SDA
CY5 1 2 0.1U_0402_10V7K HDMI_TXD0- 1 2 14 SCL
<28> UMA_HDMI_TX0- 1 2 13 Reserved
HDMI_R_CK- 12 CEC
CY3 1 2 0.1U_0402_10V7K HDMI_TXD0+ 4 3 11 CK-
<28> UMA_HDMI_TX0+ 4 3 HDMI_R_CK+ 10 CK_shield
WCM-2012HS-900T_4P HDMI_R_D0- 9 CK+
8 D0-
HDMI_R_D0+ 7 D0_shield
HDMI_R_D1- 6 D0+
5 D1-
HDMI_R_D1+ 4 D1_shield 23
LY3 EMI@ HDMI_R_D2- 3 D1+ GND 22
CY7 1 2 0.1U_0402_10V7K HDMI_TXD1- 1 2 2 D2- GND 21
3 <28> UMA_HDMI_TX1- 1 2 HDMI_R_D2+ 1 D2_shield GND 20 3
D2+ GND
CY6 1 2 0.1U_0402_10V7K HDMI_TXD1+ 4 3 Conn@
<28> UMA_HDMI_TX1+ 4 3
WCM-2012HS-900T_4P
680 +-5% 8P4R

HDMI_R_CK+ 5 4
HDMI_R_CK- 6 3
LY4 EMI@ HDMI_R_D0+ 7 2
CY9 1 2 0.1U_0402_10V7K HDMI_TXD2- 1 2 HDMI_R_D0- 8 1
<28> UMA_HDMI_TX2- 1 2
RPY3
CY8 1 2 0.1U_0402_10V7K HDMI_TXD2+ 4 3
<28> UMA_HDMI_TX2+ 4 3
WCM-2012HS-900T_4P
680 +-5% 8P4R
HDMI_R_D2+ 5 4
HDMI_R_D2- 6 3
HDMI_R_D1+ 7 2
HDMI_R_D1- 8 1
RPY4
1
QY4 D
ZZZ HDMI45@ 2
+5VS
HDMI Royalty G
RO0000003HM S
3
2N7002KW_SOT323-3
4 4
HDMI W/Logo + HDCP
HDMI W/O Logo: RO0000001HM

HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM Security Classification Compal Secret Data Compal Electronics, Inc.
please manually load Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title
this virtual material to 45@ BOM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn.
Size
Document Number Rev
0.2
VFKAA
A B C D E
5 4 3 2 1
CMOS Setting, near DDR Door SP@ RH26 GCLK@

JCMOS 1 2 PCH_RTCX1
<35> PCH_RTCX1_R
+RTCVCC RH23 1 2 PCH_RTCRST# 1 2 0_0402_5%
20K_0402_5% UH1A
CH4 1 2
1U_0402_6.3V6K 2 1 NOGCLK@ PCH_RTCX1 A20 INT.PH 20K C38 LPC_AD0
RTCX1 FWH0 / LAD0 A38 LPC_AD1 LPC_AD0 <41>
Placement near to YH1 CH2 15P_0402_50V8J INT.PH 20K FWH1 / LAD1 LPC_AD1 <41>
LPC
PCH_RTCX2 C20 INT.PH 20K B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 <41>
1
10M_0402_5%
NOGCLK@
iME Setting. SP@ NOGCLK@ INT.PH 20K C37 LPC_AD3
D20 FWH3 / LAD3 LPC_AD3 <41>
JME PCH_RTCRST#
RTCRST#
RH2
RH24 1 2 PCH_SRTCRST# 1 2 YH1 D36 LPC_FRAME#
PCH_SRTCRST# G22 FWH4 / LFRAME# LPC_FRAME# <41>
20K_0402_5% 32.768KHZ_12.5P_1TJF125DP1A000D
1
CH5 1 2 SRTCRST# E36
INT.PH 20K
2
2 1 NOGCLK@ SM_INTRUDER# K22 LDRQ0# K36
RTC
D
1U_0402_6.3V6K
INTRUDER# INT.PH 20K
LDRQ1# / GPIO23 D
CH3 15P_0402_50V8J
PCH_INTVRMEN C17 V5 SERIRQ
INTVRMEN SERIRQ SERIRQ <41>
Integrated SUS 1.05V VRM Enable AM3 SATA_PRX_C_DTX_N0

N34 SATA0RXN AM1 SATA_PRX_C_DTX_N0 <34>
High - Enable Internal VRs AZ_BITCLK SATA_PRX_C_DTX_P0
HDA_BCLK SATA0RXP AP7 SATA_PTX_DRX_N0 SATA_PRX_C_DTX_P0 <34>
PCH_INTVRMEN
SATA 6G
(must be always pulled high) AZ_SYNC L34 INT.PD 20K SATA0TXN AP5 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 <34> HDD
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <34>
PCH_SPKR T10 INT.PD 20K AM10
<39> PCH_SPKR SPKR SATA1RXN AM8
+RTCVCC AZ_RST# K34 SATA1RXP AP11
HDA_RST# SATA1TXN AP10
RH12 1 2 SM_INTRUDER# SATA1TXP
1M_0402_5% AZ_SDIN0_HD E34 INT.PD 20K AD7 SATA_PRX_C_DTX_N2
<39> AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 <34>
RH33 1 2 PCH_INTVRMEN AD5 SATA_PRX_C_DTX_P2
G34 SATA2RXP AH5 SATA_PTX_DRX_N2 SATA_PRX_C_DTX_P2 <34>
+3VS
330K_0402_5% PCH_SPKR HDA_SDIN1 INT.PD 20K SATA2TXN SATA_PTX_DRX_N2 <34> ODD
AH4 SATA_PTX_DRX_P2
@ High = Enabled "No Reboot Mode" C34 INT.PD 20K SATA2TXP SATA_PTX_DRX_P2 <34>
1 2 PCH_SPKR *Low = Disabled (Default) HDA_SDIN2 AB8
IHDA
A34 SATA3RXN AB10
RH36 1K_0402_5%
HDA_SDIN3 INT.PD 20K SATA3RXP AF3
SATA3TXN AF1
1 Rshort@ 2 AZ_SDOUT A36 SATA3TXP
<41> PWRME_CTRL HDA_SDO INT.PD 20K
RH25 0_0402_5% Y7
SATA
SATA4RXN Y5 RPH1 +3VS
+RTCBATT SATA4RXP
C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1 SERIRQ 1 8
SATA4TXP
1
Change Net name due to N32 PCH_GPIO21 2 7

HDA_DOCK_RST# / GPIO13 Y3 PCH_GPIO19 3 6
this function is high SATA5RXN
DH1 Y1 SATA_LED# 4 5
+RTCVCC BAS40-04_SOT23-3 active SATA5RXP AB3
C PCH_JTAG_TCK J3 SATA5TXN AB1 C
JTAG_TCKINT.PD 20K
T70 PAD 10K_0804_8P4R_5%
SATA5TXP
3
PCH_JTAG_TMS H7 Y11
+3VL T67 PAD JTAG_TMSINT.PH 20K SATAICOMPO
JTAG
1
PCH_JTAG_TDI K5 Y10 SATAICOMP 1 2
JTAG_TDI INT.PH 20K
CH8 T68 PAD +1.05VS_PCH
SATAICOMPI RH43 37.4_0402_1%
0.1U_0402_10V7K PCH_JTAG_TDO H1
2 T69 PAD JTAG_TDO AB12
SATA3RCOMPO
AB13 SATA3_COMP 1 2
SATA3COMPI +1.05VS_PCH
RH48 49.9_0402_1%
RPH2 PCH_SPICLK T3 AH1 RBIAS_SATA3 1 2

AZ_BITCLK_HD 1 8 AZ_BITCLK SPI_CLK SATA3RBIAS RH41 750_0402_1%
<39> AZ_BITCLK_HD 2 7 AZ_SYNC_R PCH_SPICS0# Y14
<39> AZ_SYNC_HD 3 6 AZ_RST# SPI_CS0#
<39> AZ_RST_HD# 4 5 T1
AZ_SDOUT PCH_SPICS1#
<39> AZ_SDOUT_HD SPI_CS1#
SPI
P3 SATA_LED#
33_8P4R_5% SATALED#
PCH_SPIDI V4 V14 PCH_GPIO21
SPI_MOSI INT.PD 20K SATA0GP / GPIO21
PCH_SPIDO U3 P1 PCH_GPIO19
SPI_MISO INT.PH 20K
HDA_SDO SATA1GP / GPIO19 PCH_GPIO19 <29>
INT.PH 20K
BOOT BIOS Strap Bit 0
ME debug mode, PANTHER-POINT_FCBGA989
HM76R3@
this signal has a weak internal pull down
*Low = Disable (default)
High = Enable (flash descriptor security overide)
B
HDA_SYNC SPI ROM for BIOS & ME (4MByte )
+3VALW_PCH
SPI ROM (2MByte )
+3VALW_PCH
B
This signal has a weak internal pull

*H=>On down
Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V
0206: Delete 0.1uF 0206: Delete 0.1uF
Need to pull high for Chief River Mobile platform UH3 UH4 @
PCH_SPICS0# 1 8 RH269 @ PCH_SPICS1# 1 8
PCH_SPIDO 1 Rshort@ 2 PCH_SPI0_DO 2 CS# VCC 7 RH66 0_0402_5% PCH_SPIDO 1 2 PCH_SPI1_DO 2 CS# VCC 7 RH267 0_0402_5%
+3VALW_PCH RH68 3 DO HOLD# 6 PCH_SPI0_CLK 1 Rshort@ 2 PCH_SPICLK 0_0402_5% 3 SO HOLD# 6 PCH_SPI1_CLK 1 2 PCH_SPICLK
+3VALW_PCH WP# CLK +3VALW_PCH WP# SCLK
0_0402_5% 4 5 PCH_SPI0_DI 1 Rshort@ 2 PCH_SPIDI 4 5 PCH_SPI1_DI 1 @ 2 PCH_SPIDI
+5VS GND DI RH67 0_0402_5% GND SI RH271 @ 0_0402_5%
2
W25Q32BVSSIG_SO8 MX25L1606EM2I-12G_SO8
RH55
1K_0402_5%
2
G
QH1 4MB ROM P/N: 2MB ROM P/N:

1
AZ_SYNC_R 3 1 AZ_SYNC
SA00003K800 SA000041N00
S
D
2
RH56 BSS138_NL_SOT23-3
SA00004LI00 SA00003FO10
1M_0402_5%
1
Please place UH3 & UH4 close to UH1 PCH,

please place RH66, RH67, RH68 near UH3
Please place RH267 near RH66, Please place RH271 near RH67,
A A
Please place RH269 near RH68.
RPH9
1 8 PCH_SPI0_DO
<41> EC_SDIO 2 7 PCH_SPICS0#
<41> EC_CS0# 3 6 PCH_SPI0_CLK
<41> EC_SCK 4 5 PCH_SPI0_DI
<41> EC_SDI
33_8P4R_5% Security Classification Compal Secret Data Compal Electronics, Inc.
885@ 2012/12/07 2013/12/07 Title
Issued Date Deciphered Date
PCH_HDA/JTAG/SATA/SPI/LPC
Reserve for NPCE885N EC Size Document Number
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
UH1B
+3VS
PCIE_PRX_C_LANTX_N1 BG34 +3VALW_PCH RH102 4.7K_0402_5%
<36> PCIE_PRX_C_LANTX_N1 PERN1
5
PCIE_PRX_C_LANTX_P1 BJ34 E12 PCH_SMBALERT# QH3B RH103 4.7K_0402_5%
<36> PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11 PCH_SMBALERT# <27> RPH5
LAN <36> PCIE_PTX_C_LANRX_N1 CH13 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_N1 AV32
CH11 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_P1 AU32 PETN1 H14 PCH_SMBCLK 5 4 PCH_SMBDATA 3 4
<36> PCIE_PTX_C_LANRX_P1 PETP1 SMBCLK PM_SMBDATA <11,12,35,42>
6 3 PCH_SMBCLK
2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA 7 2 PCH_SMLDATA1 QH3A 2N7002DW-T/R7_SOT363-6
<35> PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2 BF34 PERN2 SMBDATA 8 1 PCH_SMLCLK1
<35> PCIE_PRX_WLANTX_P2 PERP2
WLAN <35> PCIE_PTX_C_WLANRX_N2 CH14 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_N2 BB32 6 1
PETN2 PM_SMBCLK <11,12,35,42>
<35> PCIE_PTX_C_WLANRX_P2 CH17 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_P2 AY32 2.2K_0804_8P4R_5%
PETP2 A12
SMBUS
DRAMRST_CNTRL_PCH 2N7002DW-T/R7_SOT363-6
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7,9>
BJ36 PERN3 C8 PCH_SMLCLK0
PERP3 SML0CLK +3VS
5
D AV34 QH4B D
AU34 PETN3 G12 PCH_SMLDATA0
PETP3 SML0DATA 3 4
+3VS BF36 EC_SMB_DA2 <13,34,41>
PERN4
2
BE36 QH4A 2N7002DW-T/R7_SOT363-6
AY34 PERP4 C13 LAN_EN
PETN4 SML1ALERT# / PCHHOT# / GPIO74 LAN_EN <36>
RH1041 2 10K_0402_5% CLKREQ_WLAN# BB34 6 1
PETP4 E14 PCH_SMLCLK1 EC_SMB_CK2 <13,34,41>
RH95 1 2 10K_0402_5% CLKREQ_LAN# BG37 SML1CLK / GPIO58
PCI-E*
2N7002DW-T/R7_SOT363-6
BH37 PERN5 M16 PCH_SMLDATA1
AY36 PERP5 SML1DATA / GPIO75
Intel Spec: PETN5
BB36
PCIECLK_RQ0# is suspend well, PETP5
but we pull high to +3VS BJ38
PERN6
BG38
for LAN en/disable function AU36 PERP6 M7 +3VALW_PCH
Controller
AV36 PETN6 CL_CLK1
PETP6 DRAMRST_CNTRL_PCH RH76 1 2 1K_0402_5%
Control Link only for support Intel IAMT.
Link
+3VALW_PCH BG40 T11
RPH10 BJ40 PERN7 CL_DATA1 PCH_SMLCLK0 RH73 2 1 2.2K_0402_5%
AY40 PERP7
8 1 RI# BB40 PETN7 P10 PCH_SMLDATA0 RH77 2 1 2.2K_0402_5%
RI# <27> PETP7 CL_RST1#
7 2 LVDS_SEL
6 3 PCH_GPIO28 BE38
PCH_GPIO28 <30> PERN8
5 4 PASSWORD_CLEAR# BC38
AW38 PERP8 +3VALW_PCH
10K_0804_8P4R_5% AY38 PETN8
PETP8 CLK_REQ_VGA# RH89 2 1 10K_0402_5%
M10 CLK_REQ_VGA#
PEG_A_CLKRQ# / GPIO47 CLK_REQ_VGA# <13>
CLK_LAN# Y40
<36> CLK_LAN# CLK_LAN Y39 CLKOUT_PCIE0N
LAN <36> CLK_LAN CLKOUT_PCIE0P AB37 CLK_PCIE_VGA#
CLKOUT_PEG_A_N CLK_PCIE_VGA# <13>
Need to check dGPU
C CLKREQ_LAN# J2 AB38 CLK_PCIE_VGA C
VGA
CLOCKS
<36> CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA <13>
CLK_WLAN# AB49 AV22 RPH3

<35> CLK_WLAN# CLK_WLAN AB47 CLKOUT_PCIE1N CLKOUT_DMI_N AU22 CLK_CPU_DMI# <5> PCH_CLK_DMI 1 8
WLAN <35> CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5> PCH_CLK_DMI# 2 7
CLKREQ_WLAN# M1 CLKIN_GND1# 3 6
<35> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18 AM12 CLKIN_GND1 4 5
CLKOUT_DP_N AM13 CLK_CPU_EDP# <5>
AA48 CLKOUT_DP_P CLK_CPU_EDP <5> 120 MHz for eDP
10K_0804_8P4R_5%
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 PCH_CLK_DMI# RPH4
V10 CLKIN_DMI_N BE18 PCH_CLK_DMI CLK_DOT# 1 8
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P CLK_DOT 2 7
CLK_SATA# 3 6
Y37 BJ30 CLKIN_GND1# CLK_SATA 4 5
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_GND1
CLKOUT_PCIE3P CLKIN_GND1_P 10K_0804_8P4R_5%
+3VALW_PCH A8
PCIECLKRQ3# / GPIO25 G24 CLK_DOT# CLK_14M_PCH RH87 1 2 10K_0402_5%
RPH6 CLKIN_DOT_96N E24 CLK_DOT From Clock Gen.
1 8 EC_SWI# Y43 CLKIN_DOT_96P
2 7 EC_SWI# <27,36> Y45 CLKOUT_PCIE4N
LAN_EN
3 6 PCH_SUSPWRDN#_R CLKOUT_PCIE4P AK7 CLK_SATA#
4 5 USB_CHG_OC# PCH_SUSPWRDN#_R <27> L12 CLKIN_SATA_N AK5 CLK_SATA @EMI@ @EMI@
USB_CHG_OC# <29,38,41> PCIECLKRQ4# / GPIO26 CLKIN_SATA_P CLK_PCILOOP 1 2 1 2
10K_0804_8P4R_5% RH70 10_0402_5% CH9 10P_0402_50V8J
V45 K45 CLK_14M_PCH
V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
L14 H45 CLK_PCILOOP
PCIECLKRQ5# / GPIO44 INT. PH 20K CLKIN_PCILOOPBACK CLK_PCILOOP <29>
B RH37 B
+3VALW_PCH AB42 V47 PCH_X1 1 2 PCH_X1
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 PCH_X2 <35> PCH_X1_R
Note: place in DDR area CLKOUT_PEG_B_P XTAL25_OUT
0_0402_5%
GCLK@
PASSWORD_CLEAR# E6
1 LVDS@ 2 PANEL_SEL PEG_B_CLKRQ# / GPIO56 RH115 Placement near to YH2
1
RH119 10K_0402_5% JPW Y47 1 Rshort@ 2 XCLK_RCOMP_R

XCLK_RCOMP 1 2
XCLK_RCOMP +1.05VS_VCCDIFFCLKN
SP@ V40 RH38 0_0402_5% 90.9_0402_1%
V42 CLKOUT_PCIE6N
2
CLKOUT_PCIE6P
LVDS_SEL T13
1 IEDP@ 2 PANEL_SEL PCIECLKRQ6# / GPIO45
INT. PD 20K
RH276 10K_0402_5% V38 K43 CLK_FLEX0
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 T72 PAD
V37 INT. PD 20K NOGCLK@
FLEX CLOCKS
CLKOUT_PCIE7P F47 CLK_FLEX1 RH117 2 1 1M_0402_5%

CLKOUTFLEX1 / GPIO65 T74 PAD
PANEL_SEL K12 INT. PH 20K INT. PD 20K
PCIECLKRQ7# / GPIO46 H47 CLK_FLEX2 NOGCLK@YH2 25MHZ_20PF_7V25000016
CLKOUTFLEX2 / GPIO66 T73 PAD
AK14 INT. PD 20K
AK13 CLKOUT_ITPXDP_N K49 DGPU_PRSNT# 1 2 PCH_X1 1 3 PCH_X2
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 RH261 10K_0402_5% 1 3
GND GND
1 1
HM76R3@ PANTHER-POINT_FCBGA989 CH26 CH27
2 4
27P_0402_50V8J 27P_0402_50V8J
NOGCLK@ 2 2 NOGCLK@
LVDS_SEL PANEL_SEL
DGPU_PRSNT#
LVDS_SEL H L PANEL_SEL H L
DGPU_PRSNT# H L
A
Single A
Channel (Default) Dual Channel LVDS EDP
M/B SKU UMA DIS/OPT
Compal common design SW request to
add DGPU_Present on this GPIO67

PCH_PCI-E/SMBUS/CLK
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
UH1C
BC24 BJ14
<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
BE20 AY14
+3VALW_PCH <6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6>
BG18 BE14
BG20 BH13
RPH7 BC12
1 8 BE24 FDI_RXN4 BJ12 FDI_CTX_PRX_N4 <6>
PCH_LOW_BAT#
<6> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6>
2 7 SLP_CHG_CB0 BC20 BG10
D SLP_CHG_CB0 <29,38> <6> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> D
3 6 PCH_SMBALERT# BJ18 BG9
PCH_SMBALERT# <26> <6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6>
4 5 EC_SMI# BJ20
EC_SMI# <30,41> <6> DMI_CTX_PRX_P3 DMI3RXP BG14
AW24 FDI_RXP0 BB14 FDI_CTX_PRX_P0 <6>
10K_0804_8P4R_5%
<6> DMI_PTX_CRX_N0 AW20 DMI0TXN FDI_RXP1 BF14 FDI_CTX_PRX_P1 <6>
<6> DMI_PTX_CRX_N1 BB18 DMI1TXN FDI_RXP2 BG13 FDI_CTX_PRX_P2 <6>
<6> DMI_PTX_CRX_N2 AV18 DMI2TXN FDI_RXP3 BE12 FDI_CTX_PRX_P3 <6>
RH128 0_0402_5%
<6> DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6>
DMI
FDI
BG12 PCH_DPWROK 1 Rshort@ 2 PCH_RSMRST#
2 1 AY24 FDI_RXP5 BJ10 FDI_CTX_PRX_P5 <6>
PCH_RSMRST#
<6> DMI_PTX_CRX_P0 AY20 DMI0TXP FDI_RXP6 BH9 FDI_CTX_PRX_P6 <6>
RH163 10K_0402_5%
<6> DMI_PTX_CRX_P1 AY18 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6>
<6> DMI_PTX_CRX_P2 DMI2TXP Do not support DeepSX state
AU18
<6> DMI_PTX_CRX_P3 DMI3TXP AW16
FDI_INT FDI_INT <6>
1 2 DMI_COMP BJ24 AV12
+1.05VS_PCH DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6>
RH126 49.9_0402_1%
RPH17 BG25 BC10
1 8 PM_PWROK DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6>
2 7 PCH_GPIO32 1 2 RBIAS_CPY BH21 AV14
3 6 DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6>
PCH_GPIO37 RH127 750_0402_1%
4 5 PCH_GPIO37 <30> BB10 +RTCVCC
OPTIMUS_EN#
OPTIMUS_EN# <30> FDI_LSYNC1 FDI_LSYNC1 <6>
10K_0804_8P4R_5%
DSWVREN RH150 2 1 330K_0402_5%
Reserve this signal to EC by SW demand A18 DSWVREN
DSWVRMEN
2011/10/18a
System Power Management

1 @ 2 SUSACK#_R C12 INT.PH 20K E22 PCH_DPWROK DSWVREN must be always pulled high to +RTCVCC
<41> SUSACK# SUSACK# DPWROK
RH133 0_0402_5%
C
+3VS
1
RH47
2
1K_0402_5%
XDP_DBRESET# K3
SYS_RESET# WAKE#
B9 EC_SWI#
EC_SWI# <26,36> * ：
DSWVREN - Internal Deep Sleep 1.05V regulator
：
H Enable
L Disable C
P12 N3 PCH_GPIO32
<41,51> VGATE SYS_PWROK CLKRUN# / GPIO32
PM_PWROK L22 G8 SUS_STAT# T76 PAD

<41> PM_PWROK PWROK SUS_STAT# / GPIO61
32.768 KHz
L10 N14 Follow EC check list demand,
APWROK SUSCLK / GPIO62 CLK_EC <41>
but don't implement CLKRUN# this fuction
DRAMPWROK B13 D10 PM_SLP_S5#
<5> DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <41>
SUSACK#_R 2 @ 1 PCH_SUSPWRDN#_R
RH282 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
<41> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <41>
<26> PCH_SUSPWRDN#_R PCH_SUSPWRDN#_R K16 F4 PM_SLP_S3#

Stuff R137 if EC does not want to SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <41>
1 @ 2
involve in the handshake mechanism <41> PCH_SUSPWRDN#
RH132 0_0402_5%
for the DeepSX state entry and exit <41> PBTN_OUT#
PBTN_OUT# E20
PWRBTN#INT.PH 20K SLP_A#
G10 PM_SLP_A# T77 PAD
INT.PD 20K
1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T78 PAD
+3VALW_PCH ACPRESENT / GPIO31 SLP_SUS#
RH161 330K_0402_5%
DH2
1 2 PCH_LOW_BAT# E10 AP14 H_PM_SYNC
<41,46> ACIN BATLOW# / GPIO72 INT.PH 20K PMSYNCH H_PM_SYNC <5>
RB751V40_SC76-2
RI# A10 K14
<26> RI# RI# SLP_LAN# / GPIO29
PANTHER-POINT_FCBGA989
B Reserve this signal to EC by SW demand HM76R3@ B
2011/10/18a
DH5
PM_PWROK 2 1 PCH_RSMRST#
RB751V40_SC76-2
DH6
1 2
<41,47> POK
RB751V40_SC76-2
A A

PCH_DMI/FDI/PM
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
UH1D
EC_ENBKL J47 INT.PD 50SDVO_TVCLKINN AP43
1 2 EC_ENBKL <22,41> EC_ENBKL LCD_ENVDD M45 L_BKLTEN AP45
<22> LCD_ENVDD L_VDD_EN INT.PD 50 SDVO_TVCLKINP
RH125 100K_0402_5%
PCH_PWM P45 INT.PD 50 SDVO_STALLN AM42
<22> PCH_PWM L_BKLTCTL AM40
INT.PD 50 SDVO_STALLP
LCD_EDID_CLK T40
<22> LCD_EDID_CLK L_DDC_CLK
LCD_EDID_DATA K47 INT.PD 50 SDVO_INTN AP39
<22> LCD_EDID_DATA L_DDC_DATA
INT.PD 50 SDVO_INTP AP40
D LCTL_CLK T45 D
LCTL_DATA P39 L_CTRL_CLK
L_CTRL_DATA
INT.PD 20K
1 2 LVDS_IBG AF37 P38
AF36 LVD_IBG SDVO_CTRLCLK M39 UMA_HDMI_CLK <24>
RH143 2.37K_0402_1%
LVD_VBG SDVO_CTRLDATA UMA_HDMI_DATA <24>
INT.PD 20K
AE48
AE47 LVD_VREFH AT49
LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 HDMI_HPD
AK39 DDPB_HPD HDMI_HPD <24,30>
<22> LCD_TXCLK- AK40 LVDSA_CLK# AV42
LVDS
<22> LCD_TXCLK+ LVDSA_CLK DDPB_0N AV40 UMA_HDMI_TX2- <24>
+3VS AN48 DDPB_0P AV45 UMA_HDMI_TX2+ <24>
<22> LCD_TXOUT0- AM47 LVDSA_DATA#0 DDPB_1N AV46 UMA_HDMI_TX1- <24>
RPH8
<22> LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P UMA_HDMI_TX1+ <24> HDMI
Digital Display Interface

AK47 AU48
1 8 LCTL_CLK <22> LCD_TXOUT2- AJ48 LVDSA_DATA#2 DDPB_2N AU47 UMA_HDMI_TX0- <24>
2 7 LCTL_DATA LVDSA_DATA#3 DDPB_2P AV47 UMA_HDMI_TX0+ <24>
3 6 AN47 DDPB_3N AV49 UMA_HDMI_CLK- <24>
LCD_EDID_CLK
4 5 LCD_EDID_DATA <22> LCD_TXOUT0+ AM49 LVDSA_DATA0 DDPB_3P UMA_HDMI_CLK+ <24>
<22> LCD_TXOUT1+ AK49 LVDSA_DATA1
<22> LCD_TXOUT2+ AJ47 LVDSA_DATA2 P46
2.2K_0804_8P4R_5%
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
INT.PD 20K
2 1 UMA_CRT_DATA AF40
RH142 2.2K_0402_5% AF39 LVDSB_CLK# AP47
CRT@ LVDSB_CLK DDPC_AUXN AP49
2 1 UMA_CRT_CLK AH45 DDPC_AUXP AT38 RH141 2 1 100K_0402_5%
RH144 2.2K_0402_5% AH47 LVDSB_DATA#0 DDPC_HPD
CRT@ AF49 LVDSB_DATA#1 AY47
AF45 LVDSB_DATA#2 DDPC_0N AY49
LVDSB_DATA#3 DDPC_0P AY43
C AH43 DDPC_1N AY45 C
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P
UMA_CRT_B N48 M43

1 2 UMA_CRT_B <23> UMA_CRT_B UMA_CRT_G P49 CRT_BLUE DDPD_CTRLCLK M36
<23> UMA_CRT_G UMA_CRT_R T49 CRT_GREEN DDPD_CTRLDATA
RH154 150_0402_1%
<23> UMA_CRT_R CRT_RED INT.PD 20K
CRT@
1 2 UMA_CRT_G AT45
DDPD_AUXN
CRT
RH156 150_0402_1% <23> UMA_CRT_CLK UMA_CRT_CLK T39 AT43
CRT@ UMA_CRT_DATA M40 CRT_DDC_CLK DDPD_AUXP BH41 RH255 2 1 100K_0402_5%
<23> UMA_CRT_DATA CRT_DDC_DATA DDPD_HPD
1 2 UMA_CRT_R
RH152 150_0402_1% BB43
CRT@ M47 DDPD_0N BB45
<23> UMA_CRT_HSYNC M49 CRT_HSYNC DDPD_0P BF44
<23> UMA_CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
2 1 CRT_IREF T43 DDPD_2N BE42
RH138 1K_0402_0.5% T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N BG42
CRT@ DDPD_3P
HM76R3@
RH138
1K_0402_5%
NOCRT@
B B
A A

PCH_CRT/LVDS/HDMI
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
UH1E
AY7
For Optimus +3VS
RSVD1 AV7
BG26 RSVD2 AU3 +3VS
TP1 RSVD3
1
BJ26 BG4
BH25 TP2 RSVD4 RH175
BJ16 TP3 AT10
TP4 RSVD5 10K_0402_5%
BG16 BC8 0206: Delete 0.1uF
AH38 TP5 RSVD6
2
TP6
5
D AH37 AU2 UH6 D
AK43 TP7 RSVD7 AT4 PLT_RST# 1
P
AK45 TP8 RSVD8 AT3 IN1 4
C18 TP9 RSVD9 AT1 2 O PLTRST_VGA# <13>
DGPU_RST#
TP10 RSVD10 IN2
G
N30 AY3
TP11 RSVD11
1
H3 AT5 2 SN74AHC1G08DCKR_SC70-5
3
TP12 RSVD12
2
AH12 AV3
AM4 TP13 RSVD13 AV1 RH173 CH12 RH288
AM5 TP14 RSVD14 BB1 100K_0402_5% 0.47U_0402_6.3V6K 100K_0402_5%
Y13 TP15 RSVD15 BA3 1
2
K24 TP16 RSVD16 BB5
1
L24 TP17 RSVD17 BB3
AB46 TP18 RSVD18 BB7
AB45 TP19 RSVD19 BE8
TP20 RSVD20
RSVD
BD4
RSVD21 BF6
RSVD22
B21 AV5 NV_ALE
+3VS M20 TP21 RSVD23 AV10
RPH12 AY16 TP22 RSVD24
BG46 TP23 AT8
1 8 PCH_GPIO52 TP24 RSVD25
2 7 PCH_GPIO2 AY5
3 6 PCH_GPIO51 RSVD26 BA2
4 5 ODD_DA# U3RXDN1 BE28 RSVD27
<38> U3RXDN1 U3RXDN2 BC30 USB3Rn1 AT12
<38> U3RXDN2 USB3Rn2 RSVD28
Note: HM70 only enable
8.2K_0804_8P4R_5% BE32 BF3 USB port 0, 1, 2, 3, 8, 9, 10, 11
BJ32 USB3Rn3 RSVD29
U3RXDP1 BC28 USB3Rn4
<38> U3RXDP1 U3RXDP2 BE30 USB3Rp1
RPH13
<38> U3RXDP2 BF32 USB3Rp2
USB3Rp3 INT.PD 20K
1 8 PCI_PIRQD# BG32 C24 USB20_N0
C 2 7 PCI_PIRQA# U3TXDN1 AV26 USB3Rp4 USBP0N A24 USB20_P0 USB20_N0 <38> C
USB20_P0 <38> USB-Right1 Intel Anti-Theft Techonlogy
3 6 PCI_PIRQB# <38> U3TXDN1 U3TXDN2 BB26 USB3Tn1 USBP0P C25 USB20_N1
4 5 <38> U3TXDN2 AU28 USB3Tn2 USBP1N B25 USB20_N1 <38>
PCI_PIRQC# USB20_P1 USB-Right2 High=Endabled
AY30 USB3Tn3 USBP1P C26 USB20_P1 <38>
USB20_N2 NV_ALE
U3TXDP1 AU26 USB3Tn4 USBP2N A26 USB20_P2 USB20_N2 <36>
8.2K_0804_8P4R_5% USB-Left Low=Disable(floating)
<38> U3TXDP1 U3TXDP2 AY26 USB3Tp1
USB3Tp2
USBP2P
USBP3N
K28 USB20_N3 USB20_P2
USB20_N3
<36>
<37>
*
<38> U3TXDP2 AV28 H28 USB20_P3
AW30 USB3Tp3 USBP3P E28 USB20_P3 <37> CardReader +1.8VS
10K_0402_5% RH176 EHCI 1
1 2 DGPU_PWR_EN USB3Tp4 USBP4N D28
USBP4P C28 NV_ALE 1 @ 2
USBP5N A28 RH164 1K_0402_5%
8.2K_0402_5% RH305 USBP5P C29
1 2 PCH_GPIO4 USBP6N B29
PCI_PIRQA# K40 USBP6P N28
8.2K_0402_5% RH306 PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P
PCI
1 2 PCH_GPIO5 PCI_PIRQC# H38 L30 USB20_N8
G38 PIRQC# USBP8N K30 USB20_N8 <22>
PCI_PIRQD# USB20_P8 Touch Screen
PIRQD# USBP8P G30 USB20_P8 <22>
USB20_N9
C46 USBP9N E30 USB20_N9 <35>
DGPU_RST# USB20_P9 BT
REQ1# / GPIO50 USBP9P USB20_P9 <35>
USB
PCH_GPIO52 C44 C30
DGPU_PWR_EN E40 REQ2# / GPIO52 USBP10N A30
<17> DGPU_PWR_EN REQ3# / GPIO54 EHCI 2 USBP10P L32 USB20_N11
D47 USBP11N K32 USB20_N11 <22>
PCH_GPIO51 INT.PU 20K USB20_P11 Int. Camera
E42 GNT1# / GPIO51 USBP11P G32 USB20_P11 <22>
GNT2# / GPIO53 INT.PU 20K USBP12N
F46 INT.PU 20K E32
GNT3# / GPIO55 USBP12P C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
ODD_DA# G40 PIRQE# / GPIO2
<34> ODD_DA# PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBBIAS 1 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# RH165 22.6_0402_1%
PIRQH# / GPIO5
B B33
Within 500 mils B
PCI_PME# K10 USBRBIAS
T80 PAD PME# INT.PU 20K
PLT_RST# C6 A14 USB_OC#0 USB-Right Rear
<35,36,41,5> PLT_RST# PLTRST# OC0# / GPIO59 K20 USB_CHG_OC#
USB_OC#0 <38,41>
OC1# / GPIO40 B17 USB_CHG_OC# <26,38,41>USB-Right Front
USB_OC#2 USB-Left
OC2# / GPIO41 USB_OC#2 <36,41>
22_0402_5% 1 EMI@ 2 RH167 CLK_EC_R H49 INT.PD 20K C16 SLP_CHG_CB1
<41> CLK_PCI_EC H43 CLKOUT_PCI0 OC3# / GPIO42 L16 SLP_CHG_CB1 <38> +3VALW_PCH
0_0402_5% 1 Rshort@ 2 RH166 CLK_PCH INT.PD 20K SLP_CHG_CB0
<26> CLK_PCILOOP CLK_PCI_DDR J48 CLKOUT_PCI1 OC4# / GPIO43 A16 USB_OC#5_7 SLP_CHG_CB0 <27,38>
T81 PAD INT.PD
CLKOUT_PCI2 20K OC5# / GPIO9
1 K42 INT.PD 20K D14 RPH11
CLKOUT_PCI3 OC6# / GPIO10
22P_0402_50V8J
CH115
H40 INT.PD 20K C14

CLKOUT_PCI4 OC7# / GPIO14 USB_OC#0 1 8
@RF@ USB_OC#5_7 2 7
2 PANTHER-POINT_FCBGA989 SLP_CHG_CB1 3 6
HM76R3@ USB_OC#2 4 5
10K_0804_8P4R_5%
Boot BIOS Strap

PCH_GPIO51 PCH_GPIO19 Boot BIOS Loaction
0 0 LPC
ESD@ Reserved
180P_0402_50V8J 1 2 CH105 ODD_DA# 0 1
1 0 PCI
1K_0402_5% 2 @ 1 RH293 PCH_GPIO51
1 1 SPI *
1K_0402_5% 2 @ 1 RH294 PCH_GPIO19
A PCH_GPIO19 <25> A
A16 Swap Override Strap

Low= A16 swap override Enable
WL_OFF# * High= A16 swap override Disable Security Classification Compal Secret Data Compal Electronics, Inc.
PCH_PCI/USB/NAND
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
+3VS
UH1F
INT.PH 20K RPH16
HDMI_HPD T7 C40 ODD_EN#
+3VALW_PCH <24,28> HDMI_HPD BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <43> ODD_EN# 1 8
INT.PH 20K
A42 B41 CPU_PGA_BGA# GATEA20 2 7
TACH1 / GPIO1 INT.PH 20K TACH5 / GPIO69 for common BIOS on PBA/BGA CPU KB_RST# 3 6
INT.PH 20K
2 1 EC_LID_OUT# H36 C41 SPK_DET CPU_PGA_BGA# 4 5
TACH2 / GPIO6 INT.PH 20K TACH6 / GPIO70 SPK_DET <40>
RH204 1K_0402_5% INT.PH 20K
EC_SCI# E38 A40
TACH3 / GPIO7 INT.PH 20K
<41> EC_SCI# 10K_0804_8P4R_5%
TACH7 / GPIO71
C10 INT.PH 20K
D <27,41> EC_SMI# GPIO8 D
C4
LAN_PHY_PWR_CTRL / GPIO12
+3VS EC_LID_OUT# G2 INT.PD 20K P4 GATEA20
<41> EC_LID_OUT# GPIO15 A20GATE GATEA20 <41> Non-Harman detection
INT.PD 350 AU16
PCH_GPIO16 U2 PECI
1 2 ODD_DETECT# SATA4GP / GPIO16 P5 KB_RST#
RH178 200K_0402_5%
For Optimus RCIN# KB_RST# <41> 0 ONKYO
GPIO
VGA_PWROK D40 INT.PH 20K AY11 H_PWRGOOD SPK_DET
<17,54> VGA_PWROK TACH0 / GPIO17 PROCPWRGD H_PWRGOOD <5>
CPU/MISC
VRAM_DR_SR# T5 AY10 PCH_THRMTRIP#1 2
H_THERMTRIP# <5>
(GPIO70) 1 Non-Brand
SCLOCK / GPIO22 THRMTRIP# RH191 390_0402_5%
+3VS E8 INT.PH 20K T14
GPIO24 INIT3_3V#
This signal has weak internal
PCH_GPIO27 E16 AY1 NV_CLE
GPIO27 INT.PH 20K INT.PD 20K DF_TVS
RPH15
1 8 PCH_GPIO34 pull-up, can't be pulled low
2 7 PCH_GPIO16 P8
3 6 EC_SCI# <26> PCH_GPIO28 GPIO28 INT.PH 20K
AH8
4 5 PCH_GPIO49 PCH_GPIO34 K1 TS_VSS1
STP_PCI# / GPIO34 AK11
10K_0804_8P4R_5% K4 TS_VSS2
GPIO35 AH10
ODD_DETECT# V8 TS_VSS3
GVDR@
<34> ODD_DETECT# SATA2GP / GPIO36 INT.PD 20K
2 1 VRAM_DR_SR# AK10
M5 TS_VSS4
SATA3GP / GPIO37 INT.PD 20K
RH202 10K_0402_5%
2 1 SM_DET <27> PCH_GPIO37
RH200 269@ 10K_0402_5% N2 P37
<27> OPTIMUS_EN# SLOAD / GPIO38 NC_1
M3
SDATAOUT0 / GPIO39
GVSR@ SM_DET V13 BG2
C 2 1 VRAM_DR_SR# SDATAOUT1 / GPIO48 VSS_NCTF_15 C
RH203 10K_0402_5% PCH_GPIO49 V3 BG48
2 1 SM_DET SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
RH201 259@ 10K_0402_5% D6 BH3
2 1 PCH_GPIO27 GPIO57 VSS_NCTF_17
Follow Compal ORB
RH199 @ 10K_0402_5% and Intel Check list 460603 V1.5 BH47
VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
A45 BJ45
NCTF
A46 BJ46
A5 BJ5
SM_DET BIOS setup Speaker Type BOM A6 BJ6
(GPIO48) B3 C2
1 S&M option Harman/Kardon 269@ B47 C48 DMI & FDI Termination Voltage
BD1 D1
Set to VCC when HIGH
0 Non Harman 259@ BD49 D49 NV_CLE
Set to VSS when LOW
BE1 E1
BE49 E49
VSS_NCTF_12 VSS_NCTF_30 +1.8VS
BF1 F1
B VSS_NCTF_13 VSS_NCTF_31 B
1
BF49 F49
VSS_NCTF_14 VSS_NCTF_32 RH187
2.2K_0402_5%
2
HM76R3@
NV_CLE 2 1
H_SNB_IVB# <5>
RH189 1K_0402_5%
GPIO28
On-Die PLL Voltage Regulator
* H: Enable
L: Disable
GPIO8
OPTIMUS_EN#
Integrated Clock Chip Enable (Removed)
H: Disable OPTIMUS_EN# H L
L: Enable
*
SKU NonOPT Optimus
A A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable

PCH_CPU/GPIO
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCP UH1G POWER +3VS

JP@ PCH Power Rail Table
PJ4 1730mA RH309 LH1
2
2 1
1 1U_0402_6.3V6K +1.05VS_PCH AA23
VCCCORE[1] 1mA VCCADAC
U48 +VCCA_DAC 0.1U_0402_10V7K 1 2 +VCCA_DAC_R2 1 Refer to PCH EDS R1.0
AC23 1 1 1_0603_1% BLM18PG181SN1D_0603
AD21 VCCCORE[2]
JUMP_43X79 1 1 1 1 CH35 CH36 CH37 S0 Iccmax
CRT
AD23 VCCCORE[3] U47
CH32 CH33 CH31 CH34
VCCCORE[4] VSSADAC
0.01U_0402_25V7K 10U_0603_6.3V6M Voltage Rail Voltage Current (A)
D AF21 D
VCC CORE
10U_0603_6.3V6M AF23 VCCCORE[5] 2 2
2 2 2 2 AG21 VCCCORE[6] +3VS
VCCCORE[7]
V_PROC_IO 1.05 0.001
AG23
AG24 VCCCORE[8] AK36 +VCCA_LVDS 1 Rshort@ 2
1U_0402_6.3V6K 1U_0402_6.3V6K
VCCCORE[9] 1mA VCCALVDS
AG26 RH208 0_0402_5% V5REF 5 0.001
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
AJ23 VCCCORE[12]
VCCCORE[13]
V5REF_Sus 5 0.001
+1.8VS
LVDS
AJ26 AM37
AJ27 VCCCORE[14] VCCTX_LVDS[1] LH2
AJ29 VCCCORE[15] AM38 +VCCTX_LVDS 2 1
VCCCORE[16] VCCTX_LVDS[2]
0.01U_0402_25V7K Vcc3_3 3.3 0.228
AJ31 1 BLM18PG181SN1D_0603
VCCCORE[17] AP36
+1.05VS_PCH 60mA VCCTX_LVDS[3]
CH40
CH38 CH39 22U_0805_6.3V6M VccADAC 3.3 0.063
AP37 0.01U_0402_25V7K
AN19 VCCTX_LVDS[4] 2
VCCIO[28]
VccADPLLA 1.05 0.08
This pin can be left as NC if BJ22 +3VS
PAD T82
On-Die VR is enabled (Default) VCCAPLLEXP
VccADPLLB 1.05 0.08
V33
AN16 VCC3_3[6]
HVCMOS
VCCIO[15]
1 VccCore 1.05 1.7
AN17 CH42
VCCIO[16] V34 0.1U_0402_10V7K
VCC3_3[7]
VccDMI 1.1 0.047
AN21 2
VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 VccIO 1.05 3.711
VCCIO[18] RH221 0_0402_5%
AN27 AT16 +VCCAFDI_VRM 1 Rshort@ 2
C VCCIO[19] 3709mA VCCVRM[3] C
VccASW 1.05 0.903
+1.05VS_PCH AP21 +VCCP_VCCDMI +1.05VS_VCCP
VCCIO[20] RH213 0_0402_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 Rshort@ 2 VccSPI 3.3 0.01
VCCIO[21] VCCDMI[1]
1
+1.05VS_PCH
DMI
1 1 1 1 1 AP24
VCCIO[22]
VCCIO
CH43 CH45 CH46 CH47 CH44 RH214 0_0402_5% CH48 VccDSW 3.3 0.001
AP26 AB36 +1.05VS_VCC_DMI 1 Rshort@ 2 1U_0402_6.3V6K
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 75mA VCCCLKDMI 2
2 2 2 2 2 1
AT24 VccDFTERM 1.8 0.002
VCCIO[24] CH49
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
AN33 2 VccRTC 3.3 N/A
VCCIO[25]
VCCDFTERM
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCDFTERM[1]
VccSus3_3 3.3 0.095
BH29 AG17
VCC3_3[3] VCCDFTERM[2]
1 DFT / SPI 1 VccSusHDA 3.3 0.01
CH50 190mA
0.1U_0402_10V7K AJ16 CH51
VCCDFTERM[3] 0.1U_0402_10V7K VccVRM 1.5 0.167
2 +VCCAFDI_VRM AP16 2
VCCVRM[2] AJ17
VCCDFTERM[4]
VccCLKDMI 1.05 0.07
This pin can be left as NC if BG6
PAD T83 VccAFDIPLL +3VALW_PCH
On-Die VR is enabled (Default) VccSSC 1.05 0.095
AP17
+1.05VS_PCH VCCIO[27] V1
FDI
20mA VCCSPI
VccDIFFCLKN 1.05 0.055
AU20 1
B +VCCP_VCCDMI VCCDMI[2] B
CH53 VccALVDS 3.3 0.001
PANTHER-POINT_FCBGA989 1U_0402_6.3V6K
2
HM76R3@ VccTX_LVDS 1.8 0.04
+3VALW to +3VALW_PCH
+3VALW +3VALW_PCH
JP@
PJ2
2 1
2 1
JUMP_43X39
QH2
AO3413_SOT23
3 1
S
D
CH111
CH112
CH113
G
1 1
2
0.01U_0402_25V7K
0.1U_0402_10V7K
0.1U_0402_25V6
2 2
A A
PCH_PWR_EN# 2 1
<32,43> PCH_PWR_EN#
RH3 47K_0402_5%

PCH_POWER-1
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
+5VALW JP@ +5VALW_PCH

+3VS JUMP_43X39
PJ5
LH5 2 1
1 2 +3VS_VCC_CLKF33
This pin can be left as NC if 2 1
10UH_LB2012T100MR_20% On-Die VR is enabled (Default)
1 1 UH1J POWER +1.05VS_PCH
CH73 CH74
10U_0603_6.3V6M 1U_0402_6.3V6K AD49 N26 QH6
2 2 +3VALW_PCH VCCACLK VCCIO[29] AO3413_SOT23
1
P26 3 1
D
VCCIO[30]
0.1U_0402_10V7K~D
T16 CH56
D VCCDSW3_3 3mA D
0.1U_0402_10V7K~D
P28 1U_0402_6.3V6K
VCCIO[31] 2
G
1 1
2
CH55 V12 T27 1
DCPSUSBYP VCCIO[32]
CH59
0.1U_0402_10V7K
CH80
T29
2 +3VS_VCC_CLKF33 T38 VCCIO[33] +3VALW_PCH 2
VCC3_3[5] 2
T23 RH328
BH23 VCCSUS3_3[7] 2 1
VCCAPLLDMI2 1 <31,43> PCH_PWR_EN#
119mA VCCSUS3_3[8] T24 CH60 +3VALW_PCH 47K_0402_5%
AL29 0.1U_0402_10V7K
+1.05VS_PCH VCCIO[14] V23
VCCSUS3_3[9] 2
USB
1
AL24 V24
DCPSUS[3] VCCSUS3_3[10] CH61
P24 0.1U_0402_10V7K
VCCSUS3_3[6] 2 Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
AA19
+1.05VS_PCH VCCASW[1] T26
VCCIO[34] +1.05VS_PCH
AA21 1010mA
VCCASW[2]
AA24 M26 +PCH_V5REF_SUS +5VALW_PCH +3VALW_PCH
VCCASW[3] 1mA V5REF_SUS
1 1 AA26
Clock and Miscellaneous

VCCASW[4]
2
1
CH64 CH65 AN23
AA27 DCPSUS[4] RH232 DH3
22U_0805_6.3V6M VCCASW[5] AN24
VCCSUS3_3[1] +3VALW_PCH 10_0402_5% RB751V40_SC76-2
2 2 AA29
22U_0805_6.3V6M VCCASW[6] 1 2
1
2
AA31 CH66 0.1U_0402_10V7K +PCH_V5REF_SUS
VCCASW[7]
1
1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN CH63
C
1 1 1
VCCASW[8] 1mA V5REF +3VALW_PCH C
CH67 CH68 CH69 AC27 0.1U_0402_10V7K
VCCASW[9] N20 2
+1.05VS_PCH 1U_0402_6.3V6K 1U_0402_6.3V6K AC29 VCCSUS3_3[2]
PCI/GPIO/LPC
2 2 2 VCCASW[10] 1
N22 CH70
LH7 AC31 VCCSUS3_3[3] 1U_0402_6.3V6K
1 2 +1.05VS_VCCADPLLA VCCASW[11] P20
BLM18PG181SN1D_0603 AD29 VCCSUS3_3[4] 2
VCCASW[12] P22 +5VS +3VS
LH8
VCCSUS3_3[5]
CH63 & CH71 are
1 2 +1.05VS_VCCADPLLB AD31 +3VS
VCCASW[13] different by Intel CRB.
BLM18PG181SN1D_0603
2
W21 AA16
VCCASW[14] VCC3_3[1] RH237 DH4
1 1 1 1 +3VS 1
CH93 CH94 CH95 CH96 W23 W16 CH72 10_0402_5% RB751V40_SC76-2
1U_0402_6.3V6K VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K
1U_0402_6.3V6K W24 T34
1
2 2 2 2 VCCASW[16] VCC3_3[4] 2 +PCH_V5REF_RUN
10U_0603_6.3V6M 10U_0603_6.3V6M W26 1 2 1
VCCASW[17] CH75
W29 0.1U_0402_10V7K +3VS CH71
VCCASW[18] 1U_0402_6.3V6K
W31 AJ2 2
VCCASW[19] VCC3_3[2] +1.05VS_PCH
1
W33
VCCASW[20] AF13 CH76
VCCIO[5] 0.1U_0402_10V7K
+VCCRTCEXT N16 2
DCPRTC 1
1 AH13 CH77
CH78 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14
VCCVRM[4] VCCIO[13] 2
2 Place CH77 near pin AF13, AH13, AH14, AF14
B AF14 B
+1.05VS_VCCADPLLA BD47 VCCIO[6] This pin can be left as NC if
VCCADPLLA 80mA AK1 On-Die VR is enabled (Default)
SATA
+1.05VS_PCH +1.05VS_VCCADPLLB BF47 VCCAPLLSATA +VCCAFDI_VRM
VCCADPLLB 80mA
Place CH79 near pin AF17 1 AF11 +VCCAFDI_VRM
AF17 VCCVRM[1] +1.05VS_PCH
CH79
VCCIO[7] 55mA
1U_0402_6.3V6K AF33
AF34 VCCDIFFCLKN[1] AC16
+1.05VS_PCH +1.05VS_VCCDIFFCLKN 2 +1.05VS_VCCDIFFCLKN AG34 VCCDIFFCLKN[2] VCCIO[2]
RH247 0_0402_5% +1.05VS_PCH VCCDIFFCLKN[3] AC17
VCCIO[3] 1
1 Rshort@ 2 +1.05VS_VCCDIFFCLKN CH82
1 AG33 AD17 1U_0402_6.3V6K
CH81 VCCSSC 95mA VCCIO[4]
1 2
1U_0402_6.3V6K CH84
1U_0402_6.3V6K +VCCSST V16 Place CH82 near pin AC16, AC17, AD17
2 DCPSST +1.05VS_PCH
2 1
0.1U_0402_10V7K
T17 T21
CH85 V19 DCPSUS[1] VCCASW[22]
2 DCPSUS[2]
MISC
+1.05VS_VCCP V21
VCCASW[23]
1mA
CPU
0.1U_0402_10V7K BJ8
V_PROC_IO T19
VCCASW[21]
1 1 1
CH87 CH88 +RTCVCC
CH86 +3VALW_PCH
4.7U_0603_6.3V6K 0.1U_0402_10V7K 0.1U_0402_10V7K A22 10mA P32
RTC
2 2 2 VCCRTC VCCSUSHDA
HDA
1 1
CH90 PANTHER-POINT_FCBGA989 CH92
A HM76R3@ 0.1U_0402_10V7K A
Place CH86, CH87, CH88 near pin BJ8
2 2

PCH_POWER-2
Rev
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
UH1I
AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
UH1H AY8 VSS[161] VSS[261] K39
H5 B11 VSS[162] VSS[262] K46
VSS[0] B15 VSS[163] VSS[263] K7
AA17 AK38 B19 VSS[164] VSS[264] L18
AA2 VSS[1] VSS[80] AK4 B23 VSS[165] VSS[265] L2
D AA34 VSS[4] VSS[83] AK8 B35 VSS[168] VSS[268] L28 D
AB11 VSS[5] VSS[84] AL16 B39 VSS[169] VSS[269] L36
AB14 VSS[6] VSS[85] AL17 B7 VSS[170] VSS[270] L48
AB39 VSS[7] VSS[86] AL19 F45 VSS[171] VSS[271] M12
AB4 VSS[8] VSS[87] AL2 BB12 VSS[172] VSS[272] P16
AB43 VSS[9] VSS[88] AL21 BB16 VSS[173] VSS[273] M18
AC19 VSS[12] VSS[91] AL27 BB24 VSS[176] VSS[276] M30
AC34 VSS[17] VSS[96] AM11 BB46 VSS[181] VSS[281] M42
AC48 VSS[18] VSS[97] AM14 BC14 VSS[182] VSS[282] M46
AD10 VSS[19] VSS[98] AM36 BC18 VSS[183] VSS[283] M8
AD11 VSS[20] VSS[99] AM39 BC2 VSS[184] VSS[284] N18
AD12 VSS[21] VSS[100] AM43 BC22 VSS[185] VSS[285] P30
AD13 VSS[22] VSS[101] AM45 BC26 VSS[186] VSS[286] N47
AD26 VSS[25] VSS[104] AN2 BC36 VSS[189] VSS[289] T33
AD27 VSS[26] VSS[105] AN29 BC40 VSS[190] VSS[290] P40
AD36 VSS[29] VSS[108] AP12 BD46 VSS[193] VSS[293] P7
AD37 VSS[30] VSS[109] AP19 BD5 VSS[194] VSS[294] R2
AD38 VSS[31] VSS[110] AP28 BE22 VSS[195] VSS[295] R48
AD39 VSS[32] VSS[111] AP30 BE26 VSS[196] VSS[296] T12
AD4 VSS[33] VSS[112] AP32 BE40 VSS[197] VSS[297] T31
AD40 VSS[34] VSS[113] AP38 BF10 VSS[198] VSS[298] T37
C AD43 VSS[36] VSS[115] AP42 BF16 VSS[200] VSS[300] W34 C
AD8 VSS[39] VSS[118] AR2 BF24 VSS[203] VSS[303] T8
AE2 VSS[40] VSS[119] AR48 BF26 VSS[204] VSS[304] V11
AE3 VSS[41] VSS[120] AT11 BF28 VSS[205] VSS[305] V17
AF10 VSS[42] VSS[121] AT13 BD3 VSS[206] VSS[306] V26
AF12 VSS[43] VSS[122] AT18 BF30 VSS[207] VSS[307] V27
AD14 VSS[44] VSS[123] AT22 BF38 VSS[208] VSS[308] V29
AD16 VSS[45] VSS[124] AT26 BF40 VSS[209] VSS[309] V31
AF16 VSS[46] VSS[125] AT28 BF8 VSS[210] VSS[310] V36
AF19 VSS[47] VSS[126] AT30 BG17 VSS[211] VSS[311] V39
AF27 VSS[50] VSS[129] AT39 BG44 VSS[214] VSS[314] W17
AF29 VSS[51] VSS[130] AT42 BG8 VSS[215] VSS[315] W19
AF31 VSS[52] VSS[131] AT46 BH11 VSS[216] VSS[316] W2
AF38 VSS[53] VSS[132] AT7 BH15 VSS[217] VSS[317] W27
AF4 VSS[54] VSS[133] AU24 BH17 VSS[218] VSS[318] W48
AF42 VSS[55] VSS[134] AU30 BH19 VSS[219] VSS[319] Y12
AF46 VSS[56] VSS[135] AV16 H10 VSS[220] VSS[320] Y38
AF5 VSS[57] VSS[136] AV20 BH27 VSS[221] VSS[321] Y4
AG19 VSS[60] VSS[139] AV38 BH35 VSS[224] VSS[324] Y8
AG2 VSS[61] VSS[140] AV4 BH39 VSS[225] VSS[325] BG29
AG31 VSS[62] VSS[141] AV43 BH43 VSS[226] VSS[328] N24
AG48 VSS[63] VSS[142] AV8 BH7 VSS[227] VSS[329] AJ3
AH11 VSS[64] VSS[143] AW14 D3 VSS[228] VSS[330] AD47
AH3 VSS[65] VSS[144] AW18 D12 VSS[229] VSS[331] B43
AH36 VSS[66] VSS[145] AW2 D16 VSS[230] VSS[333] BE10
AH39 VSS[67] VSS[146] AW22 D18 VSS[231] VSS[334] BG41
B AH40 VSS[68] VSS[147] AW26 D22 VSS[232] VSS[335] G14 B
AH42 VSS[69] VSS[148] AW28 D24 VSS[233] VSS[337] H16
AH46 VSS[70] VSS[149] AW32 D26 VSS[234] VSS[338] T36
AH7 VSS[71] VSS[150] AW34 D30 VSS[235] VSS[340] BG22
AJ19 VSS[72] VSS[151] AW36 D32 VSS[236] VSS[342] BG24
AJ21 VSS[73] VSS[152] AW40 D34 VSS[237] VSS[343] C22
AJ24 VSS[74] VSS[153] AW48 D38 VSS[238] VSS[344] AP13
AJ33 VSS[75] VSS[154] AV11 D42 VSS[239] VSS[345] M14
AJ34 VSS[76] VSS[155] AY12 D8 VSS[240] VSS[346] AP3
AK12 VSS[77] VSS[156] AY22 E18 VSS[241] VSS[347] AP1
AK3 VSS[78] VSS[157] AY28 E26 VSS[242] VSS[348] BE16
VSS[79] VSS[158] G18 VSS[243] VSS[349] BC16
PANTHER-POINT_FCBGA989 G20 VSS[244] VSS[350] BG28
G26 VSS[245] VSS[351] BJ28
HM76R3@ G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
HM76R3@
A A

PCH_GND
Rev
Custom 0.2
VFKAA
5 4 3 2 1
A B C D E
SATA HDD Conn. SATA ODD Conn

JHDD
Close to JHDD
True Power Consumption
1
GND 2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K JODD
Close to JODD
A+ 3 SATA_PTX_DRX_P0 <25>
SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K Peak 1800 mA
A- 4 SATA_PTX_DRX_N0 <25> 1
GND 5 GND Read (CD) 1100 mA
SATA_PRX_DTX_N0 C368 1 2 0.01U_0402_25V7K 2 SATA_PTX_C_DRX_P2 C376 1 2 0.01U_0402_25V7K
B- 6 SATA_PRX_C_DTX_N0 <25> A+ SATA_PTX_DRX_P2 <25> Read (DVD) 950 mA
SATA_PRX_DTX_P0 C370 1 2 0.01U_0402_25V7K 3 SATA_PTX_C_DRX_N2 C377 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P0 <25> A- SATA_PTX_DRX_N2 <25>
7 4 Write 1300 mA
GND GND 5 SATA_PRX_DTX_N2 C378 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N2 <25> Standby 20mA
6 SATA_PRX_DTX_P2 C375 1 2 0.01U_0402_25V7K
1 8 B+ 7 SATA_PRX_C_DTX_P2 <25> 1
V33 9 GND
V33 10 +3VS
V33 11 8
GND 12 DP 9 ODD_DETECT# <30>
GND +5V +5VS_ODD
13 10
GND 14 +5V 11
V5 15 15 MD 12 ODD_DA# <29>
V5 16 14 GND GND 13
V5 17 +5VS GND GND
GND 18 +5VS_ODD
DAS/DSS Place components closely ODD CONN.
19 SANTA_202401-1
23 GND 20 +5VS
24 GND V12 21
Place closely JHDD SATA CONN. Conn@
GND V12
1.2A 1 1 1
22 C355 C360 C380
V12
1 1 1
C356 C357 C358 10U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K
SUYIN_127043FR022G196ZR 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 2
Conn@ 10U_0805_10V4Z
2 2 2
G-Sensor
2 2
+5VS +3VS_HDP UG1 GSENSOR@

2 3 VOUTX CG1 1 2 GSENSOR@ 0.033U_0402_16V7K
+3VS_HDP Vdd1 Voutx
12 5 VOUTY CG2 1 2 GSENSOR@ 0.033U_0402_16V7K
Vdd2 Vouty 7 VOUTZ CG3 1 2 GSENSOR@ 0.033U_0402_16V7K
1 1 Voutz
CG12 UG3 GSENSOR@ CG13
1U_0402_6.3V6K 1U_0402_6.3V6K SELF_TEST 4 10
GSENSOR@ 1 5 GSENSOR@ 6 ST NC1 11
2 VIN VOUT 2 8 PD NC2 14
2 FS NC3 15
GND NC4 16
3 4 NC5
SHDN# BP 9 1
+3VS_HDP Rev GND1 13
G9191-330T1U_SOT23-5 GND2
SA000022I00 TSH352TR LGA 16P
SA00004GB00
UG2
1 11
3 <13,26,41> EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 HDPACT <41> 3
2
SELF_TEST 2 12 RG9
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5%
+3VS_HDP GSENSOR@
+3VS_HDP_R 3 13
1
RESET# P1_4/TXD0
RPG1 GXOUT 4 14
XOUT/P4_7 P1_3/KI3#/AN11/TZOUT HDPLOCK <41>
1 8 +3VS_HDP_R RG10 47K_0402_5%
2 7 GXOUT 5 15 VOUTZ 2 1
3 6 GXIN VSS/AVSS P1_2/KI2#/AN10/CMP0_2 GSENSOR@
4 5 +3VS_HDP_M SA00003A600
GXIN 6 16
XIN/P4_6 P4_2/VREF +3VS_HDP
4.7K_8P4R_5%
GSENSOR@ 1
+3VS_HDP 7 17 VOUTX CG6
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_10V7K
GSENSOR@
+3VS_HDP_M 8 18 VOUTY 2
MODE P1_0/KI0#/AN8/CMP0_0
HDPINT RG7 2 1 1K_0402_5% 9 19

<41> HDPINT GSENSOR@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
1 1 10 20
P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 EC_SMB_DA2 <13,26,41>
CG8
CG7 GSENSOR@
0.1U_0402_10V7K 0.1U_0402_10V7K R5F211B4D34SP GSENSOR@
GSENSOR@ 2 2
4 4

HDD/ODD/G-Sensor
Size
Document Number Rev
0.2
VFKAA
A B C D E
A B C D E
WLAN&BT Combo module circuits

Slot 1 Half PCIe Mini Card-WLAN
BT BT
on module on module
+3V_WLAN
40 mils Enable Disable
0.1U_0402_10V7K BT_ON H L
1 1 1
CM1 CM2 CM3
1 1
2 2 2
0.1U_0402_10V7K 4.7U_0603_6.3V6K
BT_ON 1 RM27 2 E51_RXD

From EC <41> BT_ON
1K_0402_5%
For isolate BT_ON and

Compal Debug Card.
+3V_WLAN
JWLAN
To EC
1 2
(Need pull-up +3VL) <41> WLAN_WAKE# 3 1 2 4
BT_ON 1 RM24 2 BT_CTRL_R 5 3 4 6
@ 0_0402_5% 7 5 6 8
<26> CLKREQ_WLAN# 9
11
7
9
8
10
10
12
+3VALW TO +3V_WLAN for WOWL
<26> CLK_WLAN# 13 11 12 14
To PCH <26> CLK_WLAN 13 14
15 16 To EC
17 15 16 18 +3VALW
19 17 18 20
19 20 WL_OFF# <41> +3VALW
21 22
23 21 22 24 PLT_RST# <29,36,41,5>
<26> PCIE_PRX_WLANTX_N2 25 23 24 26
To PCH <26> PCIE_PRX_WLANTX_P2 25 26
To PCH
1
27 28 2 WOWL@
29 27 28 30
WLAN/ WiFi 29 30 PM_SMBCLK <11,12,26,42> RM31 CM9 Vgs=-4.5V,Id=3A,Rds<97mohm
31 32 WOWL@ 10K_0402_5% 0.1U_0402_10V7K
2 <26> PCIE_PTX_C_WLANRX_N2 31 32 PM_SMBDATA <11,12,26,42> 2
To PCH 33 34
<26> PCIE_PTX_C_WLANRX_P2 35 33 34 36 1
USB20_N9 <29>
2
35 36
3
S
37 38 WiMax/ BT If system don't support WOWL
37 38 USB20_P9 <29> G
39 40 1 2 2 AO3413_SOT23
+3V_WLAN
41 39 40 42 LED_WIMAX# To EC <41> WOWL_EN# QM2
43 41 42 44 LED_WIMAX# <42> +3V_WLAN
47K_0402_5% 2
D
1
45 43 44 46 RM30 WOWL@ WOWL@
45 46
1
47 48 1 2 CM10
47 48 +3VS WOWL@
E51_TXD 49 50 RM6 100K_0402_5% RM2 0.01U_0402_25V7K RM1
<41> E51_TXD E51_RXD 51 49 50 52 1 1 2
100K_0402_5% +3VS
<41> E51_RXD 51 52 0_0603_5%
53 54 NOWOWL@
2
GND1 GND2
Debug card using
LOTES_AAA-PCI-049-P06-A
Conn@
+3VL +1.05VS_VCCP +3VS_DGPU +3VALW

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 1 1
CCL1 CCL3 CCL6 CCL8
GCLK@ GCLK@ GCLK@ GCLK@
3 2 2 2 2 3
1 1
for safety request CCL7 CCL11
22U_0805_6.3V6M 2.2U_0402_6.3V6M
RCL4 GCLK@ UCL1 GCLK@ GCLK@
120_0603_5% 2 2
2 1 +RTCGCLK 10 14
+RTC VBAT VDD_RTC_OUT
GCLK@
15
+3VL +V3.3A
2
+3VALW VDD 9
32kHz PCH_RTCX1_R <25>
GCLK@
11 12 VGA_X1_R 1 2
+3VS_DGPU VDDIO_27M 27MHz VGA_X1 <13>
RCL3 22_0402_5%
8 6
VDDIO_25M_A 25MHz_A 22 ohm for NV chip
3 5 PCH_X1_R_R PCH_X1_R_R 1 Rshort@ 2
+1.05VS_VCCP VDDIO_25M_B 25MHz_B PCH_X1_R <26>
RCL1 0_0402_5%
CLK_X1 1
CLK_X2 16 XTAL_IN
XTAL_OUT
GND1
GND2
GND3
GND4
SLG3NB304VTR_TQFN16_2X3
4
7
13
17
GCLK@
YCL1 25MHZ 12PF X3G025000DK1H-X
4 CLK_X1 1 3 CLK_X2
PN: SA000063300 4
1 3
GND GND
1 2 4 1
CCL9 CCL12
18P_0402_50V8J 18P_0402_50V8J
GCLK@ GCLK@
2 2
WLAN/GCLK
Size
Document Number Rev
0.2
VFKAA
A B C D E
A B C D E
Left USB 2.0 x 1
+5VALW W=80mils
For EMI JLAN
2.0A +USB_VCCC
+3V_LAN
1
UR1 @EMI@ 2 1
2 6 2 1 <29,35,41,5> PLT_RST# LANCLK_REQ# 3 2 2
EMI@ LR1
<29> USB20_N2 USB20_N2 2 1 USB20_N2_L 3 IN OUT 7 CR38 1000P_0402_50V7K ISOLATE# 4 3
2 1 USB_EN#2 4 IN OUT 8 5 4 4
<41> USB_EN#2 1 EN/ENB OUT 5 <26,27> EC_SWI# 6 5
GND OCB USB_OC#2 <29,41>
<29> USB20_P2 USB20_P2 3 4 USB20_P2_L 7 6 6
1 3 4 SY6288DCAC_MSOP8 8 7 1
WCM-2012-900T_0805 SA00004KB00 9 8 8
<26> CLK_LAN# 10 9
SA00003TV00 <26> CLK_LAN 11 10 10
12 11
<26> PCIE_PTX_C_LANRX_N1
13 12 12
<26> PCIE_PTX_C_LANRX_P1
14 13
<26> PCIE_PRX_C_LANTX_N1 15 14 14
<26> PCIE_PRX_C_LANTX_P1 16 15
USB20_P2_L 17 16 16
USB20_N2_L 18 17
19 18 18
20 19
+USB_VCCC 20 20
21
G1 22
W=80mils G2 23
G3 24
G4
ACES_50559-02001-001
+3VS Conn@
For LAN function
+3VS
1
RL24 2 1 10K_0402_5% LANCLK_REQ#
1K_0402_5%
RL6
@
2
LAN_EN ISOLATE# 1 Rshort@ 2 WOL_EN# WOL_EN# <41>
<26> LAN_EN
2
RL433 0_0402_5%
G
2 2
CLKREQ_LAN# 1 3 LANCLK_REQ#
<26> CLKREQ_LAN#
RL7
D
15K_0402_5%
QL53
Sx Enable Sx Disable S0
2N7002KW_SOT323-3
Wake up Wake up
WOL_EN# LOW HIGH HIGH
JP@
PJ29
2 1
+3VALW_PCH 2 1 +3V_LAN
JUMP_43X39
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

3 3
LAN WOL LAN_EN ISOLATEB

S0 Sx S0 Sx
----------------------------------------------
0 0 0 0 1 1
0 1 0 0 1 1
1 0 1 1 1 1
1 1 1 1 1 0*
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
4 4

LUSB20/LAN conn.
Custom 0.2
VFKAA
A B C D E
5 4 3 2 1
1
CW8
0.1U_0402_10V7K UW1
2 For EMI request
22 (Place close to chip)
RSTZ
5
2 MS_INS 17 SD_DATA2
<29> USB20_N3
3 DM SD_D2/MS_D5/SB13 16 SD_DATA3
<29> USB20_P3
D DP SD_D3/MS_D4/SB12 15 SDCMD LW5 D
30mils SD CMD/SD_CMD 14 SDCLK 2 1 SDCLK_R
1 Rshort@ 2 +3VS_CR 1 SD CLK/SD_CLK 21 SDCD# BLM15BD121SN1D_0402
+3VS DVDD SD_CDZ
RW1 0_0402_5% 24 13 SD_DATA0 EMI@
+VCC_3IN1 PMOS SD_D0/MS_D6/SB9
1 CW1 12 SD_DATA1 2
30mils SD_D1/MS_D7/SB8 11 CW9
2.2U_0402_6.3V6M +3VS_CR 19 MS BS/MS_BS 10 SDWP
DVDD SD_WP/MS_D1/SB5 4.7P_0402_50V8J
+3VS_CR 23 9 EMI@
2 20 DVDD SD_D4/MS_D0/SB4 8 1
GPIO0 SD_D5/MS_D2/SB3 7
+3VS_CR 4 SD_D6/MS_D3/SB1 6
please close the pin19 of UW1 AVDD SD_D7/MS_CLK/SB0
+VDD18 18
VDD18
12mils
+3VS_CR 1 25
+3VS_CR Thermal pad
30mils 1 CW5
0.1U_0402_10V7K GL834L-OGY01_QFN24_4X4
CW2 2 NC (default) 10K pull down
0.1U_0402_10V7K
2
GPIO0 Power saving mode Normal mode
please close the pin4 of UW1

De-coupling and Bulk capacitor should place near to Cardreader chip and Combo Socket
+3VS_CR
+3VS_CR
30mils 1 1
CW3 CW4
C 2.2U_0402_6.3V6M 0.1U_0402_10V7K C
2 2
Close to connector Close to IC
+VCC_3IN1
1 1
CW6 CW7 30mil
< 2 in 1 Card Reader > 0.1U_0402_10V7K 2.2U_0402_6.3V6M
2 2
Conn@ JCARD
5
VDD 3 SDCMD_R BLM15BD121SN1D_0402 2 1 LW6 SDCMD
CMD 6 SDCLK_R @EMI@
CLK 7 1 2
VSS 4 @EMI@ CW16
VSS 4.7P_0402_50V8C
8 SD_DATA0_R BLM15BD121SN1D_0402 2 1 LW1 EMI@ SD_DATA0
DAT0 9 SD_DATA1_R BLM15BD121SN1D_0402 2 1 LW2 EMI@ SD_DATA1
CD/DAT3
4.7P_0402_50V8C
4.7P_0402_50V8C
4.7P_0402_50V8C
4.7P_0402_50V8C
1 1 1 1
CW12
CW14
CW13
CW15
B 12 10 SDWP# B
13 GND_SW WP_SW 11 SDCD
GND_SW CD_SW 2 2 2 2 For EMI request
(Place close to connector)
T-SOL_156-2000302604
EMI@ EMI@ EMI@ EMI@
"Normal Close" type connector For normal close type connector invert circuit
+3VS_CR +3VS_CR
CD_SW WP_SW
1
Protect disable Protect Enable
1
Card Uninsertion SDCD#
Close RW3 SDWP
RW4
Close Close 100K_0402_5%
100K_0402_5%
2
6
QW1A D
3
Card Insertion SDCD 2 QW1B
Open Open Close G SDWP# 5
D
2N7002KDWH_SOT363-6 G
S 2N7002KDWH_SOT363-6
1
S
4
A A

USB-CardReader GL834L
Custom 0.2
VFKAA
5 4 3 2 1
5 4 3 2 1
USB Sleep & Charge

State table for MAX14641
CB0 CB1 Mode STATUS

2A auto-detection charger mode for Apple device.
0 0 AM2 Resistor dividers are connected to DP/DM. Including DCP
Forced 1A charger mode for Apple devices. UR2 14641@ 14641@
D 1 8 CHG_CB0 RR1 0_0402_5% D
0 1 AP1 Resistor dividers are connected to DP/DM. CEN CB0 SLP_CHG_CB0 <27,29>
<41> CHG_PWR_GATE# USB20_N1_S 2 7
USB20_P1_S 3 DM TDM 6 USB20_N1 <29>
DP TDP USB20_P1 <29>
1 0 PM USB pass-through mode.DP/DM are connected to TDP/TDM <29> SLP_CHG_CB1 RR2 14641@ CHG_CB1 4 5
+5VALW
0_0402_5% 9 CB1 VCC
PGND 1
USB pass-through mode with CDP emulation. CR9
1 1 CM Auto connects DP/DM to TDP/TDM depending MAX14641ETA-TGH7_TDFN8 0.1U_0402_10V7K
on CDP detection status. 2
Right rear USB3.0 Conn. Right front USB3.0 Conn. UR2
(Support S&C function)

Address
0x35
LR7 EMI@ MAX14640ETA+TGH7

LR6 EMI@ USB20_N1_S 2 1 USB20_N1_R 14640@
2 1 USB20_N0_R 2 1
<29> USB20_N0 2 1
USB20_P1_S 3 4 USB20_P1_R
3 4 USB20_P0_R 3 4 +3VALW +3VALW
<29> USB20_P0 3 4 WCM-2012-900T_0805
WCM-2012-900T_0805
2
C LR2 EMI@ LR3 EMI@ C
1 2 U3RXDN1_L 1 2 U3RXDN2_L RR3 RR4
<29> U3RXDN1 1 2 <29> U3RXDN2 1 2 4.7K_0402_5% 4.7K_0402_5%
2
QR1A 14640@ 14640@
4 3 U3RXDP1_L 4 3 U3RXDP2_L
1
<29> U3RXDP1 4 3 <29> U3RXDP2 4 3 6 1 CHG_CB1
<41,45,46> EC_SMB_CK1
KINGCORE WCM-2012HS-670T KINGCORE WCM-2012HS-670T
5
2N7002KDWH_SOT363-6
14640@
3 4 CHG_CB0
<41,45,46> EC_SMB_DA1
LR5 EMI@ LR4 EMI@ 2N7002KDWH_SOT363-6 QR1B
1 2U3TXDN1_C 1 2 U3TXDN1_C_L 1 2 U3TXDN2_C 1 2 U3TXDN2_C_L 14640@
<29> U3TXDN1 1 2 <29> U3TXDN2 1 2
CR14 0.1U_0402_10V7K CR16 0.1U_0402_10V7K
1 2U3TXDP1_C 4 3 U3TXDP1_C_L 1 2 U3TXDP2_C 4 3 U3TXDP2_C_L

<29> U3TXDP1 4 3 <29> U3TXDP2 4 3
CR15 0.1U_0402_10V7K CR17 0.1U_0402_10V7K
KINGCORE WCM-2012HS-670T KINGCORE WCM-2012HS-670T
+USB_VCCB +USB_VCCA
W=80mils W=100mils
+5VALW 2.0A +USB_VCCB W=80mils +5VALW 2.5A +USB_VCCA W=100mils
UR4 0.1U_0402_10V7K 1000P_0402_50V7K UR3 0.1U_0402_10V7K 1000P_0402_50V7K
2 6 2 6
3 IN OUT 7 3 IN OUT 7
IN OUT 1 1 IN OUT 1 1
1
1
4 8 CR12 CR13 CR39 4 8 CR10 CR11 CR40
B <41> USB_EN#0 1 EN/ENB OUT 5 <41> USB_CHG_EN# 1 EN/ENB OUT 5 B
USB_OC#0 <29,41> @EMI@ USB_CHG_OC# <26,29,41> @EMI@
GND OCB GND OCB
2
2
SY6288DCAC_MSOP8 2 2 SY6288DCAC_MSOP8 2 2
SA00004KB00 SA00006DN00
47U_0805_6.3V6M 47U_0805_6.3V6M
SA00003TV00
D3 @ESD@ DR4 @ESD@ JUSBF Conn@

U3TXDP1_C_L1 9 U3TXDP1_C_L JUSBR Conn@ U3TXDP2_C_L 1 9 U3TXDP2_C_L U3TXDP2_C_L 9 13
U3TXDP1_C_L 9 13 U3TXDN2_C_L 8 StdA-SSTX+ GND 12
U3TXDN1_C_L2 8 U3TXDN1_C_L U3TXDN1_C_L 8 StdA-SSTX+ GND 12 U3TXDN2_C_L 2 8 U3TXDN2_C_L 7 StdA-SSTX- GND 11
7 StdA-SSTX- GND 11 U3RXDP2_L 6 GND-DRAIN GND 10
U3RXDP1_L 4 7 U3RXDP1_L U3RXDP1_L 6 GND-DRAIN GND 10 U3RXDP2_L 4 7 U3RXDP2_L U3RXDN2_L 5 StdA-SSRX+ GND
U3RXDN1_L 5 StdA-SSRX+ GND 4 StdA-SSRX-
U3RXDN1_L 5 6 U3RXDN1_L 4 StdA-SSRX- U3RXDN2_L 5 6 U3RXDN2_L USB20_P1_R 3 GND
USB20_P0_R 3 GND USB20_N1_R 2 D+
USB20_N0_R 2 D+ 1 D-
D- +USB_VCCA VBUS
1
+USB_VCCB VBUS
3 3 LOTES_AUSB0015-P001A
LOTES_AUSB0015-P001A
TVWDF1004AD0_DFN9 TVWDF1004AD0_DFN9
A A

RUSB30/S&C
Custom 0.2
VFKAA
5 4 3 2 1
A B C D E
20 mil 35mA for 3.3V level 40 mil 650mA for 5V level

UA1 close to pin 25 close to pin 38
+DVDD 1 Rshort@ 2 +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 Rshort@ 2
+3VS +5VALW
MIC1_LINE1_R_R 4.7U_0603_6.3V6K CA58 MIC1_LINE1_R_C_R 22 1 +DVDD 1 RA22 0_0402_5% 2 1 2 1 RA18
MIC1_LINE1_R_L 4.7U_0603_6.3V6K CA57 MIC1_LINE1_R_C_L 21 MIC1_R DVDD 9 +DVDD 0_0603_5%
MIC1_L DVDD_IO 1
CA4 CA42 CA47 CA37 CA50
17 25 +AVDD 0.1U_0402_10V7K CA3
16 MIC2_R AVDD1 38 +AVDD 2 10U_0603_6.3V6M 1 2 1 2
MIC2_L AVDD2 close to pin1 2
2.2U_0402_6.3V6M
10U_0603_6.3V6M
31 39 +PVDD
+MIC1_VREFO_L MIC1_VREFO_L PVDD1
30 46 +PVDD
+MIC1_VREFO_R MIC1_VREFO_R PVDD2
29 1
<41> EC_MUTE_INT MIC2_VREFO
1
60 mil 1
15 45 SPKR+ CA45
14 LINE2_R SPK_OUT_R+ 44 SPKR- 0.1U_0402_10V7K +PVDD 1 Rshort@ 2
LINE2_L SPK_OUT_R- 2 +5VALW
1 2 RA24
close to pin9 CA33 0_0603_5%
20 40 SPKL+ 0.1U_0402_10V7K
MONO_OUT SPK_OUT_L+ 41 SPKL-
SPK_OUT_L-
close to pin39 CA35
@ESD@ MONO_IN 12 2 1 10U_0603_6.3V6M
0.01U_0402_25V7K PCBEEP 75_0402_1%
CA65 1 2 10 33 HPOUT_R RA19 HP_R <40>
<25> AZ_SYNC_HD SYNC HPOUT_R 32 HPOUT_L RA20
11 HPOUT_L 75_0402_1% HP_L <40>
<25> AZ_RST_HD# RESET# 1
CA32
10 mil 5 0.1U_0402_10V7K
SDATA_OUT AZ_SDOUT_HD <25>
close to pin19 8 AZ_SDIN0_HD_R 2 1 For P/N and footprint close to pin46
2 1 19 SDATA_IN AZ_SDIN0_HD <25> 2
close to pin 28 AC_JDREF RA23 33_0402_5%
1 2 LDO_CAP 28 JDREF 6 AZ_BITCLK_HD
Please place them to ISPD page
RA30 20K_0402_1%
AC_VREF 27 LDO_CAP BCLK AZ_BITCLK_HD <25>
CA60 10U_0603_6.3V6M
1 2 CPVEE 34 VREF 269@ UA1
CA54 2.2U_0402_6.3V6M CBN 35 CPVEE 23 LINE1_R_C_L 1 2 MIC1_LINE1_R_L
1 CBN LINE1_L
1
1 2 CBP 36 24 LINE1_R_C_R CA9 0.1U_0402_10V6K

CA25 CA55 CA53 2.2U_0402_6.3V6M CBP LINE1_R 48 269@
2.2U_0402_6.3V6M 0.1U_0402_10V7K NC 1 2 MIC1_LINE1_R_R
2
2 2 CA10 0.1U_0402_10V6K
<22> INT_MIC_DATA INT_MIC_CLK_R 3 GPIO0/DMIC_DATA 26 ALC269Q-VB6-CG
GPIO1/DMIC_CLK AVSS1 37 269@
AVSS2 42
For S&M
SENSE_A 13 PVSS1 43
Sleep and Music
2 @ 1 SENSE_B 18 SENSE_A PVSS2 7
RA34 20K_0402_1% SENSE_B DVSS
47 AGND 259@ No
4 EAPD 49
<41> EC_MUTE# PD# Thermal Pad
2
269@ Yes 2
ALC259-VC2-CG_MQFN48_6X6 For EMI reserve 1 Rshort@ 2
2
269@ 259@ RA44 0_0603_5%

RA50 close to codec 1 Rshort@ 2
4.7K_0402_5% RA43 0_0603_5%
For EMI reserve DGND @EMI@ CA51 1 Rshort@ 2
To solve S&M noise issue AZ_BITCLK_HD 2 1 1 2 @EMI@ RA39 0_0603_5%
1
10_0402_5% RA41 1 Rshort@ 2

RA42 INT_MIC_CLK_R Internal AMP 10P_0402_50V8J RA38 0_0603_5%
<22> INT_MIC_CLK FBMA-10-100505-301T EC_MUTE# 1 Rshort@ 2
CAM_EMI@ Hight Enable RA31 0_0603_5%
LOW Disable
Beep sound SPK MIC/LINE IN

2W 4ohm =40mil For EMI reserve RA47 2 1
+MIC1_VREFO_R
1W 8ohm =20mil close to codec
1K_0402_5% RA48 2.2K_0402_5%
MIC1_LINE1_R_R 2 1 MIC1_R <40>
SPKL+ 1 Rshort@ 2
PCI Beep CA70 RA7 0_0603_5%
SPK_L1 <40>
MIC1_LINE1_R_L 2 1 MIC1_L <40>
1 RA52 2 1 2 MONO_IN 1K_0402_5%
<25> PCH_SPKR SPKL- 1 Rshort@ 2 2 1
47K_0402_5% SPK_L2 <40> RA45 +MIC1_VREFO_L
0.1U_0402_10V7K RA8 0_0603_5% 1 1 RA46 2.2K_0402_5%
3 CA31 CA30 3
2
1 1000P_0402_50V7K 1000P_0402_50V7K MIC_SENSE

RA49 CA27 2 2
@EMI@ @EMI@
6
4.7K_0402_5%
100P_0402_50V8J RA29 269@
2 QA1A 100K_0402_5%
1
2N7002KDWH_SOT363-6 2
For better sound SPKR+ 1 Rshort@ 2 SPK_R1 <40> 269@
RA9 0_0603_5%
by customer request
1
RA37
0_0402_5%
SPKR- 1 Rshort@ 2 SPK_R2 <40> RA35 100K_0402_5%
+3VL
RA10 0_0603_5% 1 1 259@
<41> SM_SENSE#
CA34 CA36
3
1000P_0402_50V7K
@EMI@
2 2
1000P_0402_50V7K
@EMI@ EC QA1B
2N7002KDWH_SOT363-6 5 JACK_SENSE <40>
269@
4
Sense Pin Impedance Codec Signals Function
39.2K PORT-I (PIN 32, 33) Headphone out
place close to chip
20K PORT-B (PIN 21, 22) Ext. MIC MIC_SENSE 2 1 SENSE_A
SENSE A
RA32 20K_0402_1%
10K PORT-C (PIN 23, 24)
4 4
5.1K (PIN 48)

<40> NBA_PLUG
RA33 39.2K_0402_1%
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17) Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-H (PIN 20) HDA-ALC259-VC/269-VB
Rev
Custom
A B C D E
SPK Conn. For common design,
pull-high resistor should be placed at connector side.
+3VS SM_DET BIOS setup Speaker Type BOM

(GPIO48)
1 S&M option Harman/Kardon 269@
2
RA95 JSPK
10K_0402_5% 8 0 Non Harman 259@
7 GND
GND
1
6
<39> SPK_R1 5 6
<39> SPK_R2 4 5
<39> SPK_L1 3 4
<39> SPK_L2 2 3 Non-Harman detection
<30> SPK_DET 1 2
1
ACES_50228-0067N-001 0 ONKYO
Conn@
SPK_DET
(GPIO70) 1 Non-Brand
HeadPhone/LINE Out JACK
JLINE Conn@
6
1
1 Rshort@ 2 HP_R_L 2
<39> HP_L
RA54 0_0402_5%
1 Rshort@ 2 HP_R_R 3
<39> HP_R
RA53 0_0402_5%
100P_0402_50V8J CA11
100P_0402_50V8J CA12
4
<39> NBA_PLUG
3
DA6
1 1 5
YSDA0502C_SOT23-3
@ESD@ TYCO_2041280-1_3.6D
2 2
@EMI@
@EMI@
1
MIC/LINE IN JACK
JEXMIC Conn@
6
1
1 Rshort@ 2 MIC1_R_L 2
<39> MIC1_L
RA56 0_0402_5%
1 Rshort@ 2 MIC1_R_R 3
<39> MIC1_R
RA55 0_0402_5%
CA14
CA13
4
<39> JACK_SENSE
1 1
3
DA7 RA40 5
+3VL
YSDA0502C_SOT23-3
100P_0402_50V8J
100P_0402_50V8J
4.7K_0402_5% TYCO_2041280-1_3.6D
@ESD@ 2 2
@EMI@
@EMI@
269@ RA36
0_0402_5%
259@
1

AUDIO CONN
Size
Document Number Rev
0.2
A B C D E
+3VL +3VL
CB3
1 1 0.1U_0402_10V7K 1 Rshort@ 2 H_PROCHOT# <5>
1 2 <51> VR_HOT#
CB1 CB2 RB1 0_0402_5%
For RF 0.1U_0402_10V7K 0.1U_0402_10V7K
1
D
2 2 1
H_PROCHOT#_EC 2 CB8
111
125
CLK_PCI_EC G 47P_0402_50V8J
22
33
96
67
9
UB1 QB1
1
2N7002KW_SOT323-3 S 2
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
3
RB3
22_0402_5% @RF@
1 21 @
<30> GATEA20 WL_BT_LED# <42>
2
1 2 GATEA20/GPIO00 GPIO0F 23 BATT_PRES 1 2 1

1 <30> KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 USB_EN#0 <38>
3 26 CB9 100P_0402_50V8J
<25> SERIRQ 4 SERIRQ GPIO12 27 FANPWM <5>
CB11 @RF@
<25> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 CLK_REQ_GC6# <13>
ACIN_D 1 2
10P_0402_50V8J
2 <25> LPC_AD3 7 LPC_AD3
<25> LPC_AD2 LPC_AD2 PWM Output CB10 100P_0402_50V8J
8 63 BATT_PRES
<25> LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_PRES <45>
<25> LPC_AD0 LPC_AD0LPC & MISC GPIO39 USB_OC#0 <29,38>
65
12 ADP_I/GPIO3A 66 ADP_I <45,46>
<29> CLK_PCI_EC CLK_PCI_EC AD Input GPIO3B ADP_V <46> +3VS
13 75
<29,35,36,5> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 GPIO42 76 HDPLOCK <34>
+3VL 20 EC_RST# IMON/GPIO43 EC_ENBKL <22,28>
RB2
<30> EC_SCI# 38 EC_SCII#/GPIO0E H_PROCHOT#_EC 1 2
47K_0402_5% @
1 2 <35> WOWL_EN# GPIO1D 68
EC_RST# RB6 10K_0402_5%
DAC_BRIG/GPIO3C 70 885_EC_ON HDPINT <34>
1 2 EN_DFAN1/GPIO3D 71 +3VL
DA Output IREF/GPIO3E PCH_SUSPWRDN# <27>
CB12 0.1U_0402_10V7K KSI0 55 72
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F SUSACK# <27>
KSI2 57 KSI1/GPIO31 LID_SW# 1 2
KSI2/GPIO32
Reserve this signal to EC by SW demand
KSI3 58 83 RB35 47K_0402_5%
KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# <39> 2011/10/18a
KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 PM_SLP_S4# <27> WLAN_WAKE# 1 2
ESD@
1 2 PLT_RST# KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D
RB7 10K_0402_5%
CB13 100P_0402_50V8J KSI7 62 87 TP_CLK
39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_CLK <42>
KSO0 TP_DATA
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <42>
KSO1
KSI[0..7] KSO2 41 KSO1/GPIO21
<42> KSI[0..7] KSO3 42 KSO2/GPIO22 97 +3VS
KSO[0..15] 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 VGATE <27,51>
KSO4
<42> KSO[0..15] 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 GPS_DOWN# <13> 1 2
KSO5 TP_CLK
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 PWRME_CTRL <25>
VCIN0_PH connect to RB8 4.7K_0402_5%
+3VL KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <45>
2 KSO7/GPIO27 SPI Device Interface power portion (9012 only) 2
KSO8 47 TP_DATA 1 2
KSO9 48 KSO8/GPIO28 119 RB9 4.7K_0402_5%
1 2 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SDIO <25>
CHG_PWR_GATE# KSO10
50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SDI <25>
RB11 10K_0402_5% KSO11 SPI Flash ROM
KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_SCK <25>
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A EC_CS0# <25>
KSO14 53 KSO13/GPIO2D SYSON 1 2
KSO15 54 KSO14/GPIO2E 73 WLAN_WAKE# RB10 4.7K_0402_5%
81 KSO15/GPIO2F ENBKL/GPIO40 74 WLAN_WAKE# <35>
CHG_PWR_GATE# 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 WOL_EN# <36> SUSP# 1 2
<38> CHG_PWR_GATE# KSO17/GPIO49 FSTCHG/GPIO50 90 HDPACT <34>
RPB1 RB21 10K_0402_5%
BATT_CHG_LED#/GPIO52 91 BATT_FULL_LED# <42>
1 8 77 CAPS_LED#/GPIO53 92 CAPS_LED# <42> 1 2
+3VL EC_SMB_CK1 EC_SMB_CK1 GPIO VR_ON
2 7 <38,45,46> EC_SMB_CK1 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 PWR_SUSP_LED# <42>
EC_SMB_DA1 EC_SMB_DA1 RB23 10K_0402_5%
3 6 EC_SMB_CK2 <38,45,46> EC_SMB_DA1 EC_SMB_CK2 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_CHG_LOW_LED# <42>
+3VS <13,26,34> EC_SMB_CK2 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON <48>
4 5 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
<13,26,34> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <51>
127 FB_CLAMP_R 1 Rshort@ 2
PM_SLP_S4#/GPIO59 FB_CLAMP <13,14,17>
2.2K_8P4R_5% RB5 0_0402_5%
6 100
<27> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 PCH_RSMRST# <27>
<27> PM_SLP_S5# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# <30>
<27,30> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 PROCHOT_IN <45>
16 103 H_PROCHOT#_EC PROCHOT_IN connect VCOUT0_PH_L 1 Rshort@ 2
<29,36> USB_OC#2 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VS_ON <47>
VCOUT0_PH_L to power portion (9012 only) RB34 0_0402_5%
<26,29,38> USB_CHG_OC# 18 GPIO0B VCOUT0_PH/GPXIOA07 105
<38> USB_CHG_EN# GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# <22>
VCOUT0_PH connect to power portion (9012 only)
19 GPIO 106
<36> USB_EN#2 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# <27>
RB18
<42> KB_LED 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 PCH_PWR_EN <43>
RB27 330K_0402_5%
<5> FAN_SPEED1 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD <50> 2 1
100K_0402_5% +3VL
1 2 E51_TXD <35> WL_OFF# E51_TXD 30 EC_PME#/GPIO15
<35> E51_TXD 31 EC_TX/GPIO16 110 ACIN_D
<35> E51_RXD 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON_R ACIN_D 2 1
3 <27> PM_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 ACIN <27,46> 3
RB751V40_SC76-2 DB1
<35> BT_ON 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 ON/OFFBTN# <42>
GPI LID_SW#
<39> SM_SENSE# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP# LID_SW# <42>
SUSP#/GPXIOD05 117 +VTT_EC SUSP# <43,48,49> 1 885@ 2
GPXIOD06 +1.05VS_VCCP
RB37 0_0402_5% 118 EC_PECI RB4 1 2 0_0402_5%
PECI_KB9012/GPXIOD07 H_PECI <5>
AGND/AGND
1 Rshort@ 2 EC_MUTE_INT_R 122 RB19 43_0402_5%

<39> EC_MUTE_INT 1 2 123 XCLKI/GPIO5D 124
POK_R +EC_V18R
GND/GND
GND/GND
GND/GND
GND/GND
<27> CLK_EC XCLKO/GPIO5E V18R

RB13 @ 0_0402_5% 1
GND0
1 2 CB15
1 2 <27,47> POK
EC_MUTE_INT_R RB14 0_0402_5% 4.7U_0603_6.3V6K Close to EC
1
RB12 4.7K_0402_5% 1
RB22 CB16 KB9012QF-A3_LQFP128_14X14 2 @ESD@
11
24
35
94
113
69
100K_0402_5% 20P_0402_50V8 9012@ 1 2 SUSP#

@ @ CB14 180P_0402_50V8J
2 UB1
2
NPCE885NB0DX LQFP 128P

885@
885@
2 1
+3VL
RB20 330K_0402_5%
EC_ON_R 1 9012@ 2
EC_ON <47>
RB36 0_0402_5%
1 3
S
D
QB2
2N7002KW_SOT323-3
4 885@ 4
Voltage Comparator Pins FOR 9012 A3 RB24 885@

G
2
885_EC_ON 2 1
10K_0402_5%
VCIN0 pin109 >1.2V <1.2V
VCIN1 pin102
HIGH Security Classification Compal Secret Data Compal Electronics, Inc.
VCOUT0 pin104
(default) LOW
LOW LPC-EC-KB9012&NPCE885N
VCOUT1 pin103 HIGH (default) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
A B C D E
5 4 3 2 1
Power Button Conn. Touchpad Connector

JTP Conn@
16 15
14 16 15 13 +3VS
14 13 TP_DATA <41>
12 11
10 12 11 9 TP_CLK <41>
JPWR
1 2 ON/OFFBTN# 8 10 9 7
+3VL 3 1 2 4 6 8 7 5
3 4 6 6 5 PM_SMBDATA <11,12,26,35>
5 4 3
5 6 8 4 3 PM_SMBCLK <11,12,26,35>
7 +5VS
2 1
7 8 2 1
2 R395 ACES_50611-0040N-001
D Conn@ HB_A060877-SAVR01 D
100K_0402_5%
1
ON/OFFBTN# ON/OFFBTN# <41>
ESD diode on SB
BATT CHARGE /FULL LED Keyboard LED

Q38
Screw Hole
D24 R60 KBL@
390_0402_5% +5VS AO3413_SOT23
2 1 1 2
BATT_FULL_LED# <41>
D
3 1 +5VS_LED CPU VGA standoff WLAN standoff
+5VALW HT-F196BP5_WHITE
1
H1 H2 H3 H4 H5 H29
D23 R587 H_4P6 H_4P6x4P2 H_4P2 H_3P3 H_3P3 H_3P3
G
2
2 1 1 2 10K_0402_5% JBLG Conn@ @ @ @ @ @ @
BATT_CHG_LOW_LED# <41>
R3 KBL@ 1
1
1
1
HT-191UD5_AMBER_0603 510_0402_5% 2 1
2
3 2
C 3 C
+5VS_LED
4
5 4
White LED bright when both AC-adaptor is plugged in and Battery is full charged GND
6
1
D
Amber LED bright while charging battery from AC-adaptor. 2 Q52
GND
Amber LED blink during Critical Low Battery <41> KB_LED G 2N7002KW_SOT323-3 ACES_50578-0040N-001
KBL@
S PTH NPTH
3
H6 H7 H8 H9 H10 H11
H_3P0 H_4P0 H_3P2 H_3P0 H_3P0 H_3P0
POWER LED @ @ @ @ @ @ H19
H_3P2N
KEYBOARD CONN.
1
1
@
1
D25 R61
390_0402_5% KSI[0..7]
KSI[0..7] <41>
+5VALW
2 1 1 2 H12 H13 H14 H15 H17 H18
PWR_SUSP_LED# <41> KSO[0..15] JKB H_3P0 H_3P0 H_7P0 H_3P0 H_3P2 H_3P2x3P7
KSO[0..15] <41>
HT-F196BP5_WHITE 1 @ @ @ @ @ @
2 1
1
1
1
3 2
<41> CAPS_LED# 3
+3VS
2 1 4
R376 300_0402_5% KSI1 5 4
White LED bright when system is power on. 5
KSI6 6
White LED blink when system is sleep mode. KSI5 7 6
KSI0 8 7
KSI4 9 8
KSI3 10 9
KSI2
KSI7
11
12
10
11
12
PCB Fedical Mark PAD
KSO15 13
WLAN/WiMAX LED KSO12 14 13
14
KSO11 15 FD1 FD2 FD3 FD4
KSO10 16 15
LED_WIMAX# <35> 17 16
KSO9 @ @ @ @
17
2
KSO8 18
1
R819 KSO13 19 18
B B
2 1 6 1 KSO7 20 19
+5VS 20
10K_0402_5% KSO6 21
21
5
@ Q157A KSO14 22
D26 2N7002DW-T/R7_SOT363-6 KSO5 23 22
2 1 1 2 3 4 @ KSO3 24 23
+5VS 24
R66 KSO4 25
HT-191UD5_AMBER_0603 510_0402_5% Q157B 2N7002DW-T/R7_SOT363-6
@
KSO0
KSO1
KSO2
26
27
28
25
26
27
28
ISPD
WL_BT_LED# <41>
29
30 29 PCH GPU
31 30
32 31
33 32
34 33 UH1 HM76R1@ UV1 N14PGV2R1@
34 35 (Default) (Default)
GND1 36
Amber LED bright while Wireless and/or WiMAX turns on. GND2 HM76R3@ N14PGV2R3@
SA00005FHA0 BD82HM76 SLJ8E C1 SA00006DO00 N14P-GV2-S-A1
CVILU_CF17341U0R0-NH
Conn@ SA00005FHE0 SA00006DO40
BD82HM76 SLJ8E C1 N14P-GV2-S-A1 FCBGA
UH1 HM70R1@ UH1 HM70R3@ UV1 N14MGLR1@ UV1 N14MGLR3@

Lid SW
SA00005MQ50 SA00005MQC0 SA000069000 SA000069010
EC Reset
+3VL BD82HM70 SJTNV C1 BD82HM70 SJTNV C1 N14M-GL-S-A2 FCBGA N14M-GL-S-A2 FCBGA
U21
APX9132ATI-TRL_SOT23-3
2 3
GND
VDD VOUT LID_SW# <41>

A A
1 1 ZZZ
1
@ TJG-533-V-T/R_6P
C453 C452 3 1
0.1U_0402_10V7K 10P_0402_50V8J DAZ0WG00100
2 2 4 2
<47> ENLDO
SW4 PCB LA-9863P
5
6

TP/ISPD/KB/LED/Screw
0.2
VFKAA
5 4 3 2 1
A B C D E
+5VALW TO +5VS +5VALW VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+5VS
+3VALW TO +3VS 1
2
U1
VIN1 VOUT1
14
13
Load switch @
1 C1
SUSP# 3
VIN1
ON1
VOUT1
CT1
12
C2
1
180P_0402_50V8J
2 @
2
C3
1U_0402_6.3V6K
0.1U_0402_10V7K
+5VALW 4 11
2 VBIAS GND C9 330P_0402_50V7K 1
SUSP# 5 10 1 2
ON2 CT2 +3VS
6 9
+3VALW 7 VIN2 VOUT2 8
VIN2 VOUT2
1 15 2 1
GPAD @ C8
TPS22966DPUR_SON14_2X3
0.1U_0402_10V7K
1 1
@ C10
1U_0402_6.3V6K
2
+5VALW
+5VALW +0.75VS +1.05VS_VCCP
+3VL
2
+1.8VS
2
R5545
10K_0402_5% R422 R421 R468
2
100K_0402_5% 22_0805_5% 470_0805_5%
885@ R5546 R470
1
10K_0402_5% PCH_PWR_EN# PCH_PWR_EN# <31,32> 470_0805_5%
1
SUSP
<9> SUSP
1
D Q189 Q60 D
1
Q5527 D
2 Q6A 2 SUSP 2
<41> PCH_PWR_EN
1
D Q190 G G
G 2N7002KW_SOT323-3 SUSP# 2 2N7002KDWH_SOT363-6
2 SUSP <41,48,49> SUSP#
2
S 2N7002KW_SOT323-3 G S 2N7002KW_SOT323-3 S 2
3
3
1
2N7002KW_SOT323-3
S
3
For S3 CPU Power Saving
<49,50> VCCP_PWRGOOD 1 2 0.75VR_EN

0.75VR_EN <48>
R158 220K_0402_5%
3
SUSP 5
Q6B
2N7002KDWH_SOT363-6
+5VS_ODD +5VS TO +5VS_ODD
2
R457
ZPODD@ 470_0805_5%
6 1
3 3
Q53A
ZPODD@ 2 ODD_EN#
2N7002DW-T/R7_SOT363-6
1
+5VS
+3VS +5VS
2
ZPODD@ ZPODD@ C471 Vgs=-4.5V,Id=3A,Rds<97mohm
R441 0.1U_0402_10V7K
100K_0402_5%
5
1 ZPODD@
1
S
R440 Q45
1
G
4 3 1 2 2 NONZP@
<30> ODD_EN#
R120
2N7002DW-T/R7_SOT363-6 47K_0402_5% 2
D 0_0805_5%
1
Q53B ZPODD@ AO3413_SOT23 +5VS_ODD
2
ZPODD@ C217
ZPODD@ 0.01U_0402_25V7K
1
4 4

DC-DC INTERFACE
0.2
VFKAA
A B C D E
A B C D
EMI Part (47.1)

EMI@
A51 need add fuse PL102
FBMA-L11-201209-121LMA50T_0805
1 2
VIN
1 1
EMI@
PL101
@ PJP1 PF1 FBMA-L11-201209-121LMA50T_0805
1 1 2 DC_IN_S1 1 2
1 2
2 3 7A_32V_S1206-H-7.0A
3 4
4
ACES_50299-00401-001
1
EMI@ EMI@ EMI@ EMI@
PC102 PC103 PC101 PC104
1000P_0603_50V7K 100P_0603_50V8 100P_0603_50V8 1000P_0603_50V7K
2
2 2
For ML1220 RTC (38.2)
- PBJ101 @ + PR101
560_0603_5%
PR102
560_0603_5%
2 1 1 2 +RTC_R 1 2
+RTCBATT
ML1220T13RE
+RTC
3 3
4 4

DCIN/PRECHARGE
VFKAA
Date: Sheet 44 of 55
A B C D
A B C D
EMI@ PL3
FBMA-L11-201209-121LMA50T_0805
1 2
Other component (37.1) VMB
@ EMI@ PL2
ACES_50299-01001-W01 PF2 FBMA-L11-201209-121LMA50T_0805
1 BATT_S1 1 2 1 2
1 2 BATT+
2 3 10A_125V_TR2/6125FF10-R
3 4
4 5 BATT_P5 EMI@ EMI@
5 6 OTP (39.7)
1
EC_SMDA PC8
6 7 PC7
1
EC_SMCA
7 8 PR14 1000P_0402_50V7K 0.01U_0402_25V7K
2
1
8 9 1K_0402_1%
1
9 10
10
2
PJP2 +3VL
<41,46> ADP_I
12.1K_0402_1%
2
1
1K_0402_1%
PR4
EMI Part (47.1)
PR1
PR16
2
6.49K_0402_1% @ PR2 @PR5
@ PR5
2 1 0_0402_5% 0_0402_5%
+3VL 1 2 1 2
100K_0402_1%_TSM0B104F4251RZ
<41> PROCHOT_IN <41> VCIN0_PH
1
PR19
1
20K_0402_1%
1K_0402_1%
1
@ PC11
PR3
PH1
0.1U_0402_10V7K
2
2
2
PR20 PR21 BATT_PRES <41>
2
100_0402_1% 100_0402_1%
1
EC_SMB_DA1 <38,41,46>
2 2
EC_SMB_CK1 <38,41,46>
PH1 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
Initial Protect Recovery
65W 0.75V 0.752V 0.626V
75W 0.9V 0.902V 0.722V

3 3
Initial Protect Recovery
CPU OTP 65W 93 C 56 C
4 4

BATTERY CONN / OTP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VFKAA 0.1
A B C D
A B C D
for reverse input protection
Charger controller (40.1), Support component (40.2)
1
D
2 PQ209
G SSM3K7002FU_SC70-3
S
3
PR225 PR226
1 2 1 2
10U_0805_25V6K
1
1M_0402_5% 3M_0402_5%
EMI Part (47.1) 1
PC211
TPCA8057-H_PPAK56-8-5
VIN P1 P2 B+ EMI@
2
PQ203 PR211 PL201
0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 1
PQ205 1 4 1 2 PQ207 1
2200P_0402_25V7K
2 2 2
10U_0805_25V6K
5 3 3 5 2 3 5 3
0.1U_0402_25V6
1
PC213
@EMI@ PC214
2200P_0402_50V7K
0.01U_0402_50V7K
1
PC231 VIN
4
PC234
SI7716ADN-T1-GE3_POWERPAK8-5 SI7716ADN-T1-GE3_POWERPAK8-5
2
1 2
PC230
2
1
2
3
2
PC236
0.1U_0402_25V6 PD230
2
BQ24735_ACDRV_1 BAS40CW_SOT323-3
BQ24735_BATDRV 1 2 BQ24735_BATDRV_1
0.1U_0402_25V6
0.047U_0402_25V7K PR233
0.1U_0603_25V7K
1 1
10_1206_1%
4.12K_0603_1%
PC237
1
PC238
PC235
PR228
5
1 2
1
2.2_0603_5%
PR229
PD231 PQ201
BQ24735_VCC
2
RB751V-40_SOD323-2 AON7408L
DH_CHG 1 @ 2 4
PR210 0_0603_5%
BQ24735_BST 2
BQ24735_REGN2
4.12K_0603_1%
4.12K_0603_1%
2
PC239 2
BQ24735_LX
1
1
1 2 BATT+
PR235
PR234
3
2
1
DH_CHG
PL202
1U_0603_25V6K PC205 4.7UH_ETQP3W4R7WFN_5.5A_20% PR227
BQ24735_ACP
BQ24735_ACN
1 2 0.01_1206_1%
BQ24735_LX 1 2 CHG 1 4
2
2
1U_0603_25V6K
5
2 3
20
19
18
17
16
4.7_1206_5%
PU200
CSON1
CSOP1
1
@EMI@ PR206
BTST
PHASE
HIDRV
VCC
REGN
10U_0805_25V6K
10U_0805_25V6K
21 PQ202
PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC222
PC223
1
1
1 15 DL_CHG 4 AON7406L
ACN LODRV
PC241
PC240
2
2
2 14
680P_0603_50V8J
ACP GND PR236
3
2
1
2
1
BQ24725RGRR_QFN20_3P5X3P5 10_0603_1%
3 13 SRP1 2 CSOP1
@EMI@ PC206
BQ24735_CMSRC
CMSRC SRP
1
PR237
2
6.8_0603_5%
BQ24735_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN
5 11 BQ24735_BATDRV PC242
ACOK BATDRV 0.1U_0603_16V7K
EMI Part (47.1)
ACDET
IOUT
SDA
SCL
ILIM
1 2 BQ24735_ACOK +3VALW
+3VL
6
10
PR239 10K_0402_1%
3 3
BQ24735_ILIM 1 2
PR241
0.01U_0402_25V7K
<27,41> ACIN VIN
100K_0402_1%
357K_0402_1%
1
PC243
PR242
1
BQ24735_ACDET
VIN
1
422K_0402_1%
2
1
PR247
PR244
309K_0402_1%
PR248
2
10K_0402_1%
2
1 2
ADP_V <41>
Vin Dectector
0.1U_0402_25V6
1
66.5K_0402_1%
EC_SMB_CK1 <38,41,45>
1
1
@ PC247
Min. Typ Max. PR249
1
PR245
0.1U_0402_10V7K
PC244
47K_0402_1%
H-->L 17.23V
2
EC_SMB_DA1 <38,41,45>
2
2
L--> H 17.63V
2
@ PR246
PC245 0_0402_5%
2 1 1 2
ILIM and external DPM ADP_I <41,45>
100P_0402_50V8J
3.61A For A51 ADP_V function
1
@ PC246
0.1U_0402_10V7K
2
4 4
Please locate the RC

Near EC chip
2011-02-22
CHARGER
Custom VFKAA 0.1
A B C D
A B C D
3/5VALW controller (35.1), Support component (35.2) 5V

Peak Current 10A
OCP current 12.03A
FSW=390kHz
Delta I=4.29A,ripple=4.29*17m=72.93mV
DCR 15.5mohm+/-15%
ESR 17mohm
1
TYP MAX 1
H/S Rds(on) :27mohm , 34mohm

@ PC345
L/S Rds(on) :10.8mohm , 13.6mohm
100P_0402_50V8J PR350
1 2 30K_0402_1%
EMI Part (47.1) 1 2
B+ EMI@ PR330
3/5V_B+
PL331 14K_0402_1%
1 2 3/5V_B+
HCB2012KF-121T50_0805
56K_0402_1%
143K_0402_1%
226K_0402_1%
2
2
1 2 PR331
PR342
PR357
PR337
20K_0402_1%
1 2 FB_3V PR351
10U_0805_25V6K
2200P_0402_50V7K
10U_0805_25V6K
19.1K_0402_1%
FB_5V 1 2
1
PC340
1
1
1
@EMI@ PC339
PC361
1 2
+3VL
PR335
2
2
5
AON7408L
100K_0402_1%
1
PQ331
4 <27> POK
FB2
ENTRIP2
ENTRIP1
FB1
TON
21
6 PAD
PC335 @ PR333 PGOOD 20 4
0.1U_0402_10V7K 0_0402_5% BYP1 @ PR355 PC355
1
2
3
1 2 BST1_3V 1 2 BST_3V 7 0_0402_5% 0.1U_0402_10V7K AON7408L
BOOT2 19 BST_5V 1 2 BST1_5V 1 2 PQ351
BOOT1
3
2
1
UG_3V 8
2
PL332 UGATE2 18 UG_5V 2
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE1 PL352

2 1 LX_3V 9 2.2UH_ETQP3W2R2WFN_8.5A_20%
+3VALWP PHASE2 17 LX_5V 1 2
PHASE1 +5VALWP
5
LG_3V 10
LGATE2
1
16
4.7_1206_5%
LG_5V
150U_D2_6.3VY_R15M
ENLDO
SECFB
LGATE1
1
@EMI@ PR336
4.7_1206_5%
LDO5
LDO3
1
VIN
@EMI@
PR356
150U_D2_6.3VY_R15M
+
PC331
1
4 PU330
1 SNUB_3V 2
11
12
13
14
15
+
PC351
RT8243AZQW_WQFN20_3X3
2
SNUB_5V
2 4
AON7406L PR334 +3VLP PQ352 2

1
2
3
680P_0603_50V8J
680P_0603_50V8J
PQ332 499K_0402_1% FDMC7692S_MLP8-5
1
1 2 PC344 PC341
3/5V_B+
3
2
1
@EMI@ PC336
4.7U_0603_10V6K 4.7U_0603_10V6K
@EMI@
100K_0402_1%
PC356
1U_0603_10V6K
0.1U_0603_25V7K
2
1
2
1
1
PR338
PC342
PC360
2
2
2
2
EMI Part (47.1)
ENLDO <42>
PR340
2.2K_0402_1%
EMI Part (47.1)
1 2
<41> EC_ON
3
@ PR341 3
0_0402_5%
1 2
<41> VS_ON
4.7U_0603_6.3V6K
100K_0402_5%
1
PC343
@ PR332
3.3V 2
1
Peak Current 8A
OCP current 9.68A
Delta I=1.28A ,ripple=1.28x15m=19.2mV
@ PJ333 @ PJ331
FSW=455kHz 2 1 1 2
+3VLP 2 1 +3VL +3VALWP 1 2 +3VALW
DCR 35mohm +/-15% JUMP_43X39 JUMP_43X118
ESR 15mohm (100mA,40mils ,Via NO.= 2)
TYP MAX
@ PJ332
H/S Rds(on) :27mohm , 34mohm 1 2
+5VALWP 1 2 +5VALW
L/S Rds(on) :19mohm , 23.5mohm JUMP_43X118
4 4

3VALW/5VALW
A B C D
A
DDR controller (35.3), Support component (35.4)
EMI@
PL151
EMI Part (47.1)
HCB1608KF-121T30_0603
B+ 1 2 1.5V_B+
BST_1.5V-1 1 @ 2 BST_1.5V +1.5V

PR155 0_0603_5%
2200P_0402_50V7K
10U_0805_25V6K
DH_1.5V +0.75VSP
0.1U_0603_25V7K
@EMI@ PC152
PC154
2
PC155
SW_1.5V
10U_0805_6.3V6K
10U_0805_6.3V6K
2
1
PC159
PC160
1
5
DL_1.5V
16
17
18
19
20
PU150
2
BOOT
VTT
PHASE
UGATE
VLDOIN
21
AON7408L
PAD
PQ151
4 15 1
LGATE VTTGND
PR158 14 2
PL152 27.4K_0402_1% PGND VTTSNS
1
2
3
0.68UH_PCMB053T-1R0MS_8.5A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC162 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
FDMC7692S_MLP8-5
VDDP VTTREF
390U_2.5V_M
PR159
1
1 5.1_0603_5%
+1.5VP
PQ152
@EMI@ 1 2 VDD_1.5V 11 5
+ VDD VDDQ
PC157
PR156 4
PGOOD
1
4.7_1206_5%
TON
+5VALW PC163
FB
S5
S3
SNUB_+1.5VP 2
1
2 0.033U_0402_16V7K
2
PC164
1
2
3
10
6
1U_0603_10V6K
+5VALW
2
PR160
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP
TON_1.5V
1
@EMI@
PC156
680P_0402_50V7K
2
2
PR161
510K_0402_1% PR162
@ PR163 1.5V_B+ 1 2 10K_0402_1%
0_0402_5%
1 2 EN_1.5V
<41> SYSON
1
1 1
EN_0.75VSP
1
@ PC166 @ PR164
@ PJ151 0.1U_0402_10V7K 0_0402_5%
2 1 1 2
2
2 1 <43> 0.75VR_EN
@ PJ153 JUMP_43X118
2 1
+0.75VSP 2 1 +0.75VS @ PJ152
1
JUMP_43X39 2 1
+1.5VP 2 1 +1.5V
@ PC167
JUMP_43X118 0.1U_0402_10V7K
2
(0.5A,40mils ,Via NO.= 1) @ PJ180
(15A, 600mils ,Via NO.= 30) 1 2
OCP=18A +1.8VSP 1 2 +1.8VS
JUMP_43X79
1.5V
Peak Current 16.8A 1.8VS controller (35.15), Support component (35.16)
OCP current 20 A
FSW=495kHz
DCR 13mohm PL181
PU180
SY8032ABC_SOT23-6 PL182
ESR 9mohm HCB1608KF-121T30_0603
1 2 4 3 LX_1.8V
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2
TYP MAX +5VALW IN LX +1.8VSP
5 2
68P_0402_50V8J
H/S Rds(on) :27mohm , 34mohm PG GND
1
4.7_0402_1%
2
1
1
PC187
6 1
L/S Rds(on) :10.8mohm , 13.6mohm PC184 FB EN
PR186
22U_0805_6.3VAM PR183
20K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
2
1
1
PC183
PC182
1
@ PR181 FB_1.8V
680P_0402_50V7K
2
2
1 2 EN_1.8V
STATE S3 S5 1.5VP VTT_REFP 0.75VSP <41,43,49> SUSP#
1
PC186
0_0402_5% PR184
1
S0 Hi Hi On On On
2
1
10K_0402_1%
@ PR182 PC185
Off
2
499K_0402_1% @ 0.1U_0402_10V7K
S3 Lo Hi On On
2
(Hi-Z)
2
S4/S5 Lo Lo Off Off Off

(Discharge) (Discharge) (Discharge) Security Classification Compal Secret Data Compal Electronics, Inc.
Note: S3 - sleep ; S5 - power off THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/0.75VSP/1.8VSP
A
5 4 3 2 1
D D
1.05VCCP controller (35.5), Support component (35.6)
PR402
@
2 1
SUSP# <41,43,48>
0_0402_5%
1
@ PC402
@PC402
0.1U_0402_16V7K
2
EMI Part (47.1)
@EMI@ @EMI@
EMI Part (47.1) PR403 PC403
4.7_1206_5% 680P_0603_50V7K
PL401 1 2 1 2
C EMI@ SNUB_+1.05VSP C
HCB2012KF-121T50_0805 PU400
2 1 +1.05VSP_B+ 8 1 PC406
B+ IN EN
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0603_25V7K
6 1 2 PL402
BS
1
PC401
0.68UH_PCMC063T-R68MN_15.5A_20%
@EMI@ PC404
9 10 SW_+1.05VSP 1 2
GND LX +1.05VS_VCCPP
2
1K_0402_1% 4700P_0402_16V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC407
4
FB
PC408
PC409
PC410
PC411
2
3 7
+3VS +3VALW
2
ILMT BYP
1 2 PGD_1.05V 2 5
4.7U_0603_6.3V6K
2.2U_0603_6.3V6K
+3VS PG LDO
75K_0402_1%
PC413
1
1
PC412
PR401 SY8208DQNC_QFN10_3X3
1
PR404
100K_0402_5%
1
<43,50> VCCP_PWRGOOD @ PR413
PR406
0_0402_5%
2
2
VCCIO_SENSE <8>
1
PR405
The current limit is set to 8A, 12A or 16A when this pin 100K_0402_1%
is pull low, floating or pull high respectively.
2
B B
@ PJ401
2 1
+1.05VS_VCCPP 2 1 +1.05VS_VCCP
JUMP_43X118
(17A,680mils ,Via NO.=34)
OCP=23.91A
A A

+1.05VS_VCCP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VFKAA 0.1
5 4 3 2 1
5 4 3 2 1
VID [0] VID[1] VCCSA Vout

0 0 0.9V
0 1 0.85V
1 0 0.775V
1 1 0.75V
D D
VCCSA controller (35.17), Support component (35.18)

+VCCSAP @ PJ602 +VCCSA
1 2
1 2
JUMP_43X118
PEN@ PR611
1 2
+1.05VS_VCCP +VCCSA
0.005_1206_1%
C C
+3VS
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC628
PC626
100K_0402_5%
1
PU601
2
9
GND
PR610
5 4 +VCCSAP
+VCCSA_B+ VIN Vo
2
6 3 @ PR621
0.9V
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+5VALW VPP Vo 0_0402_5%
22U_0603_6.3V6M
@ PR601 7 2 1@ PR622 2 H_VCCSA_VID1 <9>
POK D1
1
<41> SA_PGOOD 0_0402_5% 0_0402_5%
PC613
PC615
PC616
PC618
<43,49> VCCP_PWRGOOD 1 2 8 1 1 2 H_VCCSA_VID0 <9>
VEN/MODE D0
2
G978F11U_SO8
1U_0603_6.3V6M
1U_0603_6.3V6M
1
1
PC624
PC629
2
2
@ PJ601
2 1
B +1.05VS_VCCP 2 1 +VCCSA_B+ B
JUMP_43X79
(6A, 240mils ,Via NO.= 6)
A A

VCC_SAP
Custom VFKAA 0.1
5 4 3 2 1
5 4 3 2 1
+5VS 1 2 CSP1A
PR502 @0_0402_5%
DIS only:
CSP1A, CSP2A to +5VS. All AXG components are @.
Except
PR272 and PR273 are 0ohm.
LGA, SWA, HGA, BSTA, DIFFA, TRBSTA#, ILIMA, PWMA are float.
PC223, PC226, PR202 are 0ohm.
VSPA, VSNA to GND (HW side). FBA and COMPA are short. PC220, PC215, PR206 are 0ohm.
CSREFA, TSNSA, IOUTA to GND. CSCOMPA, CSSUMA, DROOPA are short.
D D
@330P_0402_50V7K
PC502
1000P_0402_50V7K
1 PR501 2 FBA3 1 2 PC501 1 2
PUT COLSE
75K_0402_1%
10_0402_1% 0.033U_0402_16V7K .1U_0402_16V7K
TO GT
1
PR548 1 PR550 2
PC503
PC504
PR551
TRBSTA# 1 2
PR549 FBA1 1 2 PH503 Inductor
2P: 24K 24.9K_0402_1% PR546 PC507
1
1
8.06K_0402_1% 806_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC505 1P: 24.9K
2
PR545 PC508 PC509 2 PR544 1 NTC_PH203 1K_0402_1% 1000P_0402_50V7K
2
0.033U_0402_16V7K 1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 2P: 1.65K
560P_0402_50V7K PR541 10P_0402_50V8J PC510
1 PR542 2 1 2 COMPA1 1 2 1P: 1K
1K_0402_1% 5.11K_0402_1% 1500P_0402_50V7K CSREFA
PC511 TSENSEA
2
1 PR540 2 0.047U_0402_16V7K
SW1A <51,52>
2P: 21.5K 59K_0603_1% PR539 4.7K_0402_1%
1
CSP1A 1 2
1P: 15.8K SW1A <51,52>
2
2
DROOPA 15.8K_0402_1%
PC512
<9> VCC_AXG_SENSE
1
2
2
23.2K_0402_1%
1000P_0402_50V7K
1PR538
1
PC513 PH504
CSREFA <52>
PR537
1000P_0402_50V7K
1
+5VS 100K_0402_1%_TSM0B104F4251RZ
<9> VSS_AXG_SENSE
PC514
1
CSP1A
1 2
CSCOMPA
TRBSTA#
CSSUMA
CSREFA
TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K
DIFFA
ILIMA
C C
PR543 2P: 36K
1 2 PUT COLSE
26.1K_0402_1% 1P: 26.1K
61
60
56
55
53
51
50
49
48
47
59
58
57
54
52
46
+5VS 1 PR535 2 PU501 TO V_GT
2_0603_5% HOT SPOT
VSNA
FBA
COMPA
ILIMA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
PAD
VSPA
DIFFA
IOUTA
DROOPA
TSNSA
TRBSTA#
+1.05VS_VCCP 6132_PWMA <52>
PC517
1 2 81012_VCC
.1U_0402_16V7K
.1U_0402_16V7K
1 45
2.2U_0603_10V7K 2 VCC PWMA 44
VDDBP BSTA
130_0402_1%
54.9_0402_1%
3 43
VRDYA HGA
1
1
PR534 2
1 2 VR_ON_CPU 4 42
<41> VR_ON EN SWA
PR533
PC518 PC519 @ PR532 0_0402_5% VR_SVID_DAT 5 41 PC520

VR_SVID_ALRT# 6 SDIO LGA 40 BST2 1 PR530 2 BST2_1 1 2
2
2
PR527 PR529 VR_SVID_CLK 7 ALERT# BST2 39 2.2_0603_5% 0.22U_0402_10V6K

SCLK HG2 HG2 <52>
66.5K_0402_1% 1 2 VBOOT 8 38
SW2 <51,52>
1
1 2 10K_0402_1% ROSC_CPU 9 VBOOT NCP81012BMNR2G_QFN60_7X7 SW2 37 PC521

<8> VR_SVID_DAT ROSC LG2 LG2 <52>
CPU_B+ 1 2 VRMP 10 36 81012P_VCCP 1 2 1 2
<8> VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 @ PR528 0_0402_5% 2.2U_0603_10V7K
<8> VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K
PR525 1K_0402_1% VGATE 12 34

VRDY LG1 LG1 <52> +5VS
1
13 33
+1.05VS_VCCP VSN SW1 SW1 <51,52>
PC522 14 32 PC523
+3VS VSP HG1 HG1 <52>
DIFF_CPU 15 31 BST1 1 PR524 2 BST1_1 1 2
CSCOMP
2
DIFF BST1
TRBST#
2.2_0603_5% 0.22U_0402_10V6K
DROOP
CSSUM
DRVEN
CSREF
1
COMP
TSNS
CSP2
CSP3
CSP1
PWM
IOUT
ILIM
1
PR523
@75_0402_1% PR522 FB
10K_0402_5%
16
19
20
26
28
29
30
17
18
21
22
23
24
25
27
3P: 73.2K
2
1 PR521 2
<41> VR_HOT# 2P: 41.2K
2
COMP_CPU
41.2K_0402_1%
FB_CPU
TRBST#
<27,41> VGATE
DROOP
TSENSE
ILIM_CPU
<8> VSSSENSE 3P: 22p

1
IMON
2P: 10p DRVEN <52>

PC524
B 1000P_0402_50V7K B
2
PC525
<8> VCCSENSE
2
PR520 12.4K_0402_1%
1 2
.1U_0402_16V7K
PC527 CSP1 TSENSE

3P: 330p 1 PR519 2 2 1 CSP2 +5VS
1
1K_0402_1% CSP2 1 PR518 2

2P: 1000p SW2 <51,52>
1
10P_0402_50V8J
PC528 4.7K_0402_1%
PR517 PC529 PR515 PC530 3P: 21K 0.047U_0402_16V7K
2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1 CSREF
PR514 PC531 49.9_0402_1% 2P: 12.4K
23.2K_0402_1%
1 2FB_CPU3 1 2 560P_0402_50V7K 6.34K_0402_1% 1800P_0402_50V7K
PR512 1
2
10_0402_1% 3P: 6.04K CSP1 1 PR513 2
CSREF <52> SW1 <51,52>
CSCOMP
1
0.033U_0402_16V7K 4.7K_0402_1% PH502
PR511 PR510 2P: 4.32K PC532 PC533
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p 0.047U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
1
2
0.033U_0402_16V7K
CSREF
2P: 1200p
1
1
8.06K_0402_1% 806_0402_1%
PC534
CSSUM
2
PC535
1 2
1000P_0402_50V7K 1 PR509 2 SW1
24.9K_0402_1%
120K_0603_1% PUT COLSE

2
2
.1U_0402_16V7K
TO VCORE
PC537
3P: 23.7K 1 2 PC538 1 PR507 2 SW2

330P_0402_50V7K
PR508
2P: 24.9K
120K_0603_1% HOT SPOT
1
1 PR505 2NTC_PH201 1 PR504 2

1
75K_0402_1%
PR503 PC539 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF PH501
A PUT COLSE A
1K_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE
2P: 1K Phase 1 220K_0402_5%_ERTJ0EV224J
Inductor
Security Classification
2012/09/24
Compal Secret Data Compal Electronics, Inc.
Issued Date Deciphered Date 2013/09/24 Title
PWR-CPU_CORE
Custom VFKAA 0.1
5 4 3 2 1
5 4 3 2 1
EMI Part (47.1) EMI@

CPU_B+ PL501
FBMA-L11-201209-121LMA50T_0805 CPU_B+
1 2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B+ EMI@
2200P_0402_25V7K
PL505
FBMA-L11-201209-121LMA50T_0805
1
1 2
@EMI@ PC552
PC541
PC542
PC543
PC544
CPU_B+
1 1
2
HG1_1 HG2_1
100U_25V_M
+CPU_CORE
33U_D2_25VM_R60M
D <51> HG1 + + <51> HG2 D
PC551
PC598
+CPU_CORE
PL502 2 @ 2 PL503
0.22UH_MMD-06DZNR22MEO1L_25A_20% 0.22UH_MMD-06DZNR22MEO1L_25A_20%
1 2 1 2
<51,52> SW1 <51,52> SW2
1
EMI@ PQ505 EMI@
D1
G1
S1/D2
2
7
PR506 FDMS3664S_POWER56-8-7 PR526
4.7_1206_5% 4.7_1206_5%
D1
G1
S1/D2
2
PR552 PR553
G2
S2
S2
S2
2 1 2 1CSREF
1SNUB_CPU1
SNUB_CPU2
FDMS3664S_POWER56-8-7 CSREF <51>
10_0402_1%
G2
S2
S2
S2
6
PQ501 10_0402_1%
6
SW1 <51,52> SW2 <51,52>
EMI@
PC506
EMI@
680P_0402_50V7K
1
PC526
<51> LG2
2
<51> LG1 680P_0402_50V7K
EMI Part (47.1)
2
EMI Part (47.1)
C C
DC 35W CPU
CPU_B+ VID1=1.05V
IccMax=53A
10U_0805_25V6K
10U_0805_25V6K
Icc_Dyn=43A
Icc_TDC=33A
1
PR284 R_LL=1.9m ohm
PC547
PC548
BSTA1 1 2 BSTA1_1
2.2_0603_5%
OCP~65A
2
2
0.22U_0402_10V6K
1
PC286
2
PU202
1 9
BST FLAG PL504 +GFX_CORE
2 8 HG1A 0.22UH_MMD-06DZNR22MEO1L_25A_20%
<51> 6132_PWMA PWM DRVH
PR285
B B
2 1EN_GFX1 3 7 SW1A 1 2
<51> DRVEN EN SW
2K_0402_1%
1
+5VS 2 1VCC_GFX1
2 1 4
VCC GND
6
2
PR272 @ PR275 EMI@

@ 5 LG1A PR516
D1
G1
S1/D2
0_0402_5% 0_0402_5% DRVL

1
4.7_1206_5%
NCP5911MNTBG_DFN8_2X2
2
PC289
2
2.2U_0603_10V6K FDMS3664S_POWER56-8-7
G2
S2
S2
S2
PQ503
SNUB_GFX1
3
2 PR5541
CSREFA <51>
10_0402_1%
EMI@
1
PC516
680P_0402_50V7K SW1A <51>
2
EMI Part (47.1)

DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
A
Icc_TDC=21.5A A
R_LL=3.9m ohm
OCP~40A
Security Classification Compal Secret Data

PWR-CPU_CORE
Custom VFKAA 0.1
5 4 3 2 1
Compal Electronics, Inc.

5 4 3 2 1
CPU_CORE output cap (36.4) +CPU_CORE
GFX_CORE output cap (36.5)

VCCP output cap (36.6)
1
22U_0603_6.3V6M
PC555
22U_0603_6.3V6M
PC556
22U_0603_6.3V6M
PC557
22U_0603_6.3V6M
PC558
22U_0603_6.3V6M
PC559
2
2
D D
1
+GFX_CORE
22U_0603_6.3V6M
22U_0603_6.3V6M
PC560
PC561
22U_0603_6.3V6M
PC562
22U_0603_6.3V6M
PC563
22U_0603_6.3V6M
PC564
2
2
PC584
PC586
PC585
PC587
PC588
PC589
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1
2 2 2 2 2 2
+CPU_CORE
1 1 1 1 1 1 1 1
22U_0603_6.3V6M
PC565
22U_0603_6.3V6M
PC567
22U_0603_6.3V6M
PC566
22U_0603_6.3V6M
PC568
22U_0603_6.3V6M
PC569
22U_0603_6.3V6M
PC570
22U_0603_6.3V6M
PC571
22U_0603_6.3V6M
PC572
PC590
PC591
PC592
PC593
PC594
PC595
2 2 2 2 2 2 2 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1
2 2 2 2 2 2
C C
1 1 1 1 1 1 1 1
PC579
22U_0603_6.3V6M
PC573
22U_0603_6.3V6M
PC574
22U_0603_6.3V6M
PC575
22U_0603_6.3V6M
PC576
22U_0603_6.3V6M
PC577
22U_0603_6.3V6M
PC578
22U_0603_6.3V6M
22U_0603_6.3V6M
PC580
2 2 2 2 2 2 2 2
330U_D2_2V_Y
1
+
PC596
+CPU_CORE
1 1
+ PC581 + PC582
330U_D2_2V_Y 330U_D2_2V_Y
2 2
B B
+1.05VS_VCCP
+1.05VS_VCCP
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC420
PC424
PC417
PC418
PC419
PC421
PC422
PC423
PC425
PC426
2 2 2 2 2 2 2 2 2 2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 1
PC428
PC427
PC429
PC430
PC431
PC432
PC433
PC434
2 2 2 2 2 2 2 2
A A

CPU_CORE_CAP
5 4 3 2 1
A B C D
+VGA_CORE Under VGA Core GB4-128 package
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
VGA_CORE controller (43.1), Support component (43.2) EMI Part (47.1)
1
1
PC903
PC904
PC905
PC909
PC907
PC908
PC958
PC911
PC912
PC913
@ PC950
@ PC951
@ PC949
@ PC902
+VGA_B+ EMI@
2
2
PL901
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
2 1
B+
1 1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2200P_0402_50V7K
1
1
PC918
PC919
PC920
PC921
10U_0805_25V6K
10U_0805_25V6K
5
1
EMI@ PC915
PC910
PC917
2
2
2
PQ901
AON7518
2
<13>
+3VS_DGPU
+3VS_DGPU
DGPU_VID
4
<13>
+VGA_CORE Near VGA Core
PSI
PR907 PC922
2.2_0603_5% 0.22U_0603_10V7K
3
2
1
2 1BOOT1_2_VGA 1 2 @
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M 7x7
PR908
22U_0603_6.3V6M
47U_0805_6.3V6M
1
1
1
1
PR929 10K_0402_5%
PC923
PC925
PC926
PC927
PC929
@ PC952
@ PC953
@ PC955
@ PC954
@ PC956
PC924
PC928
2 1 UGATE1_2_VGA
.1U_0402_16V7K
PL903
+VGA_CORE
1
@ PR932 0_0402_5%
10K_0402_5%
0.22UH_MMD-06DZNR22MEO1L_25A_20%
1
1 2
BOOT1_VGA
2
2
2
2
2 0_0603_5%
PR912
2
5
0_0402_5%
1
@ PR909
PQ902
2
TPCA8059 EMI@
2
PR906
PC930
4.7_1206_5%
560U_D2_2VM_R4.5M
1
1
LGATE1_VGA 4
1 SNUB1_VGA 2
+
PC931
1
10K_0402_5%
GV@ PR915 GV@ PR913 GPU_VID
2
PSI_VGA
PR911
20K_0402_1% 20K_0402_1% UGATE1_VGA
EN_VGA
3
2
1
VREF 2 1 2 1 VIDBUF
2
EMI@ 2
1
1
@ PC933 @ PC906
2
PHASE1_VGA
1500P_0402_50V7K 680P_0402_50V7K
GV@ PR930
2
PU900
1
GV@ PR914 2K_0402_1%
18K_0402_1%
PSI
HG1
BST1
VIDBUF
VID
EN
2
2 1
GV@ PC940 2700P_0402_50V7K
2 1 REFIN 7 24
EMI Part (47.1)
REFIN PH1
PRV11 = 71.5K ==>Fsw = 450KHz 1 2 VREF 8 23
VREF LG1 PC935 4.7U_0603_10V6K
@ PR917 PC934 .01U_0603_16V7K 2 1 FS 9 22 1 2
0_0402_5% PR931 34K_0402_1% FS PGND
1 2 10 21 PVCC_VGA 2 1
<15> VGA_VSS_SENSE FBRTN PVCC +5VS
1000P_0402_50V7K
@ PR901
PC936
PC937 PR919 FB_VGA 11 20 0_0402_5%

FB LG2
1
47P_0402_50V8J 51_0402_1% PC938 10P_0402_50V8J +VGA_B+

1 2 FB1_VGA1 2 1 2 COMP_VGA 12 19
TALERT#
@ PR920 PR921 COMP PH2
PGOOD
2
TSNS
0_0402_5% 10K_0402_1%
BST2
GND
VCC
HG2
1 2 1 2 1 2FB2_VGA1 2
<15> VGA_VCC_SENSE
10U_0805_25V6K
10U_0805_25V6K
5
PC939 PR922
25
13
14
15
16
17
18
1
PC942
PC943
100P_0402_50V8J 82K_0402_1% NCP81172MNTWG_QFN24_4X4
BOOT2_VGA
VCC_VGA
PR923
2
@
UGATE2_VGA 2 1 UGATE2_2_VGA 4
N14P-GV2 N14M-GL PQ903
VGA_PWROK <17,30> 0_0603_5%
3
GL@ PR913 AON7518 3
PR926 5.9K_0402_1%
39K_0402_1% PR925 10K_0402_5% PR924 PC944

R1 PR913 20 Kohm 39 Kohm
3
2
1
2 1 +3VS 2.2_0603_5% 0.22U_0603_10V7K
GL@ PR915 2 1 BOOT2_2_VGA 1 2 7x7
1
30K_0402_1% PR927 2.2_0402_5% PL904

R2 PR915 20 Kohm 30 Kohm 2 1 +5VS 0.22UH_MMD-06DZNR22MEO1L_25A_20% +VGA_CORE
GL@ PR930 PHASE2_VGA 1 2
2
1U_0402_10V6K
3K_0402_1%
R3 PR930 2 Kohm 3 Kohm
5
2
1
PC946
GL@ PR914 PQ904

1
27K_0402_1% TPCA8059 EMI@

R4 PR914 18 Kohm 27 Kohm PR916
GL@ PC940 4.7_1206_5%
330U_D2_2V_Y
VREF
1
1800P_0402_50V7K LGATE2_VGA 4
C PC940 2.7 nF 1.8 nF
1SNUB2_VGA 2
+
PC947
2@
3
2
1
EMI@
PC916
680P_0402_50V7K
2
MDU1512, Rdson(max)=5mohm
EMI Part (47.1)
4 4

+VGA_COREP
A B C D
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------

Power PIR
Rev
Custom 0.1
QFKAA
5 4 3 2 1
HW PIR (Product Improve Record)

VFKAA LA-9863P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 to 0.2
GERBER-OUT DATE: 2012/12/06

-----------------------------------------------------------------------------------------------------------------------------------
D 1. 11/20 06 Mount CC37 To solve S3 shutdown issue D
2. 11/20 29 Change USB port 10 to NC No support NFC

3. 11/20 42 Delete JNFC No support NFC
4. 11/20 37 Add QW1, RW3, RW4; change JCARD.10 to SDWP# and JCARD.11 to SDCD To solve card reader no function issue
5. 11/27 40 Change JSPK to ACES_50228-0067N-001_6P For SPK recognize design
6. 11/28 08 Mount CC17, CC18, CC19 For ESD request
7. 11/28 29 Mount CB13 For ESD request
8. 11/28 05 Mount CC63 For ESD request
9. 12/03 38 Add S&C 14640/14641 co-layout circuit Reserved for S&C SPEC update
VFKAA LA-9863P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.2 to 0.3
GERBER-OUT DATE: 2013/01/23
1. 12/19 41 Change CB13 to SE071101J80 (100pF) ESD request

C C
2. 12/26 17 Change RV43 to 270K, RV53 to 10K, RV54 to 33K For VGA power sequence
3. 01/16 41 Add RB12, RB37, connect EC_MUTE_INT from codec to EC To solve audio "bo" sound issue
4. 01/16 42 Modify JTP pin define For ME drawing update
5. 01/16 13 Connect GPIO12 as GPS_DOWN# to EC For GPS function
6. 01/16 26 Mount RH38 For EMI request
7. 01/16 22 Reserve R266, R267 For EMI request
B B
A A

5 4 3 2
HW-PIR 1

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5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 6A +5VS

Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 5A +3VALW

DESIGN CURRENT 330mA +3V_LAN

DESIGN CURRENT 3A +3V_WLAN

DESIGN CURRENT 6A +3VS

DESIGN CURRENT 1.5A +LCD_VDD

Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A +1.05VS_VCCP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

N-CHANNEL DESIGN CURRENT 11A +VRAM_1.5VS

( O MEANS ON X MEANS OFF )

HM76R1@ HM70R1@ N14MGL@ N14PGV2@

BTO 269@ 259@ KBL@ EMI@ ESD@

PCH SM Bus Address

Power Device HEX Address

+3VS Touch Pad 2C H 0010 1100 b

G3 LOW LOW LOW

Security Classification Compal Secret Data Compal Electronics, Inc.

Stuff R41 and R42 if do not support eDP

100 MHz +1.05VS_VCCP

JTAG & BPM

0206: Delete 0.1uF

FAN Control Circuit

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS* - GRAPHICS

RC9 SANDY Bridge Gen1/Gen2 180 nF~265 nF

NV N14x Gen1/2/3 Suggest 220 nF

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

JCPUF POWER +1.05VS_VCCP +1.05VS_VCCP

V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 2

V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <51>

R27 VCC88 AJ35

A P28 VCC97 RC96 RC98 A

+GFX_CORE Intel DDR Vref M3 Place near SO-DIMM side

DDR3 -1.5V RAILS

AH23 VAXG49 VCCSA2 L26

A2 VCCPLL2 VCCSA_VID[0] C24 H_VCCSA_VID0 <50>

1U_0402_6.3V6K TYCO_2013620-2_IVY BRIDGE

+1.5V_CPU JP@ +1.5VS

Security Classification Compal Secret Data Compal Electronics, Inc.

AN16 AE9 L1 B13 F25

1: (Default) PEG Train immediately following xxRESETB

Security Classification Compal Secret Data Compal Electronics, Inc.

B DDR_A_D35 143 144 B

139 140 DDR_B_D38

RV4 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK_OUT C11 XTALIN

Security Classification Compal Secret Data Compal Electronics, Inc.

VRAM Interface Place close to the first T point

MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5

Place close to BGA MDA60 V26 RV10 100_0402_5% RV11 100_0402_5%

D24 OPT@ OPT@

F16 62mA D25

Security Classification Compal Secret Data Compal Electronics, Inc.

BINARY STRAPS (for N14M-GL) MULTI LEVEL STRAPS (for N14P-GV2)

Physical Logical Logical Logical Logical

ROM_SCLK SMB_ALT_ADDR PD 10k ROM_SO +3VS_DGPU FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE

K2 E12 STRAP1 STRAP3 ROM_SI

Security Classification Compal Secret Data Compal Electronics, Inc.